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Glitches and Hazards in Digital Circuits

Glitches and Hazards in Digital Circuits

“After a moment you change your mind”

© John Knight

Electronics Department, Carleton University

Printed; March 19, ’01 Modified; November 1, ’97

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Glitches and Hazards in Digital Circuits

Hazards
Glitches and a Hazards
A glitch is a fast “spike” usually unwanted. A hazard in a circuit may produce a glitch. if the propagation delays are unbalanced.

The Classification of Hazards by the Glitch They May Produce
static-zero hazard; signal is static at zero, glitch rises. static-one hazard; signal is one, glitch falls. dynamic hazard; signal is changing, up or down

© John Knight

Electronics Department, Carleton University

Printed; March 19, ’01 Modified; November 1, ’97

2

Glitches and Hazards in Digital Circuits

The Two Basic Static-Hazard Circuits

The Two Basic Static-Hazard Circuits
Basic Static-Zero Hazard Circuit
FIG. 1-1 x

Basic static-0
1 1

Any circuit with a static-0 hazard must reduce to the equivalent circuit of FIG. 1-1, if other variables are set to appropriate constants.
0 x FIG. 1-2 x 0 1

An imbedded static-0 hazard
1 x x 0 1 x 0 x x x

Static-zero Hazard’s Characteristics
• Two parallel paths for x. • One inverted. • Reconverge at an AND gate.

© John Knight

Electronics Department, Carleton University

Printed; March 19, ’01 Modified; November 1, ’97

3

Glitches and Hazards in Digital Circuits Basic Static-One Hazard Circuit
FIG. 1-3 x

The Two Basic Static-Hazard Circuits

Basic static-1 hazard circuit
0 0

Any circuit with a static-1 hazard must reduce to the equivalent circuit of FIG. 1-3

t

FIG. 1-4 1

An imbedded static-1 hazard
0 0 x x 1 1

x 0

Static-One Hazard’s Characteristics
• Two parallel paths for x. • One inverted. • Reconverge at an OR gate.

© John Knight

Electronics Department, Carleton University

Printed; March 19, ’01 Modified; November 1, ’97

4

Glitches and Hazards in Digital Circuits

The Two Basic Dynamic-Hazard Circuits

The Two Basic Dynamic-Hazard Circuits
Basic Dynamic Hazard Circuits
A static hazard with an extra gate for the static level change. Three parallel paths, one containing a static hazard.
x FIG. 1-5 delay

The basic dynamic hazard circuit with an imbedded static-1 hazard.

Three Parallel paths x

delay FIG. 1-6

The basic dynamic hazard circuit with an imbedded static-0 hazard.

Note that a dynamic hazard always has three parallel paths.

© John Knight

Electronics Department, Carleton University

Printed; March 19, ’01 Modified; November 1, ’97

5

’01 Modified. With standard cells and field-programmable arrays. Note the hazard appears on the falling edge of x.Glitches and Hazards in Digital Circuits Adding Delay to Hazards The Two Basic Dynamic-Hazard Circuits Adding delay can remove hazards. FIG. March 19. • Adding too much delay will make the glitch appear on the rising edge. if you can! delay 0 0 x At the silicon layout level. if one has good control of propagation delays. FIG. 1-8 Adding delay. one might balance delays closely enough to suppress the glitch. November 1. Carleton University Printed. 1-3. But see ”Absorption of Glitches by Gates” on page 53. balancing is harder. 0 0 x • Adding an equal delay in the other path removes the falling-edge glitch. moves the glitch from x to x . © John Knight Electronics Department. 1-7 Basic static-1 hazard circuit from FIG. To kill the glitch balance the delays exactly. The original circuit with the delay in the inverter. ’97 6 .

© John Knight Electronics Department. 1-9 Map of a static-1 hazard. Carleton University Printed. x 0 1 1 1 map of y x=0 x=1 An interpretation of the map of y. March 19. ’01 Modified. each OR gate input is a separate circle.” Changing hills causes a “0” glitch as one crosses the valley. x y FIG. ’97 7 . The shows the hazard. Standing on top of a hill gives a “1. November 1. On the Σ of Π map.Glitches and Hazards in Digital Circuits Hazards on a Karnaugh Map Hazards on a Karnaugh Map Adjacent but nonoverlapping circles on the map are hazards.

X A The equation F = BX + AX has redundant term AB added F = BX + AX + AB This fills the valley between terms BX and AX. AB X 00 01 11 10 0 0 BX 0 1 0 0 AX AX AB B BX BX + AX + AB AB FIG. 1-10 0 0 AX AND gates have been added to the hazard. To mask static-1 hazards add a gate that stays high across the This gate is logically redundant. November 1. B = 1. © John Knight Electronics Department. The hazard appears only when A = 1. Masking a Hazard. Then signal x travels right through the ANDs. 1-11 transition. The hazard is still the inverter and the OR gate. March 19. AB X 00 01 11 10 0 0 BX 0 A X AX AX + BX B BX 1 FIG. ’01 Modified. Carleton University Printed. ’97 8 . not static-0 or dynamic hazard.Glitches and Hazards in Digital Circuits A Static-1 Hazards on a Map Hazards on a Karnaugh Map Σ of Π maps can only show static-1 hazards.

+. .) a) Bracket all groups of ANDs b) Change AND to OR and OR to AND Clean brackets c) Invert all variables F = [A·B·C + D·(A·B+C)]·A F = {[{A·B·C} +{D·({A·B} +C)}]·A} {[{A+B+C} ·{D+({A+B}·C)}]+A} {A+B+C}·{D+{A+B}·C}+A F = {A+B+C}·{D+{A+B}·C}+A Examples F = A·B·C F = A·B·C + A·B F = A·B·(C + A·B) © John Knight {A·B·C} {A·B·C} + {A·B } {A·B}·(C+{ A·B }) Electronics Department. . Carleton University F = {A+B+C} F = {A+B+C}·{A+B } F = {A+B}+(C·{ A+B }) Printed. +. . ’01 Modified. . .·. March 19.) = F(A. ·. .B.C.Glitches and Hazards in Digital Circuits DeMorgan’s General Theorem (Review) DeMorgan’s General Theorem (Review) Simple form of DeMorgan’s Theorems A·B = A+B A·B = A+B D+E = D·E D+E = D·E The general form F(A. . ’97 9 . November 1.C.B.

March 19. ’97 10 . F = XB + XA AB X 00 01 11 10 0 0 1 1 0 1 0 0 1 1 Circling the “1s” on the map gives an implementation of F. ’01 Modified. F ={X·B} + { X·A} {X + B}·{ X + A} F = {X + B}·{ X + A} The result is the Π of Σ expression for F. It was obtained by circling “0s”.Glitches and Hazards in Digital Circuits Product of Sum ( Π of Σ) Maps (Review) Product of Sum ( Π of Σ) Maps (Review) Take the usual Σ of Π map for F. F = X·B + X·A AB X 00 01 11 10 0 0 1 1 0 1 0 0 1 1 Apply generalized DeMorgan to the formula for F F = X·B + X·A This gives a formula for F. Make a map of F by circling the zeros Extract the formula for F. Carleton University Printed. Circling the “0s” gives an implementation of F. November 1.” AB X 00 01 11 10 0 0 1 1 0 1 F = {X + B}·{ X + A} 0 0 1 1 © John Knight Electronics Department. not “1s.

The hazard is X. E + X Gaps between adjacent circles show static-0 hazards. Plot “0s” not “1s. Carleton University Printed.D. March 19. Consider wrap around Masking a Static-0 Hazard on a Π of Σ Map XD E 00 01 11 10 D+E 1 E+X D+E 1 FIG.E = -.0.0. 1-13 1 1 1 D+E D X E D+X E+X hazard F= (D + X)(E + X) (D + E) To mask the static-0 hazard: AND F with a term which stays 0 across the hazard. 1-12 Get Π of Σ implementation. ’97 11 .0. D + X. not AND. XD 00 01 11 10 E D+X D+E 1 D+E © John Knight Electronics Department. ’01 Modified.Glitches and Hazards in Digital Circuits Showing a Static-0 Hazard on a P of S Map Showing a Static-0 Hazard on a Π of Σ Map Π of Σ maps can only show static-0 hazards. November 1. or (D + E). The term which stays 0 across the gap is X.E = 1. not static-1 or dynamic hazards XD E 00 01 11 10 0 1 E+X 1 1 1 1 D+X D X D+X F = (D + X)(E + X) E E+X hazard FIG.D.0.0 to 0.0.” Connect letters with OR.

treat x and x as separate variables. The Distributive Laws x(y + z) = xy + xz x + yz = (x + y)(x + z) © John Knight Electronics Department. They will not remove or create static hazards. even a masked one. Carleton University Printed. avoid the distributive law. delays temporarily make x = x. November 1. ’01 Modified. ’97 12 . March 19. do not use: Complementing xx = 0 x+x=1 Simplification x + xy = x + y (x + y) = xy xy + xy = y (x + y)(x + y) = y Multiplying Out (x + y)(x + z) = xz + xy xy + xz = (x + z)(x + y) Consensus xy + yz + xz = xy + xz (x + y)(y + z)(x + z) = (x+y)(x + z) For work with dynamic hazards. In hazards. In algebra with hazards. Algebra and Hazards.Glitches and Hazards in Digital Circuits Algebra and Hazards. For work with hazards. (Factoring) The distributive laws can create dynamic hazards from static hazards.

November 1. 1-15 x c FIG. Carleton University Printed. ’97 13 . 1-14 x Static-0 xx x Dynamic xx + x x Static-1 x+x x Dynamic (x + x )x An Example Below. ’01 Modified. c x Static-1 hazard cx + x FIG. x and x are treated as separate variables. FIG. March 19. the equation of the circuit will reduce to one of these forms. get (0 + x)x0 = 0 There are no hazard © John Knight Electronics Department. get (1 + x)x1 = x When c = 0. If a circuit has a hazard. 1-16 No Hazard (c + x )xc Circuit equation is cx + x when c = 1 get 1x + x = x + x The hazard is “exposed” Circuit equation is (c + x)xc When c = 1. a hazard in x must reduce to a basic hazard circuit when c=1 or when c=0.Glitches and Hazards in Digital Circuits Algebra of Hazards Algebra of Hazards The basic forms for hazards and their equations.

FIG. and thus may create a dynamic hazard from a static one. Carleton University Printed. 1-17 bottom). ’97 14 . CIRCUIT AFTER APPLYING DISTRIBUTIVE LAW x c (0 + x )(x + x) = x(x + x)Dynamic hazard when c = 0 x c Masked Hazard xc(c + x ) When c=1 x1(1 + x ) = x = x c xc + xcx x1 + x1x = x + xx Dynamic hazard when c = 1 © John Knight Electronics Department. November 1.Glitches and Hazards in Digital Circuits The Distributive Law and Hazards Algebra of Hazards The distributive laws can change 2 parallel paths into 3. 1-17 The distributive law changing static hazards to dynamic hazards. ’01 Modified. ORIGINAL CIRCUIT c x Static-1 hazard xc + x When c=1 x + x = (c + x )(x + x) (1 + x )(x + x) = x + x Static-1 hazard when c = 1. They can create a dynamic hazard from a masked hazard ( FIG. March 19.

Find masking terms if needed. Need both X and X 3. Method 1. ’01 Modified. (A + B) + A·C => A·B + (A + C) 2. March 19. X + X. Select one variable for checking make other variables 1 or 0 to bring out hazard 4. X·X. Remove confusing extended overbars. • The circuits do not need to be Σ of Π or Π of Σ. F = (a + b + cb)de + (ea + db)c • Much faster than maps. and dynamic. X + X·X AX + (BX + C) 1X + (1X + 0) X + X © John Knight Electronics Department. 2.Glitches and Hazards in Digital Circuits Method Locating and Repairing Hazards Algebraically • This method will find all hazards static-1. static-0. 1. Carleton University Printed. It will find all types of hazards on one pass. 3. ’97 15 . Check for hazards in each variable. Find which variables cannot have hazards. • It can also find how to mask them. November 1.

Carleton University Printed. Example Find All The Hazards In F.Glitches and Hazards in Digital Circuits Find All The Hazards In F. November 1. ’97 16 . ’01 Modified. March 19. b c a d F © John Knight Electronics Department.

using DeMorgan’s theorem. NAND and NOR. Carleton University 17 . 1-18 Find All The Hazards In F. OR. ’97 © John Knight Electronics Department. ’01 Modified. A·B A B AND = C C = A B A+B AND C D E D+E OR = F F = D E D·E OR F G·H G H NAND FIG. 1) Select alternate levels starting at output. 2) Transform gates 3) Cancel back-to-back inverting circles 4) Result F = (a + c)(b + c) + cd Printed. Equivalent graphical forms for AND. March 19. November 1. 1-19 = K K = G+H G K NAND H D+E D E NOR = F F = D·E D NOR E F Removing confusing inversions.Glitches and Hazards in Digital Circuits DeMorgan’s Laws in Graphical Form (Review) FIG.

One path must have an even number of inversions. Carleton University Printed. Find All The Hazards In F. Can also tell from expression. 1-20 To tell what variable need to be checked for hazards: Remove most inverting circles using DeMorgan’s laws. A hazard. Only variable c has such a path. FIG. and the other path must have an odd number. Only c has both c and c type b c a d b c a d F = (a + c)(b + c) + cd F F © John Knight Electronics Department.Glitches and Hazards in Digital Circuits Estimating which variables might have hazards. ’01 Modified. Check for reconvergent paths one of which is inverting. hence only c can have a hazard. One need only check for hazards in variables which have such paths. ’97 18 . has two paths which reconverge in an AND or OR gate. November 1. Checking a circuit for potentially hazardous paths. March 19.

F = (a + c)(b + c) + cd 2. a.0. Static-0 Dynamic Static-1 c c c c c c c c 0 1 1 0 0 1 1 0 cc cc+c c+c c c c+c 1+c 1 Static-0 hazard when Dynamic hazard when Static-1 hazard when a.1. b and d. © John Knight Electronics Department.1.d = 0.b. a bc d 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 (a + c) (b + c) + cd (0 + c) (0 + c)+c0 0 + c 0 + c c1 0 + c 1 + c c1 0 + c 1 + c c0 1 + c 0 + c c0 1 + c 0 + c c1 1 + c 1 + c c1 1 + c 1 + c c0 f Type of hazard. Take the circuit equation. 3.1. => only c needs to be checked.d = 0.d = 0. cc + c. Try to get forms like: cc. c + c. a. November 1. Substitute 0s and 1s for the other variables.0.b.b.Glitches and Hazards in Digital Circuits Locating Hazards From the Circuit Equation Locating Hazards From the Circuit Equation 1. In this case a. (c + c)c. Carleton University Printed. March 19. ’97 19 . Note which variables do not have both x and x. ’01 Modified.0.

0 1 cd 0 1 c1 0 0 cd 0 0 c0 0 0 c1 = c+c Static-1 for 0 1 c 1 try b = 0 = c(0 + c)+ cd = c·c + cd d may be 0 = c·c + c0 = c·c or d may be 1 = c·c + c1 = c·c + c a 1 0 1 Static-0 for 0 0 c 0 Dynamic for 0 0 c 1 c d 0 1 0 b 0 c+c c·c c·c + c Printed. or no c. a bcd a b cd 0 bcd (a + c)(b + c) + cd (a + c)(b + c)+ cd (0 + c)(b + c)+ cd try b = 1 d must be 1 a must be 0. November 1. F = (a + c)(b + c) + cd Note only c can have a hazard. Carleton University 20 .b. ’01 Modified. ’97 d 1 © John Knight Electronics Department.c.d. else a + c = 1 => no c => no hazard Set a = 0 first. Sequentially substitute 1 or 0 for the other letters. A little thought shows a must be 0. = c(b + c)+ cd = c(1 + c)+ cd = c + cd = c + c1 a.Glitches and Hazards in Digital Circuits Same Example With More Organization and Same Example With More Organization and Less Writing Equation. March 19. Select c to to be the variable that changes.

’97 21 .1. or F ≡ 0 d must be 0 or no b Static-0 for 0 b . = [a·0+ a1]a = a·a Static-0 for a100 or d may be 1 = [a·1+ a0]a = a·a Static-0 for a101 a bcd a 1 cd a1 0d a 10 0 a 10 1 a bcd 0 bcd 0 bc 0 a b cd 0 1 cd a bc d 0 1 cd © John Knight [ (a + bc)d +(b + ac)d]ab [ (0 + bc)d +(b + 0c)d]1b = [ bcd + b·d ]b [(bc0 + b1]b = [b]b [ (a + bc)d +(b + ac)d]ab = [ (0 + 1c)d +(0 + 0c)d]11 = [ cd ] [ (a + bc)d +(b + ac)d]ab = [ (0 + 1c)d +(0 + 0c)d]11 = [ cd ] Electronics Department. a. More Complex Exmple Equation. ’01 Modified. or F ≡ 0 [ (a + 1c)d +(0 + ac)d]a1 = [(a+c)d+ ac·d ]a c.b must be 1. Here all variables need further checking. Sequentially (one at a time) substitute 1 or 0 for the other letters. or no a set c = 0 = [(a+0)d+ a1d ]a= [a·d+ ad]a d may be 0 .0 This hazard is independent of c. November 1. Select one letter to to be the variable that changes. a bcd [(a + bc)d + (b + ac)d ]ab [ (a + bc)d +(b + ac)d]ab b must be 1. F = [(a + bc)d + (b + ac)d ]ab Note which variables do not have both x and x.Glitches and Hazards in Digital Circuits Locating Hazards. or F ≡ 0 There is no c. must be 0.1. hence no hazard Printed. hence no hazard a.b must be 1. Carleton University a must be 1. March 19. A little thought helps select which letter to make 1 (or 0) first. More Complex Exmple Locating Hazards. or F ≡ 0 There is no d.

March 19. ’97 22 .Glitches and Hazards in Digital Circuits Graph of the previous hazard search F = [(a + bc)d + (b + ac)d ]ab [(a+c)d+ ac·d ]a [a·d +ad]a 0 1 a b 1 0 c d 0 1 a·a a·a [ bcd + b·d ]b [(bc0+ b1]b 0 1 b a 0 1 d c 0 1 b·b b·b c a 0 1 b 1 0 [cd] d 0 1 d a 0 1 b 1 0 [cd] c 0 1 © John Knight Electronics Department. November 1. ’01 Modified. Carleton University Printed.

Example three Equation. If all Xs have a common factor.1. no y => No hazards in y. b(c·X + a·c·X) + a·c·X·y c must be 1 or no X a bce y y(e + b·c) + b(c·e + a·c·e) + a·c·e·y y(e + b·c) + b(c·e + a·c·e) + a·c·e·y y(e + b·0) + b(1·e + a0e) + a1e·y = y·e + b·e + a·e·y y(e + b·c) + b(c·e + a·c·e) + a·c·e·y 1(0 + b·1) + b(0·1 + a·1·0) + a·0·1·0 = b + 0 y(e + b·c) + b(c·e + a·c·e) + a·c·e·y y(0 + b·c) + b(c·1 + a·c·0) + a·c·1·y = y·b·c + b·c + a·c·y = 1·1·c + 0·c + a·c·0 y(e + b·c) + b(c·e + a·c·e) + a·c·e·y y(e + b·0) + b(1·e + a·0·e) + a·1·e·y = y·e + be + a·e·y = 1e + be + a·e·0= e + be = e+e y(e + b·c) + b(c·e + a·c·e) + a·c·e·y y(0 + b·0) +b(1·1 + 0·0·0) + 1·1·1·y = b + y c must be 1.1 or no X. F = y(e + b·c) + b(c·e + a·c·e) + a·c·e·y Select one letter.1 or no b.1 or no c no c => No hazards.Glitches and Hazards in Digital Circuits Locating Hazards. If only one X. have no haxards.1.e.0. set symbols ANDing X at 1. call it X. e must be 1 or no c.y to 1. set all symbols ANDing X to 1.e to1. y·b must be 1. to to be the variable that changes.1 or no X If only one X. a bce y a b 1ey a bce y a b 010 a b ce y a b c1 y a 0c 01 a b ce y a b 1e y a b 1e 0 a 11e 0 a b ce y 1 b 11 y © John Knight Electronics Department. y(e + X·c) set c. or no a no a => no hazards in a c.y must be 1. March 19. Carleton University Printed.e. c must be 1 or no e y must be 1 or no e b must be 1 Static-1 for a11e0 a. no b => no hazards in b. ’01 Modified.c.1 or no y. + a·c·e·X set a. fix factor at 1. November 1.0. Example three Locating Hazards.c. Variables which do not have both forms.e must be 1. and ORing X at 0. X and X. ’97 23 .

Glitches and Hazards in Digital Circuits Graph of the previous hazard search F = y(e + b·c) + b(c·e + a·c·e) + a·c·e·y a e 1 0 no a no a b c 0 1 e no b 1 0 y no b 0 1 no b c e 1 0 y 1 0 b 0 1 no c e c 1 0 y 0 1 b 1 0 e+e y a 1 0 c 1 0 e 1 0 no y © John Knight Electronics Department. ’01 Modified. ’97 24 . March 19. Carleton University Printed. November 1.

’01 Modified. ’97 25 . November 1.Glitches and Hazards in Digital Circuits Masking Hazards Mask a static-1 with an AND gate. the function is 1 in those two squares Mask it with a function which is guaranteed 1 in those two squares 0 elsewhere That function is G = AB . March 19. Carleton University Printed. 1-21 AB X 00 01 11 10 0 0 1 1 0 1 Masking a static-1 AB X 00 01 11 10 0 0 0 1 0 1 0 0 1 1 0 0 1 AB 0 G X A A X AX AX + BX B BX AX G BX + AX + G B BX © John Knight Electronics Department. FIG. A hazard is between two squares Since hazard is static-1.

1 G=0 anywhere else. F is 1.1. c+c The hazard appears when a. elsewhere F + 0 = F there. cd ab a 00 01 11 10 00 01 d 11 10 c.b.1.Glitches and Hazards in Digital Circuits Masking Hazards Algebraically Masking Hazards Algebraically Expression F = (a + c)(b + c) + cd c+c Static-1 for 0 1 c 1 c·c Static-0 for 0 0 c 0 c·c + c Dynamic for 0 0 c 1 Masking the static-1 hazard. November 1. March 19. but F actually has a hazard Define G: G=1 when a.b. Carleton University Printed. ’97 26 . F+G=F Since when G is 1.d = 0. ’01 Modified.1 and c F was designed to be “1” there.d = 0. cd 00 ab 00 0 0 0 0 01 0 1 1 0 b 11 0 0 0 0 10 0 0 0 0 G 01 11 10 But F + G is solidly 1 over the hazard. Desired G = abd ab 00 cd 00 F 01 F 11 F 10 F F F F F+G 01 11 10 F F F F=1 F F=1 F F F F with c+c masked is F + G = F = (a + c)(b + c) + cd + abd Expression F = (a + c)(b + c) + cd © John Knight Electronics Department.

’97 27 . 00 01 c. November 1. d 11 10 b cd 00 ab 00 0 1 1 0 01 1 1 1 1 11 1 1 1 1 10 1 1 1 1 H 01 11 10 But F·H is solidly 0 over the hazard.b.d = 0. Carleton University Printed.Glitches and Hazards in Digital Circuits Expression Masking Hazards Algebraically F = (a + c)(b + c) + cd c·c Static-0 for 0 0 c 0 cd ab a 00 01 11 10 Masking the static-0 hazard.0 and c F was designed to be “0” there.b. March 19. c·c The hazard appears when a. F is 0. elsewhere F·1 = F there. F·H = F Since when H is 0. but F actually has a hazard Define H: H=0 when a.0 H=1 anywhere else.0.0.d = 0. ’01 Modified. ab 00 01 cd 00 F=0 F 11 F F F F 10 F F F F F·H Desired H = (a+b+d) 01 11 F F F F F F with cc masked is F·H = F = (a+b+d((a + c)(b + c) + cd) Note it could have been masked as (a+b)(a + c)(b + c) + cd 10 F=0 © John Knight Electronics Department.

November 1.Glitches and Hazards in Digital Circuits Masking Both Hazards at Once Masking Both Hazards at Once Combining the masks for static-1 and static-0 F with both cc and c+c masked is F = (a+b+d) (a + c)(b + c) + cd] + abd [ Prove that the static hazards are both masked. a b c d 0 0 0 0 0 0 1 1 c c c c 0 1 1 0 (a+b+d)((a + c)(b + c) + cd) + abd 0+0+0 0+0+1 0+1+1 0+1+0 (0 + c (0 + c (0 + c (0 + c 0+c 0+c 1+c 1+c c0) c1) c1) c0) 100 101 111 110 F 0cc cc+c 1 c Type of hazard. No more hazard Dynamic No more hazard © John Knight Electronics Department. March 19. Carleton University Printed. ’97 28 . ’01 Modified.

for a.b=0.Glitches and Hazards in Digital Circuits Masking Dynamic Hazards. © John Knight Electronics Department.b=0. November 1. March 19. cc + c cd Extract the Static Hazard Cannot hold F constant over a. cc + c ab a 00 01 11 10 Masking Dynamic Hazards. ’97 29 .0. F = f1 + cd = f1g1 + cd = (a + b){(a + c)(b + c)} + cd cd ab a 00 01 11 10 00 f1 01 11 10 0 1 d b This F has masked the embedded static hazard and thus the dynamic hazard. F = f1 + cd f1 has a static hazard in c when a.0.b = 0. HoweverA static hazard resides inside every dynamic hazard.b.d = 0.0 Make f1 the part of F with the embedded static-0 hazard. when a.1 Define g1 = 0. Carleton University Printed. ’01 Modified.0 = 1. cc.1 because F changes with c. 00 F 01 11 10 0 1 d b F=(a + c)(b + c)+ cd f1=(a + c)(b + c) this makes static hazard dynamic static-0 hazard. otherwise f1 = f1g1 = (a + b){(a + c)(b + c) has masked the hazard.

b c d 1 0 1 1 1 1 (a + b) {(a + c)(b + c)} + cd + abd (a +1) (a +1) {(a + 1)(1 + 0)} + 01 + a11 {(a + 0)(1 + 1)} + 11 + a11 F 1 1 Type of hazard. As a check.Glitches and Hazards in Digital Circuits Masking Dynamic Hazards. ’01 Modified. cc + c Masking does not introduce new hazards? Were new hazards introduced because a and a now appear in F? This will not happened. No hazard No hazard © John Knight Electronics Department. Carleton University Printed. consider a. ’97 30 . November 1. March 19.

Table to expose hazards in b with a fixed. November 1. No hazard Static-1 hazard © John Knight Electronics Department. ’97 31 . Carleton University Printed.Glitches and Hazards in Digital Circuits An Example of Locating Hazards An Example of Locating Hazards Find all the hazards in FIG. 1-22. a 0 1 a(a + b) + b(a + b) + ab 0(1 + b) +b(1 + b) +0b 1(0 + b) +b(0 + b) +1b F b b + bb + b Type of hazard. Write circuit equation. ’01 Modified. a f b f a b b) a) Residual inverters are better at the inputs. a f b f a b c) Cancel inverters using DeMorgan’s law graphically. March 19. FIG. F = a(a + b) + b(a + b) + (a + b) Potential hazards in both a and b. 1-22 Circuit with a lot of paths for potential hazards.

24 bb b+b Ideally they cancel Realistically.” A rising glitch b+b is ORed with a falling glitch bb. ’97 32 . Carleton University Printed. ’01 Modified.Glitches and Hazards in Digital Circuits Explanation of b + bb + b FIG. only the static-1 appears This could even be a “glitch inside glitch. With very good luck the two glitches to come exactly at the same time and cancel. changes in “a” have the same behavior. November 1. © John Knight Electronics Department. March 19. Only the falling glitch will appear. From symmetry. More likely the rising glitch will be lost in the static 1 signal. 1-23 An Example of Locating Hazards Explanation the weird hazard FIGURE 1.

. . . November 1.Glitches and Hazards in Digital Circuits Sum-of-Product Circuits Have No Static-0 Implementing Hazard Free Circuits Sum-of-Product Circuits Have No Static-0 Hazards Sum of products circuits always have an equation of the form F = abc + abd + abcd + .+ abcd Static-0 hazards are like cc. . c Σ of Π implementations have no static-0 hazards. ’01 Modified. March 19. ’97 33 . . Carleton University Printed. © John Knight Electronics Department. { c + c is static-1} To get cc in F as above on must place c and c as inputs to the same AND gate. Rule I: a Except for the gross carelessness of including terms like acc. . This is ignorant.

Carleton University Printed. . ’01 Modified. ’97 34 . . In F above. . November 1. In F.Glitches and Hazards in Digital Circuits Sum-of-Product Circuits Have No Dynamic Hazards Σ of Π circuit have equations of the form F = abc + abd + abcd + . a Σ of Π implementations have no dynamic hazards. must have a term containing cc. Thus Rule II is: Except for the gross carelessness of including terms like acc. March 19. . try fixing a. . c © John Knight Electronics Department.+ abcd + abccd Dynamic hazards are of the form cc + c or (c+c)c. A dynamic hazard in c. one can only get a dynamic hazard by using the “ignorant” term abccd. b and d at any combination of 0 or 1. .

.Glitches and Hazards in Digital Circuits Sum-of-Product Circuits Have Only Easily Sum-of-Product Circuits Have Only Easily Eliminated Static-1 Hazards Σ of Π circuits can still have static-1 hazards They are easily found and removed using: a Karnaugh map. Hazard when a. ’97 ax © John Knight Electronics Department. November 1. 1-25 Map of function F = bx + ax It is Σ of Π The hazards must all be static-1. March 19. ab x 0 1 00 01 0 0 11 10 0 ab x 0 bx 0 00 01 11 10 0 0 bx ab ax Printed.1. ’01 Modified. FIG. Carleton University 35 . Add term ab to mask the hazard. or algebraically. F = bx + ax + ab Is shown on the right.b = 1.

)(a+b+c+d) Static-1 hazards are of the form c + c. c Product-of Sum Circuits Have No Dynamic Hazards Except for the gross carelessness of including terms like acc. c Product-of Sum Circuits Have Only Easily Eliminated Static-0 Hazards Π of Σ circuits can still have static-0 hazards They are easily found and removed using a Π of Σ Karnaugh map © John Knight Electronics Department. . This is ignorant. . .Glitches and Hazards in Digital Circuits Product-of Sum Circuits Have No Static-1 Product-of Sum Circuits Have No Static-1 Hazards Π of Σ circuit equations are of the form F = (a+b+c)(a+b+d)(a+b+c+d)( . . a Π of Σ implementations have no static-1 hazards. November 1. March 19. Except for the gross carelessness of including terms like a+c+c. Carleton University Printed. To get c+c in F one must place c and c as inputs to the same OR gate. a Π of Σ implementations have no dynamic hazards. . ’01 Modified. ’97 36 . .

1-26(left). is - F = a·b + b·c + b·d + a·c + a·d FIG. ’97 37 . March 19. Choose a circling for the map. cd ab 00 01 11 10 00 01 11 10 ab 00 01 11 10 00 0 0 01 b·cd 0 ab b·cd cd 11 10 bc 0 ab 00 01 11 00 0 0 1 0 01 cd 11 10 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 ad 1 0 1 0 1 0 1 1 1 ac 1 1 bc 1 10 1 F = a·b + b·c + b·c·d F = a·b + b·c + b·c·d + a·c + a·d © John Knight Electronics Department. The hazard free equation. see FIG. FIG. 1-26(right). FIG. F = a·b + b·c + b·c·d Then add circles which cover the arrows. Right) The map with the hazards covered. Centre) A possible Σ of Π encirclement showing hazards.Glitches and Hazards in Digital Circuits Product-of Sum Circuits Have Only Easily Example: Single-Variable-Change Hazard-Free Circuit From a Map A digital function defined by a map. ’01 Modified. Carleton University Printed. indicate the hazards. 1-26 (middle). November 1. on this final map. 1-26 Left) Example to be implemented as a hazard free circuit.

12 2. Algebraic operations do not create hazards unless they make x interact with x. Except the distributive laws can convert static dynamic hazards.) 3. Carleton University Printed. DeMorgan’s law has no effect on hazards. March 19. The distributive laws cannot create or destroy static hazards. ’01 Modified. November 1. 4. 1-27 Distributive Laws Normal Law (a + b)x = bx + ax ab + x = (a + x)(b + x) Special For Boolean Only © John Knight Electronics Department. ’97 38 . They can even convert masked hazards dynamic hazards.." p. FIG.Glitches and Hazards in Digital Circuits Factoring and Hazards For Σ of Π / Π of Σ Factoring and Hazards For Σ of Π / Π of Σ 1. See "Algebra and Hazards.

’01 Modified.c.Glitches and Hazards in Digital Circuits Example: hazard free expression from last page. u=>b 3 parallel paths u = (a + b)(c + d) b a c d u a F Dynamic hazard when a=0.0. c or d =1 F => (0 + b)(b + b) We can still guarantee no static hazards u = (a + b)(c + d) Using Forbidden Algebra That May Insert Hazards F = a·b + b·c + b·d + a·c + a·d = a(b + c + d) + b(c + d) = a(b + c + d) + b(b +c + d) = (a + b)(b + c + d) Static-0 when a. F = a·b + b·c + b·d + a·c + a·d Factoring and Hazards For Σ of Π / Π of Σ Factoring (uses the distributive law) reduces parallel paths. Carleton University F = (a + u)(b + u) Using bb = 0.0 © John Knight Electronics Department. (don’t do that!) Printed.d= 0. Use xc + xd = x(c + d) F = a·b + b·(c + d) + a·(c + d) = a·b + (a + b)(c + d) = a·b + u No dynamic hazards (or static) Multiplying out (also uses distributive law) creates parallel paths Use ab + x = (a + x)(b + x) F = a·b + u F = (a + u)(b + u). ’97 39 . March 19. November 1.

Carleton University Printed. Some 2-change hazards are maskable. ’01 Modified. (lower arrow) l X AB00 01 11 10 0 BX BX 0 0 AX FIG.0.X =1. A masking term AB can cover the valley. 1-28) Many 2-variable hazards are not maskable. It only removes the glitch on the upper path. move two squares on the Karnaugh map.0 (the tail of the arrows) Change both B and X to move to square A. November 1. The valley between AX and BX may glitch.1. ’97 40 .Glitches and Hazards in Digital Circuits Two-variable-change hazards Hazards With Multiple Input Changes Two-variable-change hazards Two-variables changes. A X BX AX F AX + BX + BX B BX © John Knight Electronics Department. 1-28 0 1 Start at square A. one takes the lower path . Covering the offending “0” changes the function. March 19. one travels the upper route .X =1.1 (the head of the arrows).B. If X changes slightly before B. This will always glitch. It cannot be covered. (upper arrow in FIG.B. If B changes slightly before X.

November 1. Another 2-variable function hazard. 0 1 Maskable. Double-Variable Hazards See a little later © John Knight Electronics Department. X AB00 01 11 10 0 BX BX 0 0 AX 0 1 Associated Maskable.1. static-1. ’97 41 . If A changes first (long path) there is a glitch. single-variable. If B changes first (short path) there is no glitch.0. One cannot fill in the “0” to mask the hazard. ’01 Modified.Glitches and Hazards in Digital Circuits Nonmaskable or function hazards X AB00 01 11 10 0 BX BX 0 0 AX Two-variable-change hazards 0 1 The lower arrow goes through a “0. Single-Variable Hazards X AB00 01 11 10 0 BX 0 0 AB AX F= AX + AB +BX When AB=10 => F = X + X When AX=11 => F = B + B Maskable. It is a nonmaskable or function hazard.B. F is supposed to be low for input A.X=1. Carleton University Printed. March 19. hazards.” This “0” is part of the function.

If both detectors respond at the same time. Cosmic rays from outside will activate both detectors. 1-29 B A 0 1 00 01 0 AB A B F Suppose one AND gate is slower than the other. November 1. the result is ignored. There is a detector on each side of the duct. Then the cosmic ray pulses will not cancel exactly because of the two-variable hazard. The rejection circuit uses an XOR which has a 2-variable hazard. ’97 42 . ’01 Modified.Glitches and Hazards in Digital Circuits Example of a 2-Variable Change Hazard Two-variable-change hazards Detect the decay of radon passing through a long thin air duct. March 19. Carleton University Printed. A radon decay inside the duct will activate one detector. One cannot reliably exclude the double pulses with XOR. FIG. AB 0 RAYDON DECAY COSMIC RAY A AIR B AB F May Cancel Won’t Cancel DETECTOR A DETECTOR B AB + AB AB Recall A⊕B = AB + AB © John Knight Electronics Department. Moreover one cannot mask the hazard without losing pulses generated by radon decay.

c + c. November 1. that may be travelled through. . 2) Condition for no maskable hazards Fixing the stationary variables cannot reduce F to one of the forms P=2 AB CD P=3 10 AB CD 00 01 11 00 01 11 10 00 01 11 10 00 0 0 0 0 01 11 10 1 1 1 1 1 1 1 1 a + a. if and only if: 1) Condition for no function hazards All 2P squares. © John Knight Electronics Department. aa. ’01 Modified. cc. ’97 43 . . Conditions to be Hazard Free F is free of multiple-variable static hazards for the P changes. have the same value. March 19.b. 2P AB CD P=2 00 01 11 10 CD AB P=3 00 01 11 10 00 01 11 10 00 01 11 10 For static hazards F has the same value before and after the changes.c. .).Glitches and Hazards in Digital Circuits General Multiple Variable Changes General Multiple Variable Changes Definition of Static Multivariable Hazards Consider a function F(a. aacc. Carleton University Printed. c+c +aa. . There are squares through which this P variable transition may travel. or combinations of these like a+a + c+c. Let P of its variables change at the same time.

P = 2 = numper of variables changing at once. as shown. Carleton University Printed. ’01 Modified. There are no hazards for any of the transitions. If other pairs.0.0 ->1. The direct path will cross the gap and give a glitch. a function hazard results.1 Transitions can move over 2P =4 squares. such as A and D change. A and C.B = 0.0 -> 1. If the transition via the “wrap around. ’97 44 .=. November 1. is a hazard.1.Glitches and Hazards in Digital Circuits Example: A Double Change With No Hazard Two variables changing A. The possible transitions cover 2P = 4 squares. General Multiple Variable Changes Start End Squares in path AB CD 00 00 01 11 10 P=2 01 11 10 1 1 1 1 Example: A Function Hazard Two variables changing A.” has no hazard. AB CD 00 00 01 11 10 01 11 10 1 1 1 1 1 Example: Maskable Hazards Any transitions between the centre variables.C. March 19. A change AB CD 00 01 00 01 11 10 11 10 A change AB CD 00 01 00 01 11 10 11 10 C change D change © John Knight Electronics Department. The hazards can be masked by covering the centre four squares as shown on the right.

The equation for the function is F = AB + ABD + CD + BCD Fix BD = 11 to expose the hazard. ’01 Modified. ’97 45 .Glitches and Hazards in Digital Circuits Example. F=A+A+C+C This is a static-1. It may give a glitch when A and C both change at once. March 19. A Real Two-Variable Maskable Hazard General Multiple Variable Changes There is a “hole” in the centre. two-variable hazard. A change CD AB 00 01 11 10 00 01 11 10 C change Example: A Nonmapable Two-Variable Maskable Hazard This hazard cannot be mapped onto Σ of Π F=BA + AD + C(C + B) Set BD=11 F= A + A + CC CC A+A © John Knight Electronics Department. Carleton University Printed. November 1.

’01 Modified.Glitches and Hazards in Digital Circuits Multiple Variable Change Hazards are Plentiful When Are Hazards Important? Multiple Variable Change Hazards are Plentiful Take a synchronous circuit Let 4 flip-flops change at once. Most paths will have function hazards FIG. 1-30 The vast number of glitches generated by multiple variable changes CLK DA DA DA DA C1 1D 1D 1D 1D A B C D COMBINATIONAL LOGIC AB CD 00 00 01 11 10 01 11 10 P=4 2P=16 GLITCH HEAVEN A few of the possible paths for 4-variable changing With 2 variables changing it is almost impossible not to have hazards. With more variables changing they are like waves in the ocean. November 1. Carleton University Printed. March 19. © John Knight Electronics Department. ’97 46 . Then P=4. 2P=16 possible map squares.

1-31 The flip-flops only respond in the circled region on the waveforms below.Glitches and Hazards in Digital Circuits Hazards do not hurt synchronous circuits Hazards do not hurt synchronous circuits In clocked logic. All variables change shortly after the clock edge. The clock cycle is made long enough so the glitches die out long before the clock edge. INPUT CLOCK D INPUT CLOCK Q1 D2 Q2 D3 Q3 1D C1 Q1 D2 1D C1 Q2 slow D3 1D C1 Q3 Glitches must die out by setup time © John Knight Electronics Department. See the circles on the waveforms below. ’01 Modified. flip-flops only respond to the inputs slightly before the clock edge. Carleton University Printed. March 19. November 1. ’97 47 . The glitches die out long before the clock edge. The glitches have negligible influence. FIG. A glitch at any other time will not influence state of the machine.

November 1. A glitch may causes a wrong value to be latched.Glitches and Hazards in Digital Circuits Hazards Kill Asynchronous Circuits Hazards Kill Asynchronous Circuits By asynchronous circuits. All hazards must be eliminated. March 19. we mean ones with feedback that can latch signals. or proven harmless. SET S1 1 RESET R Q SET RESET Q Example: Placing an R-S Latch in a Synchronous Circuit FIG. 1-32 The Russian Roulette of digital design CLK GLITCH HEAVEN DA 1D DA 1D DA 1D DA 1D C1 A B C D COMBINATIONAL LOGIC S1 1 R KILLER GLITCH CLK C1 1D 1D 1D 1D © John Knight Electronics Department. ’97 48 . Carleton University Printed. Analog simulation can prove it harmless. ’01 Modified.

The latch has a hazard when D.1. ’97 49 . This glitch can feed back and latch itself. q=1 Q = 1C + C1 Q= C+C C q To mask the hazard Keep Dq =11 across the change in C Q = DC + Cq +Dq D C Q Q = DC + Cq +Dq SET D=1. March 19. November 1.Glitches and Hazards in Digital Circuits Example: The Hazard in the Transparent D-Latch Hazards Kill Asynchronous Circuits The simple form of D-latch (transparent latch) is just a MUX. q=1 Q = 1C + C1 +1 Q= 1 q Hazard-free latch © John Knight Electronics Department. ’01 Modified.q =1. FIG. Carleton University Printed. 1-33 MUX 1D C1 C 1 Q D q 1 1 G1 D Q Q Q = DC + Cq SET D=1.

November 1. An input glitch on the clock edge. Carleton University Printed.Glitches and Hazards in Digital Circuits Outputs where hazards are of concern Outputs where hazards are of concern Some displays are very sensitive to glitches. ’01 Modified. Cathode-ray tube displays will usually show any glitches on their input signals. may be captured a valid CLK input. and are sensitive to glitches. Memories Memory chips are asynchronous latches. Light emitting-diode displays will show slight “ghosts” in dim light. Glitches in asynchronous inputs to synchronous circuits Asynchronous inputs to synchronous circuits must be hazard free. Memory control leads must be glitch free. March 19. DA QA CLK DA C1 1D 1D 1D 1D QA FALSE SIGNAL © John Knight Electronics Department. ’97 50 .

Hazards on the driver-enable lines may turn on two drivers at once. FIG. If one driver is “1” and one “0”. 1-34 A bus with several drivers. This may cause flip-flops or memory cells to change state. A hazard may turn on a second driver. B is high and C is low. a high current will flow. © John Knight Electronics Department. Bus Line En A En B=1 En C=0 En D En 0=off Enable D a) Tri-state Bus driver showing symbolically how the signal is disconnected. Carleton University Printed. Normally only one driver is connected at a time. Below. ’97 51 . ’01 Modified. It causes a dip in the power supply voltage. The glitch shorts the power to ground. 0=off Enable A 1=on Enable B Enable C A short high-current glitch on a bus Normally does not damage the gates (at least in the short term). The “En” (Enable) signal connects and disconnects the driver. November 1.Glitches and Hazards in Digital Circuits Hazards may hurt bus drivers Outputs where hazards are of concern In control circuits for tri-state bus drivers. Only one “En” signals is high at a time. March 19.

FIG. The bus stray capacitance will maintain the bus voltage during the glitch. ’01 Modified. Π of Σ logic (NOR followed by NOR logic) has static-0. These drivers are sensitive only to static-0 hazards. but no static-1 hazards Preferred for bus drivers which connects on En=0. but no static-0 hazards. There is no other bus driver trying to pull the bus the other way.Glitches and Hazards in Digital Circuits Turn-Off Glitches Don’t Bother Bus Drivers Outputs where hazards are of concern Case: Drivers that connect for En = 1. 1-35 A glitch that turns off a driver momentarily does no damage. © John Knight Electronics Department. The bus capacitance will not allow significant change in the bus voltage. A static-1 glitch may puts opposing signals on the bus. Preferred for bus control which connects on En=1. March 19. With no connected driver for a short time. and disconnect (tri-state) for En = 0. Bus Line Bus voltage change from glitch on Enable C Enable C A=1 En B=1 En C=1 En D En 0=off Enable A 0=off Enable B Enable C 0=off Enable D Σ of Π logic (NAND followed by NAND) has static-1. ’97 52 . A static-0 glitch only turns off the “on driver” momentarily. November 1. not static-1. Carleton University Printed.

Simulators normally suppress glitches shorter that a certain duration. A A B A rule of thumb A pulse shorter than the propagation delay of the gate will not pass through it. November 1. © John Knight Electronics Department. it must be long enough to charge the gate internal capacitance. Carleton University Printed. The default duration is the propagation delay of the gate passing the glitch. Propagation Delay B A B Synchronous circuits would have many many glitches except for inertial delay.Glitches and Hazards in Digital Circuits Absorption of Glitches by Gates Absorption of Glitches by Gates Gate Inertia (Inertial Delay) For a fast pulse to propagate through a gate. ’97 53 . ’01 Modified. Otherwise its energy is too small to change the output. Digital simulator software uses inertial delay to keep simulation waveform displays from being a wasteland of glitches. This is called gate inertia or inertial delay. March 19.

Power is used charging and discharging gate capacitances. ’01 Modified. and an xc cw z Masking is not a viable for power saving • Masking gates add extra capacitance.Glitches and Hazards in Digital Circuits Glitches Increase Power Consumption Glitches Increase Power Consumption Power consumption is very important in: circuits run from batteries. Map for z z = xc + cw +xw c xw 00 01 11 10 0 1 w xw s@0 z = xc + cw +xw Map for z with xw stuck-at-zero z = xc + cw +0 c xw 00 01 11 10 0 1 0 0 0 0 xc xw cw 0 0 0 0 0 xc cw 0 Adding the masking gate xw increased circuit capacitance. and hence power consumption from 6 inputs to 9. 1-37 No normal test can find gate xw output stuck-at-0. 1->0 FIG. • Masking glitches creates untestable redundant gates . c A circuit with a masked hazard. Carleton University Printed. 1-36 CMOS uses power only during variable changes. Electronics Department. Most of these are unmaskable. March 19. circuits that have cooling problems. but mega-glitches may happen in a large IC. ’97 © John Knight 54 .c = 1. • Most circuit glitches are multi-variable. x Glitches are known to waste significant power. FIG. November 1.w. This uses more power than the saving by hazard elimination. One glitch uses little power. (50%) Glitch happens only with x. 1.

1-3 ( FIG. moves the glitch from x Rising x to x delay . Falling x 0 0 0 0 At the silicon layout level. With standard cells and field-programmable arrays. 1-38 Basic static-1 hazard circuit from FIG. © John Knight Electronics Department. glitch is eliminated. 1-39 Adding delay. balancing is hard. 1-39 left). November 1. With delays balanced.Glitches and Hazards in Digital Circuits Avoiding Glitches by Balancing Delays Review of Adding Delay to Hazards Glitches Increase Power Consumption Most glitches can be removed by balancing the two paths at the hazard inputs. Carleton University Printed. but it requires good control of propagation delays. ’01 Modified. ’97 55 . x delay 0 0 • Adding too much delay will make the glitch appear on the opposite input edge. FIG. March 19. balanced delays usually suppress glitchs. FIG.

FIG. November 1. FIG. With equal path lengths. glitchs appear. 1-41 CLK DA 1D DA DA DA 1D 1D 1D C1 A B C D AB F CD Clocking the register changes several variables at once.Glitches and Hazards in Digital Circuits Avoiding Glitches by Balancing Delays Take synchronous logic. 1-40 CLK DA 1D DA DA DA 1D 1D 1D C1 A B C D AB Glitches Increase Power Consumption Register clocking gives multiple variable changes. a reconverging signal will have passed through equal (we hope) delays. ’01 Modified. Register outputs all change at once. A tree structure balances delays. Carleton University Printed. TREE(Chopped Dow STRUCTURE © John Knight Electronics Department. March 19. ’97 56 . Unbalanced delays can cause many glitches. With unbalanced delays. CHAIN STRUCTURE C D Balancing the path delays can remove most glitches.

Glitches and Hazards in Digital Circuits Balancing May Not Be Too Hard Glitches Increase Power Consumption • Inertial delay allows balance if the two paths are within a gate delay. (more or less) • A few glitches getting through is not fatal if the objective is power saving. November 1. March 19. © John Knight Electronics Department. Carleton University Printed. ’01 Modified. ’97 57 .

Hazards are important in Asynchronous circuits. May be reducable to single variable change. Don’t mention false-paths. March 19. Carleton University Printed. Latches and flip-flops Pulse catchers Debouncers Memory interface signals High speed displays Bus Control © John Knight Electronics Department. See race-free state assignment in the Section on races and cycles. they are part of the logic. ’97 58 . Hazards are not important in truly synchronous circuits Except for power consumption.Glitches and Hazards in Digital Circuits Glitches Increase Power Consumption Summary Of Hazards Single variable change hazards Can be found and cured. ’01 Modified. November 1. Multiple variable change hazards Can be found Are very plentiful Cannot be cured in general.