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System Generator: The State-of-art FPGA Design tool for DSP Applications

Sparsh Mittal, Saket Gupta, and S. Dasgupta

Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee Roorkee, 247667, India email: {sparsh0mittal, sgrefreshing},,

Abstract- Digital signal processing functions have traditionally been implemented on programmable platform of DSPs. However, as the needs of many computationally intensive applications are outstripping the processing capabilities of DSPs, the use of FPGAs has become very much prevalent. Moreover, the research is ongoing to develop and employ high level design tools, which help shorten the development time required for implementing signal processing solutions using FPGAs. In this paper, we present our methodology of designing the model for a useful communication technique, namely MIMO, using Xilinx System Generator (XSG) and AccelDSP (for supporting XSG). Our approach shows the distinct advantages such as reusability, shorter design times due to fewer bugs, which such tools offer. We also review the relative merit of FPGA over DSPs as platforms for DSP implementation. We survey state-of-art applications of FPGAs for DSP applications such as MIMO and digital electronics. As a design tool for FPGA, special emphasis is on the advantages and limitations of Xilinx System Generator as choice of efficient design tool is very crucial decision. An already large user base of Matlab and Simulink along with System Generators own superior performance makes it an increasingly preferred choice of many DSP engineers of today.

Keywords Digital Signal Processing, FPGA, DSP processor, Xilinx System Generator, .MIMO

Recently, Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms suited to Digital Signal Processing applications. Field-programmable gate arrays (FPGAs) are nonconventional processors built primarily out of logic blocks connected by programmable wires. Each logic block has one or more lookup tables (LUTs) and several bits of memory. As a result, logic blocks can implement arbitrary logic functions (up to a few bits). Therefore FPGAs, as a whole can implement circuit diagrams, by mapping the gates and registers onto logic blocks. With more than 1,000 built-in functions as well as toolbox extensions, MATLAB is an excellent tool for algorithm development and data analysis. An estimated 90% of the algorithms used today in DSP originate as MATLAB models. Simulink is a graphical tool, which lets a user graphically design the architecture and simulate the timing and behavior of the whole system. It augments MATLAB, allowing the user to model the digital, analog and event driven components together in one

simulation. Using Simulink one can quickly build up models from libraries of pre-built blocks. Xilinx System Generator (XSG) for DSP is a tool which offers block libraries that plugs into Simulink tool (containing bit-true and cycle-accurate models of their FPGAs particular math, logic, and DSP functions). The AccelDSP tool allows DSP algorithm developers to create HDL designs from MATLAB and export them into System Generator for DSP. This paper surveys the features and application domains of FPGAs in digital signal processing. The emphasis is on providing example of advantages of high level design tool such as System Generator for FPGA design. The rest of the paper is organized as follows. Section 2 provides a comparison between FPGA and DSP processors for DSP implementation. In section 3, we highlight many application areas of FPGAs. Section 4 summarizes design options available for FPGA design and introduces System Generator. Section 5 demonstrates our approach for building a MIMO system using the tools XSG and also gives many insights into the design procedure. In section 6, we survey evaluations on performance and efficacy of System Generator as a premier tool for DSP algorithms and we also highlight its advantages and limitations. In section 7 we cover a small part of emerging research in applications of FPGA in the field of MIMO, digital electronics etc. Finally, section 8 presents the conclusions.

Presently two primary platforms for implementation of DSP functions are: DSPs and FPGAs. DSPs are specialized form of microprocessors, while the FPGA is a form of highly configurable hardware. Here we briefly review the advantages of FPGA over DSPs. The primary reason most engineers choose an FPGA over a DSP is driven by the MIPS requirements of an application. The shift towards FPGA today is motivated by the emergence of innovative technologies like MIMO that utilize complex DSP algorithms (figure 1). Such high performance and complexity requirements call for the massive parallel processing capabilities inherent to FPGA. Furthermore, the FPGAs ability to deliver

unmatched design flexibility to help adapt to changing standards and time to market make it the best choice where early implementation of evolving standards is a strategic imperative. Even novices in FPGA design can easily implement and validate FPGA-based DSP designs by using model-based design tools and methodologies which have greatly simplified the whole design [1]. As many of its features demonstrate, an FPGA is a more native implementation for most digital signal processing algorithms.

changing standards and needs. In addition, the complex nature of many of the signal processing algorithms better suits a DSP processor design: it is much easier for a DSP device to change the processing algorithm on-the-fly by calling a different software routine. Although modern FPGAs can be reconfigured quickly, to achieve this dynamically while continuing to process data is a complex and challenging task [4]. To answer to the needs such as hand-held devices, some next generation high-performance DSPs are incorporating power management techniques. This allows overall system power dissipation to be reduced during times of low traffic or to prevent over-temperature. However, to achieve similar optimization in FPGA configuration would require greater development efforts.


Figure 1The need for a shift to FPGAs to cope up with the increasing complexity (from [1])

Ref. [2] discusses the advantage that FPGAs have due to their product reliability and maintainability which also improves its development process. Since FPGA verification tools are closely related cousins of their ASIC counterparts, they have benefited enormously from the many years of investment in the ASIC verification. The use of FPGA partitioning, test benches and simulation models have made both integration and on-going regression testing very effective for quickly isolating problems, speeding the development process, and simplifying product maintenance and feature additions. Reference [3] compares the development effort and performance of a field programmable gate array (FPGA)-based implementation of a signal processing solution with that of a traditional digital signal processor (DSP) implementation. They have implemented an acoustic array processing task, where several traditional DSP functions found in many applications can be employed. As they note, in terms of timing performance, the FPGA implementation is significantly faster than the DSP. However there is a flip side to it also. DSP processors are highly tailored for efficient implementation of certain common DSP tasks, such as floating point arithmetic. DSP development cost is relatively low, and as a mature technology it can be argued that it has a lower risk and faster timeto-market than FPGAs and other signal processing technologies. Moreover with time, a large community of experienced DSP engineers has also grown, providing a substantial base of design tools, code, debug and optimization tools etc for DSP cores. As DSP algorithms can be readily implemented in an accessible language such as C, it is easier to design it for the scenario of

FPGAs have been put into many practical applications areas such as image processing [5], medical science, as a tool in teaching curriculum to engineering students (such as versatile educational platform for wireless transmission [6]) etc. In the field of digital signal processing, FPGAs have been used widely, for implementation of various algorithms of diverse complexity. Ref. [7] discusses the implementation of an FIR (Finite-Impulse Response) filter with variable coefficients that fits in a single FPGA. In some application of DSP such as Software-defined radio (SDR) [8] the performance depend, not only on latency and throughput but also on speed and energy efficiency. Due to SDRs adaptivity and high computational requirement, an FPGA based system is very viable solution. Reference [9] presents techniques for energy-efficient design at the algorithm level using FPGAs. They apply these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication.

Choosing an appropriate tool for FPGA design is of crucial importance as it affects the cost, development time and various other aspects of design. The initial efforts to generate a hardware netlist for an FPGA target have been to use some form of a Hardware Description Language (HDL), such as VHDL or Verilog, as a behavioral or structural specification. The focus has been shifting, however, from traditional HDLs to higher level languages. Presently, a range of high-level tools and languages for FPGA design are available including: Celoxicas Handel-C a C based parallel language that generates EDIFs; C++ extensions such as SystemC, AccelChips AccelFPGA a Matlab synthesis tool that generates RTL; Xilinxs Forge Java a Java to Verilog

tool, X-BLOX from Xilinx(see also [10]). Annapolis MicroSystems has developed CoreFire which uses prebuilt blocks which removes the need for the back-end processes of the FPGA design flow. Ptolemy [11] is a system that allows modeling, design, and simulation of embedded systems. Ptolemy provides software synthesis from models. However, all these systems are still under development and have their own limitations. 4.1 Xilinx System Generator System Generator [12] is a DSP design tool from Xilinx that enables the use of the Mathworks model-based design environment Simulink for FPGA design. It is a system-level modeling tool in which designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific Blockset. All of the downstream FPGA implementation steps including synthesis and place and route are automatically performed to generate an FPGA programming file. Over 90 DSP building blocks are provided in the Xilinx DSP blockset for Simulink. These blocks leverage the Xilinx IP core generators to deliver optimized results for the selected device. System Generator provides many features such as System Resource Estimation to take full advantage of the FPGA resources, Hardware Co-Simulation and accelerated simulation through hardware in the loop co-simulation; which give many orders of simulation performance increase. It also provides a system integration platform for the design of DSP FPGAs that allows the RTL, Simulink, MATLAB and C/C++ components of a DSP system to come together in a single simulation and implementation environment. Figure 2 presents the design flow of XSG.

System Generator, our program was synthesized very easily. Error-free designs are very easy to make in high level languages such as Matlab where the designers are more likely to have expertise at. Apart from the blocks provided by the standard library, we have also made custom blocks using both MCode blocks (for non-algorithmic code) and AccelDSP (for algorithmic code). This helped us to extend the utility of the XSG tool. An important attribute of our design using AccelDSP was that the blocksets generated in AccelDSP for XSG, are reusable and can be neatly divided into appropriate libraries each containing blocks specific to a certain field such as (for example) ImageProcessingLibrary , MIMOSystemLibrary etc depending on their applications. The MIMOSystemLibrary for example may contain all blocks made by us which are useful in MIMO communication field and so on. Figure 3 shows the library consisting of custom blocks designed by us. MySysGenBlocks library in Simulink Library Browser (encircled) contains blocks used in design of MIMO systems. Another Simulink file, named MyMCodeBlocks contains is the library of blocks made from MCode and gives the user facility to augment the functionality in XSG. The model file of the user named untitled can use blocks from both of these sets also.

Figure 3 A snapshot of user-defined blocks augmenting functionality of XSG


The design of our model has been carried out by one engineer using the GUI design offered by the Xilinx System Generator, with total learning time and development time of less than a month.

The experience of many of the designer using low level languages for FPGA design shows that it is very difficult to write a VHDL code that synthesizes easily, without requiring weeks of time. However, since our approach does not require us to write the actual VHDL directly, but it is generated automatically by the tool

XSG is a relatively new tool and many efforts are going on to explore its features and assess its suitability for practical designs. Reference [10] compares two high level FPGA design tools namely, XSG tool and Streams -C

language and compiler for a BPSK signal detection application (a signal processing algorithm ). These systems are evaluated in terms of their ease of use, the accuracy of their functional simulators, and generated hardware. The values of the percentage of area used and the placement speed are shown and compared. As their results suggest, XSG provides a nice balance between the amount of control capable in the design processes and the advanced design entry and data testing properties one would expect in a high-level tool. This feature will prove to very helpful for the design engineers. Reference [13] compares the design flows from Alteras DSP Builder Version 5.0 and Xilinxs System Generator Version 7.1; describe the strengths and weaknesses of the two different approaches and give a conclusive evaluation. They perform both qualitative and quantitative evaluation based on several parameters. On parameters such as Library Blocks (number, ease of use, availability of useful basic blocks etc) , money (using Cost break even analysis for total cost for a period of 5 years etc), and Quality-of-results (QOR) (size and speed data, number of embedded multipliers with a comparison from hand optimized HDL, compile time) both the tools score even. On features such as Library Organization (ease of finding and proper associations) Simulink Design Support (features such as data type, control signals, pipelining the design and Simulink symbol manipulation for their user-friendliness and amount of time required) XSG is found to be better. However, for issues such as Design Flow Implementation (availability of Synthesis, Fitter and board programming within a single GUI to save time), Development Board Support (availability and support of specific own collection of development boards), the tool from Altera is found to be superior. To compare high level design of Simulink FPGA design flow with hand optimized HDL code, they have evaluated several different examples of common modules. The overall performance data in terms of size and speed has been evaluated for 6 different examples. Overall, both the high level tools give good results. 6.1 The Advantages of System Generator Based on our survey, we found the following advantages of Xilinx System Generator 1. An important feature of XSG is its capability of the bittrue and cycle-accurate simulation for DSP, due to which the user can validate the design before implementing it on hardware. 2. Because it is generic to any Xilinx FPGA device, by simply changing one single parameter the user can compare the results of say, a Virtex-II implementation to that of a Virtex-4 device. 3. The models of any circuit of system developed in XSG can easily be simulated in Matlab, which is one of the strongest arguments of using Xilinx Blockset and the XSG. 4. Synthesis using code generated from the Xilinx model with System Generator is very easy to make, and the





generation of test bench and test vectors is excellent for verifying. With a graphical environment based on Simulink and a pre-defined block set of Xilinx DSP cores, System Generator meets the needs of both system architects who need to integrate the components of a complete design and hardware designers who need to optimize implementations. Efficient GUI for design entry and facility of code reuse, together with automatic configuration of design blocks for varying bit widths and number of iterations reduce the design time and overhead of the engineer by many orders. A unique hardware in the loop co-simulation feature allows designers to greatly accelerate simulation while simultaneously verifying the design in hardware. Along with the high level abstraction, the tool also provides access to underlying FPGA resources through low-level abstractions, allowing the construction of highly efficient FPGA designs.

6. 2 The Limitations of System Generator As all other systems, XSG has its own limitations which need to be addressed, before it can be used widely and efficiently. 1. Not all blocks from Simulink are available in Xilinx Blockset. And there exists no way to generate hardware from models which use the basic Simulink Blockset (apart from those provided by the Xilinx). So though, for simulation purpose, Simulink blocks provide graphical block based design, the actual implementation possible on hardware is quite different from it. This creates a big gap between modeling and hardware design and as such, greatly restricts the usefulness of the tool. System Generator requires a lot from the computer and the generation step can be a problem for larger models. A large model consisting of a large number of components like an FFT built of butterflies can be hard to control for the reason of its size. As shown in [10] proclaiming XSG to be a truly high-level design tool, is not fully justified as it may give the impression that tool automatically takes care of small details, once the user connects the higher level blocks. The blockbased approach still requires the designer to be intimately involved with the timing, delays and control aspects of cores in addition to being able







to execute the back-end processes of the FPGA design flow. The blocks provided in Xilinx do not provide as much flexibility as their counterparts in Simulink Blockset. Apart from a need of different treatment for these blocks, this also puts a burden on the designer for having to calculate many design parameters and specifications such as binary points etc for every block output, and also for constants used in blocks. The number of blocks and functions of the blocks are also limited today. For example, the existing FFT block provided with System Generator can only handle 16-bit input and 16-bit output. There is a significant learning curve in using tools such as XSG which is rather undesired for many situations such as the undergraduate system-level design experience in universities [6]. The time to simulate models with components from Xilinx Blockset is longer than the time it takes to simulate in Simulink. The simulation using Simulink blocks is frame-based, which enables them to process hundred of pieces of data on one simulation step. Blocks in Xilinx Blockset can only process one piece of data in one simulation step. Still, using XSG inside Simulink for bit and cycle true simulations is an order of magnitude faster than running the same simulation through an HDL simulator.



MIMO being a recent technology and hence likely to evolve very fast, the amount of processing power required is likely to increase exponentially. There is a necessity to employ complex algorithms to reach higher data rates. Moreover, multiple processors may also be required for performing such calculations.

Reference [1] discusses the design a complete 2 2 transceiver, including the Alamouti space-time decoder, using blocks from the System Generator for DSP tool, thus eliminating the need for VHDL programming. 7.2 Digital Electronics Reference [14] discusses design of digital electronics using XSG and Matlab. The design of digital electronics today begins with the building of a model in Simulink Matlab. The model is later implemented in an FPGA from Xilinx using VHDL source code. They implemented a model of a frequency estimator often used in digital radar receivers in Matlab using XSG. To compare, the same model was also separately implemented (however, unsuccessfully) by other engineers, directly in VHDL. Central to the design of their digital receiver is FFT operation, which investigates the spectrum of the input signals. Some other modules which form a part of the receiver like buffering, windowing and sorting functions etc are also discussed. Reference [15] presents a methodology for implementing real-time DSP applications on a reconfigurable logic platform using XSG for Matlab. The developed methodology provides a step-by-step template that eases the learning curve of the complex design tools. The steps employed begin with determining the design specifications, designing a system in Simulink utilizing XSG design blocks, simulating the design in Simulink up to producing VHDL code and test bench using XSG and finally implementing the VHDL code utilizing the Modelsim software. As an example for the demonstration of the design methodology they implement a function that measures the time delay between two sine waves. This function has applications in a radar system. They demonstrate many minute details that need to be addressed in development of a typical system, which include selection of proper frequency, Xilinx blocks, sampling period, number of bits and creation of test bench etc. 7.3 Wireless communications FPGA-based DSP will play a vital role in the wireless communications domain. The authors in reference [6] have developed a rapid prototyping FPGA-based platform for wireless transmission using the Matlab and System Generator softwares. Their goal is to build a versatile educational platform for wireless transmission based on

Many of the problems of the System Generator can be explained by the fact that it is a new product not fully developed yet and it is expected that experience of the experts from industry and universities will help it grow into a more practical system. Moreover, it is updated continually, giving better performance and more blocks in Xilinx Blockset. There are other solutions being proposed, which requires change in design methodology or experience of working with the tool. For example, the problem of unavailability of all blocks can often be solved by building blocks from simpler components like adders and logical components, however it consumes some time.

We briefly summarize the applications of FPGA in DSP domain, with example of use of System Generator. 7.1 MIMO The newly emerging technology called MIMO, or multiple input, multiple output antenna configurations promises enormous performance and reliability improvements in fields of its applications [1]. However, MIMO also poses new levels of challenges in DSP complexity, performance, and changing standards that require platform FPGA. The processing requirements for the MIMO receiver are substantially greater than that of the SISO system. These complexity and processing demands far exceed the capabilities of traditional DSP processors, necessitate the use of FPGA. Other system integration challenges for implementing MIMO solutions include:

FPGA design. Here the reprogrammable nature of FPGAs makes them ideal as it allows students to iterate in their design task. They propose an FPGA-based platform for wireless transmissions, along with its hardware and software description. The communication system was successfully validated through the transmission and reception of a character string between the host PC and the FPGA-based module. The FPGA-based platform design flow in System Generator consisted of a basic four-step methodology, namely system design, verification and simulation, implementation and configuration. At the push of a button, XSG produces a cycle and bit accurate HDL netlist that can be synthesized and placed-and-routed using Xilinx ISEFoundation FPGA implementation software. All necessary files for the FPGA application, such as VHDL file of the circuit, VHDL testbench, and Synthesis scripts for different synthesizers etc are generated by XSG itself.

9. REFERENCES [1] Telikepalli, A. Fiset, E. Platform FPGA design for highperformance DSP. Available [2] Michael Parker, FPGA versus DSP design and maintenance Altera Corporation, Technical Papers. Available [3] Duren R., Stevenson J. and ThompsonM.A comparison of FPGA and DSP development environments and performance for acoustic array processing Available [4] DSPs vs. FPGAs for multiprocessing, Edward Young and Paul Moakes Available [5] Draper, B.A. Beveridge, J.R. Bohm, A.P.W. Ross, C. Chawathe, M. Accelerated image processing on FPGAs, In IEEE Transactions on Image Processing, Dec. 2003 Vol. 12, issue 12, pp. 1543- 1551 [6] G.E. Martinez-Torres J.M. Luna-Rivera R.E. Balderas-Navarro, FPGA-Based Educational Platform for Wireless Transmission Using System Generator, IEEE International Conference on Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. Sept. 2006, pp. 1-9. [7] FPGA-based FIR filter using bit-serial digital signal processing, Atmel, Available [8] C. Dick, The Platform FPGA: Enabling the Software Radio, Software Defined Radio Technical Conference and Product Exposition (SDR), November 2002. [9] S. Choi, R. Scrofano, and V.K. Prasanna, J.W. Jang, Energyefficient signal processing using FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, pp. 225 - 234 [10] Frigo J., Braun T., Arrowood J., Gokhale M. Comparison of HighLevel FPGA Design Tools for A BPSK Signal Detection Application Software Defined Radio Technical Conference and Product Exposition (SDR), November 2003. [11] Lee, E., et. al. Overview of the Ptolemy project, Department of Electrical Engineering and Computer Science, University of California, Berkeley, July 1999. [12] Xilinx Inc., System Generator for DSP, [13] Meyer-Base, U. Vera, A. Meyer-Base, A. Pattichis, M. Perry, R. , "Discrete wavelet transform FPGA design using MatLab/Simulink" In Proceedings of SPIE The International Society For Optical Engineering, 2006, vol. 6247, pages 624703. [14] Fandn, Petter Evaluation of Xilinx System Generator, Masters Thesis, Linkping University, Department of Science and Technology 2001 [15] Ownby, M. Mahmoud, W.H., A design methodology for implementing DSP with Xilinx System Generator for Matlab, Proceedings of the 35th Southeastern Symposium on System Theory , 16-18 March 2003, pp. 404- 408

Advances in FPGA technology along with development of elaborate and efficient tools for modeling, simulation and synthesis have made FPGA a highly useful platform. Currently, it is the medium of choice for the hardware development and implementation of high-performance applications, requiring rigorous computations. Many experiments have been performed which substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing, while still being highly energy efficient [9]. It has been shown that the right tools and techniques coupled with innovative features in silicon architecture can yield complete DSP functions in a single FPGA [7]. Xilinx System Generator is a system level modeling tool that facilitates FPGA hardware design by extending Simulink/Matlab in numerous ways in order to provide a powerful modeling environment. This survey clearly demonstrates the salient features of System Generator, which make it an excellent high level design tool for FPGA design on DSP processing platform. It has been argued ([10]) that the decrease in time for testing and verification alone is worth the migration to System Generator. A 2X to 4X productivity improvement is likely to be achieved using System Generator over conventional HDL language development methods due to its design environment and simulation speed. Future research trend should bring System Generator as an efficient all-inone design tool valuable for wide areas of application.