This action might not be possible to undo. Are you sure you want to continue?
Subject Contact Hrs. / wk. FIRST SEMESTER VLSI Technology & Design 4 Digital System Design 4 Analog IC Design 4 Electronic Design Automation Tools 4 Elective –I 4 Computational Techniques in Micro Electronics Digital Data Communications CPLD and FPGA Architecture and Applications Elective –II 4 VHDL Modeling of Digital Systems Modelling and Synthesis with Verilog HDL Embedded Systems Concepts HDL Programming & EDA Tools 3 Laboratory SECOND SEMESTER Algorithms for VLSI Design Automation Design for Testability Low Power VLSI Design Scripting Language for VLSI Design Automation Elective-III Hardware Software Co-Design System Modeling & Simulation Network Security and Cryptography Elective-IV DSP Processors and Architectures Advanced Operating Systems Advanced Computer Architecture M.Tech.
4 4 4 4 4
Mixed Signal Laboratory 3 -----------------------------------------------------------------------------------------------------------THIRD & FOURTH SEMESTERS SEMINAR PROJECT
2 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, HYDERABAD M.Tech.(VLSI) – I Semester VLSI TECHNOLOGY & DESIGN UNIT – I: REVIEW OF MICROELECTRONICS AND INTRODUCTION TO MOS CMOS, Bi CMOS) Technology trends and projections. TECHNOLOGIES: (MOS, 2005/06
UNIT – II: BASIC ELECTRICAL PROPERTIES OF MOS, CMOS & BICOMS CIRCUITS: Ids-Vds relationships, Threshold voltage Vt, Gm, Gds and Wo, Pass Transistor, MOS,CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model,Latch-up in CMOS circuits. UNIT – III: LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias , Scalable Design rules ,Layout Design tools. UNIT – IV: LOGIC GATES & LAYOUTS: Static complementary gates, switch logic, Alternative gate circuits , low power gates, Resistive and Inductive interconnect delays. UNIT – V: COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, interconnect design, power optimization, Switch logic networks, Gate and Network testing. UNIT – VI: SEQUENTIAL SYSTEMS: Memory cells and Arrays, clocking disciplines, Design ,power optimization, Design validation and testing. UNIT – VII: FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods, off-chip connections, Highlevel synthesis, Architecture for low power, SOCs and Embedded CPUs, Architecture testing. UNIT – VIII: INTRODUCTION TO CAD SYSTEMS (ALGORITHMS) AND CHIP DESIGN: Layout Synthesis and Analysis, Scheduling and printing; Hardware/Software Co-design, chip design methodologies- A simple Design exampleTEXT BOOKS: 1. Essentials of VLSI Circuits and Systems, K. Eshraghian et . al( 3 authors) PHI of India Ltd.,2005 2. Modern VLSI Design, 3rd Edition, Wayne Wolf ,Pearson Education, fifth Indian Reprint, 2005. REFERENCES: 1. Principals of CMOS Design – N.H.E Weste, K.Eshraghian, Adison Wesley, 2nd Edition. 2. Introduction to VLSI Design – Fabricius, MGH International Edition, 1990. 3. CMOS Circuit Design, Layout and Simulation – Baker, Li Boyce, PHI, 2004.
3. N. Roth Jr. Abramovici. UNIT – VI: PROGRAMMING LOGIC ARRAYS: Design using PLA’s. Nolman Balabanian. UNIT – V: FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault detection experiment. A. Hardware description language and control sequence method. TEST GENERATION: Fault diagnosis of Combinational circuits by conventional methods – Path Sensitization technique. Kohavi algorithm. Biswas – “Logic Design Theory” (PHI) 3. design of sequential circuits using ROMs and PLAs. REFRENCE BOOKS: 1. minimal closed covers. bridging faults. Test generation and Testable PLA design.Tech. flow table. N.3 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. HYDERABAD M. UNIT – IV: TEST PATTERN GENERATION: D – algorithm. UNIT – II: SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits. Boolean difference method. J. UNIT – III: FAULT MODELING: Fault classes and models – Stuck at faults. Machine identification. PLA minimization and PLA folding. Signature analysis and testing for bridging faults. Charles H. – “Fundamentals of Logic Design”. Reduction of state tables. UNIT – VIII: ASYNCHRONOUS SEQUENTIAL MACHINE: fundamental mode model. cycles and hazards. Frederick. Hill & Peterson – “Computer Aided Logic Design” – Wiley 4th Edition. TEXT BOOKS: 1. FPGAs. Design of fault detection experiment. Random testing. sequential circuit design using CPLD. Z. 2005/06 . Bradley Calson – “Digital Logic Design Principles” – Wily Student Edition 2004. transition and intermittent faults. D. Breues. Jaico Publications 2. Kohavi – “Switching & finite Automata Theory” (TMH) 2. UNIT – VII: PLA TESTING: Fault models. M. A.(VLSI) – I Semester DIGITAL SYSTEM DESIGN UNIT – I: DESIGN OF DIGITAL SYSTEMS: ASM charts. transition count testing. state assignments. M. races. Friedman – “Digital System Testing and Testable Design”. state reduction. PODEM.
Two Step. Charge Injection Error.A.Interpolating.Latched Comparator And Bi CMOS Comparators.Hybrid Converters.Continuous Time Filters. UNIT II OPERATIONAL AMPLIFIER DESIGN AND COMPENSATION: Two Stage CMOS Operational Amplifier. Charge Injection . Performance Limitations. High Output Impedence Current Mirrors And Bipolar Gain Stages. 2005/06 . Common Source . Practical Considerations. Switched Capacitor Gain Circuit.1997. Current Feedback Operational Amplifier. Frequency Response.Cyclic Flash Type. CMOS. Nyquist Rate D/A Converters: Decoders Based Converters. UNIT IV DATA CONVERTERS: Ideal D/A & A/D Converters.Comparator.(VLSI) – I Semester ANALOG IC DESIGN UNIT I INTEGRATED DEVICES AND MODELING AND CURRENT MIRROR: Advanced MOS Modelling . REFERENCE 1. UNIT V OVER SAMPLING CONVERTERS AND FILTERS: Over Sampling With And Without Noise Shaping . Source Follower With Current Mirror To Supply Bias Current .Successive Approximation.Switched Capacitor Circuits:Basic Operation And Analysis.Common Gate Amplifier With Current Mirror Active Load . UNIT III SAMPLE AND HOLD SWITCHED CAPACITOR CIRCUITS: MOS. John Wiley . GREGOLIAN &TEMES: Analog MOS Integrated Circuits.First Order And Biquard Filters.High Order Modulators.Fully Differential Operational Amplifier.4 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY.Correlated Double Sampling Technics.Other Switched Capacitor Circuits.Quantization Noise.Large Signal And Small Signal Mo0delling For BJT/Basic Current Mirrors And Single Stage Ampliers:Simple CMOS Current Mirror.JOHN & KEN MARTIN: Analog Integrated Circuit Design.Folded –Cascode Operational Amplifier.Binary Scaled Converters.Advanced Current Mirror. 1986.A/D Converters.Folding And Pipelined. TEXT BOOKS: 1.Nyquist Rate A/D Converters: Integrating . Feedback And Operational Amplifier Compensation. John Wiley. 1.Digital Decimation Filter. Common Mode Feedback Circuits.Tech.D. HYDERABAD M.Band Pass Over Sampling Converter. Current Mirror Operational Amplifier. Bimos Sample And Hold Circuits.
RASHID:SPICE FOR Circuits And Electronics Using PSPICE (2/E)(1992) Prentice Hall. ORCAD: Technical Reference Manual . And Digital System Building Blocks. J. Switch-Level Simulation Transistor-Level Simulation. TEXTBOOKS 1.Memory Synthesis.Bhaskar.H. VHDL And Logic Synthesis. Other Verilog Features. 2. Design Entry. A VHDL Synthesis Primer. D/A Converters. HYDERABAD M.Orcad. A/D & D/A Sample And Hold Circuits Etc.Timing Controls And Delay. Performance-Driven Synthesis. Analyses Of Analog Circuits Eg.(VLSI) – I Semester 2005/06 ELECTRONIC DESIGN AUTOMATION TOOLS UNIT I IMPORTANT CONCEPTS IN VERILOG: Basics Of Verilg Language. BSP. 3. 2. UNIT II SYNTHESIS AND SIMULATION USING HDLS: Verilog And Logic Synthesis. Analogy Nic. Understanding Modeling. Memory Synthesis.5 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. M. Operators. Logic-Gate Modeling. Tasks And Functions Control Statements. Simulation And Layout Tools For PCB. Altering Parameters. 2003. 2003.Bhaskar.FSM Synthesis. A Verilog HDL Synthesis BSP. Delay Models State Timing Analysis. USA.Procedures And Asignments. CAD Tools For Synthesis And Simulation Modelism And Leonardo Spectrum(Exemplar). BSP.Bhaskar. UNIT IV AN OVER VIEW OF MIXED SIGNAL VLSI DESIGN: Fundamentals Of Analog And Digitla Simulation.Formal Verification.A/D. Up And Down Converters. Integration To CAE Environmets. 2003 3. Modeling Delay. REFERENCES 1.Mixed Signal Simulator Configurations. Hierarchy. Addison Wesley 4.J. Logic Systems Working Of Logic Simulation. M.Tech. . UNIT V TOOLS FOR PCB DESIGN AND LAYOUT: An Overview Of High Speed PCB Design.S. Simulation-Types Of Simulation. J. USA. UNIT III TOOLS FOR CIRCUIT DESIGN AND SIMULATION USING PSPICE: Pspice Models For Transistors. Design And Analysis Of Analog And Digital Circuits Using PSPICE. SABER: Technical Reference Manual. Introduction To Orcad PCB Design Tools.SMITH :Aplication-Specific Integrated Circuits(1997). J.Cell Models. A Verilog Primer. Companders Etc.
Introduction To Physical Design.FVM And FDM.1995. Frequency Domain Analysis.1993. Part Training Algorithms .O.ROHRER AND C.LIN. 2005/06 COMPUTATIONAL TECHNIQUES IN MICRO-ELECTRONICS . L.Tech. 3. Moment Methods. Algorithms For Placement And Floor Planning . Numerical Solution Of Differential Equations-FEM.R. TEXT BOOKS: 1.6 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY.M. Introduction To VHDL Medeling.Global Routing And Detailed Routing. Electronics Circuits And Simulation Methods.CHUA AND P. Kluwer Academic . Mc. Transient Analysis. Grid Generation.VISWESWARAIAH.Yield Estimation Algorithms.PALLAGE. Graw Hall. Error Estimates. 2. L. Computer Aided Analysis Of Electronics Circuits : Algorithms And Computational Techniques. NAVEED SHEWANI. Transient And Small Signal Solutions Applications To Device And Process Simulation. Symbolic Analysis And Synthesis Of Analog Ics. Layout Algorithms . Sensitivity Analysis Timing Simulation. Algorithms For VLSI Physical Design Automation. Prentice –Hall 1975. HYDERABAD M.(VLSI) – I Semester (ELECTIVE I) Linear And Non-Linear Circuit Simulation Techniques-Algorithms And Computational Methods.
Asynchronous and Synchronous Protocols. Ethernet .QAM . Real Time Interactive Video and Audio . Topology .W. Electronic communication systems . Line Encoding . Transmission modes . Data communication and networking .7 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. ISDN. Addressing.Wave Division Multiplexing . Frame Synchronization Inter Leaving Statistical TDM FDM . VOIP TEXT BOOKS 1.Tech. 16. 16-PSK . HYDERABAD M. Traditional . Hierarchy . North American Hierarchy . UNIT VIII MULTI MEDIA Digitalizing Video and Audio Compression Streaming Stored and Live Video and Audio .QAM . public Data Networks . LCU. 8-PSK .(VLSI) – I Semester DIGITAL DATA COMMUNICATIONS (ELECTIVE I) UNIT I DIGITAL MODULATION TECHNIQUES FSK . Parallel configuration . 8.B. l2 Cap . UNIT V LOCAL AREA NETWORKS : token ring . BPSK . Serial . UNIT VII WIRELESS LANS IEEE 802. Other Upper Layers . clock recovery . CCITT . Blue Tooth Architecture Layers.A. Probability of error and bit error rate. T-carrier . Character and block Mode . Fast and GIGA bit Ethernet. 2. FDDI UNIT VI DIGITAL MULTIPLEXING : TDM . COMBO CHIPS . MSK . Telephone Networks and Circuits . Error Control Synchronization. TOMASI . UNIT III Serial and Parallel Interfaces . QPSK . fundamentals through advanced . codes . Data modems UNIT IV Data Communication Protocols . CODECS. Band width efficiency carrier recovery DPSK . Forouzen 2005/06 . UNIT II Data Communications .Pearson 4th Edition .11 Architecture Layers . T1 carrier .
UNIT IV FSM Architectures and Systems Level Design: Architectures centered around non-registered PLDs. Problem of initial state assignment for one hot encoding. programming and applications using complex programmable logic devices Altera series – Max 5000/7000 series and Altera FLEX logic – 10000 series CPLD. UNIT V Digital Front End Digital Design Tools for FPOGAs & ASICs: Using Mentor Graphics EDA Tool (“FPGA Advantage”) – Design Flow Using FPGAs – Guidelines and Case Studies of paraller adder cell. 1994. multiplexers. properties. Kluwer Pubin. Lattice pLSI’s Architectures – 3000 Series – Speed Performance and in system programmability.Vransic. PLA. data path and functional partition. Cypres FLASH 370 Device Technology. State machine designs centered around shift registers. Field Programmable Gate Array. 2.8 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY.2. S. jPrentice Hall (Pte).Chan & S.Dorf. Kluwer Academic Publicatgions. Z.Tech.K. HYDERABAD M.Trimberger. Derivations of state machine charges. UNIT II FPGAs: Field Programmable Gate Arrays – Logic blocks. Old Field. Petrinetes for state machines – basic concepts. One – Hot state machine. Extended petrinetes for parallel controllers. Edr. 1995. Alternative realization for state machine chart suing microprogramming. System level design – controller. 3. Realization of state machine charts with a PAL. Use of ASMs in One – Hot design.. routing architecture. PLD. state assignments for FPGAs.Rose. 4. counters. Meta Stability. K Application of One – Hot method. John Wiley & Sons. Linked state machines. Newyork. PAL. Field Programmable Gate Arrays. UNIT III Finite State Machines (FSM): Top Down Design – State Transition Table. paraller adder sequential circuits.Francis. Digital Design Using Field Programmable Gate Array. 1994. R. 1992. AMD’s – CPLD (Mach 1 to 5). Finite State Machine – Case Study.Brown. One – Hot design method. SUGGESTED BOOKS: 1. R. .3 and their speed performance. Synchronization. parallel controllers. Field Programmable Gate Array Technology. P. PGA – Features. Design flow.(VLSI) – I Semester 2005/06 CPLD AND FPGA ARCHITECTURE AND APPLICATIONS (ELECTIVE I) UNIT I Programmable logic : ROM. J. S. Mourad. J. Technology Mapping jfor FPGAs. Case studies – Xilinx XC4000 & ALTERA’s FLEX 8000/10000 FPGAs: AT & T – ORCA’s (Optimized Reconfigurable Cell Array): ACTEL’s – ACT-1.
Open Collector Gates. Design Libraries. Structural Specification Of Hardware: Parts Library Wiring Of Primitives. Predefined Attributes. Mcgraw Hill. Place And Route. Updating Basic Utilities. VHDL As A Modelling Language. Other Types And Type Related Issues. Synthesis. Modeling A Test Bench Binding Alternative Top Down Wiring. State Machine Description. Wiring Interactive Networks. Interface Design And Modeling. Concurrent And Sequential Assignments. Packaging Parts And Utilities. User Defined Attributes.(VLSI) – I Semester VHDL MODELLING OF DIGITAL SYSTEMS (ELECTIVE II) UNIT I INTRODUCTION : An Overview Of Design Procedures Used For System Design Using CAD Tools. Signal Assignments. PERRY : VHDL. Design Entry. Data Flow Description Test Bench For The Parwan CPU. HYDERABAD M. UNIT III DESIGN ORGANIZATIN AND PARAMETERIZATION: Definition And Usage If Subprograms. Design Parametrization. (3/E) Mcgraw Hill 2005/06 .9 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Examples Using Commercial PC Based On VHDL Elements Of VHDL Top Down Design With VHDL Subprograms. (1998) REFERENCE: 1. Subprogram Parameter Types And Overloading. A More Realistic Parwan. Utilities For High –Level Descriptions-Type Declaration And Usage. Controller Description VHDL Operators. Bussing Structure. MSI-Based Design. Behavioral Description Of Hardware: Process Statement Assection Statements. Optimization. Three State Bussing A General Data Flow Circuit. Design Verification Tools.Tech. VHDL Operators.NAWABI : VHDL Analysis And Modelling Of Digital Systems. UNIT IV DATA FLOW DESCRIPTION IN VHDL Multiplexing And Data Selection. (2/E). Simulation. Design Configuration. Objects And Classes. Sequential Wait Statements Formatted ASCII I/O Operators. UNIT II BASIC CONCEPT IN VHDL: Characterizing Hardware Languages. Z. Packing Basic Utilities. Behavioural Description Of Parawan. UNIT V CPU MODELLING FOR DESCRIPTION IN VHDL: Parwan CPU. TEXT BOOKS: 1.
Variable Scope Revisited. Benefits Of Synthesis. Synthesis Of Latches. Data Types. Operator Precedence Models Of Propagation Delay. Intra-Assignment. HYDERABAD M. Procedural Timing Controls And Synchronization. Three State Outputs And Don’t Cares. Intra-Assignment Delay: Non-Blocking Assignment. Built-In Constructs For Delay. Synthesis Of Sequential Logic Synthesis Of Sequential Udps. Path Delays And Simulation. Registered Combinational Logic. Signal Transitions. Arrays Of Instances. Verilog Variables. Time Scales For Simulation. Verilog Models For Gate Propagation Delay (Interila Delay). Constants. Initialization Of Sequential Primitives. Strings.(VLSI) – I Semester 2005/06 MODELING AND SYNTHESIS WITH VERILOG HDL (ELECTIVE II) UNIT I HARDWARE MODELING WITH THE VERILOG HDL : Hardware Encapsulation – The Verilog Module. Descriptive Styles. . UNIT IV SYNTHESIS OF COMBINATIONAL LOGIC : HDL-Based Synthesis. Procedural Assignment. Technology-Independent Design. Constructs For Activity Flow Control. Indeterminate Assignments And Ambiguity. UNIT III BEHAVIORAL DESCRIPTIONS IN VERILOG HDL : Verilog Behaviors. Behavioral Statements. System Tasks For Timing Checks. Hardware Modeling Verilog Primitives. DATA TYPES AND OPERATORS FOR MODELING IN VERILOG HDL : User-Defined Primitives. Three State Buffers.10 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. User Defined Primitives – Combinational Behavior User-Defined Primitives – Sequential Behavior. Delay-Blocked Assignments. Hierarchical Descriptions Of Hardware. Resets. Procedural Continuous Assignments. Simulation Of Simultaneous Procedural Assignments. Logic Value Set. Module Paths And Delays. Representation Of Numbers. Module Contents. Behaviral Description In Verilog. Language Conventions. Shift Registers And Counters. Synthesis Of Finite State Machines. Summary Of Delay Constructs In Verilog. Vendor Support. Expressions And Operands. Structural Connections. Styles For Synthesis Of Combinational Logic. Operators. Synthesis Of Gated Clocks. Tasks And Functions. Synthesis Methodology. Behavioral Models Of Finite State Machines.Tech. Structured (Top Down) Design Methodology. Design Partitions And Hierarchical Structures. Synthesis Of Edge-Triggered Flip Flops. Inertial Delay Effects And Pulse Rejection. Repeated Intra Assignment Delay. Verilog Models For Net Delay (Transport Delay). UNIT II LOGIC SYSTEM. Technology Mapping And Shared Resources. NonBlocking Assignment. Using Verilog For Synthesis.
Signal Strengths And Wired Logic. M. Switch Level Models Of Static CMOS Circuits. 6 Synthesis Of Case And Conditional Statement. Synthesis Of The Disable Statement Synthesis Of User-Defined Tasks. Synthesis Of User-Defined Functions. M. Switch Level Models Of MOS Transistors. Synthesis Of Resets. Restrictions On Synthesis Of “X” And “Z”. Synthesis Of Register Variables. Timings Controls In Synthesis. Synthesis If Fork Join Blocks. Combination And Resolution Of Signal Strengths.G. . Modeling. Synthesis Of Expressions And Operators. Synthesis Of Assignments.CILETTI: Prentice-Hall.ARNOLD : Verilog Digital – Computer Design. Strength Reduction By Primitives. Ambiguous Signals. REFERENCE 1. Prentice-Hall (PTR). Design Examples In Verilog. (1999).11 UNIT V SYNTHESIS OF LANGUAGE CONSTRUCTS : Synthesis Of Nets. Synthesis Of Specify Blocks. Synthesis Of Loops. Synthesis Of Multi-Cycle Operations. Synthesis Of Compiler Directives. TEXTBOOK 1. Switch-Level Models In Verilog MOS Transistor Technology. Signal Strengths. Bio-Directional Gates (Switches). CMOS Transmission Gates.D. Alternative Loads And Pull Gates. Synthesis And Rapid Prototyping With The Verilog HDL (1999).
serial communication using the “I2 C” CAN. embedded system design and co-design issues in system development process. 2005/06 . timer and counting devices. segments and blocks and memory map of a system.(VLSI) – I Semester EMBEDDED SYSTEMS CONCEPTS (ELECTIVE II) UNIT I: AN INTRODUCTION TO EMBEDDED SYSTEMS An Embedded system. 3. HYDERABAD M. 4. memories and Input Output Devices. C++. 2. Issues in embedded system design. PCI-X and advanced buses. device drivers for internal programmable timing devices. other hardware units. UNIT V: HARDWARE – software co-design in an embedded system.Tech. host systems or computer parallel communication between the networked I/O multiple devices using the ISA. VC++ AND JAVA Interprocess communication and synchronization of processes. PCI. multiple processes in an application. design cycle in the development phase for an embedded system. memory selection for an embedded systems. PEA Embedded systems design:Real world design be Steve Heath.12 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. task and threads. interprocess communication. embedded system – on – chip (SOC) and in VLSI circuit. Newton mass USA 2002 Data communication by Hayt. UNIT III: DEVICE DRIVERS AND INTERRUPTS SERVICING MECHANISM Device drivers. allocation of memory to program cache and memory management links. hardware tests. Embedded systems: Architecture. TEXT BOOK: 1. use of software tools for development of an embedded system. software embedded into a system. interfacing processors. and advanced I/O buses between the network multiple devices. exemplary embedded systems. UNIT II: DEVICES AND BUSES FOR DEVICE NETWORKS I/O devices. embedded system project management. parallel port and serial port device drivers in a system. processor in the system. Butterworth Heinenann. TMH REFERENCE: 1. interrupt servicing mechanism UNIT IV: PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C. Embedded system design by Arnold S Burger. profibus foundation field bus. CMP An embedded software primer by David Simon. programming and design by Rajkamal. memory devices. Processor and memory organization – Structural Units in a Processor. problem of sharing data by multiple tasks and routines. use of target systems. use of scopes and logic analysis for system. DMA. Processor selection for an embedded system.
Synthesis of Digital circuits 5. 6. HYDERABAD M.13 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. . Altera and Actel etc. 4.(VLSI) – I Semester 2005/06 HDL PROGRAMMING AND EDA TOOLS LABORATORY 1. Digital Circuits Description using Verilog and VHDL 2. Verification of the Functionality of Designed circuits using function Simulator. Place and Route techniques for major FPGA vendors such as Xilinx. 3. Timing simulation for critical path time calculation. Implementation of Designed Digital Circuits using FPGA and CPLD devices.Tech.
Floorplanning And Routing Problems. Binary-Decision diagrams.Chip Array based and Full Custom Approaches. Topologic routing. Placement . UNIT IV MODELLING AND SIMULATION: Gate Level Modelling and Simulation. Allocation. Assignment and Scheduling. Integer Linear Programming. Routing – Maze routing. Design Automation tools. Some Scheduling Algorithms. UNIT VIII PHYSICAL DESIGN AUTOMATION OF MCM’S: MCM technologies. UNIT V LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology. Genetic Algorithms. Some aqspects of Assignment problem. Concepts and Algorithms. Dynamic Programming. MCM phsical design cycle. UNIT II GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION: Backtracking. Tractable and Intractable problems. Partitioning. Multiple stage routing. HYDERABAD M. . UNIT VII PHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies. Algorithimic Graph Theory. Placement. Physical Design cycle for FPGA’s. Branch and Bound. partitioning and Routing for segmented and staggered Models. Integrated Pin – Distribution and routing.Tech. Internal representation of the input Algorithm. Simulated Annealing.(VLSI) – II Semester 2005/06 ALGORITHMS FOR VLSI DESIGN AUTOMATION UNIT I PRELIMINARIES: Introduction to Design Methodologies. UNIT III Layout Compaction. Routing and Programmable MCM’s. Tabu search. Computational complexity. Local Search. Highlevel Transformations.14 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Two-Level logic Synthesis UNIT VI HIGH-LEVEL SYNTHESIS: Hardware Models. Switch level Modelling and Simulation.
2. WILEY Student Edition. John wiley & Sons (Asia) Pvt. 1999. 1998 .. S. 2005.H. Ltd. Algorithms for VLSI Design Automation. Computer Aided Logical Design with Emphasis on VLSI – Hill & Peterson. 2nd Edition. 3rd edition. Modern VLSI Design: Systems on silicon – Wayne Wolf. Algorithms for VLSI Physical Design Automation.Gerez. 2.15 TEXTBOOKS: 1. Naveed Sherwani. Springer International Edition. 1993. Pearson Education Asia. Wiley. REFERENCES 1.
UNIT IV Design for testability – testability trade-offs. SST. Logic Simulation: Types of simulation. Englehood Cliffs. Embedded memory testing model. Functional testing with specific fault models. Design for Test for Digital ICs & Embedded Core Systems.(VLSI) – II Semester DESIGN FOR TESTABILITY UNIT I Introduction to Test and Design for Testability (DFT) Fundamentals. Digital Systems Testing and Testable Design. UNIT V Built-in self-test (BIST) – BIST Concepts and test pattern generation. Specific BIST Architectures – CSBL. Memory BIST (MBIST): Memory test architectures and techniques – Introduction to memory test. HYDERABAD M. Jaico Publishing House. 2001. 3. syndrome test and signature analysis. Selecting ATPG Tool. Introduction to VLSI Testing. Modeling: Modeling digital circuits at logic level. Boundary scans standards. Steven M. formats. BILBO. Memory test requirements for MBIST. CSTP. full integrated scan. Compression techniques – different techniques. Robert J. Prentice Hall. Element evaluation. Scan architectures and testing – controllability and absorbability. RTD.Friedman. storage cells for scan design. Single stuck and multiple stuck – Fault models. Arthur D. generic boundary scan. Alfred Crouch. UNIT III Testing for single stuck faults (SSF) – Automated test pattern generation (ATPG/ATG) for SSFs in combinational and sequential circuits.Feugate. Fault simulation applications. Introduction to automatic in circuit testing (ICT). JTAG Testing features.Mentyn. CATS. 1998. Gate level event driven simulation. 2.. techniques. Fault detection and redundancy. Board level and system level DFT approaches. Brief ideas on embedded core testing. Prentice Hall. CEBS. RTS. Compaction and compression. Levels of modeling. register level and structural models. SUGGESTING READING 1. Melvin A.Tech. Types of memories and integration. Hazard detection. CBIST.16 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Delay models. Brief ideas on some advanced BIST concepts and design for self-test at board level. Fault equivalence and fault location. Vector simulation – ATPG vectors. Jr. 2005/06 . General techniques for Combinational circuits. BEST. Breur. LOCST. UNIT II Fault Modeling – Logic fault models. STUMPS. Miron Abramovici.
Integrated Analog/Digital CMOS Process. future trends and directions of CMOS/BiCMOS processes.2002 . limitations. TEXT BOOKS 1. Bipolar models. UNIT II MOS/BiCMOS PROCESSES : Bi CMOS processes. UNIT IV DEVICE BEHAVIOR AND MODELING: Advanced MOSFET models. CMOS/BiCMOS ULSI low voltage. Silicon-on-Insulator.Tech. limitations of MOSFET models. Design perspective. 2005/06 MOSFET in a Hybrid- UNIT VI CMOS AND Bi-CMOS LOGIC GATES: Conventional CMOS and BiCMOS logic gates.SOI CMOS. UNIT VIII LOW POWER LATCHES AND FLIP FLOPS: Evolution of Latches and Flip flops-quality measures for latches and Flip flops. AN OVER VIEW: Introduction to low.17 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. mode environment. low power by Yeo Rofail/ Gohl(3 Authors)-Pearson Education Asia 1st Indian reprint. Performance evaluation UNIT VII LOW.VOLTAGE LOW POWER LOGIC CIRCUITS: Comparison of advanced BiCMOS Digital circuits. UNIT III LOW-VOLTAGE/LOW POWER CMOS/ BICMOS PROCESSES: Deep submicron processes . Digital circuit operation and comparative Evaluation. Integration and Isolation considerations. ESD-free Bi CMOS . UNIT V Analytical and Experimental characterization of sub-half micron MOS devices. lateral BJT on SOI.voltage low power design.(VLSI) – II Semester LOW POWER VLSI DESIGN UNIT I LOW POWER DESIGN. HYDERABAD M.
CMOS Digital ICs sung-moKang and yusuf leblebici 3rd edition TMH 2003 (chapter 11) 3. VLSI DSP systems .18 REFERENCES 1.J 1996 2. Digital Integrated circuits . 2003 (chapter 17) 4. and other National and International Conferences and Symposia. Parhi. . IEEE Trans Electron Devices. John Wiley & sons.Rabaey PH. N. IEEE J.Solid State Circuits. J.
Oreilly Publications. Compilation & Line Interfacing. Data Structures.. 3rd Edn. UNIT IV Debugger Internal & Externals Portable Functions. Nathan Torkington. CGI.(VLSI) – II Semester 2005/06 SCRIPTING LANGUAGE FOR VLSI DESIGN AUTOMATION UNIT I Overview of Scripting Languages – PERL. 3rd Edn. PERL Cookbook. Java Script.2000. UNIT V Other Languages: Broad Details of CGI. Randal L. UNIT II PERL: Operators. Java Script with Programming Examples. Tom Christiansen. “Programming PERL”. Larry Wall. 3. SUGGESTED READING: 1. Tied Variables. “Learning PERL”.Tech. UNIT III Inter process Communication Threads. Objects. Tom Christiansen. Oreilly Publications.19 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. . Oreilly Publications. 2000. 3rd Edn. Modules. VB Script. John Orwant. 2000 2. Statements Pattern Matching etc. Schwartz Tom Phoenix.. Extensive Exercises for Programming in PERL . VB Script. HYDERABAD M.
SYNTHESIS ALGORITHMS : Co – Design Models. Architectures for Control Dominated System and Data – Dominated Systems. Interface Verification UNIT V LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN : System – Level Specification. Distributed System Co-Synthesis. UNIT III COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR ARCHITECTURES : Modern Embedded Architectures. Future Developments in Emulation and Prototyping. Verification Tools.Design Computational Model. Languages. System level specification Languages. Design representation for system level synthesis.(VLSI) – II Semester HARDWARE . Prototyping and Emulation Environments. Implementation Verification.Tech. Kluwer Academic publishers 2005/06 .20 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Embedded Software Development needs. System Communication infrastructure. Hardware – Software Synthesis Algorithms : Hardware – Software Partitioning. Compilation Technologies. The Co. Target Architectures and Application System Classes. Architectures. The cosyma system and Lycos system.Design. UNIT IV DESIGN SPECIFICATION AND VERIFICATION : Design. Concurrency. UNIT II PROTOTYPING AND EMULATION AND TARGET ARCHITECTURES : Prototyping and Emulation techniques. Hardware / Software Co – Design Principles and Practice. TEXT BOOKS : 1. HYDERABAD M.SOFTWARE CO-DESIGN (ELECTIVE III) UNIT I CO – DESIGN ISSUES AND CO. Co. Heterogeneous Specifications and Multi Language Co – Simulation. interfacing components. Practical Consideration in a compiler Development Environment. A Generic Co-Design Methodology. Design Verification. coordinating Concurrent Computations. Architecture Specialization Techniques.
delays. UNIT VIII SYSTEM OPTIMIZATION System Identification. Discrete Time Markov processes. the exponential distribution. Simulation of single server queing system. UNIT III BUILDING SIMULATION MODELS Guidelines for determining levels of model detail. Classification of Software. UNIT V EXOGENOUS SIGNALS AND EVENTS Disturbance signals. UNIT II SIMULATION SOFTWARE Comparison of simulation packages with Programming languages. System integration. Motion control models. Examples of application oriented simulation packages. simulating queing systems. Desirable Software features. simulating a poison process. Simulation of Inventory System. State Machines. Alternative approach to modeling and simulation. Extend and others. UNIT VII EVENT DRIVEN MODELS Simulation diagrams. Linear Systems. Poisson processes. Systems. System encapsulation. Types of Queues. General purpose simulation packages – Arena. 2005/06 . Discrete Event Simulation.Tech. Multidimensional Optimization. UNIT VI MARKOV PROCESS Probabilistic systems. Models and Simulation.21 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Multiple servers. Searches. Modeling and Simulation methodogy. HYDERABAD M. Queing theory.(VLSI) – II Semester SYSTEM MODELLING & SIMULATION (ELECTIVE III) UNIT I Basic Simulation Modeling. Random walks. Alpha/beta trackers. Techniques for increasing model validity and credibility. Petri Nets & Analysis. Continuous-Time Markov processes. Numerical Experimentation. UNIT IV MODELING TIME DRIVEN SYSTEMS Modeling input signals. Object Oriented Simulation.
W. 2. 2001. John Wiley & Sons. 3rd Edition. REFRENCE BOOKS 1. PHI. 2003. Systems Simulation – Geoffery Gordon.22 TEXT BOOKS: 1. System Modeling & Simulation. An Introduction – Frank L. 1978. Simulation Modelling and Analysis – Averill M. Severance. Law. TMH. David Kelton. .
Digital signature standards. Modular arithmetic. HMAC. UNIT VII IP SECURITY: Overview. DIGITAL SIGNATURES AND AUTHENTICATION PROTOCOLS: Digital signatures. MESSAGE AUTHENTICATION AND HASH FUNCTIONS: Authentication requirements and functions. Testing for primality. Fermat’s and Euler’s theorems. Elliptic Curve Cryptograpy. Block Cipher Design Principles and Modes of operations. ELECTRONIC MAIL SECURITY: Pretty Good Privacy. Data Encryption standard.509 directory Authentication service. X. Secure Hash Algorithm. RC2. Authentication Protocols. UNIT II MODERN TECHNIQUES: Symplified DES. UNIT II CONVENTIONAL ENCRYPTION: Placement of Encryption function. Message digest Algorithm. Security services. CLASSICAL TECHNIQUES: Conventional Encryption model. Security of Hash functions and MACs. HYDERABAD M. Security attacks. Diffie-Hellman Key exchange. RIPEMD-160. Hash functions. Key distribution. Traffic confidentiality. UNIT V HASH AND MAC ALGORITHMS: MD File. PUBLIC KEY CRYPTOGRAPHY: Principles. ALGORITHMS: Triple DES. Euclid’s Algorithm. Characteristics of Advanced Symmetric block cifers. RC5. Random Number Generation. Blowfish. Discrete logarithms. Key Management. Steganography.Tech. CAST-128. RSA Algorithm. Authentication. A Model for Internetwork security. Block Cipher Principles. Strength of DES. Message Authentication. Secure Electronic Transaction. the Chinese remainder theorem. WEB SECURITY: Web Security requirements. Key Management. Architecture. UNIT VI AUTHENTICATION APPLICATIONS: Kerberos.(VLSI) – II Semester 2005/06 NETWORK SECURITY AND CRYPTOGRAPHY (ELECTIVE III) UNIT I INTRODUCTION: Attacks. International Data Encryption algorithm.23 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. S/MIME. Services and Mechanisms. UNIT IV NUMBER THEORY: Prime and Relatively prime numbers. . Secure sockets layer and Transport layer security. Differential and Linear Cryptanalysis. Encapsulating Security Payload. Combining security Associations. Classical Encryption Techniques.
2000.William Stallings. Pearson Education. Trusted systems. Cryptography and Network Security: Principles and Practice . VIRUSES AND WORMS: Intruders. TEXT BOOKS 1. FIRE WALLS: Fire wall Design Principles. ..24 UNIT VIII INTRUDERS. Viruses and Related threats.
Interrupt effects. Interrupts of TMS320C54XX processors. A/D Conversion errors. Decimation and interpolation. Computation of the signal spectrum. Adaptive Filters. TMS320C54XX instructions and Programming. The sampling process. Memory space of TMS320C54XX Processors. DSP using MATLAB. Interlocking. Address Generation Unit. A Digital signal-processing system. Compensating filter. UNIT V PROGRAMMABLE DIGITAL SIGNAL PROCESSORS Commercial Digital signal-processing Devices. A Butterfly Computation. Program Control. DSP Computational Building Blocks. Speed Issues. FIR Filters. Data Addressing modes of TMS320C54XX DSPs. Relative Branch support. Dynamic Range and Precision. HYDERABAD M.(VLSI) – II Semester DSP PROCESSORS AND ARCHITECTURES (ELECTIVE IV) UNIT I INTRODUCTION TO DIGITAL SIGNAL PROCESING Introduction. 2005/06 . On-Chip Peripherals. Data Addressing Capabilities. UNIT VI IMPLEMENTATIONS OF BASIC DSP ALGORITHMS The Q-notation. Discrete time sequences. Data Addressing modes of TMS320C54XX Processors. Features for External interfacing. IIR Filters. UNIT II COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS Number formats for signals and coefficients in DSP systems. PID Controller. UNIT IV EXECUTION CONTROL AND PIPELINING Hardware looping. Overflow and scaling. UNIT III ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES Basic Architectural features. 2-D Signal Processing. D/A Conversion Errors. Programmability and Program Execution. Linear time-invariant systems. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). Stacks. Bit-Reversed index generation. Bus Architecture and Memory. Pipelining and Performance. An 8-Point FFT implementation on the TMS320C54XX. Decimation Filters. Pipeline Depth. Interpolation Filters. Sources of error in DSP implementations.25 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Analysis and Design tool for DSP Systems MATLAB.Tech. UNIT VII IMPLEMENTATION OF FFT ALGORITHMS An FFT Algorithm for DFT Computation. Interrupts. Digital filters. Pipeline Programming models. Branching effects. DSP Computational errors. Pipeline Operation of TMS320C54XX Processors.
a CODEC interface circuit. Direct memory access (DMA). Thomson Publications. Bhaskar. A Multichannel buffered serial port (McBSP). Digital Signal Processing – Avtar Singh and S. Srinivasan. DSP Processor Fundamentals. REFERENCES 1. Digital Signal Processors. Chand & Co. S. Architecture. External bus interfacing signals. Interrupts and I/O. 2004. Digital Signal Processing – Jonatham Stein. CODEC programming. John Wiley. Parallel I/O interface. 2. Memory interface. 2. Architectures & Features – Lapsley et al. McBSP Programming. Programming and Applications – B. TMH.26 UNIT VIII INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES Memory space organization. 2005. Venkata Ramani and M. 2004. TEXT BOOKS 1. A CODEC-DSP interface example. Programmed I/O. . 2000.
Standard input / output Input / output redirection.Bach (PHI) 2. HYDERABAD M. file permissions. editors and utilities. ordinary & Special files.W. FIFOs. Structure.Semaphores. UNIT VIII LINUX OPERATIONS Shell operations. type of file. Operations. filters and editors. pipes. The Complete reference LINUX – Richard Peterson (TMH) 5. file management. TEXT BOOKS 1. UNIT VI INTRODUCTION TO NETWORKS AND NETWORK PROGRAMMING IN UNIX : Network Primer.27 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Elementary Socket system calls. file structure. file and record locking. The design of the UNIX Operating Systems – Maurice J.Message queues. UNIT VII LINUX Introduction to LINUX System. . Introduction to shell. Streams & Messages. Systems V IPC. UNIT IV UNIX SYSTEMS CALLS System calls related file structures. file systems.Tech. UNIX User Guide – Ritchie & Yates.Richard Stevens (PHI) – 1998. Shared Memory. TCP/IP – Internet Protocols. 3.(VLSI) – II Semester 2005/06 ADVANCED OPERATING SYSTEMS (ELECTIVE IV) UNIT I Introduction to Operating Systems. input / output process creation & termination. UNIT II UNIX –I Overview of UNIX system. UNIX Network Programming . type of shells. The UNIX Programming Environment (PHI) – Kernighan & Pike. Client – Server example. Socket Addresses. UNIT V INTERPROCESS COMMUNICATION IN UNIX Introduction. Type of operating systems. Simple examples. 4. Name Speces. Sockets & TLI. UNIT III UNIX – II UNIX basic commands & command arguments. UNIX domain protocols. Socket Programming – Introduction & overview.
UNIT II Instruction set principles and examples. . UNIT VII Storage systems.protection and examples of VM. Peter Kacsuk.classifying instruction set.type and size of operands.multi threading.limitation of ILP UNIT IV ILP software approach. Pearson.bench marking a storage device.Technology trends. Hennessy & David A.cache performance.Kai Hwang and A.Synchronization. HYDERABAD M. Terence Fountain.Types – Buses . Dezso Sima.W solutions UNIT V Memory hierarchy design.compiler techniques.measuring and reporting performance quantitative principles of computer design. Advanced Computer Architectures.Briggs International Edition McGraw-Hill.H.symmetric shared memory architectures.memory addressing.designing a I/O system. 2.-the role of compiler UNIT III Instruction level parallelism (ILP).errors and failures.cost.reducing branch costs –high performance instruction delivery.W support for more ILP at compile time. Computer Architecture A quantitative approach 3rd edition John L.examples – clusters.H. UNIT VI Multiprocessors and thread level parallelism.RAID.designing a cluster TEXT BOOKS 1. UNIT VIII Inter connection networks and clusters.interconnection network media – practical issues in interconnecting networks.distributed shared memory.28 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY.Tech. Computer Architecture and parallel Processing .W verses S.static branch protection.addressing modes for signal processing-operations in the instruction set.instructions for control flow.hardware based speculation.reducing cache misses penalty and miss rate – virtual memory. Patterson Morgan Kufmann (An Imprint of Elsevier) REFERENCES 1.(VLSI) – II Semester 2005/06 ADVANCED COMPUTER ARCHITECTURE (ELECTIVE IV) UNIT I Fundamentals of Computer design.VLIW approach.over coming data hazards.encoding an instruction set.
(VLSI) – II Semester MIXED SIGNAL LABORATORY 1. Net List Extraction 7.Tech. HYDERABAD M. 5. Layout Extraction for Analog & Mixed Signal Circuits.29 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY. Parasitic Values Estimation from Layout. Analog Circuits Simulation using Spice 2. Layout Vs Schematic 6. 4. Mixed Signal Simulation Using Mixed Signal Simulators. 3. Design Rule Checks 2005/06 .