Chapter 6: Memory Management

Memory Management
      

Background Logical versus Physical Address Space

Contiguous Allocation Paging Segmentation Segmentation with Paging

 Program

must be brought into memory and placed within a process for it to be run
 Memory

– large array of words / bytes each with its address  address of fetched instructions (by CPU) instruction execution cycle: Fetch instruction from memory Decode instruction

 PC

 Typical
 

Possibly fetch operands from memory
After execution (CPU) – possibly store results in memory

3..Binding of Instructions and Data to Memory Address binding – Mapping from one address space to another Transformation from GOTO LABEL (symbol) to JMP 9784 (address) – 3 options:  1. base and limit registers). . Load time: Must generate relocatable (relative) addresses if memory location is not known at compile time.g. absolute addresses can be generated. Compile time: If memory location is known a priori. But. Need hardware support for address maps (e. the code must be srecompiled whenever the starting location changes. 2. Loader updates addresses to real memory locations Execution time: Binding is delayed until run time if the process can be moved during its execution from one memory segment to another.

User Program Processing Source code Compiler Other Objects Object Module Link editor Load Module Dynamic libraries Loader In memory binaries Generate absolute code if all the exact addresses are known Compile time Generate relocatable code. If the starting address changes reload System Libraries Load time When the process can be moved in memory during execution. Generate address dynamically Execute time .

Physical Address Space  The concept of a logical address space that is bound to a separate physical address space is central to proper memory management  Logical address – generated by the CPU. also referred to as virtual address Physical address – address seen by the memory unit   Logical and physical addresses are the same in compile-time and load-time address-binding schemes. logical (virtual) and physical addresses differ in execution-time address-binding scheme .Logical vs.

Memory-Management Unit (MMU)  Hardware device that maps virtual to physical address  In MMU scheme. it never sees the real physical addresses  The . the value in the relocation register is added to every address generated by a user process at the time it is sent to memory user program deals with logical addresses.

Dynamic relocation using a relocation register .

unused routine is never loaded  Useful when large amounts of code are needed to handle infrequently occurring cases special support from the operating system is required implemented through program design loading .routines loaded only if called     No  Dynamic The caller checks whether it is in memory prior to call If not there relocatable loader invoked Support might be needed for relocation .Dynamic Loading  Routine  Better is not loaded until it is called memory-space utilization.

and executes the routine  Operating system needed to check if routine is in processes’ memory address  Dynamic linking is particularly useful for libraries  Dynamic linking . used to locate the appropriate memory-resident library routine  Stub replaces itself with the address of the routine. locates the necessary code and jumps to it  OS support required (memory tables.Linking is done at run time  Used normally with system routines  In a program there is only a stub that when called.Dynamic Linking  Linking postponed until execution time  Small piece of code. stub. protection)  Version number is used as part of the routine identification .

Overlays  Keep  Needed Ex. when process is larger than amount of memory allocated to it. programming design of overlay structure is complex Symbol table 20 K Common routines Overlay driver 30 K 10 K Pass I 70 K Pass II 80 K .  Implemented by user. no special support needed from operating system. Two-Pass Assembler in memory only those instructions and data that are needed at any given time.

and then brought back into memory for continued execution store – fast disk large enough to accommodate copies of all memory images for all users. and Windows)  Modified . total transfer time is directly proportional to the amount of memory swapped versions of swapping are found on many systems (i. lower-priority process is swapped out so higher-priority process can be loaded and executed  Backing  Roll  Major part of swap time is transfer time.e. Linux.. roll in – swapping variant used for priority-based scheduling algorithms.Swapping A process can be swapped temporarily out of memory to a backing store. UNIX. must provide direct access to these memory images out.

Schematic View of Swapping Swapping of two processes using a disk as a backing store .

and from changing operating-system code and data  Relocation register contains value of smallest physical address. This mapped address is sent to memory .Contiguous Memory Allocation  Main memory usually divided into two partitions:  Resident operating system. limit register contains range of logical addresses  Each logical address must be less than the limit register  MMU maps the logical address dynamically by adding the value in the relocation register. usually held in low memory with interrupt vector  User processes held in high memory  It is possible to place operating system in low memory or high memory  Single-partition allocation  Relocation-register scheme used to protect user processes from each other.

A base and a limit register define a logical address space .

Hardware support for relocation and limit registers .

Contiguous Memory Allocation(cont.)
 Simplest

schemes for memory allocation is to divide memory into a number of fixed sized partitions  Each partition may contain exactly one process
 In

this Multiple-partition allocation  Hole – block of available memory; holes of various size are scattered throughout memory  When a process arrives, it is allocated memory from a hole large enough to accommodate it  Operating system maintains information about: a) allocated partitions b) free partitions (hole)
OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2

Dynamic Storage-Allocation Problem
 How

to satisfy a request of size n from a list of free holes?

 First-fit:

Allocate the first hole that is big enough. Searching can start either at the beginning of the set of holes or where the previous first-fit search ended. Allocate the smallest hole that is big enough. Must search entire list, unless the list is ordered by size. Produces the smallest leftover hole.
Allocate the largest hole; must also search entire list, unless the list is ordered by size. Produces the largest leftover hole. and best-fit are better than worst-fit in terms of speed unless the list is ordered by size and storage utilization first-fit nor best-fit is clearly better in terms of storage utilization, but first fit is generally faster

 Best-fit:

 Worst-fit:

 First-fit

 Neither

 Best-Fit  

sometimes performs better:

Assume holes of 20K and 15K Requests for 12K followed by 16K can be satisfied only by best-fit. First-Fit can also perform better: Assume holes of 20K and 15K

 But 

Requests for 12K, followed by 14K, and 7K, can be satisfied only by first-fit.
practice (based on trace-driven simulation) First-Fit is usually better than Best-Fit First-Fit and Best-Fit are better than Worst Fit

 In  

allocated memory may be slightly larger than requested memory.. Given N allocated blocks. but not being used rule:   50-percent Statistical analysis of First-Fit reveals that.Fragmentation  External  Internal Fragmentation – total memory space exists to satisfy a request. 1/3 memory may be unusable) external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block  Reduce   Compaction is possible only if relocation is dynamic.e. another 0. this size difference in memory is internal to a partition. but it is not contiguous Fragmentation – In fixed sized blocks.5N blocks will be lost due to fragmentation (i. and is done at execution time .

 Techniques to achieve this     PAGING SEGMENTATION SEGMENTATION WITH PAGING .  Allowing the process to be allocated physical memory wherever it is available.Compaction  Cost of Compaction need to be considered One method of compaction is to move processes toward one end of the memory and all holes to the other end producing one large hole of available memory  This scheme can be expensive  Another solution to the External fragmentation problem is to allow the phyical address space to be noncontiguous.

Paging  Solution to external fragmentation problem is to permit the physical address space of a process to be noncontiguous. process is allocated physical memory wherever it is available  Noncontiguous allocation implemented using paging    Divide physical memory into fixed-sized blocks called frames Divide logical memory into blocks of same size called pages When a process is to be executed. its pages are loaded into any available memory frames from the backing store Backing store is divided into fixed sized blocks that are same size as memory frames   Set up a page table to translate logical to physical addresses .

varying between 512 bytes and 16MB per page .Address Translation Scheme  Address   generated by CPU is divided into: Page number (p) – used as an index into a page table The page table contains base address of each page in physical memory Page offset (d) – Offset from the base address.  It  is combined with base address to define the physical memory address that is sent to the memory unit Page number   Page offset Page size ( like frame size) is defined by the hardware Size of the page is typically a power of 2.

Address Translation Architecture – Paging Hardware .

Paging model of Logical and Physical Memory .

then  the higher order m .n bits of a logical address designate the page number The low-order n bits designate the page offset Page number p m–n Page offset d n   Example: Page size of 4 bytes and Physical memory of 32 bytes ( 8 pages) Page number p=3 bits m–n Page offset d=2 bits n . and a page size is 2n addressing units ( bytes or words).Paging Example  If size of logical address space is 2m.

So physical address is 4 . Page 2 maps to frame 1. logical address 0 maps to physical address 20 (5x4+0) •Logical address 8 is in page 2 offset 0.Paging Example •Logical address 0 is in page 0 offset 0. Indexing into page table shows that page 0 is in frame 5 •So.

Free Frames Before allocation After allocation .

Implementation of Page Table  Page  Page table is kept in main memory table is implemented as a set of dedicated registers base register (PTBR) points to the page table  Page-table  Changing page table requires changing only PTBR  Substantially reduces context switch time  In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)  The .

its frame number is immediately available and is used to access memory. Otherwise get frame number from page table in memory .  Each  fast-lookup hardware cache register consists of 2 parts: A key and a value  Associative memory – parallel search Page # Frame #  When a logical address is generated by the CPU. If the page number is found. its page number is presented to TLB.Associative memory or Translation Look-aside Buffer  Small.

Paging Hardware with TLB .

the operating system must select one for replacement time new page is selected the TLB must be flushed ( erased) to ensure that next executing process does not use the wrong translation information ratio:   Every  Hit Percentage times that page number is found in the associative register percent hit ratio: Desired page is found in the associative registers 80 percent of the time  80  .Paging Hardware with TLB  In addition we add the page number and frame number to its associative registers so that they will be found quickly on the next reference  If the TLB is already full of entries.

Effective Access Time    Associative Lookup =  time unit Assume memory cycle time is 1 microsecond Hit ratio =   Effective Access Time (EAT) EAT = (1 + )  + (2 + )(1 – ) =2+– .

and is thus a legal page  ―invalid‖ indicates that the page is not in the process’ logical address space .Memory Protection  Memory protection is implemented by associating protection bit with each frame  these bits are kept in page table  One bit can define a page to be read and write or read-only  Every reference to memory goes through the page table to find the correct frame number  The protection bits can be checked to verify that no writes are being made to read only page . when the physical address is being computed  Attempt to write read only page causes hardware trap to the OS  Valid-invalid bit attached to each entry in the page table:  ―valid‖ indicates that the associated page is in the process’ logical address space.

Valid (v) or Invalid (i) Bit In A Page Table .

Page Table Structure  Hierarchical Paging Hashed Page Tables Inverted Page Tables   .

each process may need 4MB of physical address space Break up the logical address space into multiple page tables A simple technique is a two-level page table     . For example with 32 bit logical address space.e.Hierarchical Page Tables  In Modern computer systems which support a large logical address space (232 to 264) page table becomes large. then page table consist of upto 10.48.232/212) entries If each entry consists of 04 bytes.576 (i. if page size is 4KB.

the page number is further divided into:  a 10-bit page number  a 10-bit page offset page number page offset  Thus.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into:  a page number consisting of 20 bits  a page offset consisting of 12 bits  Since the page table is paged. a logical address is as follows: p1 p2 d 12 10 10 where p1 is an index into the outer page table. and p2 is the displacement within the page of the outer page table .

Two-Level Page-Table Scheme .

Address-Translation Scheme  Address-translation scheme for a two-level 32-bit paging architecture .

2. This page table contains a chain of elements hashing to the same location ( to handle collisions ) Each element consists of 3 fields 1. the corresponding physical frame(field 2) is extracted. If a match is found.   Virtual page number Mapped page frame Pointer to the next element in the list  Virtual page number are compared with field 1 in the first element in the list.Hashed Page Tables  Common approach for handling address spaces > 32 bits The virtual page number is hashed into a page table. . 3.

Hashed Page Table .

with information about the process that owns that page   Only one page table in the system and it has only one entry for each page of physical memory Decreases memory needed to store each page table.Inverted Page Table  An Inverted Page Table has one entry for each real page( or frame) of memory Each entry consists of the virtual address of the page stored in that real memory location. but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one — or at most a few — page-table entries   .

Inverted Page Table Architecture .

 Shared code must appear in same location in the logical address space of all processes code and data  Private   Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space . text editors. compilers. window systems).e..Shared Pages  Shared  code One copy of read-only (reentrant) code shared among processes (i.

Shared Pages Example .

method. object. global variables.Segmentation  Memory-management scheme that supports user view of memory  A program is a collection of segments. procedure. common block. symbol table. arrays  A segment has a name and a length  Addresses specify both the segment name and the offset within the segment  Segments are numbered and are referred to by segment number rather than segment name .stack. function. A segment is a logical unit such as: main program. local variables.

User’s View of a Program .

Logical View of Segmentation 1 1 2 4 3 4 2 3 user space physical memory space .

offset>  Segment table – maps two-dimensional user defined addresses into one dimensional physical addresses  Each table entry has:  base – contains the starting physical address where the segments reside in memory  limit – specifies the length of the segment  Segment-table base register (STBR) points to the segment table’s location in memory  Segment-table length register (STLR) indicates number of segments used by a program. segment number s is legal if s < STLR .Segmentation Architecture  Logical address consists of a two tuple: <segment-number.

it is added to the segment base to produce the address in physical memory If not trap the OS Segment table is essentially an array of base limit register pairs .Address Translation Architecture Logical address consists of 2 parts: a segment number ―s‖ and an offset into that segment ―d‖ Segment number is used as index to segment table Offset ―d‖ of logical address must be between 0 and the segment limit If offset is legal.

Example of Segmentation .

as this segment is 1000 bytes long segment 2 is 400 bytes long. giving the beginning address of the segment in physical memory (base) and the length of that segment (the limit) to byte 53 of segment 2 is mapped onto location 4300 + 53 = 4353 to segment 3. byte 852.Example of Segmentation 5 segments numbered 0 to 4  Segments  Segment are stored in physical memory table has separate entry for each segment.  Reference  Reference  Reference . and begins at location 4300. is mapped to 3200 ( the base of segment 3) + 852 = 4052 to byte 1222 of segment 0 results in a trap to the OS.

Sharing of Segments .

Segmentation with Paging – MULTICS  The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments differs from pure segmentation in that the segmenttable entry contains not the base address of the segment. but the base address of a page table for this segment  Solution .

MULTICS Address Translation Scheme .

Segmentation with Paging – Intel 386  As shown in the following diagram. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme .

Intel 30386 Address Translation .

Linux on Intel 80x86  Uses  Uses  minimal segmentation to keep memory management implementation more portable 6 segments: Kernel code   Kernel data User code (shared by all user processes. using logical addresses)    User data (likewise shared) Task-state (per-process hardware context) LDT  Uses   2 protection levels: Kernel mode User mode .

End of Chapter6 .