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designfeature By Colin MacDonald and Anis Jarrar, Freescale Semiconductor


Dealing with 130-nm crosstalk delay

n todays deep-submicron designs, signal-integrity effects, such as crosstalk delay, can cause numerous violations, negatively impacting timing closure. You can meet this challenge, however, through a methodology for crosstalk-delay prevention, analysis, and repair. In applying these methods, Freescale has rapidly achieved timing closure on 130-nm SOC (system-on-chip) designs, with ICs such as the MPC5554 32-bit embedded controller. The device is based on a PowerPC Book E-compliant e500 core and targets applications that require complex, real-time control, such as advanced automotive power-train systems. Figure 1 outlines the major peripherals that this SOC design integrates. As geometries continue to shrink, preventing crosstalk early in the design flow becomes increas-

ingly important to managing signal-integrity problems and to reducing the number of analysis and repair iterations necessary to achieve timing closure. Certain types of crosstalk-induced timing violations are difficult and time-consuming to repair, making prevention essential. Several approaches can help you achieve crosstalk prevention early in your design. CROSSTALK PREVENTION Crosstalk occurs when aggressor and victim nets are close to each other. Therefore, highly congested areas or designs provide an environment conducive to crosstalk. Consequently, more floorplanning is required to reduce congestion throughout the design. Proper floorplanning leads to reduced crosstalk




Figure 1






64-kBYTE SRAM (32 S/B)





A block diagram of the MPC5554 (a), along with its corresponding die photo (b), shows the level of integration and complexity in the 32-bit embedded controller. October 14, 2004 | edn 77

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contributions and frees room to repair START crosstalk violations when and where they arise. For example, overdesigned power NON-SIGNAL-INTEGRITY/STATIC-TIMING-ANALYSIS grids unnecessarily reduce routing reNETLIST-GENERATION FLOW sources. Although these power grids may initially speed the physical building of the IC, they may make signal-integrity reSLACK pairs more difficult. Therefore, any NO TARGET MET? Figure 2 time you take to customize power grids should free routing resources and help reduce crosstalk problems. YES To help prevent crosstalk delay in layVERIFY GENERATE INITIAL NETLIST AND PARASITIC FILES out, it is important to complete thorNETLIST LOOP ough crosstalk and noise preanalysis using a tool equipped for in-design prevention and correction. This design NETLIST FILE PARASITIC FILE uses Synopsys Astro-Xtalk. Although the timing window and other delay calculations may be less accurate than those PRIMETIME SIGNAL-INTEGRITY ANALYSIS provided by STA (static-timing-analysis) tools such as Synopsys Primetime SI, the signal-integrity-prevention capabilities help to reduce the initial size of the NO WIREcrosstalk problem. SLACK < 0? REPEL Clock networks and other high-fanLOOP out nets contain many levels of logic. FINISH Each receiver in a clock-tree network can YES incur a small crosstalk delta that, by itself, RUN PTSI CROSSTALK-FIX PROCEDURES is nearly negligible. However, the sum or total deltaof these delays from clock source to destination can be more than AUTO FIX FILE NETLIST ECO FILE enough to cause a significant violation. (SCHEME) (WRITE_SCRIPT) Although an STA tool can discount timing contributions from common porDESIGN COMPILER AUTO/MANUAL tions of the clock tree in a process called NETLIST UPDATE ASTRO NET REPEL timing-clock-reconvergence pessimism, NETLISTthis option is not normally justifiable for UPDATE PARASITIC maximum-delay analysis, when the LOOP EXTRACTION STAR-RC launch and capture clocks do not coincide. In addition, when by many small crosstalk components cause a timing violation (such as on a clock tree), repairs The top-level algorithm flow for repair of crosstalk delay shows the iterative nature of the process. can be difficult. And, even if they are successful, they may significantly perturb sources. A less expensive approach is to Another effective measure is guardthe design. Therefore, preventing cross- eliminate the use of low-drive cells, es- banding setup-and-hold timing targets, talk delay is the best approach. Double- pecially on asynchronous networks, on which provides more design margin or triple-spacing clock-network routes which crosstalk-noise glitches are dead- when you take signal-integrity effects and restricting them to less congested top ly. Specifically, using higher drive cells in into account. During synthesis that is not metal layers can effectively eliminate the construction of a reset network rais- signal-integrity-aware, it is impossible to crosstalk delay on clock networks. Shield- es the threshold for would-be aggressors predict how crosstalk will affect an indiing clock network routes is another ap- and thereby reduces the degree and num- vidual timing path. However, paths with proach, but it has the disadvantage or in- ber of victim nets. less slack are easier to turn into violacreasing clock latency due to increased An effective measure for preventing tions. Therefore, for synthesis that is not ground capacitance. crosstalk delay is setting the maximum signal-integrity-aware, guardbanding for Although triple-spacing, shielding, transition time DRC to 1 nsec for wire- setup-and-hold timing helps reduce the and using reserved metal layers all work load synthesis. This step encourages the number of crosstalk-induced violations. for clocks and other high-fan-out nets, use of stronger buffers, which are less Although such guardbanding leads to an these techniques demand costly re- prone to victimization. increase in gate count and area, the ben-

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efit is a reduced amount of overall crosstalk. To reduce the amount of crosstalk during clock-tree synthesis, eliminating small buffers and using higher drive cells makes for fewer victims on clock and reset trees. Also, reducing the insertion delays of clock trees can mean fewer incremental crosstalk deltas to sum along launch and capture clock paths. To verify that our crosstalk-prevention measures work, we use TCI (tool-command procedure) procedure in Synopsys PrimeTime SI to analyze the crosstalk contributions on the clock-tree network and write the differences between minimum and maximum contributions on each driver-receiver pair to a file. These values indicate the total impact of crosstalk on each clock-tree segment. Sorting this data allows us to easily identify problems and fix problem nets. you place more emphasis on net repels. STATIC-TIMING ANALYSIS


To clear the way for signalintegrity analysis and repair, YES ALL PATHS you iterate on your non-sigDONE? nal-integrity timing flow unOUTER GENERATE ASTRO LOOP til your design is close to REPAIR SCRIPT NO (SYNOPSYS SCRIPT) 100% free of timing violaGET NEXT FAILINGtions. When you enable sigTIMING PATH POSTPROCESS OUTPUTnal integrity in your STA REPAIR SCRIPTS tool, runtime and memory COLLECT ALL POINTS FOR THIS TIMING PATH usage can increase signifiPTSI GO TO cantly. Fortunately, there are DC OR ASTRO simple and effective steps to MORE NO TIMING carefully monitor and manPOINTS age this process. First, inINNER LEFT? LOOP crease visibility of a sessions YES memory footprint and CPU _DELTA/ SLACK RATIO_ GET NEXT TIMINGusage by inserting mem NO MIN PATH POINT and cpu commands at strategic points throughout DETERMINE X_DELTA YES FOR THIS POINT your scripts. ADD PATH TO ASTROSecond, obtain detailed FIX COLLECTION progress on report generation and especially timing MAXIMUM DELAY ONLY X_DELTANO ADD UPSIZE FILES TO DELTA_MIN updates by setting STA-tool WRITE-SCRIPT FILE timing-update and -report variables to a high setting. YES MINIMUM DELAY ONLY Memory footprints can douANALYZE PATH AND MAXIMUM DELAY ONLY GENERATE INSERTGENERATE UPSIZE FIX ble, so, on large designs, you BUFFER FIX (IF POSSIBLE) CROSSTALK-DELAY REPAIR may have to use a 64-bit verCurrent prevention techsion of your STA tool of MINIMUM DELAY ONLY ADD X_DELTA niques cannot eliminate all choice. Timing updates take ADD INSERTS TO TO _DELTA WRITE SCRIPT FILE crosstalk-induced violations, longer to execute this way making crosstalk-delay repair than with signal integrity a necessity. Figure 2 shows disabled, so you should Figure 3 For repairing timing violations due to crosstalk, the the top-level flow for avoid unnecessary updates. crosstalk-delay repair. You algorithm uses a pair of nested loops. Because this process sigstart by iterating on a nonnificantly lengthens runtime signal-integrity flow until you achieve, or put includes cell upsizes from maxi- and increases compute-resource requireat least approximate, zero negative slack. mum-delay analysis and delay-cell inser- ments, its beneficial for the team to idenYou then perform static-timing analysis, tions for minimum-delay analysis. You tify key STA modes to focus on from a with signal integrity enabled to deter- can read this file back into your STA/sig- signal-integrity perspective. When you mine whether there is any negative slack nal-integrity tool to verify the suggested sufficiently reduce the number of violato fix. A procedure to create crosstalk-re- repairs, or an RTL-synthesis tool can use tions you see in these primary modes, pair constraints generates two types of it to generate a repaired netlist. You re- you can run all STA modes for final repair output files: a scheme script for net peat the wire-repel and netlist-update analysis and fixing. repelling and a write script for netlist loops as often as required to achieve zero GENERATING REPAIRS changes. negative slack. The scheme-script output automatiThis flow employs a user-defined variYou can repair crosstalk problems by cally generate net repels or, in the final able to determine the ratio of repairs that moving the victim net away from major stages of timing closure, directs manual each method generates. If your physical- aggressors, increasing the drive strength net movement. You can check the effect layout resources are short and netlist of the victim net driver, inserting a buffer of the repairs using parasitic-file output changes allow, you can place more em- in the victim net, or reducing the from SynopsysAstro placement, routing, phasis on netlist updates. As the tolerance strength of aggressor net drivers. To genand repairing tool. The write-script out- of netlist changes drops toward tape-out, erate repairs, this design uses all but the

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last option, because reducing the strength of the aggressor net drivers could adversely impact non-signal-integrity timing. The flow automatically analyzes all timing violations individually and generates repairs based on characteristics of the failing path and the value of user-defined variables. Cell upsizing or wire repelling repairs maximum-delay violations. You can also fix minimum-delay violations by cell insertions or wire repelling. Theoretically, wire repelling alone can fix all crosstalkinduced violations, but this approach can be more iterative than desirable, especially with respect to timing paths through highly congested areas. that the repairs were successful. Following the analysis of all paths, the system generates a complete collection of paths to be repaired. Nets with crosstalk delays can generate multiple failing timing paths and, therefore, multiple entries in the repair files. The last stage in the process is to remove redundant lines from the scheme and write script files. CELL UPSIZING

Repair maximum-delay violations by upsizing driver cells on the victim nets. Because it is desirable to repair victim nets without creating new violations, we tailor the degree of cell upsizing by selecting the new driver strength based on the size of the crosstalk delta. A Tcl proSIGNAL-INTEGRITY ANALYSIS AND REPAIR cedure finds alternative driver cells and The flow for repairing timing viola- extracts all valid strength values from the tions uses two nested cell names. It then puts loops to process a collec- REPAIRING MINIMUM- these strengths into an tion of violating paths DELAY VIOLATIONS BY array, sorts them, and sets (Figure 3). The outer a pointer to the current loop processes failing DELAY-CELL INSERTION drive strength. It also paths, and the inner loop compares the crosstalk INCREASES THE RISK processes driver-receiver delta on the victim net pairs. For each segment, OF SIGNIFICANTLY DIS- with four user-supplied you select the rising or TURBING THE DESIGN threshold values. Dethe falling crosstalk delta pending upon which based on that signals BUT IS EFFECTIVE AND threshold the values transition direction in SIMPLE TO IMPLEMENT. meet, you increase the the failing path. If the driver strength by one, crosstalk on the segment is less than a two, three, or four increments or to the user-defined threshold variable, the maximum value, which-ever is closest. crosstalk contribution is deemed negliCell upsizing is sometimes impossible gible, and you can process the next seg- for a number of reasons: The target cell ment. If the crosstalk delta exceeds the may already be at the maximum minimum, you need an upsize repair for strength, or the driving cell (such as maximum-delay violations. After ana- ROM, RAM, or an I/O pad) may have a lyzing each timing path, you compare the fixed driving strength. So far, net reratio of the total crosstalk contributions pelling has been the sole option for fixalong the path, divided by the slack, with ing these cases, but enhancing the a user-supplied minimum ratio to deter- methodology to include an option for remine whether you can readily obtain a pairing these violations by buffer-cell insingle-pass fix with a wire repel. You can sertion would be relatively straightforconsider the paths with ratios exceeding ward and desirable. the minimum to be good candidates for this method and add them to a collection CELL INSERTION of paths for repair. Repair paths with Repairing minimum-delay violations crosstalk-to-slack ratios below this by delay-cell insertion increases the risk threshold by cell upsizing (maximum de- of significantly disturbing the design but lay) or buffer insertion (minimum de- is effective and simple to implement. We lay). The system does not carry out up- typically choose a delay cell for its relasizes or buffer insertions in real time but tively small size and large delay. On failwrites them to a script file that the RTL- ing timing paths, you divide the total synthesis tool can use to generate a new negative slack by a guardbanded estimate netlist. Alternatively, the STA/signal-in- of the delay cells delay value. The roundtegrity tool can use this netlist to verify ed-up result is the number of delay cells

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to add at the path endpoint to remove the violation. You write the cell insertions to a script file for batch processing in synthesis or STA. ROUTE-BASED REPAIRS Experience shows that the first iteration of the wire-repelling methodology does not repair all crosstalk-induced violations. Net repelling generally reduces the amount of crosstalk delta on failing paths, but, in many cases, the reduction you achieve is insufficient to fix the violation. To improve the first-pass success rate of wire repels, you use a minimumratio variable to determine which violating paths to include in a collection destined for repair by net repelling. You pass this collection to a customized procedure for creating crosstalk constraints for the router. The procedure is configured for crosstalk-delay (analysis), net isolation, the generation of the five worst victim nets (per failing path), and the generation of the five worst aggressors (per victim net). The output from the procedure is a net-isolation file. REPAIRS USING NET REPELS To automatically perform the net-repelling repairs, you load the net-isolation file into your router, enable timing-driven spacing, and perform a search and a repair. Depending on the size of the design, this process may take a number of hours to run. Once the process is complete, you extract the new parasitic data and feed it back into your STA/signal-integrity tool for verification. You can remove fewer violations by manually implementing net repels. With any luck, you can perform this step with fewer iterations, which is important as deadlines approach. When victim nets are in congested areas, the physical designer can look at the signals environment and implement customized fixes that might be difficult to do automatically. Net-editing capabilities, such as the automatic building of via stacks, make it easy to cut tracks and move segments. Currently, the net-isolation file contains no additional information, such as the total crosstalk delta on the victim net or the amount of delay each aggressor contributes. With that information, the physical designer could decide how many of the victim nets to move and which of the aggressors to avoid. Designers have successfully used the

methodology and techniques described in this article on a number of 130-nm projects to address crosstalk and quickly achieve timing closure. Preventive measures during synthesis and layout can largely eliminate crosstalk contributions on clock and reset networks that otherwise would be difficult to fix. By properly configuring the STA tool, you can avoid causing undue pessimism and achieve high accuracy and performance; the use of custom STA/signal-integrity routines to check prevention techniques can also be worthwhile. You should also direct the efforts to fixing timing violations toward cell or wirerepel fixing procedures, depending on the violating paths crosstalk/slack ratio. Compare this ratio with a user-specified value that you can change depending on available layout resources, the number of incurred violations, or the stage in the IC development. Although this methodology is still undoubtedly iterative, it reduces the iteration count through the use of a pair of fixing techniques, tailored cell upsizing, and selection of paths for wire repelling. Freescale is applying signal-integrity timing-closure methodology to its latest 90-nm designs, in which signal-integrity problems are more prevalent. At this process node, a comprehensive and automated signal-integrity-closure flow is mandatory. As with all flows, Freescale is constantly updating the technique to take advantage of the new capabilities and options available in the latest design-automation capabilities available. Authors bio graphies Colin MacDonald is a principal design engineer within Freescale Semiconductor, focusing on static-timing analysis, synthesis, and image-processing architectures. He holds a bachelor of science degree with honors in natural philosophy from the University of Glasgow (Scotland). Anis Jarrar is a principal design engineer within Freescale Semiconductor, working on synthesis, timing, and optimization techniques for deep-submicron designs. Jarrar holds both bachelors and masters degrees from Georgia Institute of Technology (Atlanta). Talk to us Post comments via TalkBack at the online version of this article at
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