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Chapter 3 page 1-42

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CPU REGISTERS AND STATUS FLAGS
The CPU registers and status flags for the laO may be illustrated as follows:
Alternate Flags
Flags
Sign
Zero
Auxiliary Carry
Parity10verfiow
Subtract
Carry
Stack Pointer
Program Counter
ndex Register
Index Register
nterrupt Vector Register
Refresh Register
Accumulator
} Secondary Data Counters
Primary Data Counter
Alternate Accumulator
}
Alternate Secondary
Data Counters
Alternate Primary Data Counter
~
ro-
, ,r

• I
r r
S I Z I IAct IPloi N Ic
A
B C
0 E
H L
S'I z'l lAd IP!c)'1 N'I C'
A'
B' C'
0' E'
H' L'
SP
PC
IX I
IV
I I
R
Secondary {
Accumulators
Alternate {
Secondary
Accumulators
The Accumulator is the primary source and destination for one-operand and two-
operand instructions. For example, the shortest and fastest data transfers between the
CPU and 1/0 devices are performed through the Accumulator, In addition, more Memo-
ry Reference instructions move data between the Accumu later and memory than bet-
ween any other register and memory All 8-bit arithmetic and Boolean instructions take
one of the operands from the Accumulator and return the result to the Accumulator. An
instruction must therefore load the Accumulator before the laO can perform any a-
bit arithmetic or Boolean operations.
The B. C. D. E. H. and L registers are all secondary registers. Data stored in any of
these six registers may be accessed with equal ease: such data can be moved to any
other register or can be used as the second operand In two-operand instructions.
There are, however, some important differences in the functions of Registers B, C. D. E.
H. and L
Registers Hand L are the primary Data Pointer for the laO. That is to say. you will
normally use these two registers to hold the 16-bit memory address of data being ac-
cessed. Data may be transferred between any registers and the memory location ad-
dressed by Hand L Since HL is the primary Data Pointer, It ohen takes fewer bytes of
object code and less instruction cycles to perform operations with it. The Z80 program-
mer should try to address data memory via Registers Hand L whenever possible.
Within your program logic. always reserve Registers Hand L to hold a data memo-
ryaddress.
3-2
Registers B. C. D. and E provide secondary data storage; frequently. the second
operand for two-operand instructions is stored in one of these fou r registers. (The first
operand is stored in the Accumulator. which is also the destination for the result.)
There are a limited number of instructions that treat Registers Band C. or D and E.
as 16-bit Data Pointers. But these instructions move data between memory and the
Accumulator only.
In your program logic you should normally use Registers B. C. D. and E as tempor-
ary storage for data or addresses.
Registers IX and IV are index registers. They provide a limited indexing capability of
the type described in An Introduction to Microcomputers: Volume 1 for short instruc-
tions.
The alternate registers F'. A'. B'. C'. 0'. E
/
• H'. and L' provide a duplicate set of
general purpose registers. Just two single-byte Exchange instructions select and
deselect all alternate registers; one instruction exchanges AF and the alternate AF'
as a register pair. and one instruction exchanges BC. DE. and HL with the alternate BC'.
DE'. and HL' Once selected. all subsequent register operations are performed on the ac-
tive set until the next exchange selects the inactive set. The alternate registers can be
reserved for use when a fast interrupt response is required. Or. they may be used in
any desired way by the programmer.
There are a number of instructions that handle 16 bits of data at a time. These in-
structions refer to pairs of CPU registers as follows:
F
B
D
H
F'
B'
D'
H'
~
High-
order
byte
and
and
and
and
and
and
and
and
A
C
E
L
A'
C'
E'
L'
~
Low-
order
byte
The combination of the Accumulator and flags. treated as a 16-bit unit. is used only for
Stack operations and alternate register switches Arithmetic operations access Band C.
D and E. or Hand L as 16-bit data units.
The Carry status flag holds carries out of the most significant bit in any arithmetic
operation. The Carry flag is also included in Shift instructions: it is reset by Boolean in-
structions.
The Subtract flag is designed for internal use during decimal adjust operations, This
flag is set to 1 for all Subtract instructions and reset to 0 for all Add instructions.
The Parity/Overflow flag is a multiple use flag. depending on the operation being
performed. For arithmetic operations, it is an overflow flag. For input. rotate. and
Boolean operations, it is a parity flag. with 1 = even parity and 0 = odd parity. Dur-
ing block transfer and search operations. it remains set until the byte counter decre-
ments to zero: then it is reset to zero It is also set to the current state of the interrupt
enable flip-flop (IFF2) when a LD A.I or LD A.R instruction is executed.
The Zero flag is set to 1 when any arithmetic or Boolean operation generates a
zero result. The Zero status is set to 0 when such an operation generates a non-
zero result.
3-3
The Sign status flag acquires the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction.
The Auxiliary Carry status flag holds any carry from bit 3 to 4 resulting from the
execution of an arithmetic instruction. The purpos'e of this status flag is to simplify
Binary-Coded-Decimal (BCD) operations; this is the standard use of an Auxiliary Carry
status flag as described in An Introduction to Microcomputers: Volume 1, Chapter 3.
All of the above status flags keep their current value until an instruction that modifies
them is executed. Merely changing the value of the Accumulator will not necessarily
change the value of the status flags. For example. if the Zero flag is set. and a load im-
mediate to the Accumulator is executed. that causes the Accumulator to acquire a non-
zero value: the value of the Zero flag remains unchanged.
The 16-bit Stack Pointer allows you to Implement a Stack anywhere in addressa-
ble memory. The size of the Stack is limited only by the amount of addressable memory
present In reality you will rarely use more than 256 bytes of memory for your Stack.
You should use the Stack for accessing subroutines and processing interrupts. Do not
use the Stack to pass parameters to subroutines. This is not very efficient within the
limitations of the zao instruction set. The zao Stack is started at its highest address. A
Push decrements the Stack Pointer contents; a Pop increments the Stack Pointer con-
tents
The Interrupt Vector register and the Refresh register are special-purpose
registers not normally used by the programmer.
The Interrupt Vector register is used to store the page address of an interrupt response
routine: the location on the page is provided by the interrupting device. This scheme
allows the address of the interrupt response routine to be changed while still providing
a very fast response time for the interrupting device.
The Refresh register contains a memory refresh counter in the low-order seven bits.
This counter is incremented automatically after each instruction fetch and provides the
next refresh address for dynamic memories. The high-order bit of the Refresh register
will remain set or reset. depending on how it was loaded at the last LD RA instruction.
lao MEMORY ADDRESSING MODES
The zeo provides extensive addressing modes. These Include:
· Implied
• Implied Block Transfer with Auto-Increment/Decrement
• Implied Stack
· Indexed
· Direct
• Program Relative
• Base Page
• Register Indirect
• Immediate
3-4
Implied
In implied memory addressing. the Hand L registers hold the address of the
memory location being acces.ed. Data may be moved between the identified memo-
ry location and anyone of the seven CPU registers A. B. C. D. E, H, or L. For example, the
instruction
LD C.(HU
loads the C register with the contents of the memory location currently pointed to by
HL. This is illustrated as follows:
Data
q
mmmm
mmm+ 1
1----.. mmrnm + 2
1- .. mmmm + 3
Memory
r
yy
1
-
pp qq
mmmm
~ m m m + ~
Program
Memory
I 4E
I m
s Z AcP/O N C
Fc:::I:IJ:I:]
A
S.C
D.E
H.l
SP
PC
IX
IV
I
R
LD C. (HU
~
76543210
EE:EE:EEEEl
1:1 [------Load Implied via HL
C Register
3-5
A limited number of instructions use Registers Band C or 0 and E as the Data
Pointer. These instructions move data between the Accumu lator and the memory loca-
tion addressed by Registers Band C or Registers D and E. The instruction
LD (BCLA
stores the contents of A into the memory location currently addressed by Register Pair
Be. This is illustrated as follows:
SZACPONC Data
Q
mmm
mmm+1
mmmm+2
1-----4mmmm + 3
CIIIIIl
Memorv
vv -
ppq
pp qql
1
j
- ~ V
Program
mmmm ~ m m m + 1
MemOry
I
02 m
I
m
F
A
B.C
O.E
H.L
SP
PC
IX
IY
I
R
LD (BCl.A
---
"",._...",.A....~ __...
r, 6 S:-4 3 2 1 0'
~
-..... J
T Store Implioed from A via BC
3-6
ED mmmm
...-----==80;-..... mmmm + 1
mmmm+2
1----1 mmmrri +3
Implied Block Transfer With Auto-Increment/Decrement
Block Transfer and Search instructions operate on a block of data whose size is
set by the programmer as the contents of the BC register pair. In this form of ad-
dressing. a byte of data is moved from the memory location addressed by HL to
the memory location addressed by DE; then HL and DE are incremented and Be is
decremented. Data transfer continues until BC reaches zero. at which point the In-
struction is terminated. Variations include allowing other instructions to follow
each data transfer. with the programmer supplying the loopback; auto-decrement-
ing HL and DE instead of auto-incrementing; and a complementary set of Block
Search instructions that compare the memory byte addressed by HL with the con-
tents of the A register. setting a flag if a match is found.
The Load. I ncrement. and Repeat instruction
LDIR
is illustrated as follows:
Set if BC- 1- o.eS8t otherwise
S Z AcP'ON C
Fo:::EI:E:I2IJ
Ar-__...-__..... .......
B.CI-__ .......__.."
D,E 1-__
.L
Spt- .....
PC mmmm
IX ...------...;..------....
IV ....... 4111........--_
I
R
LOIR
...+o....-+.....-.-..O-+-:... } load. Increment, and Repeat instruction
A similar group of Input/Output instructions is provided. allowing a block of data
to be input or output between memory and an I/O device. The I/O port nu mber is
taken as the contents of the C register. with the sing Ie B reg ister used as the byte
counter. Memory is addressed by HL.
3-7
Implied Stack
Since the Stack is part of ReadIWrite memory, we must consider Stack instructions as
Memory Reference instructions. Pu.h and Pop in.truction. move two byt•• of data
b.tw••n a r.gl.t.r pair and the .ddr••••d Stack Polnt.r location. i,e., current top-
of-stack, The Z80 Stack address is decremented with each Push and incremented with
each Pop. The instruction
PUSH DE
is illustrated as follows:
5 ZAcP/ON C
Data
ssss - 2
ssss - 1
ssss
mmmm
mmmm+ 1
...- oImmmm + 2
I- -tmmmm + 3
r::IJ:IJ:IJ
Memorv
-
C
qq
I
JA ssss-2 ~ -

pp I
pp qq
/'/'
ssss
~ - ~ ~
mmmm
:mmm+l
Program
Memory
I 05
I
F
A
B.C
D.E
H,l
SP
PC
IX
IV
,
R
PUSH DE
~ X ,
76543210
~ ~ , o , o , ~ _
-- PUSH instruction
---Register Pair DE
3-8
The laO allo hal instructions that exchange the two top-of-stack bytes with a
16-blt register - HL or one of the two index registers. The instruction
EX (SPl,HL
is illustrated as follows:
S Z Ac Pia N C
Data
ssss
ssss + 1
ssss + 2
mmmm
mmmm+ 1
mmmm+2
.....-----t
mmmm
+ 3
DIIIIJ
Memory
-
---
:
qq
pp
M"

xx yy
ssss
-" :v
mmmm mmmm +'
Program
Memory
I E3
I
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
3-9
Indexed
Th. zao ha. two 16-bit Ind.x r.gl.t.rs, call.d IX and IV. They may be used in-
terchangeably, All memory reference operations for which (HU can be specified can
alternatively be specified as an indexed operation, The difference between implied ad-
dressing using HL and indexed addressing using IX and IY is that the ind.x op.rand
includ•• a di.plac.m.nt valu. that i. add.d to the ind.x addr•••. ln the instruction
ADD A. (IX+40H)
the memory address is the sum of the contents of the IX register and 40
16
, This may be
illustrated as follows:
40
m
m+ 1
m+2
m+3
Data
IMemory J

ppqq
xx XX+YY

--
,


yy
; ppqQj
I
-

Program
mmmm
ppqq
-
Memory
I DO mmm
I 86

mmm
40 mmm
JI' -
.:L
mmm
ADD A,OX + 40)
S Z Ac P/O N C

A
B,C
D.E
H,l
SP
PC
IX
IV
,
R
3-10
Direct
Direct addressing can be used to load the Accumulator with any 8·bit value from
memory, load BC, DE, HL, SP, IX, or IV with any 16-bit memory value, and jump or
call subroutines direct at any memory location. The 16-bit direct address is stored in
the last two bytes of the instruction. in low-byte high-byte order (this is the reverse of
the standard high-low schemel.
The i nstructi on
LD A.(NETX)
loads the A register with the contents of the memory location addressed by the label
NETX. The instruction
LD HL.l1 FFH)
loads the L register with the contents of memory location 01 FF16 and the H register
with the contents of memory location 0200
16
. This may be illustrated as follows:
Data
OIFF
0200
mmmm
) mmmm+ t
1 01 mmmm+2
1-----1 mmmm + 3
Memory
YV
xx
6
,
xx YV
- '"
Program
mmmm mmmm + 3
- "-
Memory
I 2A
I FF
'-,
S Z Ac P/O N C
FCIIIID
A
S,C
D.E
H.L
SP
PC
IX
IV
I
R
LD HL.!IFFH)
76543210
0 0
,
0 1 0
,
0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
Load HL Direct instruction
Direct address - low byte
Direct address - High byte
The direct Jump instructions provide jumps and jumps-to-subroutines, both un-
conditional and conditional. These are all 3-byte instructions. with the direct address
stored in the second and third bytes of the instruction. as shown above for Load Direct.
There are three additional addressing modes used by zao Branch instruc-
tions: program relative. base page. and register indirect. In general. they are shorter
and/or faster than direct jumps but may have more limited addressing capabilities.
3-11
Program Relative
Jump Re.etlve instructions pro'ltde pregrem re.etive eddre.slng In the renge -128,
+129 byte. from the first byte of Relative instruction. These instructions
are all 2-byte instructions, with 1'fte signed displacement value stored in the second
byte of the instruction. There .... uaaonditlonel end conditioneI re.etive jump., e.
well ••• Decrement end Jump " Not Zero in.truction (DJNZ) thet fecllltete. loop
control.
Given the instruction
JR SRCH
assume that SRCH is a label alltdressing a location 5A
16
bytes up in memory from the
JR op-code byte. The operati.on may be illustrated as follows:
5 Z AcP/O N C
FCIIIIIJ
Data
Memory
A
B.C
D,E
H,L
SP
PC
IX
IV
I
R
- 'mmmm:f)
Program
mmmm
"""- SA
Memory

I 18
I SA
--.
JR SRCH
mmmm
mmmm+l
mmmm+2
mmmm+3
Jump Relative iAStruction

o Displacement
...."'--"'--"'--"""-"'--.....
3-12
Base Page
The Z80 has a modified base page addressing mode for the Restart instruction. This is
a special Call instruction that allows a single-byte instruction to jump to one of
eight subroutines located at specific points in lower core. The effective address is
calculated from a 3-bit code stored in the instruction. as follows:
Lower Core Address 3-Bit Code
OOH
08H
10H
18H
20H
28H
30H
38H
000
001
010
all
100
101
110
111
The decoded address value is loaded into the low-order byte of the Program Counter;
the high-order byte of the Program Counter is set to zero. For example. the instruction
RST OOH
is illustrated as follows:
s Z AcP/O N C Data
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
CIII:ID
Memory
,
mm+l
fl
mm
t:. ssss - 2
----..........
ssss
mmmm
Program
Memory
I
......-....
C7
000
I
ssss - 2
ssss - 1
ssss
mmmm
mmmm+ 1
mmmm+2
mmmm+3
RST OOH

76543210

-ccT--_Rest8rt instruction
code
3-13
Data
Memory
Register Indirect
In standard indirect addressing. a memory location contains the effective address. and
the instruction specifies the address of the memory location containing the effective
address. In register indirect addressing. a register contains the effective address. and
the instruction specifies which of the registers contains the effective address Note that
for a Load, for instance. this is just another way of describing implied addressing.
However. the l80 has Jump instructions that allow a jump to the memory location
whose address is contained in the specified register. This is a form of indirect ad-
dressing. and is described separately because. while most microcomputers have im-
plied addressing. very few have register indirect jumps.
The instruction
JP (HL)
directs that a jump is to be taken to the memory location whose address is contained in
HL This may be illustrated as follows:
S Z AC P/O N C
FCCIIIIJ
A
B,C
D.E
H.L
SP
PC
IX
IV
I
R
pp qq
D
mmmm
I
I
JP (HLl
--:x..-
.... ----...... :0-.
76543210

3-14
Program
Memory
E9 mmmm
1-__...... mmmm + ,
mmmm+2
1---...... mmmm + 3
Immediate
Some texts identify Immediate instructions as Memory Reference instructions. An Im-
mediate instruction is a 2-. 3-. or 4-byte instruction in which the last one or two bytes
hold fixed data that is loaded into a register or memory location. The Z80 provides Im-
mediate instructions to:
load 8-bit data into any of the 8-bit registers.
load 16-bit data into any of the register pairs or 16·bit registers.
store 8-bit data into any memory location using implied or indexed addressing.
perform arithmetic and logical operations using the Accumulator and 8-bit im-
mediate data.
The instruction
LD BC.OBCH
loads the immediate data value BC16 into Register Pair BC. This may be illustrated as
follows:
S Z AcP/O N C
FCD:IIIJ
Data
Memory
A
B.C
D.E
H.l
SP
PC
IX
IV
I
R
...
mmmm
Program
Memory
I
01
I BC
'- 00
mmmm
mmmm + 1
mmmm+2
mmmm+3
LD BC. 08CH
76543210

'4T """ Om"""'... M ROO'•• "',
Pair BC
76543210
1 0 1 1 1 1 0
o I
0 0 0 0 0 0 0
o I
Immediate data - low-order byte
Immediate data - high-order byte
3-15
Table 3-1. Frequently Used Instructions of the zeo
Instruction Code Meaning
ADC A Add with Carry to Accumulator
ADD Add
AND Logical AND
CALL addr Call Subroutine
CALL cond,addr Call Conditional
CP Compare
DEC Decrement
DJNZ Decrement and Jump If Not Zero
IN Input
INC Increment
JR Jump Relative
JR cond.addr Jump Relative Conditional
LD reg.(HL) Load Register
LD A,(addr) Load Accumulator Direct
LD data Load Immediate
LD (HL).reg Store Register
LD (addrl.A Store Accumulator Direct
LD dst.src Move Register-ta-Register
OUT Output
POP Pop from Stack
PUSH Push to Stack
RET Return from Subroutine
RET cond Return Conditional
RLA Rotate Accumulator Left Through Carry
RRA Rotate Accumulator Right Through Carry
SLA Shift Left Arithmetic
SRL Shift Right Logical
SUB Subtract
3-16
Table 3-2. Occasionally Used of the laO
Instruction Code Meaning
BIT Test Bit
CPD,CPDR Compare. Decrement. (Repeat)
CPI, CPIR Compare, Increment. (Repeat)
CPL Complement A<:cumulator
DAA Decill11itl Adj ust Accumu lator
01 IMerrupts
EI Enable Interrupts
EX Exchange
HALT Halt
IND.INDR Input. [)ecrement. (Repeat)
IN!. INIR Input. IncremtiHlt. (Repeat)
JP addr Jump
JP cond,addr Jump Conditional
LD A, (BC) or (DE) Load Accumulator Secondary
LD HL.(addd Load Hl Direct
LD reg, (xy+disp) Load Register Indexed
LD rp.(addr) Load Pair Direct
LD xy,(addr) Load Index Register Direct
LD (BC) or (DE),A Store Accu mu lator Secondary
LD (addr),HL Store Hl Direct
LD (xy+disp).reg Store Regfster Indexed
LD (addr),rp Store R-egis1'er Pair Direct
LD (addd,xy Store Index Register Direct
LD (HL),data Store Immediate to Memory
LD {xy+displ.data Store Immediate to Memory Indexed
LDD. LDDR Load, Decrement. (Repeat)
LD!. LDIR Load. Increment. (Retlleat)
NEG Negate (Twos Complement) Accumulator
NOP No Operation
OR Logical OR
OUTD.OTDR Output. Decrement. lRepeat)
OUTI. OTIR Output. Increment. (l\epeat)
RES Reset !i'it
RETI Retu rn from Interrupt
RL Rotate Left ThrouQh Carry
RLC Rotate Left Circular
RLCA Rotate Accumulator Left Circular
RR Rotate Right Throullh Carry
RRC Rotate RiQt1t Circll'tar
RRCA Rotate Accumu"tor Right Circular
SET Set Bit
SRA Shift Right Arithmetic
XOR Exclursi-ve OR
3-17
Table 3-3 Seldom Used Instructions of the Z80
Instruction Code Meaning
ADC HLrp Add Register Pair with Carry to HL
CCF Complement Carry Flag
EXX Exchange Register Pairs and Alternatives
1M n Set Interrupt Mode
RETN Return from Non-Maskable Interrupt
RLD Rotate Accumulator and Memory Left Decimal
RRD Rotate Accumulator and Memory Right Decimal
RST Restart
SSC Subtract with Carry (Borrow)
SCF Set Carry Flag
LD AI Load Accumulator from Interrupt Vector Register
LD AR Load Accumulator from Refresh Register
LD I.A Store Accu mu lator to Interru pt Vector Register
LD R.A Store Ac{'u mu lator to Refresh Register
LD SP.HL Move HL to Stack Pointer
LD SP.xy Move Index Register to Stack Pointer
ABBREVIATIONS
Program Counter
An 8-bit I/O port address
data
data16
These are the abbreviations used in this chapter:
A.F.B.C.D,E.H.L The 8-bit registers. A is the Accumulator and F is the Flag Word.
AF'.BC'.DE'.HL' The alternate register pairs
addr A 16-bit memory address
x(b) Bit b of 8-bit register or memory location x
cond Condition for program branching. Conditions are:
NZ - Non-Zero (Z = 0)
Z -Zero(Z=l)
NC - Non-carry (C = 0)
C - Carry (C = 1)
PO - Parity Odd (P = 0)
PE - Parity Even (P = 1)
P - Positive Sign (S = 0)
M - Negative Sign (S = 1)
An 8-bit binary data unit
A 16-bit binary data unit
An 8-bit signed binary address displacement
The high-order 8 bits of a 16-bit quantity xx
Interrupt Vector register (8 bits)
The Index registers (16 bits each)
A 16-bit instruction memory address
The low-order 8 bits of a 16-bit quantity xx
Least Sig nificant Bit (B it 0)
Most Significant Bit (Bit 7)
port
IX IY
label
disp
xx(HI)
I
xx(LO)
LSB
MSB
PC
3-18
pr
R
reg
rp
SP
xy
Object Code
Any of the following register pairs:
BC
DE
HL
AF
The Refresh register (8 bits)
Any of the following registers:
A
B
C
D
E
H
L
Any of the following register pairs:
BC
DE
HL
SP
Stack Pointer (16 bits)
Either one of the Index registers (IX or lY)
bbb Bit number 000 (LSB) to 111 (MSB)
eec Condition code 000 = non-zero
001 = zero
010 = no carry
011 = carry
100 = parity odd
101 = parity even
110 = positive sign
111 =negative sign
ddd Destination register - same coding as rrr
ppqq A 16-bit memory address
rrr Register 111 = A
000 = B
001 = C
010 =D
011 = E
100 = H
101 = L
sss Source register - same coding as rrr
x Index reg ister 0 = IX
1 =IY
xx Register pair 00 = BC
01 = DE
10 = HL
11 =SP (rp) or AF (pr)
xxx Restart code (000 to 111)
yy An 8-bit binary data unit
yyyy A 16-bit binary data unit
3-19
Statuses
[[ ]]
[]
A
V
41-
---+
The l80 has the following status flags:
C - Carry status
l - lero status
S - Sign status
P/O - Parity/Overflow status
AC - Auxiliary Carry status
N - Subtract status
The following symbols are used in the status columns:
X - flag is affected by operation
(blank) - flag is not affected by operation
1 - flag is set by operation
o - flag is reset by operation
U - flag is unknown after operation
P - flag shows paritY status
o - flag shows overflow status
I - flag shows interrupt enabled/disabled status
Memory addressing: 1) the contents of the memory location
whose address is contained in the designated register. 2) an
I/O port whose address is contained in the designated register.
The contents of a register or memory location.
For example:
([HLll +- [[HLll + 1
indicates that the contents of the memory location addressed by
the contents of HL are incremented. whereas:
[HL] +- [HL] + 1
indicates that the contents of the HL register itself are incre-
mented.
Logical AND
Logical OR
Logical Exclusive-OR
Data is transferred in the direction' of the arrow
Data is exchanged between the two locations designated on either
side of the arrows.
3-20
INSTRUCTION MNEMONICS
Table 3-4 summarizes the leO instruction set. The MNEMONIC column shows the
instruction mnemonic UN, OUT, LD). The OPERAND column shows the operands,
if any. used with the instruction mnemonic.
The fixed part of an assembly language instruction is shown In UPPER CASE. The
variable part (Immediate data. I/O device number, register name. label or address)
is .hown in lower case.
are:
For closely related operands, each type is listed separately
mnemonic. For instance, examples of the format entry
LD rp,(addr)
xy,(addr)
LD BC.(DAT2)
LD IX,(MEM)
INSTRUCTION OBJECT CODES
without repeating the
The object code a"d instruction length in byte. are shown in Table 3-4 for each
instruction variation. Table 3-5 lists the object codes in numerical order.
For instruction bytes without variations. object code. are represented as two
hexadecimal digits (e.g•• 3F).
For instruction bytes with variations in one of the two digits, the object code is
shown as one 4-bit binary digit and one hexadecimal digit le.g.• 11 x 1 D) in Table
3-5. For other instruction bytes with variation., the object code is .hown as eight
binary digits (e.g., 0118.001).
INSTRUCTION EXECUTION TIMES
Table 3-4 lists the instruction execution times in clock periods. Real time can be
obtained by dividing the given number of clock periods by the clock frequency. For
example. for an instruction that requires 7 clock periods. a 4 MHz clock will result in a
1.75 microsecond execution time.
When two possible execution times are shown (j.e., 5/11), it indicates that the
number of clock periods depends on condition flags. The first time is for "condi-
tion not met," whereas the second is for "condition met."
STATUS
The six status flags are stored in the Flag register (F) as follows:
--+-...--t--+--......--These bits are not used
......--Carry status (carry out of bi,t 7)
......---- Subtract stetus
(, aftar subtract operation. 0 otharwise)
""------ Parity/Overflow
(for logical operations. 1 for ellen. 0 for odd parity.
For arithmetic, 1 for overflow)
10.- Auxiliary Carry status (carry out of bit 3)
.....------------Zero status (1 for zero, 0 for nonzero)
.....-------------Sign status (vatue of bit 7)
3-21
In the individual instruction descriptions. the effect of instruction execution on
status is illustrated as follows:
s Z AC Pia N C
171 !ll
x
l
o
l
x
l
~ l j ~ ~ ~ I
Modified to reflect results of execution
Unconditionally reset to 0
Unconditionally set to 1
Unchanged
Unknown
An X identifies a status that is set or reset. A 0 identifies a status
that is always cleared. A 1 identifies a status that is always set. A
blank means the status does not change. A question mark (?)
means the status is not known.
3-22
STATUS
CHANGES
WITH
INSTRUCTION
EXECUTION
•• Address Bus: AO-A7: [e)
AS-A1S: [B)
Taole 3-4. A Summary of the zao Instruction Set
(,J
I
""
(,J
Clock
Status
Type Mnemonic Operend Object Code Bytes Operation Performed;
Cycles
C Z S PIO AC N
IN A,(portl DB yy 2 10 [AJ- [pertJ
Input to Accumulator from directly addressed 1/0 port.
Address Bus: AO-A7: port
AS-A15 [AI
IN reg,ICl ED 01dddOOO 2 11 X X P X 0 [regl- [[ Cll
Input to register from 1/0 port addressed by the contents of C."
ED B2 2 20/15" 1
] ] 1
If second byte is 70
16
only the flags will be affected.
INIR ? Repeat until [ BJ = 0:
[[ HLI)- [(Cll
[BJ-[Bl- 1
[ HLI - [HLI + 1
Transfer a block of data from 1/0 port addressed by contents of C
to memory location addressed by contents of HL, going from low
addresses to high. Contents of B serve as a count of bytes remain-
ing to be transferred."
0 INDR ED BA 2 20/15" 1 7 ]
? 1 Repeat until [ BJ =0:
::.
[[HL1J-[[Cll
[B)-[B]- 1
[ HLJ - [HLJ - 1
Transfer a block of data from 1/0 port addressed by contents of C
to memory location addressed by contents of HL, going from high
addresses to low. Contents of B serve.as a count of bytes remaining
to be transferred."
INI ED A2 2 15 X ?
]
? 1 [[ HLI- [[ C]]
[B)-[BJ - 1
[ HLI - [ HLI + 1
Transfer a byte of data from 1/0 port addressed bv contents of C to
memory location addressed by contents of HL Decrement byte
count and increment destination address."
··Address Bus: AO-A7: IC]
A8-A1S: IB)
Table 3-4. A Summary of the zao Instruction Set (Continued)
Co)
I
~
Clock
Statu.
Typa, Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO A
C
N
INO EDAA 2 15 X ?
]
? I [[ HU] - [[ CII
(BJ - [BI- I
t HL] - [HLI - I
Transfer a byte of data from I/O port addressed by contents of C to
memory location addressed by contents of HL. Decrement both
byte count and destination address."
OUT (portl.A 03 yy 2 II [port] - [A]
Output from Accumulator to directly addressed I/O port.
Address Bus: AO-A7: port
A8-A1S: [Al
OUT (Cl.reg EO 01555001 2 12 11 C])- [reg]
Output from register to I/O port addressed by the contents of C."
OTIR ED B3 2 20/15·· 1
]
?
]
1 Repeat until ( BI =0:
'ij
([C])-([HL])

[8]- [BI - 1
::>
.5 (HU-[HU+ 1
e
Transfer a block of date from memory location addressed by con- 0
~
tents of HL to I/O port addressed by contents of C. going from low
g
memory to high. Contents of B serve as a count of bytes remaining
to be transferred.··
OTOR ED BB 2 20/15·· I 7 7 ? 1 Repeat until [BI = 0:
[[C])-[[HL])
[BI-IBJ -,
[ HLI - I HU - ,
Transfer a block of data from memory location addressed by con-
tents of Hl to I/O port addressed by contents of C. going from high
memory to low. Contents of B serve as a count of bytes remaining
to be transferred.••
.. Address Bus: AO-A7; (C)
AS-A15: [B)
Table 3-4. A Summary of the zao Instruction Set (Continued)
w

N
C1l
Clock
Status
Type Mnemonic Operand Object Code Bytes
Cycles
Operation Performed
C Z S PIO
AC N
OUli ED A3 2 15 X ? 7 7 1 [[ClI - [[HLlJ
[Bl- [BI- 1
[HLJ - [HLl + 1
'ii
Transfer a byte of data from memory location addressed by con-
• tents of Hl to 1/0 port addressed by contents of C. Decrement byte :::I
c
....
count and increment source address.··
c
0
OUTD ED AB 2 15 X 7 7 7 1 [[C)]-[(HL)]
H
[B]- [Bl - 1
g
[HLl-[HLl-1
Transfer a byte of data from memory location addressed by con-
tents of HL to 110 port addressed by contents of C. Decrement both
byte count and source address.··
LD A,(addd 3A ppqq 3 13 [Al- [addrl
load Accumulator from directly addressed memory location.
LD HL,(addd 2A ppqq 3 16 [ HI - [ addr + 1l. [ Ll - [ addrl
load Hl from directly addressed memory.
LD rp,laddd ED 01xx1011 ppqq 4 20 [ rplHIlJ - I addr + 1l. [ rpllOI) - [ addrl or

xy,(addrl 1hl11012Appqq 20 [ xy(HIl] - [ addr + 1L [xy(LOII - [ addrl
u
4
c
• Load register pair or Index register from directly addressed memo-

...
ry. a
II:
LD laddd,A 32 ppqq 3 13 [addrl- [AI
>-
Ii
Store Accumulator contents in directly addressed memory location.
E
II LD !addd,HL 22 ppqq 3 16 [ addr + 1] - [Hl. [addrl - ( L]
~
Store contents of Hl to directly addressed memory location.
>-
..
LD laddrl,rp ED 01xxOOll ppqq 4 20 [ addr + 1] - [rp(HIlI. [addrl - [ rplLO)] or II

(addd,xy 1hl1101 22 ppqq 4 20 [ addr + 11 - [ xy(HIIl. [addr] - [ xy(lOll
.t
Store contents of register pair or Index register to directly ad-
dressed memory.
LD A,IBC) OA 1 7 [ Al - [[ BC]l or [ Al - [[ DEli
A,IDEI 1A 1 7 load Accumulator from memory location addressed by the con-
tents of the specified register pair.
Co)
I
!'oJ
(J)
Table 3-4. A Summary of the zao Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO A
C
N
LD reg.(HU 01ddd110 1 7 I reg] - I[ HLII
to
Load register from memory location addressed by contents of HL.
...
LD (Bel,A 02 1 II BClI - I Alar [[ DEll - [ A) ~ 7
!
(DEl,A 12 1 7 Store Accumulator to memory location addressed by the contents to
'0_
of the specified register pair.
11:-0
> •
LD (HLl,reg 01110sss 1 7 [I HLII - I reg)
6 . ~
E .. Store register contents to memory location addressed by the con-
.~
tents of HL.
~ ~
~
LD reg.(xy+disp 11x1110101ddd110 3 19 [ reg] - [[ xy] + disp]
'"
disp Load register from memory location using base relative addressing.
E
~
LD xy +displ,reg 11x1110101110sss 3 19 [[ xy] + displ - I reg]
disp Store register to memory location addressed relative to contents of
Index regi ster.
LDIR ED BO 2 20116·· 0 0 0 Repeat until [ BCl ~ 0:
[[ DEll - [[ HLl]
I DEI - I DEI + 1
I HLI - I HLl + 1
~
[ BC] - [ BC] - 1
!!
'"
Transfer a block of data from the memory location addressed by

III
the contents of HL to the memory location addressed by the con-
-0
~
tents of DE. going from low addresses to high. Contents of BC
'"
0-
serve as a count of bytes to be transferred.
-!
LDDR ED B8 2 20/16·· 0 0 0 Repeat until [ BC] = 0:
~
~
I[ DEll - [[ HLl]
~ I DEl - [ DE) - 1
u
IHLl-IHLl-1
0
iii
[ BC] - [BCl - 1
Transfer a block of data from the memory location addressed by
the contents of HL to the memory location addressed by the con-
tents of DE. going from high addresses to low. Contents of BC
serve as a count of bytes to be transferred.
Co)
I
N
.....
Table 3-4. A Summary of the Z80 Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes Operation Performed
Cycles
C Z S PIO
AC N
LDI EO AO 2 16 X 0 0 [[ DEll [[ HLlI
[ DEl [DEI + 1
[ HLI [HLI + 1
[ BCI [ BCI - 1
Transfer one byte of data from the memory location addressed by
the contents of HL to the memory location addressed by the con-
tents of DE. Increment source and destination eddresses and decre-
ment byte count.
LDD ED AS 2 16 X 0 0 [[ DEll
'ii [ DE] - [ DEI - 1
•:l

[ BCI [ BCI - 1
c
0
Transfer one byte of data from the memory location addressed by

.t:. Ihe conlents of HL to Ihe memory location addressed by the con-
l,)
Iii tents of DE. Decrement source and destination addresses and byte
• II)
count.
'C
CPIR ED B1 2 20/16" X X X X Repeat until [AI =[[ HLll or [ BCI =0: c: 1
II
I A] - [[ HLll (only flags are affected)
.!
.. [ HLI [HLI + 1
c:
l! [ BCI [BCI - 1
I-
Compare contents of Accumulator with those of memory block ad-
'"
u
dressed by contents of HL. going from low addresses to high. Stop
.S!
III
when a match is found or when the byte count becomes zero.
CPDR ED B9 2 20/16" X X X X 1 Repeat until [AI =[[ HLll or [ BCI =0:
[A] - [[ HLlI (only flags are affected)
[ HLl [ HLI - 1
IBCI 1
Compare contents of Accumulator with those of memory block ad-
dressed by contents of HL. going from high addresses to low. Stop
when a match is found or when the byte count becomes zero.
CtJ
I
N
CD
Table 3-4. A Summary of the lSO Instruction Set (Continued)
Clock
Stetus
Type Mnemonic Operand Object Code Byte.
Cycles
Operation Performed
C Z S PIO
AC
N
CPI ED Al 2 16 X X X X 1 rAl - II HLIl (onlV flags are affected)
[ HLl - [HLl + 1
..,- I BC) - ! Bel - 1
t: '0
·~
Compare contents of Accumulator with those of memory location
~ t:
·.-
addresslid bv contllnts of HL. Increment addrllss and dllcrement ....
• t: C 0 byte count.
! ! ~
".r.
CPO ED A9 2 16 X X X X 1 I Al - [[ HLII (onlV flags are affectedI
~ u
[ HL] - [HLl - 1 u ~
o • - .
[ BCI - [ BCI - 1
CIIU1
Compare contents of Accumulator with those of memory location
addressed bV contents of HL. Decrement address and byte count
ADD A.(HLI 86 1 7 X X X 0 X D [ Al - [AI + II HLlI or [ Al - ( Al + [( xvI + disp]
A.(xV +disp) l1xll101 86 disp 3 19
.
Add to Accumulator using implied addressing or base relative ad-
dressing.
ADC A.IHLI 8E 1 7 X X X 0 X 0 [ Al - [AJ + II HLlJ + C or [ AI - ( Al + [[ xvi + disp! + C
A,(xV +disp) l1xl11018Edisp 3 19 Add with Carry using implied addressing or base relative address-
•u ing.
t:
i
SUB IHLI 96 1 7 X X X 0 X I I Al - rAI - II HLlI Or I Al - [ AI - [( xvI + displ

(XV + disp) l1xl1101 96 disp 3 19 Subtract from Accumulator using implied addressing or base rela-
IZ:
tive addressing.
~
SBC A.IHLI 9E 1 7 X X X 0 X 1 I Al - [ Al - [I i'lL]) - C or [ Al ~ [A] • II xvi + disp] - C
0
e
A,(xV+disp) llxl11D19Edisp 3 19 SUbtract with Carry using implied addressing or base relative ad-

:! dressing.
>-
AND IHLI A6 1 7 0 X X P 1 0 [ Al - I Al A [[ HLlI or ( Al ~ [AI A [[ xvi + displ
lii
'0
(XV + d i s p ~ l1xl1101 A6 disp 3 19 AND with Accumulator using implied addressing or base relative e:
0
addressing. u
• UI
OR (HL) 86 1 7 0 X X
...
I 0 rAl - [ Al V II HLlJ or [AI ~ [ Al V rr xyJ + disp!
(XV + displ l1x11101 B6 disp 3 19 OR with Accumulator using implied addressing or base relative ad-
dressing.
ff
~
Table 3-4. A Summary of the Z80 Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operend Object Code Byte.
Cycle.
Operation Performed
C Z S P/O
AC N
XOR IHU AE 1 7 0 :,( X P 1 0 I A] - I AI :!J-II HlJl or ( Al - I Al :!J- [[ xy] + displ
>-'ii (XV + disp) 1h1 1101 AE disp 3 19 Exclusive-OR with Accumulator usin9 implied addressing or base
.. .
relative addressing.
o :I
E .=
·..
CP (HU BE 1 7 X X X 0 X 1 [ Al - [[ HlJl or [ Al - [[ XV) + disp]
::i S
>-y
(XV + disp) 11x11101 BE disp 3 19 Compare with Accumulator using implied addressing or base rela-
..
tive addressing. Onlv the flags are affected.
• •
" ... c c
INC (HU 34 1 11 X X 0 X 0 II Hlll -II HlJl + 1 or II XV] + disp) - II xy) + disp) + 1
o •
u ..
(xy + disp) 11x1110134disp 3 23 Increment using implied addressing or base relative addressing.
• •
Ul';
DEC (HU 35 1 11 X X 0 X 1 [[ Hlll - II HLII - 1 or II xvI + disp] - [( XV) + disp] - 1 II:
(XV + disp) 11x1110135disp 3 23 Decrement using implied addressing or base relative addressing.
&y
7 oj:] RlC (HU CB 06 2 15 X X X P 0 0
~
(XV + disp) 11x11101 CB disp 4 23
II Hlll or [[ XV] + displ
06 Rotate contents of memory location (implied or base relative address-
ing) left with branch Carry
• ..
LEJ..
oJ:]
• ..
I7
0
II:
Rl (Hll CB 16 2 15 X X X P 0 0 ..
"
c

(xy + disp) 11x11101 CBdisp 4 23
II Hl)J or [I xvI + disp]
::
16
:c Rotate contents of memory location left through Carry.
Ul
>-
lj
.. o ~
Ii
E
RRC (Hll CB OE 2 15 X X X P 0 0 7

::i
{XV + disp} 11xl1101 CB disp 4 23
[( Hl)J or [( XV] + dispJ
OE
Rotate contents of memory location right with branch Carry.
W
I
W
o
Table 3-4. A Summary of the laO Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operlnd Object Code Bytes
Cyc'e.
Operation Performed
C 2 S P/O AC N
l:f7
·EJJ
o f
RR IHLI CB1E 2 15 X X X P 0 0 ~
Ixy + displ lhlll0l CBdisp 4 23
[[ HLlI or [[ xv1 + disp]
IE
Rolale conlenls of memory location right through Carry
SLA (HLI CB 26 2 15 X X X P 0 0
EJ.. I7
-4 O ~ O
'i;
(XV + disp) lhlll0l CB disp 4 23 II
::I [[ HLll or [[ xvI + disp]
.5
26
IShift contenlS of memory location lefl and clear LSB !Arithmelic ;:
0
g
Shift)
:l
.:l
o I 0
SRA (HLI CB 2E 2 15 X X X P 0 0 7 .- C
II:
I
...
(XV + disp) 1hll101 CB disp 4 23
c
[( HLlI or [( XV] + disp)
co
:: 2E
:E
I/)
>- Shift contents of memory location right and preserlle MSB
;;
E
(Arithmetic Shift).
II
~
SAL (HLl CB 3E 2 15 X X X
p
0 0
o -.J 7 ... 0 I
-8
(xV + disp) llxll101 CBdisp 4 23
[( HLlJ or I[ xvI + disp)
3E
Shift contents of memory location right and clear MSB (logical Shift)
W
I
W
Table 3-4. A Summary of the zao Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes
Cycles
Operation Performed
C Z S PIO A
C
N
LD reg.data OOdddllO VV 2 1 [reg] -data

load immediate into register.
..
LD rp.data16 OOxxOOOl yyyy 3 10 (rp) - datal 6 or [xy] - datal 6 01
'ij
xv.data16 1hlll0l 21 Vyyy 4 14 load 16 bits of immediate data into register pair or Index register.

E
lD (HLI.data 36 yy 2 10 II HLl] - data or [[ xy] + disp] - data
E
-
(xy+ displ. 1h11l01 36 disp VY 4 19 load immediate into memory location using implied or base relative
data addressing
JP label C3 ppqq 3 10 .
I PC) -label
a.
Jump to instruction at address represented by label.
E JR disp 18Idisp-2) 2 12 I PC] - I PCI + 2 + (disp-2)
:::I
Jump relative to p ~ e s e n t contents of Program Counter.
..,
JP (HLI E9 1 4 I PC] - I HLI or [PC) - I XV]
(xy) 1hlll01 E9 2 8 Jump to address contained in Hl or Index register.
CAll label CD ppqq 3 17 [[SP] -l)-[PCIHU]
II SP) - 2) - [ PC(lOI]
[ SP] - [SP] - 2
c:
[PCl -label
..
Jump to subroutine starting at address represented by label. :::I
..
• CAll cond.label 11 cccl 00 ppqq 3 10/17 Jump to subroutine if condition is satisfied; otherwise. continue in
a:
"
sequence.
c:
III
RET C9 1 10 [ PCILO)) - I[ SPJI
..
[PCIH1lJ - [[ SP] + 1]
0

[ SP] - I SPJ + 2
. ~
Return from subroutine.
S
~
RET cond 11 cccOOO 1 5/11 Return from subroutine if condition is satisfied; otherwise. continue
:::I
in sequence.
ell
c.>
I
to)
N
Table 3-4. A Summary of the laO Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes
Cycles
Operation Performed
C Z S PIO A
C
N
ADD A,data C6 yy 2 7 X X X 0 X 0 ( Al ~ I A] + data
Add immediate to Accumulator.
ADC A,data CE yy 2 7 X X X 0 X 0 { Al ~ I A] + data + C
Add immediate with Carry,
SUB data 06 yy 2 7 X X X 0 X 1 [ A] - I A] - data
I>
...
Subtract immediate from Accumulator .
•~
SBC 0 X [ A] ~ I A] - data - C I> A,data DE yy 2 7 X X X 1
a.
0
Subtract immediate with Carry.
I>
[ A] ~ I A] A data
...
AND data E6 yy 2 7 0 X X P 1 0

:s
AND immediate with Accumulator
I>
E
OR data F6 yy 2 7 0 X X P 1 0 [ A] ~ { A] V data
.5
OR immediate with Accumulator.
XOR data EE yy 2 7 0 X X P 1 0 [A] ~ I A] -¥Odata
Exclusive-OR immediate with Accumulator.
CP data FE yy 2 7 X X X 0 X 1 [AI - data
Compare immediate data with Accumulator contents; only the
flags are affected.
JP cond,label 11 cccO10 ppqq 3 10 If cond, then I PCI ~ label
Jump to instruction at address represented by label if the condition
is true.
JR C,disp 38 (disp-21 2 7/12 If C = 1, then (PCI ~ (PC) + 2 + (disp - 2)
c
Jump relative to contents of Program Counter if Carry flag is set.
:8
:s
JR NC,disp 30 (disp-21 2 7/12 If C =0, then (PC) - (PC) + 2 + Idisp -2)
c
Jump relative to contents of Program Counter if Carry flag is reset.
0
0
JR Z,disp 28 (disp-2) 2 7/12 If Z = 1, then I PCI ~ [PCl + 2 + (disp -2)
c
0
Jump relative to contents of Program Counter if Zero flag is set.
a.
E JR NZ,disp 20 (disp-2) 2 7/12 If Z = O. then I PCI ~ [PC] + 2 + (disp -2)
:::l
... Jump relative to contents of Program Counter if Zero flag is reset.
DJNZ disp 10 {disp-2l 2 8/13 IB] ~ ( B I - 1
If [B] ." 0, then (PC] + 2 + (disp -21
Decrement contents of B and Jump relative to contents of Program
Counter if result is not O.
W
I
W
W
Table 3-4. A Summary of the zao Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes Operation Performed
Cycles
C Z S P/O A
c
N
lD dstsrc 01 dddsss 1 4 [ dstl - [ srcl
Move contents of source register to destination register. Register
designations src and dst may each be A, B, C, 0, E, H or L.
LD A,I ED 57 2 9 X X I 0 0 [AJ-II]
Move contents of Interrupt Vector register to Accumulator.
LD A,R ED SF 2 9 X X I 0 0 [AI-[R)
Move contents of Refresh register to Accumulator.
LD I,A ED 47 2 9 [Il-[A)
Load Interrupt Vector register from Accumulator.
LD R,A ED 4F 2 9 [R)-[A]
Load Refresh register from Accumulator.
LD SP,HL F9 1 6 [SP)- [HLl
..
Move contents of HL to Stack Pointer. >
0
:E LD SP.xy 11x11101 F9 2 10 [SP]- [xy]
;; Move contents of Index register to Stack Pointer.
..
EX OE,HL EB 1 4 [DEI- ~ [HLl
'iii
..
Exchange contents of DE and HL,
~
EX AF,AF' 08 1 4 [ AF] - ~ [ AF'I
..
..
Exchange program status and alternate program status.
..
'iii
.. EXX 09 1 4
CBC) CBC')
Cl:
[DEl - ~ [ DE'l
[ HLl [HL')
Exchange register pairs and alternate register pairs.
Co)
I
Co)
~
Table 3-4. A Summary of the laO Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes
Cycles
Operation Performed
C Z 5 PIO AC
N
ADD A.reg 10000rrr 1 4 X X X 0 X 0 l AI - [AI + [reg]
Add contents of register to Accumulator.
AOC A.reg 10001 rrr 1 4 X X X 0 X 0 [ AI - [AI + [ reg] + C
Add contents of register and Carry to Accumulator.
SUB reg 10010", 1 4 X X X 0 X 1 [ AI - [ AI - [ reg]
Subtract contents of register from Accumulator.
SBC A.reg 10011", 1 4 X X X 0 X 1 [ AI - [ Al - [ reg] - C
Subtract contents of register and Carry from Accumulator.
AND reg 10000rrr 1 4 0 X X P 1 0 [ Al - [AI A [ regl
AND contents of register with contents of Accumulator.
OR reg 10110rrr 1 4 0 X X P 1 0 [ Al - [ AI V [ reg]
..
OR contents of register with contents of Accumulator.
..
XOR reg 10101", 1 4 0 X X P 1 0 [A] - [AI-¥-[ reg]


hclusive-OR contents of register with contents of Accumulator.
Q.
0
CP reg 10111rrr 1 4 X X X 0 X 1 [A] - [reg]
..
! Compare contents of register with contents of Accumulator. Only
..
'0. the flags are affected.
..
~
ADD HL.rp 00nl00l 1 11 X
}
0 [ HLl - [ HLl + [rpl

16-bit add register pair contents to contents of Hl.
..
..
ADC HL.rp [ HLl - [ HLl + [rp] + C
'0. ED Olxxl0l0 2 15 X X X 0
}
0
..
16-bit add with Carry register pair contents to contents of HL. a:
SBC HL.rp ED Olxx0010 2 15 X X X 0
}
1 [ HLl - [ HLl - [rp] - C
16-bit subtract with Carry register pair contents from contents of
HL.
ADD IX.pp DO 00xxl00l 2 15 X ? 0 [ IX] - [ IX) + [ pp]
16-bit add register pair contents to contents of Index register IX
(pp ~ BC. DE. IX, SPI
ADD IV." FD 00nl00l 2 15 X ? 0 [ IV] - [ IV] + [ rrl
1B-bit add register pair contents to contents of Index register IV
(n ~ BC. DE. IV. SPI
Co)
,
Co)
U1
Table 3-4. A Summary of the zao Instruction Set (Continued)
Clock
5t.tu.
Type Mnemonic Operand Object Code Byte. Oper.tion Performed
Cycle.
C Z 5 PIO AC
N
DAA 27 1 4 X X X P X Decimal adjust Accumulator, assuming that Accumulator contents are
the sum or difference of BCD operands.
CPL 2F 1 4 1 1 [A)-[AJ
II
Complement Accumulator (ones complement).
..
NEG ED 44 2 8 X X X 0 X
,
[A)-[AJ +' II
..
II
Negate Accumulator (twos complement).
a.
0
INC OOm'OO 1 4 X X 0 X 0 [ regl - [ reg] + 1

reg
.. Increment register contents.
II
'iiI
INC rp OOxxOO'1 1 6 ( rpJ - [ rp) + , or [ XV] - ( XV) + ,
II
II:
xy '1xlll0l 23 2 10 Increment contents of register or Index register.
DEC reg OUrrr101
,
4 X X 0 X 1 ! reg] - [ reg) - 1
Decrement register contents.
DEC rp 00xx10'1 1 6 [rp] - [rpl - , or! xVJ - [xy] - ,
xv llxl11012B 2 10 Decrement contents of register pair or Index register.
&y7 op
RLCA 07 1 4 X 0 0 4
II
[A]
..
Rotate Accumulator left with branch Carry.
..
..
0
II:
LE]4
oj:] ""
I7
c
RLA 17 1 4 X 0 0

..
:::
:c [AJ
qj
i
Rotate Accumulator left through Carry
..
II
q7 o ~
'co
II
II:
RRCA OF 1 4 X 0 0 ...
[AJ
Rotate Accumulator right with branch Carry.
W
I
Co)
0)
Table 3-4. A Summary of the zao Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operand Object Code Byte.
-
Operation Performed
Cycle.
C Z S Ip/O
"c
N
l:f7
:§J
oI
RRA IF 1 4 X 0 0 ..
(AJ
'Rotate Accumulator right through Carry.
&y
17
of:J
RlC reg CB OOOOOrrr 2 8 X X X P 0 0 ..
~ I [ reg]

IRotate contents of register left with branch Carry. ~
c
;::
L£].
oiJ
g
t7
9
CB 00010rrr 2 B X X X P 0 0
• •
Rl reg
..
~
0 [ reg]
II:
'I::J Rotate contents of register left through Carry,
c

l:j7
O ~
i:
.l:
RRC reg C8 ס ס o o 1 rrr 2 8 X X X P 0 0

C/)
..
• ..
[ reg)

'a.
Rotate contents of register right with branch Carry.

II:
l:j7
oI
.E}J RR reg CB 0001 1m 2 8 X X X p 0 0 ...
[ reg!
Rotate contents of register right through Carry.
SlA reg CB 00100rrr 2 8 X X X P 0 0
El-
I7
...
o J.- 0
[reg]
Shift contents of register left and clear lSB (Arithmetic ShiftJ.
W
I
W
.....
Table 3-4. A Summary of the laO Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO
Ac
N
Cj
o I
"0
SRA reg CB 00101rrr 2 8 X X X P 0 0 ...
[ reg]
Shift contents of register right and preserve MSB (Arithmetic Shift).
SRL reg CB 00111rrr 2 8 X X X P 0 0 0
-.1
7
...
o I
--EJ
;;
[ reg]

Shift contents of register right and clear MSB (Logical Shiftl.
:::I
c:
;::
I

c:
0
tJ
-
I 7 4 I 3 o I I 7 4 I 3 o I

RLD ED 6F 2 18 X X P 0 0
..
• ..

I
~
0 [Al
a::
'tl
c:

:::
Rotate one BCD digit left between the Accumulator and memory loca-
:c
tion (implied addressingl.Contents of the upper half of the Accumula-
III
a
tor are not affected.
J I

I
• RRD ED 67 2 18 X X P 0 0
I 7 4 I 3 o I I 7 4 I 3 o I
[AI

[[ HLlJ I
Rotate one BCD digit right between the Accumulator and memory
location (implied addressingl.Contents of the upper half of the Ac-
cumulator are not affected.
to)
I
(0)
co
Table 3-4. A Summary of the zao Instruction Set (Continuedl
Clock
Statu.
Type Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO
Ac
N
BIT b,reg CB 01bbbrrr 2 8 X ? ? 1 0 Z - reglbl
Zero flag contains complement of the selected register bit.
BIT b.IHlI CB 01bbbllO 2 12 X ? ? 1 0 Z - [[ HLlJlbl or Z - [[ xvI + displlb)
b.(xV" disp) 1lx11101 CB disp 4 20 Zero flag contains complement of selected bit of the memory loca-
e:
01bbb110 tion (implied addressing or base relative addressing).
.g
SET b.reg CB 11 bbbrrr 2 8 reglbl - 1
.!
Set indicated register bit.
:::l
a.
SET b.(HU CB 11bbb1 10 2 15 [( HLlJlb) - 1 or [[ XV] + dispJlb) - 1
'i:
II
b.lxV +disp) 1h11101 CB disp 4 23 Set indicated bit of memory location (implied addressing or
~
..
11bbb110
base relative addressing/.
iii
RES b.reg CB 10bbbrrr 2 8 reg(b) - 0
Reset indicated register bit.
RES b.(HU CB 10bbbll0 2 15 [[ HLlJlbl - 0 or [[ XV] + dispJlbl - 0
b.(xV + displ 1lx11 101 CB disp 4 23 Reset indicated bit in memory location limplied addressing or base
10bbb110 relative addressing).
PUSH pr 1'u0101 1 11 ([ SP]-ll - [ pdHIIl
xv 1h11101 E5 2 15 (( SPl-21- [ pr(LOl]
[ SP)- [ SPl-2
Put contents of register pair or Index register on top of Stack and
decrement Stack Pointer.
POP pr lhxOO01 1 10 [ pr(LOll - [[ SPII
.;0: xv 1h11101 E1 2 14 [ pr(HIlI - [[ SPI + 1I
u
[ SP] - [SP] + 2 II
..
(/)
Put contents of top of Stack in register pair or Index register and
increment Stack Pointer.
EX ISPl.HL E3 1 19 [ HI - - [[ SP] + 1]
(SPl,xv llxlllOl E3 2 23 [Ll -- [[ SPII
Exchange contents of HL or Index register and top of Stack.
CAl
,
CAl
CD
Table 3-4. A Summary of the zao Instruction Set (Continued)
Status
Type Mnemonic Operand Object Code Bytes
Clock
Operetion Performed
Cycles
C Z S P/O
Ac
N
01 F3 1 4 DiSable interrupts,
EI FB 1 4 Enable interrupts.
RST n 1lxxx1 11 1 11 [[ SP)-1] - [PCIHIIl
[[ SP)-2J - [ PCILOI)
..
[ SP] - [ SPI-2
a.
[PCl -18.nl,6
i
Restart at designated location.
S
RETI ED 40 2 14 Return from interrupt.
RETN ED 45 2 14 Return from nonmaskable interrupt.
1M 0 ED 46 2 B Set interrupt mode O. 1. or 2.
1 ED 56 2 B
2 ED 5E 2 B
SCF 37 1 4 1 0 0 C-1
• Set Carry flag.
a
II CCF 3F 1 4 X ? 0 C-C
et)
Complement Carry flag.
NOP 00 1 4 No operation - volatile memories are refreshed,
HALT 76 1 4 CPU halts. executes NOPs to refresh volatile memories.
"Execution time shown is for one iteration.
Table 3-5. Instruction Object Codes in Numerical Order
OBJECT CODE INSTRUCTION
00 NOP
01 yyyy LD BC.data16
02 LD (BCl.A
03 INC BC
04
INC B
05
DEC B
06 VV
LD B,data
07 RLCA
08 EX Af.AF
09 ADD HL,BC
OA LD A,lBC)
OB DEC BC
DC INC C
DO DEC C
OEvv
LO C,data
OF RRCA
10 disp-2 OJNZ disp
II yyyy Lo oE,data16
12 LO (DEI,A
13 INC DE
14 INC 0
15
DEC 0
16 vv
to o,data
17 RLA
18 disp-2 JR disp
19 ADD HL,OE
lA LD A,(OE)
18 DEC DE
lC INC E
10 DEC E
IE vv
LO E,data
1f RRA
20 disp-2 JR NZ,disp
21 yyyy LO HL,datal€
22 ppqq LO (addr),HL
23 INC HL
24 INC H
25 DEC H
26 vv LO H,data
27 OM
28 disp-2 JR Z,disp
29 ADO HUiL
2A ppqq LO HL,laddr)
28 DEC HL
2C INC L
20 DEC L
2E LO L,data
2f CPL
30 disp-2 JR NC,disp
31 yyyy LO SP,data16
32 ppqq LO (addrl,A
33 INC SP
34 INC (HU
35 DEC iHU
36 vv LO (HU,data
37 SCF
38 JR C.disp
OBJECT CODE INSTRUCTION
39 ADO HL,SP
3A ppqq LO A,laddr)
38 DEC SP
3C INC A
3D DEC A
3E vv LD A,data
3F CCf
4 Osss LO B,reg
46 LO B,(HLJ
4 lsss LO C,reg
4E LO C,(HU
5 Osss LD O,reg
56 LO O,(HLJ
5 lsss LO E,reg
5E LO E.lHU
6 Osss LO H.reg
66 LO H.lHU
6 lsss LO L,reg
6E LO L,(HU
7 Osss LO IHU,reg
76 HALT
7 lsss LO A,reg
7E LO A,(HU
80m ADD A,reg
86 ADD A,(HLI
8 1m ADC A,reg
8E AOC A,{HLl
90m SUB reg
96 SU8 (HU
9 lrrr sac A,reg
9E SBC A,{HU
AOm AND reg
A6 AND (HU
A 1m XOR reg
AE XOR (HU
BOrn OR reg
B6 OR (HLI
B 1m CP reg
BE CP (HU
CO RET NZ
Cl
pop
BC
C2 ppqq JP NZ,addt
C3 ppqQ JP addr
C4 ppqQ CALL NZ,addr
C5 PUSH BC
C6 vv ADD A,data
C7 RST OOH
C8 RET Z
C9 RET
CA ppqq JP Z,addr
CB 0 Orr, RLC reg
CB06 RLC (HU
ca 0 1,rr RRC reg
CB Of RRC (HU
CB 1 Orrr RL reg
CB 16 RL {HLI
CB 1 1m RR reg
3-40
Table 3-5. Instruction Object Codes in Numerical Order (Continued)
OBJECT CODE INSTRUCTION
CB IE RR (HU
CB 2 Om SLA reg
CB 26 SLA (HU
CB21m SRA reg
CB 2E SRA (HLI
CB 31m SRL reg
CB 3E SRL (HLI
CB 01bbbm BIT b.reg
CB 01bbbl10 BIT b.IHU
• CB IObbbm RES b.reg
CB IObbbl10 RES b.IHU
CB l1bbbm SET b.reg
CB llbbbllO SET b.IHL)
CC PPQq CALL Z,addr
CO PPQq CALL addr
CE yy ADC A,data
CF RST 08H
00 RET NC
01
pop
DE
02 PPQq JP NC,addr
03 yy OUT (portl.A
D4 PPQq CALL NC,addr
05 PUSH DE
Deyy SUB data
07 RST 10H
D8 RET C
09 EXX
DA PPQq JP C,addr
DB yy IN A,(port)
DC ppqq CALL C,addr
DO OOxx 9 ADD IX,pp
DO 21 yyyy LD IX,dllta16
DO 22 PPQq LO (addrl.lX
DO 23 INC IX
DO 2A PPQq Lo IX,(addrl
DO 2B DEC IX
DO 34 disp INC (IX + displ
00 35 disp DEC (IX + diep)
DO 36 disp yy Lo (IX + displ.dlltl
DO 01ddd110 disD LD reg,(lX + diapl
00 I Oass disD Lo (IX + displ.reg
DO S6 disp ADD A,(lX+disp)
DO SE disp ADC A,(IX + diap)
DO 96 disp SUB (IX +disp)
DO 9E disp SBC A'(lX+disp)
DO A8 disp AND (IX + disp)
DO AE disp XOR (IX + displ
DO B6 disp OR (IX + disp)
DO BE disp CP (lX+disp)
00 CB disp 06 RLC (lX+disp)
00 CB disp DE RRC (IX +displ
DO CB disp 16 RL IIX +disp)
DO CB disp 1E RR (IX +diap)
DO CB disp 26 SLA (IX +disp)
DO CB disp 2E SRA (IX +disp)
DO CB disp 3E SRL (lX+displ
DO CB disp 01bbbl 10 BIT b,(lX + displ
OBJECT CODE INSTRUCTION
DO CB disp lObbbl10 RES b.(lX+displ
DO CB disp l1bbb110 SET b,(lX+displ
DO El pop
IX
DO E3 EX (SPI.IX
DO E5 PUSH IX
DO E9 JP (IX)
DO F9 LD SP.IX
DE yy SBC A,data
OF RST ISH
EO RET PO
E1
pop
HL
E2 PPQq JP PO.addr
E3 EX (SP).HL
E4 PPQq CALL PO.addr
E5 PUSH HL
E6 yy AND data
E7 RST 20H
E8 RET PE
E9 JP IHLI
EA PPQq JP PE,addr
EB EX OE,HL
EC ppqq CALL PE,addr
EO 01dddOOO IN reg,(CI
ED 01sss001 OUT (CI.reg
EO 01xx 2 sse HL,rp
EO 01xx 3 ppqq LD (addrl.rp
EO 44 NEG
ED 45 RETN
ED 01Onnl10 1M m
EO 47 LD I.A
ED 01xx A ADC HL,rp
ED 01xx B ppqq LD rp,(addrl
ED 40 RETI
ED 4F Lo R,A
EO 57 Lo A.I
ED 5F Lo A,R
ED 67 RRO
EO 6F RLO
EO AO LDI
ED Al CPl
ED A2 INI
ED A3 OUTI
EO AS LOO
ED A9 CPO
EO AA iND
ED AS OUTO
ED SO LDIR
ED B1 CPlR
ED 82 INIR
ED B3 OTIR
ED 88 LDDR
ED B9 CPOR
EO SA INDR
EO Be OTOR
EE yy XOR dIIta
EF RST 2SH
3-41

ADC A,data - ADD IMMEDIATE WITH CARRY TO
ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC Pia N
Data

I
Memory
..

xx
.. '" Program
mmmm mmmm+2
""""-
Memory

CE
I
-
yy
mmmm
mmmm+ 1
mmmm+2
mmmm+ 3
ADC A.
--
CE
data
--
yy
1 010
1 1 00
o
001 1
o1 1 1
Add the contents of the next program memory byte and the Carry status to the Ac-
cumulator.
Suppose xx=3A16. yy=7C16. and Carry=O. After the instruction
ADC A.7CH
has executed. the Accumulator will contain 8616:
3A
7C
Carry
1 sets S to 1
No carry. set C to 0
a.If 1= 1. set P/0 to 1
1011 0110
f.J ,esult set Z to 0
"'-------Carry. set AC to 1
Addition instruction. set N to 0
The ADC instruction is frequently used in multibyte addition for the second and subse-
quent bytes.
3-43
ADC A,reg - ADD REGISTER WITH CARRY TO
ACCUMULATOR
F
A
S.C
D.E
H.L
SP
PC
IX
IV
I
R
SZACP/ON!
i
- ~ ~
~
r,
~ x + v y + c
}-l
xx
contents of
A,B.C,D,E,H
orLisvy
- ~
mmmm mmmm + 1
........
I
I
Data
Memory
Program
Memory
10001xxx mmmm
....__--1mmmm + 1
....__--1mmmm + 2
1-__...... mmmm +3
reg
--
ADC A
-..-
10001 xxx
-.-
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Add the contents of Register A. B. C. D, E, H or L and the Carry status to the Accumula-
tor.
Suppose xx=E316, Register E contains A016. and Carry=l. After the instruction
ADC AE
has executed, the Accumulator will contain 8416:
E3
AO
Carry
1 1 1 0 001 1
1010 0000
1
1 sets S to 1
Carry. set C to 1
1000 01 00
t
u
LNon.mo ,.sult. Sol Z to 0
,,",-----No carry. set AC to 0
1¥ 1=0, set P/0 to 0 Addition instruction. set N to 0
The ADC instruction is most frequently used in multibyte addition for the second and
subsequent bytes.
3-44
ADC A,(HL) - ADD MEMORY AND CARRY TO
ADC A,(IX+disp) ACCUMULATOR
ADC A,(IY+disp)
S ZAcP/ON C Data
Q
m
mm+l
mmmm+2
~ - - - t mmmm + 3
IxlXIXlxlOIX
Memory
l
- ~ ~
~ X
_ I.,,:,x,+ YV + C
YV PPQ
,
QQ
PP
- ~ V
Program
mmmm ~ m m m + 1
Memory
I BE mmm
I
mm
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of ADC A.(HU:
ADC A(HU
----
8E
Add the contents of memory location (specified by the contents of the HL register pair)
and the Carry status to the Accumu lator
Suppose xx=E316, yy=A016, and Carry=l. After the instruction
ADC A(HU
has executed, the Accumulator will contain 8416:
E3
AO
Carry
1110 0011
1010 0000
1
1 sets S to 1
Carry. set C to 1
1¥ 1=0. set P/O to 0
1000 0100
.fJ LNon,,.,o cesult. set Z to a
~ - - - - No carry, set AC to 0
Addition instruction, set N to 0
ADC A(lX+disp}
~ - . . -
DO BE d
Add the contents of memory location (specified by the sum of the contents of the IX
register and the displacement digit d) and the Carry to the Accumulator
ADC A(lY+disp)
~ - . -
FD BE d
This instruction is identical to ADC A(lX+displ. except that it uses the IY register in-
stead of the IX register
The ADC instruction is most frequently used in multibyte addition for the second and
subsequent bytes.
3-45
ADC HL.rp - ADD REGISTER PAIR WITH CARRY TO HAND L
S Z AC P/O N C
F ~
Data
Memory
A
B.C
D,E
H.L
SP
PC
IX
IY
I
R
Be, DE, HL or SP
:" contain yyyy
xx xx
- ~ x x + y y y y
..""""
+C
mmmm
~
~ m m m + v
I
I
Program
Memory
ED mmmm
01xxl010 mmmm + 1
mmmm+2
t-----t mmmm + 3
K
EDOlxxl010
-..-
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Add the 16-bit value from either the BC, DE. HL register pair or the Stack Pointer. and
the Carry status, to the HL register pair.
Suppose HL contains A53616, BC contains 104416, and Carry=l. After execution of
ADC HLBC
Addition instruction, set N to 0 011-0=0, set P!O to 0
the HL register pair will cqrtain:
A536 1010{)101 0011 0110
1044 0001 000001000100
Carry 1
1011010101111011
1 sets S tc 1 V t.Ncncmc result. set Z to 0
No carry, set C to 0 1 No carry, set AC to 0
The ADC instruction is most frequently used in multibyte addition for the second and
subsequent bytes.
3-46
:xx+vvr
xx
"
Program
mmmm mmmm + 2
""""'- Memory
I C6
I
.....
YV
ADD A,data - ADD IMMEDIATE TO ACCUMULATOR
5 Z AcP/O N C Data
F(E[E[[IE]]JEJ Memory
to
S,C
D,E
H,L
SP
PC
IX
IY
I
R
mmmm
mmmm+ 1
mmmm+2
mmmm+3
ADD A, data
---..-- -.-
C6 yy
Add the contents of the next program memory byte to the Accumulator,
Suppose xx=3A16. yy=7C16. and Carry=O, After the instruction
ADD A,7CH
has executed. the Accumulator will contain 8616:
3A 001 1 1 01 0
7C = 0 1 1 1 1 1 0 0
101U
110
1 sets S 10 1 t LNon-ze""esu,tset Z to 0
No carry. set C to 0 - Carry. set AC to 1
o¥ 1= 1: set P/0 to 1
This is a routine data manipulation instruction,
3-47
Addition instruction. set N to 0
Data
Memory
Program
Memory
l0000xxx mmmm
mmmm+ 1
t-----1mmmm + 2
mmmm+3
t-----1

..

r.
} 0001..,
xx

H or L is yy
. r 3>
mmmm _ + 1
I
I
F
ADD A.reg - ADD CONTENTS OF REGISTER TO
ACCUMULATOR
S Z Ac P/O N C
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
ADD reg
-v-" -.-
10000 xxx
000 for reg=B
001 for reg=C
010 for reg""-D
011 for reg=E
100 for reg =H
101 for reg=L
111 for reg=A
Add the contents of Register A. B. C. D. E. H or L to the Accumulator.
Suppose xx=E316. Register E contains A016. After execution of
ADD A.E
Addition instruction. set N to 0
1 sets S to 1
Carry. set C to 1
1¥ 1=0. set PIO to 0
the Accumulator will contain 8316:
E3 1 1 1 0 00 1 1
AO = 1 0 1 0 0 0 0 0
1000 0011
r LNon-wo msull. set Z to a
.....-----No carry. set AC to 0
This is a routine data manipulation instruction
3-48
ADD A.(HL) - ADD MEMORY TO ACCUMULATOR
ADD A. (IX+disp)
ADD A.(lY+disp}
d
m
m+ 1
m +2
m + 3
Data
X X X X 0 X
Memory
-
"""" xx
"" xx+yy
yy ppqq+

-
Program
mmmm mmmm+3
ppqq
I--
........
Memory
I 00 mmm
I 86

mmm
d mmm
mmm
S ZACP/ON C

A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
The illustration shows execution of ADD A,(IX+disp).
ADD A,(IX+disp}
--...-- --
DO 86 d
Add the contents of memory location (specified by the sum of the contents of the IX
register and the displacement digit d) to the contents of the Accumulator
Suppose ppqq=4000 16. xx= 1A16. and memory location 400F16 contains 5016, After
the instruction
Addition instruction. set N to 0 o¥O=O; set P/O to 0
ADD A(lX+OFH)
has executed. the Accumulator will contain 6A16,
lA = 0001 1010
50 = 0 1 0 1 0 0 0 0
o1 1 0 101 0
o sets S to 0 fJ LNon-,em ,""It. set Z to 0
No carry. set C to 0 . No carry. set AC to 0
ADD A(lY+disp)

FD 86 d
This instruction is identical to ADD A(lX+disp). except that it uses the IY register in-
stead of the IX reg ister.
ADD A(HL)

86
This version of the instruction adds the contents of memory location, specified by the
contents of the HL register pair. to the Accumulator.
The ADD instruction is a routine data manipulation instruction
3-49
ADD HL,rp - ADD REGISTER PAIR TO HAND L
Data
Memory
A
B.C
D.E
H.l
SP
PC
IX
IY
I
R
Be, DE, HL or SP
=t." YVVYv.J
-
-,
xx xx II. xxxx + VYYY

mmmm
-


I
I
Program
Memory
OOxxl001 mmmm
mmmm+ 1
1------1mmmm + 2
mmmm+3
1------1
1K
00 xx 1001
--- 00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Add the 16-bit value from either the BC, DE. HL register pair or the Stack Pointer to the
HL register pair.
Suppose HL contains 034A16 and BC contains 214C16. After the instruction
ADD HLBC
has executed. the HL register pair will contain 249616.
034A 0000 0011 0100 1010
214C = 0010 0001 0100 1100
001aa100 1001 a11 a
No carry. set C to 0....J carry. set AC to a
Addition instruction. set N to a
The ADD HLHL instruction is equivalent to a 16-bit left shift.
3-50
ADD xy,rp - ADD REGISTER PAIR TO INDEX REGISTER
Data
Memory
A
B.C
D.E
H,L
SP
PC
IX
IV
I
R
rr 55
- ~ ~ mmmm mmmm + 2
ppqq t'--.. ..........
..................
-.
" G q q + r r 5 ~
I
Program
Memory
llvl1101 mmmm
OOxx 1001 mmmm + 1
1-__---1mmmm + 2
1-__........ mmmm + 3
The illustration shows execution of ADD IX,DE,
ADD xi,.rp
/Xk
11 \l. 11 a1 OO-¥- 1001
"'_-----J. ,
ofor Index register=IX 00 for rp is register pair BC
1 for Index register=IY 01 for rp is register pair DE
10 for rp is specified Index register
11 for rp is Stack Pointer
Add the contents of the specified register pair to the contents of the specified Index
register.
Suppose IY contains 4FF016 and BC contains 000F16 After the instruction
ADD IY.BC
has executed. Index Register IY will contain 4FFF16
3-51
AND data -AND IMMEDIATE WITH ACCUMULATOR
S Z AC P/O N C
F ~
Data
Memory
A
B,C
O,E
H,L
SP
PC
IX
IV
I
R
- ~ ").
xx
_ - I ~ xx·yy
-
" mmmm
-
-r mmmm+ 2
Program
.........
Memory
I E6
I '-
yy
mmmm
mmmm+1
mmmm+2
mmmm+3
AND
--..-
data
--
E6 yy
AND the contents of the next program memory byte to the Accumulator.
Suppose xx=3A16- After the instruction
AND 7CH
has executed, the Accumulator will contain 3816.
3A 001 1 1 0 1 0
7C = 0 1 1 1 1 1 0 0
0011 1000
osets S to o..J LThree 1 bits, set PIO to 0
LNon-zero result. set Z to 0
This is a routine logical instruction: it is often used to turn bits "off' For example. the
instruction
AND 7FH
will unconditionally set the high order Accumulator bit to 0,
3-52
AND reg -AND REGISTER WITH ACCUMULATOR
F
A
B.C
D.E
H,L
SP
PC
IX
IY
I
R
s Z ACP/O N C Jt'
~
f,
-...,. xx'vy
"-
}-,oJ'OI
xx
A,B,C,D,E,
H or L is yy
_ Jt'
mmmm
-
Il mmmm + 1
.......
I
I
Data
Memory
Program
Memory
10100xxx mmmm
mmmm+ 1
t-----t
mmmm
+ 2
mmmm+3
t---........
AND reg
~ -..--
10100 xxx
-..-
000 for reg=B
001 for reg=C
010 for reg =0
011 for reg=E
100 for reg =H
101 for reg=L
111 for reg=A
AND the Accumulator with the contents of Register A, B, C, 0, E, H or L. Save the resu It
in the Accumulator.
Suppose xx=E316, and Register E contains A016 After the instruction
AND E
has executed, the Accumulator will contain A016
001 1
0000
0000
1==Two 1 bit>. se1 P/O 10 1
Non-zero result set Z to 0
E3 1 1 1 0
AO = 1010
----......;.--
101 0
sets S to 1.-J
AND is a frequently used logical instruction
3-53
AND (HL) - AND MEMORV WITH ACCUMULATOR
AND (lX+disp)
AND (IV+disp)
+d
Data
m
m+ 1
d mmmm+2
1--;;""'--1 mmmm + 3
x X 1 X 0 0
Memory
- ~ ,-
xx

xxoyy
yy ppqq
........
~
,
Program
mmmm
mmmm+3
ppqq
........
Memory
ppqq+dJ-
I FD mmm
I A6 mmm
S Z AC P/O N C
F ~
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of AND (IY+disp).
AND (IY +disp)
~ -:-r-
FD A6 d
AND the contents of memory location (specified by the sum of the contents of the IY
register and.the displacement digit d) with the Accumulator
Suppose xx=E316, ppqq=400016, and memory location 400F16 contains A016. After
the instruction
AND (IY+OFH)
has executed, the Accumulator will contain A016
o1 1 1
0000
0000
LTWO 1 bits, set PIO to 1
LNon-zero result. set Z to 0
E3 1 1 1 a
AO = 1 01 0
-------
1 0 1 0
sets S to 1..J
AND (IX+disp)
~ - . . -
DD A6 d
This instruction is identical to AND (lY+displ. except that it uses the IX register instead
of the IY register.
AND (HL)
--.-..
A6
AND the contents of the memory location (specified by the contents of the HL register
pair) with the Accumulator.
AND is a frequently used logical instruction.
3-54
BIT b,reg - TEST BIT b IN REGISTER reg
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
s tAC P/O N C 1
~
r
b
yyy yyyy,
_ . ~
mmmm mmmm + 2
.......
I
I
BIT b, reg
-.- --.-
--
CB 01 bbb xxx
-.-
--
Bit Tested Register
a 000 000 B
1 001 001 C
2 010 010 0
3 all all E
4 100 100 H
5 101 101 l
6 110 111 A
7 111
Data
Memory
Program
Memory
CB mmmm
01bbbxxx mmmm + 1
mmmm+2
I------t mmmm + 3
Place complement of indicated register's specified bit in Z flag of F register.
Suppose Register C contains 1110 1111. The instruction BIT 4,C will then set the Z flag
to 1, while bit 4 in Register Cremains O. Bit a is the least significant bit.
3-55
BIT b, (HL) - TEST BIT b OF INDICATED MEMORY POSITION
BIT b,(lX+disp)
BIT b, (lY+disp)
5 Z AC Pia N C
F ~
Data
Memory
q
mm
mm+l
mmmm+2
1-----1mmmm + 3
b
.-/-
yyyByyyy
Pi
PP
qq
- ~ :V
Program
mmmm ~ m m m + 2
Memory
I CB mm
I
01bbbll0 mm
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of BIT 4.(HL). Bit a is the least significant bit
BIT b.
(HL)
-...- -,- -,-
CB 01 bbb 110
---
Bit Tested bbb
a 000
1 001
2 010
3 all
4 100
5 101
6 110
7 111
Test indicated bit within memory position specified by the contents of Register HL. and
place bit's complement in Z flag of the F register.
Suppose HL contains 4000H and bit 3 in memory location 4000H contains 1. The in-
struction
BIT 3.(HL)
will then set the Z flag to O. while bit 3 in memory location 4000H remains 1.
2K-
DD CB dOl bbb 110
bb.b is the same as in BIT b.(HL)
Examine specified bit within memory location indicated by the sum of Index Register IX
and disp. Place the complement in the Z flag of the F register.
3-56
Suppose Index Registel' IX contains 4000H and bit 4 of memory location 4004H is O.
The instruction
BIT 4, (IX+4H)
will then set the Z flag to 1, while bit 4 of memory location 4004H remains 0
BIT b,(IY+disp)

bbb is the same as in BIT b,(HU
This instruction is identical to BIT b, (Ix+displ. except that it uses the IY register instead
of the IX register.
CALL label - CALL THE SUBROUTINE IDENTIFIED IN THE
OPERAND
Data
xxxx-2
xxxx-l
xxxx
mmmm
{
mmmm+ 1
...... mmmm + 2
1------4mmmm + 3
Memory
I mm+3
I
-C:..xxxx-2
mm

xxxx,
'#
mmmm

Program
Memory
I CD
I
pp
5 Z Ac PIO N c
FCIIIIIJ
A
S,C
D.E
H.L
SP
PC
IX
IY

R
CALL label
"'-v-' -..-
CD ppqq
Store the address of the instruction following the CALL on the top of the stack: the top
of the stack is a data memory byte addressed by the Stack Pointer Then subtract 2
from the Stack Pointer in order to address the new top of stack. Move the 16-bit address
contained in the second and third CALL instruction object program bytes to the Pro-
gram Counter. The second byte of the CALL instruction is- the low-order half of the ad-
dress, and the third byte is the high-order byte.
Consider the instruction sequence:
CALL
AND
SUBR
7CH
SUBR
After the instruction has executed, the address of the AND instruction is saved at the
top of the stack. The Stack Pointer is decremented by 2. The instruction labeled SUBR
will be executed next
3-57
CALL condition, label - CALL THE SUBROUTINE IDENTIFIED IN
THE OPERAND IF CONDITION IS
SATISFIED
CALL condition. label
T ~ I
11 xxx 100 pp qq
T Condition Relevant Flag
-'-
000 NZ Non-Zero Z
001 Z Zero Z
010 NC Non-Carry C
all C Carry C
100 PO Parity Odd PIO
101 PE Parity Even PIO
110 P Sign Positive S
111 M Sign Negative S
This instruction is identical to the CALL instruction. except that the identified
subroutine will be called only if the condition is $atisfied; otherwise. the instruction se-
quentially following the CALL condition instruction will be executed.
Consider the instruction sequence:
I
CALL : COND.SUBR
_------1 condition not satisfied
AND 7CH
condition
satisfied
SUBR
If the condition is not satisfied. the AND instruction will be executed after the CALL
COND.SUBR instruction has executed. If the condition is satisfied. the address of the
AND instruction is saved at the top of the stack. and the Stack Pointer is decremented
by 2. The instruction labeled SUBR will be executed next.
3-58
CCF - COMPLEMENT CARRY FLAG
S Z AC P/O N C
Fc:r::r::I:IJEJ........ - - - - - - - ~ ~ C : X J
Data
Memory
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
,
mmmm - -. mmmm + 1
---
I
I
Program
Memory
3F mmmm
I-__-Immmm + 1
mmmm+2
I----I
mmmm
+ 3
CCF
3F
Complement the Carry flag. No other status or register contents are affected
3-59
CP data - COMPARE IMMEDIATE DATA WITH
ACCUMULATOR
t
s Z AC Pia N C
Data

Memory

- xx
mmmm

Program
Memory
I FE
I
yy
F
A
B.C
D.E
H.l
SP
PC
IX
IV
I mmmm
R mmmm+ 1
mmmm+2
mmmm+3
CP data
FE yy
Subtract the contents of the second object code byte from the contents of the Ac-
cumulator. treating both numbers as simple binary data. Discard the result; ie.. leave
the Accumulator alone. but modify the status flags to reflect the result of the subtrac-
tion.
Suppose xx=E316 and the second byte of the CP instruction object code contains
AD16 After the instruction
CP OAOH
has executed. the Accumulator will still contain E316. but statuses will be modified as
follows:
1¥1 =0. set PIO to 0
Notice that the resulting carry is complemented.
E3
AO
osets S to 0
No borrow. set C to 0
1110 0011
1010 0000
0100 0011
t
u
LNoo-mo ,e,"lt. set Z to 0
'-------Noborrow. set AC to 0
Subtract instruction. set N to 1
3-60
CP reg - COMPARE REGISTER WITH ACCUMULATOR
F
A
B,C
D,E
H,l
SP
PC
IX
IY
I
R
-
t
1
I's Z AC P/O N C"
- XX-
yy
')
tEIEIEIEIIEl
I
} l
xx
Contents of
____A.B,C,D,E,H
or Lis yy
-

mmmm
-
I
I
Data
Memory
Program
Memory
10111xxx mmmm
mmmm+ 1
mmmm + 2
__-I mmmm + 3
CP reg
--.- --
10111 xxx
-.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 forreg=H
101 forreg=L
111 for reg=A
Subtract the contents of Register A, B, C D. E, H or L from the contents of the Ac-
cumulator. treating both numbers as simple binary data. Discard the result; i.e.. leave
the Accumulator alone. but modify status flags to reflect the result of the subtraction.
Suppose xx=E316 and Register B contains A016. After the instruction
CP B
has executed, the Accumulator will still contain E316, but statuses will be modified as
follows:
E3
AO
a sets S to a
No borrow. set C to a
= 1110 0011
1010 0000
0100 0011
fJ ",suit set Z to 0
.........----No borrow, set AC to 0
1¥ 1=0. set PIC to a
Notice that the resulting carry is complemented.
3-61
Subtract instruction, set N to 1
CP (HL) - COMPARE MEMORY WITH ACCUMULATOR
CP (lX+disp)
CP (lY+disp)
qq
mmm
mmm+1
mmmm+2
t-----t mmmm + 3
t
;' S
Z AC pia N C Data
~
Memory
xx _r ""'"
yy
1
'- xx-yy -/ _
pp qq
- ~ V
Program
mmmm _ I....:.mmm +'
Memory
I BE m
I
m
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of CP (HL):
CP (HL)
~
BE
Subtract the contents of memory location (specified by the contents of the HL register
pair) from the contents of the Accumulator. treating both numbers as simple binary
data Discard the result: ie.. leave the Accumulator alone. but modify status flags to
reflect the resu It of the subtraction
Suppose xx=E316 and yy=A016· After execution of
CP (HL)
the Accumulator will still contain E316. but statuses will be modified as follows:
E3 1 1 1 0 00 1 1
AO = 0 1 1 0 0 0 0 a
0100 0011
a sets S to a t
U
LNOn",em ,esult. set Z to 0
No borrow. set C to a . No borrow. set AC to-O
1¥ 1=0. set P/O to a
Notice that the resu Iting carry is complemented.
CP (IX+disp)
---...-- -..--
Subtract instruction. set N to 1
DO BE d
3-62
Subtract the contents of memory location (specified by the sum of the contents of the
IX register and the displacement value d) from the contents of the Accumulator. treat-
ing both numbers as simple binary data. Discard the result; i.e., leave the Accumulator
alone, but modify status flags to reflect the result of the subtraction.
CP (IY+disp)
---
FD BE d
This instruction is identical to CP (IX+displ. except that it uses the IY register instead of
the IX register.
CPO-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT ADDRESS AND BYTE COUNTER
yy ppqq
Data
Memol')!
ED mmmm
A9 mmmm+ 1
mmmm+2
......----1 mmmm + 3
5 Z Ac P/O N C
FfXT'XTXT'"J'i'n 5et if 8C-l O.
reset otherwise
A xx
B,C tt uu
D.E

H.l SP ..
PC mmmm Program
IX Memol')!
IV I----------------t
I
R
CPD
'-...-'
ED A9
Compare the contents of the Accumu lator with the contents of memory location
(specified by the HL register pairl. If A is equal to memory. set Z flag. Decrement the HL
and BC register pairs. (BC is used as the Byte Counter)
3-63
Suppose xx=E316. ppqq=400016. BC contains 000116. and yy=A016. After the in-
struction
CPO
has executed, the Accumulator will still contain E316. but statuses will be modified as
follows:
E3 1 1 1 0 001 1
AO 1 01 0 0000
0100 0011
o sets S to O.J fJ LNon-mo 'e,,". set Z to 0
'-------No borrow. set AC to 0
The P/O flag will be reset
because BC-1 =0
Subtract instruction involved.
set N to 1
Carry not affected.
The HL register pair will contain 3FFF16, and BC=O
CPDR-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT ADDRESS AND BYTE COUNTER.
CONTINUE UNTIL MATCH IS FOUND OR BYTE
COUNTER IS ZERO
CPOR
--..--
ED B9
This instruction is identical to CPO. except that it is repeated until a match is found or
the byte counter is zero. After each data transfer, interrupts will be recognized and two
refresh cycles will be executed.
Suppose the HL register pair contains 500016, the BC register pair contains 00FF16.
the Accumu lator contains F916' and memory has contents as follows:
Location Contents
5000
16 AA16
4FFF16 BC16
4FFE16 1916
4FFD16 7A16
4FFC16 F916
4FFB16 0016
After execution of
CPOR
the P/O flag will be 1. the Z flag will be 1, the HL register pair will contain 4FFB16, and
the BC register pair will contain 00FA16.
3-64
CPI-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT BYTE COUNTER.
INCREMENT ADDRESS
S Z AC P/O N C

otherwise
A XX
B.C tt uu
D,E
H.L PP QQ
SP
PC mmmm
IX
IY
I
R
CPI

ED A1
Data
Memory
YY PPQQ
Program
Memory
ED mmmm
Al mmmm+ 1
...-.----1 mmmm + 2
.....__--1 mmmm + 3
Compare the contents of the Accumulator with the contents of memory location
(specified by the HL register pair). If A is equal to memory, set the Z flag. Increment the
HL register pair and decrement the BC register pair (BC is used as Byte Cou nter)
Suppose xx=E316. ppqq=400016. BC contains 003216. and yy=E316 After the in-
struction
CPI
has executed. the Accumulator will still contain E316, but statuses will be modified as
follows:
E3 1 1 1 1 0 a 1 1
-E3 0 0 0 0 1 1 0 1
0000 0000
osets S to 0--1 fJ LResult is O. set Z to 1
1,...-----No borrow. set AC to 0
The PIO flag will be set
because BC-1 l' O.
Subtract instruction involved.
set N to 1,
Carry not affected
The HL register pair will contain 400116. and BC will contain 003116.
3-65
CPIR - COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT BYTE COUNTER.
INCREMENT ADDRESS.
CONTINUE UNTIL MATCH IS FOUND
OR BYTE COUNTER IS ZERO
CPIR
----
ED B1
This instruction is identical to CPI. except that it is repeated until a match is fou nd or
the byte counter is zero. After each data transfer interrupts will be recognized and two
refresh cycles will be executed.
Suppose the HL register pair contains 450°16. the BC register pair contains 00FF16.
the Accumulator contains F916. and memory has contents as follows:
Location Contents
4500
16 AA16
4501
16
15
16
4502
16 F916
After execution of
CPIR
the P10 flag will be 1. and the Z flag will be 1. The HL register pa ir will conta in 450316.
and the BC register pair will contain OOFC16.
3-66
CPL - COMPLEMENT THE ACCUMULATOR
S Z ACP/O N C
FCI:IIIIrIJ
Data
Memory
A
B.C
D.E
H,L
SP
PC
IX
IV
I
R
- ~
~
xx xx
"""-
"
mmmm mmmm+ 1
"""-
I
I
Program
Memory
2F mmmm
1-----1 mmmm + 1
I---......t mmmm + 2
I---......t mmmm + 3
CPL
2F
Complement the contents of the Accumu lator. No other register's contents are
affected.
Suppose the Accumu lator contains 3A16. After the instruction
CPL
has executed, the Accumulator will contain C516·
3A = 001 1
Complement = 1 1 00
1 0 1 0
o1 01
This is a routine logical instruction. You need not use it for binary subtraction, there are
special subtract instructions (SUB, SBC)
3-67
DAA - DECIMAL ADJUST ACCUMULATOR
S Z AC P/O N C

Data
Memory
A
B.C
D,E
H,L
SP
PC
IX
IY
I
R
xx
-
""-decimal
V mmmm _ I....:,mmm + 1
I
I
Program
Memory
27 mmmm
mmmm+ 1
1-----1mmmm + 2
1--__-1 mmmm + 3
DAA
27
Convert the contents of the Accumulator to binary-coded decimal form. This instruc-
tion should only be used after adding or subtracting two BCD numbers: ie, look upon
ADD DAA or ADC DAA or INC DAA or SUB DAA or SBC DAA or DEC DAA or NEG DAA
as compound, decimal arithmetic instructions which operate on BCD sources to gener-
ate BCD answers.
Suppose the Accumu lator contains 3916 and the B reg ister contai ns 4716 After the i n-
structions
ADD B
DAA
have executed, the Accumulator will contain 8616, not 8016
Z80 CPU logic uses the values in the Carry and Auxiliary Carry, as well as the Ac-
cumulator contents, in the Decimal Adjust operation.
3-68
DEC reg - DECREMENT REGISTER CONTENTS
SZACP/ONC
F ~
Data
Memory
_&
00 xxx 101
-..-
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
~ Coo,""" of Po,
B. C. D. E. H.
or Lis yy
- ~ V mmmm
...,::mmm + 1
I
I
Program
Memory
OOxxxl01 mmmm
mmmm+ 1
t----1mmmm + 2
mmmm+3
t----t
000 for reg=B
001 for reg=C
010 forreg=D
011 for reg=E
100 for reg= H
101 for reg=L
111 for reg=A
Subtract 1 from the contents of the specified register.
Suppose Register A contains 5016. After execution of
DEC A
Register A will contain 4F16
3-69
DEC rp - DECREMENT CONTENTS OF SPECIFIED REGISTER
DEC IX PAIR
DECIY
S Z AC P/O N C
Fc::o:IIIl
Data
Memory
A
RC
D.E
H.L
SP
PC
IX
IY
I
R
Co,..,,, of Be
DE, HL or SP
is yyyy
mmmm

I
I
Program
Memory
OOxxl0ll mmmm
mmmm+ 1
I-----fmmmm + 2
I-----fmmmm + 3
The illustration shows execution of DEC rp:
]X
00 xx 1011
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Subtract 1 from the 1 value contained in the specified register pair. No status flags
are affected
Suppose the Hand L registers contain 2F001 6 After the instruction
DEC HL
has executed. the Hand L registers will contain 2EFF16.
DEC IX
-.---
DD 28
Subtract 1 from the 16-bit value contained in the IX register
DEC IY
--....-
FD 28
Subtract 1 from the 16-bit value contained in the IY register.
Neither DEC rp. DEC IX nor DEC IY affects any of the status flags. This is a defect in the
Z80 instruction set. inherited from the 8080. Whereas the DEC reg instruction is used in
iterative instruction loops that use a counter with a value of 256 or less. the DEC rp
(DEC IX or DEC IY) instruction must be used if the counter value is more than 256. Since
the DEC rp instruction sets no status flags. other instructions must be added to simply
3·70
test for a zero resu It. This is a typicaI loop form:
LOOP
LD DE.DATA ;LOAD INITIAL 16-81T COUNTER VALUE
;FIRST INSTRUCTION OF LOOP
DEC
LD
OR
JP
DE
A.D
E
NZ,LOOP
;DECREMENT COUNTER
;TO TEST FOR ZERO. MOVE D TO A
;THEN OR A WITH E
;RETURN IF NOT ZERO
DEC (HL) - DECREMENT MEMORY CONTENTS
DEC (lX+disp)
DEC (IV+disp)
Data
mmm
mmm+1
mmmm+2
...------1 mmmm + 3
Cyy-1
yy
P
f
-
pp qq
mmmm
~ m m m + ~
Program
Memory
I 35
m
I m
S Z AC P/O N C
F ~
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of DEC (HL):
DEC (HL)
'-v-"
35
Subtract 1 from the contents of memory location (specified by the contents of the HL
reg ister paid.
Suppose ppqq=450016. yy=5F16 After execution of
DEC (HL)
memory location 450016 will contain 5E16.
5F = 0 1 0 1 1 1 1 1
-01 = 1 1 1 1 1 1 1 1
I?]1 0 1 1 1 1 0
~ ~ a sets S to O...jJ r LNoo-mo 'esult. set Z to a
1¥ 1=0. set PIO to 0 - No borrow. set AC to a
Subtract instruction. set N to 1
3-71
DEC (IX+disp)
'-v-' --
DD 35 d
Subtract 1 from the contents of memory location (specified by the sum of the contents
of the IX register and the displacement value d)
DEC (IY+disp)
~ - . . -
FD 35 d
This instruction is identical to DEC (IX+disp), except that it uses the IY register instead
of the IX register
01 - DISABLE INTERRUPTS
S Z AC P/O N C
FCIIIID
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
..,
mmmm mmmm+ 1
........
I
I
01
-.-'
F3
Data
~
Program
Memory
F3 mmmm
.....__-1 mmmm + 1
....----1 mmmm + 2
.....__-1 mmmm + 3
When this instruction is executed, the maskable interrupt request is disabled and the
INT input to the CPU will be ignored, Remember that when an interrupt is
acknowledged, the maskable interrupt is automatically disabled
The maskable interrupt request remains disabled until it is subsequently enabled by an
EI instruction,
No registers or flags are affected by this instruction
3-72
DJNZ disp - JUMP RELATIVE TO PRESENT
CONTENTS OF PROGRAM COUNTER IF
REG B IS NOT ZERO
s Z ACPIO N C
xx-l
~
Data
c::a::r::co
Memory
j
xx'
- .......mmmm+
mmmm
· ~ d d - 2 ) + 2,
Program
Memory

I
10
L dd-2
F
A
B.C
D.E
H.l
SP
PC
IX
IV
~ mmmm
R mmmm+ 1
mmmm+2
mmmm+3
DJNZ disp
~ --
10 dd-2
Decrement Register B If remaining contents are not zero. add the contents of the DJNZ
instruction object code second byte and 2 to the Program Counter. The jump is
measured from the address of the instruction operation code. and has a range of -126 to
+129 bytes. The Assembler automatically adjusts for the twice-incremented PC.
If the contents of B are zero after decrementing. the next sequential instruction is ex-
ecuted.
The DJNZ instruction is extremely useful for any program loop operation, since the one
instruction replaces the typical "decrement-then-branch on condition" instruction se-
Quence.
EI- ENABLE INTERRUPTS
S Z AC PIO N C
F ~
Data
Memory
A
B,C
D.E
H.L
SP
PC
IX
IV
I
R
--
mmmm mmmm + 1
"""""-
I
I
Program
Memory
FB mmmm
mmmm+ 1
t-----t mmmm + 2
t-----t mmmm + 3
3-73
EI
FB
Execution of this instruction causes interrupts to be enabled. but not until one more in-
struction executes.
Most interrupt service routines end with the two instructions:
EI
RET
;ENABLE INTERRUPTS
;RETURN TO INTERRUPTED PROGRAM
If interrupts are processed serially. then for the entire duration of the interrupt service
routine all maskable interrupts are disabled - which means that in a multi-interrupt
application there is a significant possibility for one or more interrupts to be pending
when any interrupt service routine completes execution.
If interrupts were acknowledged as soon as the EI instructions had executed, then the
Return instruction would not be executed. Under these circumstances, returns would
stack up one on top of the other - and unnecessarily consume stack memory space.
This may be illustrated as follows:
Interrupt
Interrupt service routine
By inhibiting interrupts for one more instruction following execution of EI. the zeo CPU
ensures that the RET instruction gets executed in the sequence:
EI
RET
;ENABLEINTERRUPTS
;RETURN FROM INTERRUPT
It is not uncommon for interrupts to be kept disabled while an interrupt service routine
is executing. Interrupts are processed serially:
Lt'""""s ~
Interrupt service routine
3-74
Lt'""'rus: ~
Interrupt service routine
EX AF,AF'-EXCHANGE PROGRAM STATUS AND ALTERNATE
PROGRAM STATUS
F'
A'
B',C'
D',E'
H',L'
Alternate
R . t S t
S Z ACP/O N C
- "\
egis er e
I I I I I I
I
-if
I
-, V Program
mmmm ~ m m m + 1
Memory
I DB mmmm
I
mmmm + 1
F
A
S.C
D.E
H.L
SP
PC
IX
IV
I
R
mmmm +2
t------4I mmmm + 3
EX AF,AF'
~
08
The two-byte contents of register pairs AF and AT are exchanged.
Suppose AF contains 4F9916 and A'F' contains 10AA16. After execution of
EX AF,AF'
AF will contain 1OAA16 and AF' will contain 4F9916.
3-75
EX DE,HL - EXCHANGE DE AND HL CONTENTS
S Z AC P/O N C
Fco:IID
Data
Memory
A
S,C
D.E
H,L
SP
PC
IX
IY
I
R
pp qq
,)
xx yy
-
..,
mmmm mmmm+ 1
"""'"
I
I
Program
Memory
EB mmmm
I--__---tmmmm + 1
mmmm+2
t----t
mmmm
+ 3
EX DE.HL
---...-
EB
The 0 and E registers' contents are swapped with the Hand L registers' contents
Suppose pp=0316, qq=2A16. xx=4116 and yy=FC16· After the instruction
EX DE,HL
has executed, H will contain 0316. L will contain 2A16. 0 will contain 4116 and E will
contain FC16·
The two instructions:
EX DE.HL
LD A,(HU
are eq uivalent to:
LD A,(DE)
but if you want to load data addressed by the 0 and E register into the B register.
EX DE.HL
LD B.(HL)
has no single instruction equivalent.
3-76
EX (SP).HL - EXCHANGE CONTENTS OF REGISTER AND
EX (SP).IX TOP OF STACK
EX (SP).IY
Data
ssss
ssss + 1
ssss + 2
mmmm
mmmm+ 1
mmmm+2
I-------t
mmmm
+ 3
Memory
-
-
qq
"
-
pp
K

xx YV
ssss
-, V
mmmm ~ m m m + 1
Program
Memory
I E3
I
S Z AC P/O N C
Fo:r:IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of EX (SP).HL
EX (SP).HL
~
E3
Exchange the contents of the L register with the top stack byte. Exchange the contents
of the H register with the byte below the stack top.
Suppose xx=2116. yy=FA16. pp=3A16' qq=E216 After the instruction
EX (SP).HL
has executed, H will contain 3A16. L will contain E216 and the two top stack bytes will
contain FA16 and 2116 respectively.
The EX (SP).HL instruction is used to access and man ipu late data at the top of the stack
EX (SP).IX
~
DO E3
Exchange the contents of the IX register's low-order byte with the top stack byte, Ex-
change the IX register's high-order byte with the byte below the stack top.
EX (SP).IY
~
FD E3
This instruction is identical to EX (SPl.IX. but uses the IY register instead of the IX
register.
3-77
EXX - EXCHANGE REGISTER PAIRS AND ALTERNATE
REGISTER PAIRS
S ZACP/ON C
Fc::r:::r::IIIJ
Altemate
Register Set
Program
Memory
09 mmmm
I--......;;;.;;......... mmmm + 1
mmmm+2
t----t mmmm + 3
F'
A'
{
I----+--........ B••C'
D·.E·
t-------t----f
H
·•
L
· }4
..
-
~ m m m + ~ mmmm
I
I
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
EXX
09
The contents of register pairs BC, DE and HL are swapped with the contents of register
pairs B'C', D·E·. and H'L',
Suppose register pairs BC, DE and HL contain 490116, 5F0016 and 725116 respec-
tively, and register pairs B'C DE. H'L' contain 000016, 10FF16 and 333316 respec-
tively After the execution of
EXX
the registers will have the following contents:
BC: 000016; DE: 10FF16; HL: 333316;
B'C': 490116; D'E': 5F0016; H'L': 725116
This instruction can be used to exchange register banks to provide very fast interrupt
response times,
3-78
HALT
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
S,C
D,E
H,L
SP
PC
IX
IV
I
R
-
.,
mmmm mmmm+ 1
- ........
I
I
HALT
76
Program
Memory
76 mmmm
mmmm+ 1
t-----t mmmm + 2
t-----t mmmm + 3
When the HALT instruction is executed, program execution ceases. The CPU requ ires
an interrupt or a reset to restart execution. No registers or statuses are affected:
however. memory refresh logic continues to operate.
3-79
1M 0 - INTERRUPT MODE 0
S Z AC PIO N C
FO::C:O::O
Data
Memory
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
-
~
mmmm - -. mmmm + 2
.........
-.
r
IMO
'-..,,-'
ED 46
Program
Memory
ED mmmm
46 mmmm+ 1
I-__~ mmmm +2
I-__~ mmmm +3
This instruction places the CPU in interrupt mode a In this mode. the Interrupting
device will place an instruction on the Data Bus and the CPU will then execute that in-
struction No registers or statuses are affected
1M 1 -INTERRUPT MODE 1
1M 1
'-..,,-'
ED 56
This instruction places the CPU in interrupt mode 1 In this mode. the CPU responds to
an interrupt by executing a restart (RST) to location 003816.
1M 2 - INTERRUPT MODE 2
1M 2
---
ED 5E
This instruction places the CPU in Interrupt mode 2 In this mode, the CPU performs an
indirect call to any specified location in memory. A 16-bit address is formed using the
contents of the Interrupt Vector (I) register for the upper eight bits, while the lower
eight bits are supplied by the interrupting device. Refer to Chapter 12 for a full descrip-
tion of interrupt modes. No registers or statuses are affected by this instruction
3-80
IN A,(portl-INPUT TO ACCUMULATOR
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
s Z Ac PIO N C
t
Data
CIIIIIJ
I I/O port yy j4--
Memory
I
-
- ., V Program
mmmm
~ m m m + 2
Memory
I DB
I
yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
INA
---
DB
(port)
'"-v-'
yy
Load a byte of data into the Accumulator from the I/O port (identified by the second IN
instruction object code byte)
Suppose 3616 is held in the buffer of I/O port 1A16 After the instruction
IN A,(1 AH)
has executed, the Accumulator will contain 3616
The IN instruction does not affect any statuses
Use of the IN instruction is very hardware dependent Valid I/O port addresses are
determined by the way in which I/O logic has been implemented. It is also possible to
design a microcomputer system that accesses external logic using memory reference
instructions with specific memory addresses
3-81
INC reg -INCREMENT REGISTER CONTENTS
S Z AC plo N C
F I:EIEIEIEI]D
Data
Memory
A
BC
DE
H.L
SP
PC
IX
IY
I
R
~ Co,,,,,, of A.
B, C. D, E. H or
Lis yy
_/ ~
mmmm :-.0 - . ~ m m m + 1
I
I
Program
Memory
OOxxx 100 mmmm
1-----1mmmm + 1
mmmm+2
t-----1 mmmm + 3
INC reg
I ~
00 xxx 100
000 for reg =8
001 for reg=C
010 for reg=D
all forreg=E
100 for reg =H
101 for reg=L
111 for reg=A
Add 1 to the contents of the specified register
Suppose Register E contains A816 After execution of
INC E
Register E will contain A916
3-82
INC rp - INCREMENT CONTENTS OF SPECIFIED REGISTER PAIR
INC IX
INC IV
S Z AC P/O N C
FCIIII:IJ
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
} Coo""" of DC.
DE, HL or SP
......isyyyy
- I ~ m m m + v
mmmm
I
I
Data
Memory
Program
Memory
OOxxOO11 mmmm
mmmm+ 1
t-----t
mmmm
+ 2
~ - - - - f m m m m + 3
The illustration shows execution of INC rp
~
00 xx 0011
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Add 1 to the 16-blt value contained in the specified register pair No status flags are
affected
Suppose the 0 and E registers contain 2F7A16 After the instruction
INC DE
has executed, the D and E reg isters wi II contain 2F7B 16
INC IX
.-..--
DO 23
Add 1 to the 16-bit value contained in the IX register.
INC IY
.-..--
FD 23
Add 1 to the 16-bit value contained in the IY register.
Just like the DEC rp, DEC IX and DEC IY, neither INC rp, INC IX nor INC IY affects any
status flags This is a defect In the Z80 instruction set inherited from the 8080.
3-83
qq+d
mmm
mmm+l
mmm+2
mmm+3
Data
x X X X 0
Memory
Cyy+l
.......
-
...._-
yy pp
,/

- ~
Program
mmmm
-
• mmmm + 3
ppqq --
.......
Memory

DO
m
I 34
m
-..G
Pqq
+
d
)=
d
m
m
-
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
INC (HL) - INCREMENT MEMORY CONTENTS
INC (IX+disp)
INC (lY+disp)
S Z AC PIO N C
F []J]IEI]]]I]
The illustration shows execution of INC (IX+d):
INC (IX+disp)
~ -.-
DD 34 d
Add 1 to the contents of memory I"cation (specified by the sum of the contents of
Register IX and the displacement value d),
Suppose ppqq =400016 and memory location 400F16 contains 3616 After execution
of the instruction
INC (IX+OFH)
memory location 400F16 will contain 3716,
36 = 0 0 1 1 0 1 1 0
1
Addition instruction, set N to a
O¥ 0=0, set P/O to °
001 1 0 1 1 1
osets S to 0 r LNo,-mo 'esult. set Z to 0
Carry status not affected - No carry, set AC to a
INC (IY+disp)
--..- -.-
FD 34 d
This instruction is identical to INC (IX+dispL except that it uses the IY register instead
of the IX register.
INC (HL)
~
34
Add 1 to the contents of memory location (specified by the contents of the HL register
pair),
3-84
IND -INPUT TO MEMORY AND DECREMENT POINTER
m
m+ 1
I-__---Immmm + 2
mmmm + 3
1------1
s Z AC PIO N C
Cxx-1 ~

Data
cm::G:GIIIJ
,..
,.r I/O port yy I
Memory
I
- ppqq
xx yy ~

~ ~ P p q q - 1
pp qq
Program
mmmm
mmmm+'V
..... Memory
I ED mmm
I AA mmm
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
IND
--.--
ED AA
Input from 1/0 port (addressed by Register C) to memory location (specified by HL)
Decrement Registers Band HL.
Suppose xx=0516, yy= 1516, ppqq=240016. and 1916 is held In the buffer of 1/0 port
1516 After the instruction
IND
has executed. memory location 240016 will contain 1916, The B register will contain
0416 and the HL reg ister pa ir 23FF16
INDR -INPUT TO MEMORY AND DECREMENT POINTER
UNTIL BYTE COUNTER IS ZERO
INDR
--...--
ED BA
INDR is identical to IND. but is repeated until Register B=O.
Suppose Register B contains 0316. Register C contains 1516. and HL contains 240016
The following sequence of bytes is available at 1/0 port 1516:
17
16. 5916 and AE16
After the execution of
INDR
the HL register pair will contain 23FD16 and Register B will contain zero. and memory
locations will have contents as follows:
Location
2400
23FF
23FE
Contents
17
16
59
16
AE16
This instruction is extremely useful for loading blocks of data from an input device into
memory.
3-85
INI-INPUT TO MEMORY AND INCREMENT POINTER
m
m+ 1
t----I mmmm + 2
t----I mmmm +3
s Z AC PIO N C
Cxx-l ~

Data
o:::o:::DJ

....... I/O port yy I
Memory
I
ppqq
..
xx yy ~
. ~
£Ppqq+l
pp qq
.....
mmmm
~ V
Program
~ m m m + 2
Memory
I ED mmm
I A2 mmm
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
INI
'-v-'
ED A2
Input from I/O port (addressed by Register C) to memory location (specified by HL)
Decrement Register B: increment register pair HL
Suppose xx=:0516. yy=: 1516, ppqq=:240016. and 1916 is held in the buffer of I/O port
15
16
After the instruction
INI
has executed. memory location 240016 will contain 1916 The B register will contain
0416 and the HL register pair 240116
INIR - INPUT TO MEMORY AND INCREMENT POINTER
UNTIL BYTE COUNTER IS ZERO
INIR
'-v-'
EO B2
INIR is identical to INI. but is repeated until Register 8=0,
Suppose Register B contains 0316, Register C contains 1516. and HL contains 240016
The following sequence of bytes is available at I/O port 1516
1716.5916 and AE16
After the execution of
INIR
the HL register pair will contain 240316 and Register Bwill contain zero. and memory
locations will have contents as follows:
Location
2400
2401
2402
Contents
17
16
59
16
AE16
This instruction is extremely useful for loading blocks of data from a device into memo-
ry,
3-86
IN reg,(C) -INPUT TO REGISTER
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC PIO N C
t
m:m::J]J]D
---
I/O port vv I
-
t
\'y
A B, C, D, E,
H or L
- mmmm
_ \.::mmm + 2
I
I
Data
Memory
Program
Memory
ED mmmm
01xxxOOO mmmm + 1
mmmm+2
mmmm + 3
IN reg. (C)
K
ED 01 xxx 000
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
110 for setting of status flags without
changing registers
Load a byte of data into the specified register (reg) from the 1/0 port (identified by the
contents of the C register).
Suppose 4216 is held In the buffer of 1/0 port 3616. and Register C contains 3616.
After the instruction
IN D.(C)
has executed. the 0 register will contain 4216
During the execution of the instruction. the contents of Register B are placed on the top
half of the Address Bus. making it pOSSible to extend the number of addressable 1/0
ports.
3-87
JP label - JUMP TO THE INSTRUCTION IDENTIFIED
IN THE OPERAND
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
B.C
O.E
H.l
SP
PC
IX
IY
I
R
mmmm
r
ppqq :)
Program
- Memory

I C3
I
,
qq
t
pp
mmmm
mmmm+ 1
mmmm+2
mmmm+3
JP label
-.- '-v-'
C3 ppqq
Load the contents of the Jump instruction object code second and third bytes into the
Program Counter; this becomes the memory address for the next instruction to be ex-
ecuted. The previous Program Counter contents are lost.
In the following sequence
JP NEXT
AND 7FH
NEXT CPL
The CPL instruction will be executed after the JP instruction The AND instruction will
never be executed. unless a Jump instruction somewhere else in the instruction se-
quence jumps to this instruction
3-88
condition
satisfied
JP condition, label - JUMP TO ADDRESS IDENTIFIED IN THE
OPERAND IF CONDITION IS
SATISIFED
JP condo label
Kl
11 cc 010 ppqq
I Condition Relevant Flag
000 NZ Non-Zero Z
001 Z Zero Z
010 NC No Carry C
011 C Carry C
100 PO Parity Odd Pia
101 PE Parity Even Pia
110 P Sign Positive S
111 M Sign Negative S
This instruction is identical to the JP instruction. except that the jump will be per-
formed only If the condition is satisfied: otherwise. the Instruction sequentially follow-
Ing the JP condition instruction will be executed
Consider the instruction sequence
JP COND.LABEL
---------'11 condition not satisfied
AND +7CH
LABEL OR B
After the JP cond.label instruction has executed. if the condition is satisfied then the
OR instruction will be executed If the condition IS not satisfied. the AND instruction.
being the next sequential instruction. IS executed
3-89
JP (HL) - JUMP TO ADDRESS SPECIFIED BV CONTENTS
JP (IX) OF 16-BIT REGISTER
JP (IV)
S Z Ac P!O N C
FCIIIIIJ
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
pp qq
P
mmmm
I
I
Data
Program
Memory
E9 mmmm
~ __--1 mmmm + ,
mmmm+2
J - - - ~ mmmm + 3
The illustration shows execution of JP (HL):
JP (HL)
-...--
E9
The contents of the HL register pair are moved to the Program Counter: therefore. an
implied addressing Jump is performed.
The instruction sequence
LD H.ADDR
JP (HL)
has exactly the same net effect as the single instruction
JP ADDR
Both specify that the Instruction with label ADDR is to be execu ted next
The JP (HL) instruction is useful when you want to increment a return address for a
subroutine that has multiple returns
Consider the following call to subroutine SUB:
SUB
ERR
CALL
JP
:CALL SUBROUTINE
:ERROR RETURN
:GOOD RETURN
Using RET to return from SUB would return execution of JP ERR: therefore. if SUB ex-
ecutes without detecting error conditions. return as follows:
POP
INC
INC
INC
JP
HL
HL
HL
HL
{HL)
:POP RETURN ADDRESS TO HL
:ADD 3 TO RETURN ADDRESS
.RETURN
JP (IX)
-.,,-'
DD£9
This instruction is identical to the JP {HL) instruction. except that it uses the IX register
3-90
instead of the HL register pair.
JP (lY)
'-.,.-'
FD E9
This instruction is identical to the JP (HU instruction. except that it uses the IY register
instead of the HL register pair.
JR C,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF CARRY IS SET
JR C, disp
'-.,.-' -..-
38 dd-2
This instruction is identical to the JR disp instruction. except that the jump is only ex-
ecuted if the Carry status equals 1: otherwise. the next instruction is executed
In the following instruction sequence:
AND
JR
4002
4000
C=1
C.$+8
_---------'1 c=o
, 7FH
- ~ ~ 4 0 0 8 OR B
After the JR (,$+8 instruction. the OR instruction is executed if the Carry status equals
1. The AND instruction is executed if the Carry status equals 0
3-91
JR disp - JUMP RELATIVE TO PRESENT CONTENTS OF
PROGRAM COUNTER
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
S,C
D.E
H.L
SP
PC
IX
IY
I
R
'mmmmD Program
mmmm
-
a . ~ d - 2 ) + 2
Memory
1
I 18
I dd-2
JR disp
--.--...-
18 dd-2
mmmm
mmmm+ ,
mmmm+2
mmmm+3
Add the contents of the JR instruction object code second byte. the contents of the Pro-
gram Counter. and 2. Load the sum into the Program Counter The jump is measured
from the address of the instruction operation code. and has a range of -126 to +129
bytes. The Assembler automatically adjusts for the twice-incremented Pc.
The following assembly language statement is used to Jump four steps forward from ad-
dress 400016.
JR $+4
Result of this instruction is shown below:
3-92
JR NC,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF CARRY FLAG IS RESET
JR NC.disp
-----
30 dd-2
OR
JR
4005
c=o
4000
4001
4002
4003
This instruction is identical to the JR disp instruction, except that the Jump is only ex-
ecuted if the Carry status equals 0: otherwise, the next instruction is executed.
In the following instruction sequence
I
ADD I A,7FH
I
I
I
I
After the JR NC,$-3 instruction. the OR instruction is executed if the Carry status equals
1 The ADD instruction is executed if the Carry status equals O.
JR NZ,disp-JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF ZERO FLAG IS RESET
JR NZ.disp
'-.,-.' -v-'
20 dd-2
B OR
z=o
This instruction is identical to the JR disp instruction. except that the jump is only ex-
ecuted if the Zero status equals 0: otherwise. the next instruction is executed.
In the following instruction sequence:
I
_--4..:..;0:;.;;0:..;;0----::;J.;.;R-...,' NZ.$+6
AND t
4005
'---'-4006
After the JR NZ,$+6 instruction. the OR instruction is executed if the Zero status equals
O. The AND instruction is executed if the Zero status equals 1.
3-93
Z=l
JR l,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF ZERO FLAG IS SET
JR Z,disp
--..----
28 dd-2
This instruction is identical to the JR disp instruction, except that the Jump is only ex-
ecuted if the Zero status equals 1; otherwise, the next instruction is executed
In the following instruction sequence
I
,...-__4....;;0....;.0..;;.0_--.,;.J....;.R_ ....... 1 Z, $+6
4002 AND: 7FH
4004 tz=o
4005
'---tlr- 4006 OR B
After the JR Z,$+6 instruction, the OR instruction is executed if the Zero status equals
1 The AND instruction is executed if the Zero status equals 0
LD A,I- MOVE CONTENTS OF INTERRUPT VECTOR OR
LD A,R REFRESH REGISTER TO ACCUMULATOR
S Z AC Pia N C

A
B,C
D.E
H.L
SP
PC
IX
IY
I
R
xx
- V mmmm
I
xx
I
Data

Memory
ED mmmm
57 mmmm + 1
mmmm + 2
t----I mmmm + 3
The illustration shows execution of LD A.I:
LD A.I

ED 57
Move the contents of the Interrupt Vector register to the Accumulator. and reflect inter-
rupt enable status in Parity/Overflow flag.
Suppose the Interrupt Vector register contains 7F16. and interrupts are disabled After
execution of
LD A.I
Register A will contain 7F16. and P/O will be 0
LD A.R
-.,-.'
ED 5F
Move the contents of the Refresh register to the Accumulator. The value of the interrupt
flip-flop will appear In the Parity/Overflow flag.
3-94
LD A,(addr) - LOAD ACCUMULATOR FROM MEMORY USING
DIRECT ADDRESSING
S Z ACP/ON C
Data
ppqq
mmmm
mmmm+ 1
PP mmmm +2
't----'--'-----1 mmmm + 3
D:IIIIJ
Memory
yy yy
- .I'
Program
mmmm mmmm+3
...... Memory
I 3A
I I
qq
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
LD A (addr)
--...--- --...---
3A ppqq
Load the contents of the memory byte (addressed directly by the second and third
bytes of the LD A.(addrl instruction object code) into the Accumulator Suppose memo-
ry byte 084A16 contains 2016 After the instruction
label EQU 084AH
LD A(label)
has executed. the Accumulator will contain 2016
Remember that EQU is an assembler directive rather than an instruction: It tells the As-
sembler to use the 16-bit value 084A16 wherever the label appears.
The instruction
LD A.(Iabell
is equivalent to the two instructions
LD HL.label
LD A.(HL}
When you are loading a single value from memory. the LD A(label) instruction is prefer-
red: it uses one instruction and three object program bytes to do what the LD HL.label.
LD A (HL} combination does in two instructions and four object program bytes. Also.
the LD HL.label. LD A (HLI combination uses the Hand L registers. which LD A (label)
does not.
3-95
LD A,(rp) -LOAD ACCUMULATOR FROM MEMORY LOCATION
ADDRESSED BY REGISTER PAIR
Data
ppqq
..... 1
mmmm
mmmm+ 1
mmmm+2
I------t mmmm + 3
Memory
- yy yy
} ...... BC or DE contain ppqq I
C:--:-::;mmm.~ l Program
mmmm
Memory
I OOOx1010
I
S Z ACP/0N C
FCIIIIIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
,
R
LD A(rp)
:Ilw
-o if register pair=BC
1 if register pair=DE
Load the contents of the memory byte (addressed by the BC or DE register pair) Into the
Accumu lator.
Suppose the B register contains 0816, the C register contains 4A16, and memory byte
084A16 contains 3A16 After the instruction
LD A(BC)
has executed. the Accumulator will contain 3A16
Normally. the LD A,(rp) and LD rp,data will be used together. since the LD rp.data in-
struction loads a 16-bit address into the BC or DE registers as follows:
LD BC,084AH
LD A(BCI
3-96
LD dst,src - MOVE CONTENTS OF SOURCE REGISTER TO
DESTINATION REGISTER
S Z AC PIO N C
FDIIIIJ
Data
Memory
Program
Memory
01dddsss mmmm
mmmm+ 1
I-----I
mmmm
+ 2
1-__--1 mmmm + 3
Register A. B. C,
tD.E.H;l
}lR..;"" A, B. C
D. E, H, L
-
~
mmmm mmmm+ 1
........
I
I
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
LD dst. src
III
01 ddd sss
'-v-'
000 for dst or src=B
001 for dst or src=C
010 for dst or src=D
all for dst or src=E
100 for dst or src=H
101 for dst or src=L
111 for dst or src=A
The contents of any designated register are loaded into any other register
For example
LD A,S
loads the contents of Register B into Register A.
LD LD
loads the contents of Register D into Register L
LD C,C
does nothing, since the C register has been specified as both the source and the
destination
3-97
LO HL,(addr) - LOAD REGISTER PAIR OR INDEX REGISTER
LD rp, (addr) FROM MEMORY USING DIRECT ADDRESSING
LD IX,(addr)
LD IY, (addr)
m
m + 1
m+2
m+3
Data
Memory
Xl( ppqq
yV
ppQ1

,
yy xx
.. ,- ~ Program
mmmm ".:,mmm +3
Memory
I
2A mmm
I
1
QQ mmm
~
pp
mmm
mmm
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
S Z AC P/O N C
FCIIIIIJ
The illustration shows execution of LD HL(ppqq):
LD HL.addr
--..---..,.-.-
2A ppqq
Load the HL register pair from directly addressed memory location.
Suppose memory location 400416 contains AD16 and memory location 400516 con-
tains 1216 After the instruction
LD HL(4004H)
has executed, the HL register pair will contain 12AD16.
1fL
ED 01 dd 1011 ppqq
--,-
00 for rp is register pair Be
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Load register pair from directly addressed memory.
Suppose memory location 49FF16 contains BE16 and memory location 4A0016 con-
tains 3316. After the instruction
LD DE, (49FFH)
has executed, the DE register pair will contain 33BE16.
LD lX,(addr)
--..,.-.- --..--
DD 2A ppqq
Load IX register from directly addressed memory.
3-98
Suppose memory location 011116 contains FF16 and memory location 011216 con-
tains 5616. After the instruction
LO IX,(D111H)
has executed, the IX register will contain 56FF16·
LO IY,(addrl
---..-- ---..--
FO 2A ppqq
Load IY register from directly addressed memory.
Affects IY register instead of IX. Otherwise identical to LO IX(addr),
LD I,A - LOAD INTERRUPT VECTOR OR REFRESH
LD R,A REGISTER FROM ACCUMULATOR
5 Z AC P/O N C
F o::::r::r:IIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
IV
R
xx
JJ'
mmmm mmmm + 2
--
I
I
Data
Program
Memory
ED mmmm
4F mmmm+ 1
J-----1mmmm + 2
mmmm+3
......---1
The illustration shows execution of LD R.A
LO R,A
'"-v-'
ED 4F
Load Refresh register from Accumulator.
Suppose the Accumulator contains 7F16· After the instruction
LO R,A
has executed. the Refresh register will contain 7F16·
LO I.A
'-'v-'
ED 47
Load Interrupt Vector register from Accumulator,
3-99
LD reg.data - LOAD IMMEDIATE INTO REGISTER
S Z AC P/O N C
Fo::::I::IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
}-0........,;.
Register A, B, C,
D, E, H or L
- ~ ~
mmmm mmmm + 2
- .......
I
I
Data
Program
Memory
OOxxx 11 0 mmmm
YY mmmm+ 1
mmmm+2
I----I
mmmm
+ 3
00 xxx 110 yy
-.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load the contents of the second object code byte into one of the registers.
When the instruction
LD A,2AH
has executed, 2A16 is loaded into the Accumulator.
3-100
LD rp,data - LOAD 16 BITS OF DATA IMMEDIATE INTO
LD IX,data REGISTER
LD IV,data
S Z Ac P/O N C
FD:IIIIJ
mmmm
mmmm+ 1
mmmm+2
mmmm+3
Program
Memory
OOxxOOOl
\
qq
pp
Data
~
e m o r Y
HL or
nto
tion
y.;""",.eC'D<
SP. Load ppqq i
::cted destina
mmmm mmmm+3
........
I
I
A
B.C
D,E
H,L
SP
PC
IX
IV
I
R
The illustration shows execution of LD rp,data:
_Jt1
00 xx 0001 ppqq
--
00 for rp is register pair Be
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Load the contents of the second and third object code bytes into the selected register
pair. After the instruction
LD SP,217AH
has executed, the Stack Pointer will contain 217A16·
LD IX, data
---...- --
DD 21 ppqq
Load the contents of the second and third object code bytes into the Index register IX.
LD IY, data
---- -.-
FD 21 ppqq
Load the contents of the second and third object code bytes into the Index Register IY.
Notice that the LD rp,data instruction is equivalent to two LD reg,data instructions
For example:
LD HL,032AH
is equivalent to
LD H,03H
LD L,2AH
3-101
LD reg, (HL) - LOAD REGISTER FROM MEMORY
LD reg, (IX+disp)
LD reg, (lY+disp)
S Z AC P/O N C
F o::r::::r:r::o
Data
Memory
m
m+ 1
m+2
m+3
+d
}--Bog;"" A, B, C,'"
yy
-,
D, E. H or L

Program
mmmm mmmm+3
ppqq
-
....... Memory
I DO mmm
I Olxxx110· mmm

d mmm
mmm
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of LD reg.(IX+disp)
LD reg. (IX + disp)

DD 01 xxx 110 d
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load specified register from memory location (specified by the sum of the contents of
the IX register and the displacement digit d)
Suppose ppqq=400416 and memory location 401016 contains FF16 After the instruc-
tion
LD B(IX+OCH)
has executed. Register B will contain FF16.
LD reg. (Iv + disp)

FD 01 xxx 110 d
l"------I..... same as for LD reg.(IX+disp)
This instruction is identical to LD reg,(lX+displ. except that it uses the IV register in-
stead of the IX register.
3-102
LD reg,(HU
m
01xxxll0
-...-
l... ........ ~ s a m e as for LD reg.OX+disp)
Load specified register from memory location (specified by the contents of the HL
register pair).
LD SP,HL - MOVE CONTENTS OF HL OR INDEX REGISTER
LD SP,IX TO STACK POINTER
LD SP,IV
S Z Ac P/O N C
FCIIIID
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
pp qq
::>,
mmmm ~ mmmm+ 1
I
I
Data
Program
Memory
F9 mmmm
mmmm+ 1
t-----f
mmmm
+ 2
t-__--fmmmm + 3
The illustration shows execution of LD SP.HL:
LD SP.HL
~
F9
Load contents of HL into Stack Pointer
Suppose pp=0816 and qq=3F16· After the instruction
LD SP.HL
has executed. the Stack Pointer will contain 083F16
LD SP.IX
~
DO F9
Load contents of Index Register IX into Stack Pointer
LD SP.lY
~
FD F9
Load contents of Index Register IY into Stack Pointer.
3-103
LD (addr),A - STORE ACCUMULATOR IN MEMORY USING
DIRECT ADDRESSING
S Z ACP/ON C
Data
ppqq
mmmm
mmmm+ 1
pp mmmm+2
't----'-'----1 mmmm + 3
cr:IIIIJ
Memory
yy yy
-

mmmm
Program
Memory
I 32
I
I
qq
F
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
tY
32 ppqq
Store the Accumulator contents in the memory byte addressed directly by the second
and th ird bytes of the LD (addrLA instruction object code,
Suppose the Accumulator contains 3A16 After the instruction
label EQU 084AH
LD (label).A
has executed. memory byte 084A16 will contain 3A16.
Remember that EQU is an assembler directive rather than an it tells the As-
sembler to use the 16-bit value 084AH whenever the word "label" appears,
The instruction
LD (addrl.A
is equivalent to the two instructions
LD H.label
LD (HL).A
When you are storing a single data value in memory. the LD Oabell.A instruction is
preferred because it uses one instruction and three object program bytes to do what the
LD H(label). LD (HL).A combination does in two instructions and four object program
bytes. Also. the LD H(labell. LD (HL).A combination uses the Hand L registers. while the
LD (labell.A instruction does not.
3-104
lD (addr),Hl- STORE REGISTER PAIR OR INDEX
lD (addr) ,rp REGISTER IN MEMORY USING DIRECT
lD (addr),xy ADDRESSING
S Z ACP/ON C
Data
ppqq
ppqq + 1
mmmm
mmmm+ 1
mmmm +2
mmmm+3
CIIIIlJ
Memory
yy
;
xx
~
"
I
xx yy
--
Program
mmmm mmmm+4
....... Memory
I ED
I 01010011
qq
pp
F
A
B.C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of LD (ppqql.DE:
~
ED 01 xx 0011 ppqq
........
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Store the contents of the specified register pair in memory. The third and fourth object
code bytes give the address of the memory location where the low-order byte is to be
written. The high-order byte is written into the next sequential memory location.
Suppose the BC register pair contains 3C2A16. After the instruction
label EQU 084AH
LD (labell.BC
has executed. memory byte 084A16 will contain 2A16 Memory byte 084B16 will con-
tain3C16
Remember that EOU is an assembler directive rather than an instruction; it tells the As-
sembler to use the 16-bit value 084A16 whenever the word "label" appears.
LD (addrl.HL
~
22 ppqq
This is a three-byte version of LD (addrl.rp which directly specifies HL as the source
register pair.
3·105
1X
DO 22 ppqq
Store the contents of Index register IX in memory. The third and fourth object code
bytes give the address of the memory location when'! the low-order byte is to be writ-
ten The high-order byte is written into the next sequential memory location.
~
FD 22 ppqq
This instruction is identical to the LD (addrl.lX instruction, except that it uses the IY
register instead of the IX register.
3-106
LD (HL).data -LOAD IMMEDIATE INTO MEMORY
LD (Ix+disp) ,data
LD (lY+disp) ,data
S Z AC P/O N C
Data
m
m+ 1
m+2
m+3
+d
CIIIIIJ
Memory
~
xx ppqq
I
mmmm
~ m m m + ~
Program
ppqq
Memory
I DO mmm
I
~ p q q + d ~ . _
36 mmm
d
mmm
'-- xx mmm
F
A
B.C
D,E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of LD (IX+&xx:
LD (IX+disp),data
-.".-... -..- --.-
DD 36 d xx
Load Immediate into the Memory location designated by base relative addressing.
Suppose ppqq=540016 After the instruction
LD (IX+9),FAH
has executed. memory location 540916 will contain FA16
LD (IY+disp),data
----- -.-----..-'
FD 36 d xx
This instruction is identical to LD (IX+disp),data, but uses the IY register instead of the
IX register.
LD (HL),data
-.".-... ----..-'
36 xx
Load Immediate into the Memory location (specified by the contents of the HL register
pair)
The Load Immediate into Memory instructions are used much less than the Load Im-
mediate into Register instructions
3-107
LD (HL),reg - LOAD MEMORY FROM REGISTER
LD (lX+disp),reg
LD (ly+disp),reg
Data
mmm
mm+l
mmmm+2
1------1 mmmm + 3
Contents of A, B. yy
1
c. D. E. H or L
~ i s y y
pp qq
mmmm
~ m m m + ~
Program
Memory
I
01110xxx m
I mm
S ZACP/ON C
Fo::::r::rIIl
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
The illus1ration shows execution of LD (HU,reg:
'II
01110xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load memory location (specified by the contents of the HL register pair) from specified
register.
Suppose ppqq=450016 and Register C contains F916 After the instruction
LD (HU,C
has executed, memory location 450016 will contain F916.
l ~
DDOll10xxxa
T ~ same as for LD (HU,reg
Load memory location (specified by the sum of the contents of the IX register and the
3-108
displacement value d) from specified register.
LD (lY+dispLreg
:LY
FD01110xxxa
T...-----tl... same as for LD (HU.reg
This instruction is identical to LD (IX+dispLreg. except that it uses the IY register in-
stead of the IX register.
LD (rp),A - LOAD ACCUMULATOR INTO THE MEMORY
LOCATION ADDRESSED BY REGISTER PAIR
S Z AC plO N C Data
ppqq
1
mmmm
mmmm+ 1
mmmm+2
t------t mmmm + 3
co:::IIIJ
Memory
yy
.
yy
}
Be or DE I
• contain ppr
q
-,
Program
mmmm
-
--" mmmm + 1
--
Memory
,
I
OOOxOO10
I
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
LD (rpl.A
m
'-'
oif register pair=BC
1 if register pair=DE
Store the Accumulator in the memory byte addressed by the BC or DE register pair.
Suppose the BC register pair contains 084A16 and the Accumulator contains 3A16
After the instruction
LD (BCLA
has executed. memory byte 084A16 will contain 3A16·
The LD (rp).A and LD rp.data will normally be used together. since the LD rp.data in-
struction loads a 16-bit address into the BC or DE registers as follows:
LD BC.084AH
LD (BCl.A
3-109
LDD - TRANSFER DATA BETWEEN MEMORY LOCATIONS.
DECREMENT DESTINATION AND SOURCE ADDRESSES
Program
Memory
ppqq-1
ppqq
Data

t::E::j
• •
ED mmmm
..... .. mmmm + 1
mmmm+2
1-------41 mmmm + 3
rrss- 1

Set if BC-1 ;I! 0, reset otherwise
t
5 Z AC P/G N C
FaTID:§!]
A ..... M":
B.CI- __
D.E rr ss -----
.Lt-__..:P;.:.p ...... q.:..q:..-__ ..... ------
Sp .... .......
PC mmmm
IX ----.....;,;.;;.;,;.....;.....;-----.
Iy ...... -I
I
A
LDD
---
ED A8
Transfer a byte of data from memory location addressed by the HL register pair to
memory location addressed by the DE register pair. Decrement contents of register
pairs BC. DE. and HL.
Suppose register pair BC contains 004F16. DE contains 454516. HL contains 201216.
and memory location 201216 contains 1816. After the instruction
LDD
has executed. memory location 454516 will contain 1816. register pair BC will contain
004E16. DE will contain 454416. and HL will contain 201116.
3-110
LDDR - TRANSFER DATA BETWEEN MEMORY
LOCATIONS UNTIL BYTE COUNTER IS
ZERO. DECREMENT DESTINATION AND
SOURCE ADDRESSES
LDDR
---
ED B8
Th is instruction is identical to LDD. except that it is repeated until the BC register pair
contains zero After each data transfer. interrupts will be recognized and two refresh cy-
cles will be executed.
Suppose we have the following contents in memory and register pairs:
Register/Contents Location/Contents
HL 201216 201216 1816
DE 454516 201116 AA16
BC 000316 2010162516
After execution of
LDDR
register pairs and memory locations will have the following contents:
Register/Contents Location/Contents Location/Contents
HL 200916 201216 1B16 454516 1816
DE 454216 201116 AA16 454416 AA16
BC 000016 201016 2516 454316 2516
This instruction is extremely useful for transferring blocks of data from one area of
memory to another.
3-111
LDI - TRANSFER DATA BETWEEN MEMORY
LOCATIONS. INCREMENT DESTINATION AND
SOURCE ADDRESSES
Program
Memory
A
B,C tt uu
D,E rr ss
,L pp QQ
SP
PC mmmm
IX
IY
I
R
ED mmmm
AO mmmm+ 1
.....__-1 mmmm + 2
.....__-1 mmmm+ 3
Set if BC-1 ~ 0, reset otherwise
S Z ACP'O N C
Fc:::c:I:§I]IIJ
LDI
~
ED AO
Transfer a byte of data from memory location addressed by the HL register pair to
memory location addressed by the DE register pair, Increment contents of register pairs
HL and DE Decrement contents of the BC register pair
Suppose register pair BC contains 004F16, DE contains 454516, HL contains 201216_
and memory location 201216 contains 1816, After the instruction
LDI
has executed, memory location 454516 will contain 1816, register pair BC will contain
004E16, DE will contain 454616_ and HL will contain 201316
3-112
LDIR-TRANSFER DATA BETWEEN MEMORY
LOCATIONS UNTIL BYTE COUNTER IS
ZERO. INCREMENT DESTINATION AND
SOURCE ADDRESSES
LOIR
-..-
ED BO
This instruction is identical to LDI. except that it is repeated until the BC register pair
contains zero. After each data transfer. interrupts will be recognized and two refresh cy-
cles will be executed
Suppose we have the following contents in memory and register pairs:
Register/Contents Location/Contents
HL 201216 201216 1816
OE 454516 201316 CD16
BC 000316 201416 F016
After execution of
LDIR
register pairs and memory will have the following contents:
Register/Contents Location/Contents Location/Contents
HL 201516 2012161816 4545161816
OE 454816 201316 C016 454616 C016
BC 000016 201416 F016 454716 F016
This instruction is extremely useful for transferring blocks of data from one area of
memory to another.
NEG - NEGATE CONTENTS OF ACCUMULATOR
Data
Program
Memory
,ED mmmm
,44 mmmm+ 1
1-----1 mmmm + 2
I-----t mmmm + 3
~ " ~ xx __ xx +'
"
mmmm mmmm + 2
........
I
I
S ZACP/ON C
F ~
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
Negate contents of Accumulator. This is the same as subtracting contents of the Ac-
cumulator from zero. The result is the two's complement. BOH will be left unchanged
Suppose xx=5A16. After the instruction
NEG
has executed, the Accumulator will contain A616·
5A 01 01 1 01 0
Two's complement = 1 0 1 0 0 1 1 0
3-113
NOP - NO OPERATION
S Z AC PIO N C
FCIID:D
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
_ - - · ( ~ " m m m +~ mmmm
I
I
NOP
---
00
Data
~
Program
Memory
00 mmmm
1--__--1mmmm + 1
1--__--1mmmm + 2
t-__--fmmmm + 3
This is a one-byte instruction which performs no operation, except that the Program
Counter is incremented and memory refresh continues. This instruction is present for
several reasons:
1) A program error that fetches an object code from non-existent memory will fetch
00. It is a good idea to ensure that the most common program error will do nothing.
2) The NOP instruction allows you to give a label to an object program byte:
HERE NOP
3) To fine-tune delay times. Each NOP instruction adds four clock cycles to a delay.
NOP is not a very useful or frequently used instruction.
3-114
OR data - OR IMMEDIATE WITH ACCUMULATOR
S ZAcP/ON C
F ~
Data
Memory
A
S,C
D.E
H,L
SP
PC
IX
IV
I
R
--' ~ xx ,.:x OR yy
'"
mmmm mmmm+2
Program
.........
Memory
I F6
I yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
OR
F6
data
yy
OR the Accumulator with the contents of the second instruction object code byte.
Suppose xx=3A16. After the instruction
OR 7CH
has executed. the Accumulator will contain 7E16·
3A 001 1 1 01 0
7C = 0 1 1 1 1 1 0 0
0111 1110
osets S to O ~ LSiX 1 bits. set PIO to 1
LNon-zero resu It set Z to 0
This is a routine logical instruction; it is often used to turn bits "on". For example. the
instruction
OR 80H
will unconditionally set the high-order Accumulator bit to 1.
3-115
OR reg - OR REGISTER WITH ACCUMULATOR
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
S 2 AC Pia N C
- ~
~
r.
xx OR yy
--.
} Co"JOfA
xx
....c. D, E. H or L
is yy
-
,
mmmm mmmm + 1
--
I
I
B.
Data
Memory
Program
Memory
10110xxx mmmm
1-------1mmmm + 1
mmmm+2
I------t
mmmm
+ 3
OR reg
--- -..-
10110 xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Logically OR the contents of the Accumulator with the contents of Register A B, C. D.
E, H or L. Store the result in the Accumulator.
Suppose xx=E316 and Register E contains A8l6. After the instruction
OR E
has executed. the Accumulator will contain EB16
001 1
1000
1 0 1 1
L Six 1 bits. set PIO to 1
LNon-zero resu It. set Z to 0
E3 1 1 1 0
A8 = 101 0
------
1 1 1 0
sets S to 1...J
3-116
OR (HL) - OR MEMORY WITH ACCUMULATOR
OR (IX+disp)
OR (IY+disp)
S Z AC PIO N C
Data
qq
mmm
mmm+1
mmmm+2
1-------.. mmmm + 3
~
Memory
-, ~
xx .......xx OR yy
yy
P
f
pp qQ
mmmm
~ m m m + ~
Program
Memory
I B6 m
I m
F
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of OR (HU:
OR (HU
~
86
OR contents of memory location (specified by the contents of the HL register pair) with
the AccumulatoL
Suppose xx=E316. ppqq=400016. and memory location 400016 contains A816' After
the instruction
OR (HU
has executed. the Accumulator will contain EB 16·
E3 1 1 1 0 00 1 1
AS = 1010 1000
1110 1011
1 sets S to 1...J LSix 1 bits. set PIO to 1
LNon-zero result. set Z to 0
OR (IX+disp)
-.--- -..-
DD B6 d
OR contents of memory location (specified by the sum of the contents of the IX register
and the displacement value d) with the AccumulatoL
OR (IY+disp)
--- -.-
FD 86 d
This instruction is identical to OR (IX+displ. except that it uses the IY register instead of
the IX register.
3-117
OUT (C) ,reg - OUTPUT FROM REGISTER
1)[
ED 01 xxx 001
-.-
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
5 Z AC PIO N C
+
CIIIIIJ
- I/O port vv I
I
}--"",J" B c.
I
vv
D, E, H or L
"
mmmm mmmm+ 2
........
I
I
Data
Memory
Program
Memory
ED mmmm
01xxxOO1 mmmm + 1
mmmm+2
t-----1 mmmm + 3
000 for reg=B
001 for reg=C
010 for reg=D
all forreg=E
100 for reg=H
101 for reg=L
111 for reg=A
Suppose yy= 1F16 and the contents of Hare AA16 After the execution of
OUT (C),H
AA16 will be in the buffer of I/O port 1F16'
3-118
OUTD - OUTPUT FROM MEMORY. DECREMENT ADDRESS
qq
mmm
mmm+ 1
mmmm+2
t-----t mmmm + 3
s Z AC P/O N C
xx-1
~
+
Data
~
~ I/O port yy I
Memory


I
pp
xx Vy ~
~ ~
I ~ p p q q - 1
I
qq
~
pp
--
Program
mmmm r--.. ... .J'
~ ~ m m m + 2
Memory
I ED m
I AS m
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
OUTD
~
ED AB
Output from memory location specified by HL to I/O port addressed by Register C.
Registers Band HL are decremented.
Suppose xx=OA16. yy=FF16. ppqq=500016. and memory location 500016 contains
7716 After the instruction
OUTD
has executed. 7716 will be held in the buffer of I/O port FF16. The B register will con-
tain 0916. and the HL register pair 4FFF16·
OTDR - OUTPUT FROM MEMORY. DECREMENT ADDRESS,
CONTINUE UNTIL REGISTER 8=0
OTDR
---...--
ED 88
OTDR is identical to aUTO. but is repeated until Register B contains O.
Suppose Reg ister B contains 0316. Register C contains FF 16. and HL contains 500016
Memory locations 4FFE16 through 500016 contain:
Location/Contents
4FFE16 CA16
4FFF16 1816
5000
16 F116
After execution of
OTDR
register pair HL will contain 4FFD16. Register 8 will contain zero. and the sequence
F116. 1816. CA16 will have been written to 1/0 port FF16.
This instruction is very useful for transferring blocks of data from memory to output
devices.
3-119
OUTI- OUTPUT FROM MEMORY. INCREMENT ADDRESS
qq
mmm
mmm+1
mmmm+2
I-----t!mmmm + 3
s Z Ac Pia N
C
xx-1
J
+
C
Data
GEGEIIJ
II
~
I/O port yy J
Memory
+
pp
xx
yy
....rppqq+ 1
pp qq
~
Program
mmmm
--
~ m m m + 2
Memory
I ED m
I A3 m
F
A
S.C
D.E
H.l
SP
PC
IX
IY
I
R
OUTI
-.-
ED A3
Output from memory location specified by HL to I/O port addressed by Register C
Register B is decremented and the HL register pair is incremented.
Suppose xx=OA16, yy=FF16' ppqq =500016, and memory location 500016 contains
7716 After the instruction
OUTI
has executed, 7716 wi II be held in the buffer of I/O port FF16 The B register will con-
tain 0916 and the HL register pair will contain 500116.
OTIR-OUTPUT FROM MEMORY. INCREMENT ADDRESS,
CONTINUE UNTIL REGISTER 8=0
OTIR
---
ED B3
OTIR is identical to OUTI, except that it is repeated until Register B contains 0
Suppose Register B contains 0416, Register C contains FF16, and HL contains 500016
Memory locations 500016 through 500316 contain:
Location/Contents
5000
16 CA16
5001
16 1B16
5002
16
81
16
5003
16 AD16
After execution of
OTIR
register pair HL will contain 500416, Register B will contain zero and the sequence
CA16, 1B16' B116 and AD16 will have been written to I/O port FF16
This instruction is very useful for transferring blocks of data from memory to an output
device.
3-120
OUT (port).A - OUTPUT FROM ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC PIO N C
+
Data
CIIIID
I
I/O port yy ~
Memory
+
,;t'
Program
mmmm mmmm+2
.......
Memory
I 03
I
'- yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
U
03 yy
Output the contents of the Accumulator to the I/O port identified by the second OUT in-
struction object code byte
Su ppose 3616 is held in the Accumu lator. After the instruction
OUT (lAHl.A
has executed. 3616 will be in the buffer of I/O port 1A16
The OUT instruction does not affect any statuses Use of the OUT instruction is very
hardware-dependent. Valid I/O port addresses are determined by the way in which I/O
logic has been implemented. It is also possible to design a microcomputer system that
accesses external logic using memory reference instructions with specific memory ad-
dresses OUT instructions are frequently used in special ways to control microcomputer
logic external to the CPU
3-121
POP rp - READ FROM THE TOP OF THE STACK
POP IX
POPIY
S Z AC Pia N C
Data
SSSS
SSSS + 1
SSSS + 2
mmmm
mmmm+ 1
......__~ m m m m + 2
......__--1mmmm + 3
D:IIIIJ
Memory

qq
~
I
pp
:,.(-SSSS+2
/7
ssss
~ - "
mmmm
-
-immmm + 1
Program
--
Memory
I 11000001
I
F
A
S.C
D_E
H.L
SP
PC
IX
IY
I'
R
The Illustration shows execution of POP BC:
POP rp
lZ-
11 xx 0001
00 for rp is reg ister pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is register pair A and F
POP the two top stack bytes into the designated register pair_
Suppose qq=0116 and pp=2A16- Execution of
POP HL
loads 01 16 into the L register and 2A16 into the H register. Execution of the instruction
POP AF
loads 01 into the status flags and 2A16 into the Accumulator Thus, the Carry status
will be set to 1 and other statuses will be cleared.
POP IX
~
DD E1
POP the two top stack bytes into the IX register
POP IY
-.,-
FD El
POP the two top stack bytes into the IY register.
The POP instruction is most frequently used to restore register and status contents
which have been saved on the stack: for example, while servicing an interrupt.
3-122
PUSH rp - WRITE TO THE TOP OF THE STACK
PUSH IX
PUSHIY
Data
ssss-2
ssss-1
ssss
mmmm
mmmm+ 1
mmmm+2
t-----1mmmm + 3
Memory
I
qq
----I pp
LsSSS-2 )
//
SSSS
,
~ m m m + v
mmmm
Program
Memory
ppqq
I FD
I E5
S Z AC Pia N C
FCIIIIIJ
A
B.C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of PUSH IY
PUSH IY
~
FD E5
PUSH the contents of the IY register onto the top of the stack.
Suppose the IY register contains 45FF16' Execution of the instruction
PUSH IY
loads 4516, then FF16 onto the top of the stack.
PUSH IX
~
DO E5
PUSH the contents of the IX register onto the top of the stack
LK
11 xx 0101
-..-
00 for rp is register pair Be
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is register pair A and F
PUSH contents of designated register pair onto the top of the stack
Execution of the instruction
PUSH AF
loads the Accumulator and then the status flags onto the top of the stack.
The PUSH instruction IS most frequently used to save register and status contents; for
example, before servicing an interrupt
3-123
RES b,reg - RESET INDICATED REGISTER BIT
S Z AC Pia N C
FCI:IJIIJ
Data
Memory
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
c
)
yyyyyyyy 0
.&
T
,
mmmm mmmm+2
.......
I
I
Program
Memory
CB mmmm
10bbbllllll mmmm + ,
mmmm+2
t-----t mmmm + 3
~ l \
CB 10 bbb xxx
-...- -...-
Bit bbb xxx
- -
a 000 000
1 001 001
2 010 010
3 all all
4 100 100
5 101 101
6 110 111
7 111
Reset I ndicated bit within specified register.
After the instruction
Register
B
C
D
E
H
L
A
RES 6,H
has executed, bit 6 in Register H will be reset (Bit a is the least significant bit)
3-124
RES b,{HL) - RESET BIT b OF INDICATED MEMORY POSITION
RES b,{IX+disp)
RES b, (lY+disp)
5 Z AC P/O N C Data
Fo:r:r::r:o Memory
c
0
~
yyyyyyyy ppqq+
a
T
';mmm+4
mmmm
Program
ppqq
........ Memory
1
I DD mmm
I
0
pqq
+
d
:)::
CB mmm
d mmm
10bbb110 mmm
mmm
A d
B.C
D,E
H.L
$P
PC
IX
IV
I m
R m+1
m+2
m+3
m+4
The illustration shows execution of SET b,(IX+disp). Bit a is execution of SET
b,(IX+disp). Bit a is the least significant bit.
~
DD CB d 10 bbb 110
bbb Bit Reset
000 a
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Reset ind icated bit within memory location indicated by the sum of Index Register IX
and d.
Suppose IX contains 411016 After the instruction
RES 0,(IX+7)
has executed, bit 0 in memory location 411716 will be O.
~
FD CB d 10 bbb 110
--.-
bbb is the same as in RES b.(IX+disp)
This instruction is identical to RES b, (IX+disp), except that it uses the IY register instead
3-125
of the IX register
RES b,(HL)
III
CB10bbb110
bbb is the same as in RES b,(IX+disp)
Reset indicated bit within memory location indicated by HL.
Suppose HL contains 444416· After execution of
RES 7,(HL)
bit 7 in memory location 444416 will be 0
RET - RETURN FROM SUBROUTINE
S Z Ac P/O N C Data
xxxx
xxxx + 1
xxxx + 2
mmmm
mmmm+ 1
mmmm+2
t-----4 mmmm + 3
CCIIII:l
Memory
,
qq
I
pp
.. ,
xxxx
-
Il xxxx';' 2
mmmm
.,
--
Program
Memory
L(
ppqq r- I C9
I
F
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
RET
C9
Move the contents of the top two stack bytes to the Program Counter: these two bytes
provide the address of the next instruction to be executed. Previous Program Counter
contents are lost. Increment the Stack Pointer by 2. to add ress the new top of stack.
Every subroutine must contain at least one Return (or conditional Return) instruction:
this is the last instruction executed within the subroutine, and causes execution to
return to the calling program.
3-126
RET cond - RETURN FROM SUBROUTINE IF CONDITION
IS SATISFIED
K
11 xxx 000
000
001
010
all
100
101
110
111
Condition
NZ Non-Zero
Z Zero
NC Non-Carry
C Carry
PO Parity Odd
PE Parity Even
P Sign Positive
M Sign Negative
Relevant Flag
Z
Z
C
C
Pia
Pia
S
S
CALL
AND
SUbl+--.....
This instruction is identical to the RET instruction, except that the return is not ex-
ecuted unless the condition is satisfied: otherwise, the instruction sequentially follow-
ing the RET cond Instruction will be executed
Consider the instruction sequence:
SUBR
7 C H ~
1
I
I
I ;First subroutine instruction
I
I condition satisfied
I
R T cond I
---------"
condition not
satisfied
a SOH
After the RET cond is executed. if the condition is satisfied then execution returns to the
AND instruction which follows the CALL. If the condition is not satisfied. the OR in-
struction. being the next sequentia I instruction. is executed,
3-127
RET cond - RETURN FROM SUBROUTINE IF CONDITION
IS SATISFIED
K
11 xxx 000
000
001
010
all
100
101
110
111
Condition
NZ Non-Zero
Z Zero
NC Non-Carry
C Carry
PO Parity Odd
PE Parity Even
P Sign Positive
M Sign Negative
Relevant Flag
Z
Z
C
C
Pia
Pia
S
S
CALL
AND
SUbl+--.....
This instruction is identical to the RET instruction, except that the return is not ex-
ecuted unless the condition is satisfied: otherwise, the instruction sequentially follow-
ing the RET cond Instruction will be executed
Consider the instruction sequence:
SUBR
7 C H ~
1
I
I
I ;First subroutine instruction
I
I condition satisfied
I
R T cond I
---------"
condition not
satisfied
a SOH
After the RET cond is executed. if the condition is satisfied then execution returns to the
AND instruction which follows the CALL. If the condition is not satisfied. the OR in-
struction. being the next sequentia I instruction. is executed,
3-127
RETI- RETURN FROM INTERRUPT
xxxx
xxxx +'
xxxx + 2
mmmm
mmmm+ 1
mmmm+2
mmmm+3
Data
Memory
qq
pp
- ~
xxxx I xxxx+2
mmmm
~
.-. Program
Memory
p p q q ~

ED
I 4D
S Z AC Pia N C
Fo:::I:IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
RETI
---
ED 4D
Move the contents of the top two stack bytes to the Program Cou nter: these two bytes
provide the address of the next instruction to be executed. Previous Program Counter
contents are lost Increment the Stack Pointer by 2, and address the new top of stack.
This instruction is used at the end of an interrupt service routine, and, in addition to
returning control to the interrupted program, it is used to signal an I/O device that the
interrupt routine has been completed. The I/O device must provide the logic necessary
to sense the instruction operation code: refer to An Introduction to Microcom-
puters: Volume 2 for a description of how the RETI instruction operates with the Z80
family of devices
3-128
RETN - RETURN FROM NON-MASKABLE INTERRUPT
Data
mmmm
mmmm+ 1
mmmm +2
mmmm
mmmm+ 1
1-----1 mmmm + 2
mmmm+3
t-----t
Memory
, qq
II
pp
-, )
xxxx _ t. xxxx + 2
mmmm
Ii-<ppqq =>-
Program
Memory
I ED
I
45
S ZACP/ON C
FOIIIlJ
A
B,C
D,E
H,L
SP
PC
IX
IV
I!
R
RETN
--.--
ED 45
Move the contents of the top two stack bytes to the Program Counter; these two bytes
provide the address of the next instruction to be executed. Previous Program Counter
contents are lost Increment the Stack Pointer by 2 to address the new top of stack.
Restore the interrupt enable logic to the state it had prior to the occurrence of the non-
maskable interrupt.
This instruction is used at the end of a service routine for a non-maskable interrupt, and
causes execution to return to the program that was interrupted.
3-129
RL reg - ROTATE CONTENTS OF REGISTER LEFT
THROUGH CARRY
Data
Memory
Program
Memory
CB mmmm
00010001 mmmm + 1
mmmm+2
t-----t mmmm + 3
s Z AC Pia N 1
F I x I x I 0\ x \ 0,\

t ~ A
u , ~
D,E
H,L
SP
- ~ V PC mmmm
~ m m m + 2
IX
IY
I

R
I
The illustration shows execution of RL C:
l\
CB 00010 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register left one bit through Carry,
Suppose 0 contains A916 and Carry=O After the instruction
RL 0
has executed, 0 will contain 5216 and Carry will be 1:
Before After
Register 0 Carry Register 0 Carry
11010 100 11
a sets S to a
3 ones. set P/0 to a
OJ
Non-zero resu It. set Z to 0
3-130
RL (HL) - ROTATE CONTENTS OF MEMORY LOCATION
RL (IX+disp) LEFT THROUGH CARRY
RL (IY+disp)
Data
Memory
......................... ..... + d
Program
Memory
DO mmmm
CB mmmm+ 1
d mmmm+2
___ mmmm + 3
mmmm+4
1---"""'1
A
_-----t--------i
B.C
D.E t--------t-------I
H.L
SP t---------"-------I
PC IX ppqq - __--
IY ... .....------.,
I
R
The illustration shows execution of RL (IX+disp)
RL (IX+disp)
--.,,- -.-

Rotate contents of memory location (specified by the sum of the contents of Index
Register IX and displacement integer d) left one bit through Carry.
Suppose the IX reg ister contains 400016. memory location 400716 contains 2f 16. and
Carry is set to 1. After execution of the instruction
RL
memory location 400716 will conta in 5F16. and Carry is 0
Before After
Memory Carry Memory Carry
1001 0 1 1 1 1] OJ [Q)
osets S to 0.J L...Non-zero result. set Z to 0
6 ones. set P10 to 1
RL (IY+disp)
R
This instruction is identical to RL (IX+dispL but uses the IY register instead of the IX
register.
3-131
RL (HL)
~
CB 16
Rotate contents of memory location (specified by the contents of the HL register pair)
left one bit through Carry
RLA - ROTATE ACCUMULATOR LEFT THROUGH CARRY
Data
Memory
Program
Memory
17 mmmm
~ __--1mmmm + 1
I-__~ m m m m + 2
I-__~ m m m m + 3
s Z AC PIO N 1
FI I 101 loP
s.c
D.E
H.L
SP
~ m m m + ~
PC mmmm
IX
IV
I
I
R
I
RLA
17
Rotate Accumu lalor contents left one bit through Carry status
Suppose the Accumulator contains 2A16 and the Carry status is set to 1 After the in-
struction
RLA
has executed. the Accumulator will contain F516 and the Carry status will be reset to 0:
Before After
Accu mu lator Carry Accumulator Carry
1011110101 OJ 111110101\ @]
3 -132
RLC reg - ROTATE CONTENTS OF REGISTER LEFT CIRCULAR
S Z AC-P/0 N C )
FIXIXIOIXlol....-
Data
Memory
Ar- """4 ......
B,C
. ~
H.L .-------"'-----------t
SP
~ ~ t------m==m:":m::':m=------i-_---4-..,.:rrmmmm +'9
IV
I: ...------r-.-------t
R I
Program
Memory
CB mmmm
00000011 mmmm + 1
mmmm +2
....------tl
mmmm
+ 3
The illustration shows execution of RLC E:
1-1
CB 00000 xxx
OJ
Carry
Non-zero result. set Z to 0
After
Register 0
osets S to 0
4 ones, set P/0 to 1
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register left one bit. copying bit 7 into Carry.
Suppose Register 0 contains A916 and Carry is 1, After execution of
RLC 0
Register 0 will contain 5316 and Carry will be 1.
Before
Reg ister 0 Carry
11 01010011 OJ
3-133
RLC (HL)-
RLC (Ix+disp)
RLC (lY+disp)
ROTATE CONTENTS OF MEMORY LOCATION
LEFT CIRCULAR
c
Data
Memory
L_.h::Q;iiIi++U-_Jppqq
m
m+ 1
mmmm+2
t--------I mmmm + 3

pp qq
mmmm

Program
Memory
I CS mmm
I 06 mmm
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of RLC (HL):
RLC

CB 06
Rotate contents of memory location (specified by the contents of the HL register pair)
left one bit. copying bit 7 into Carry.
Suppose register pair HL contains 54FF16 Memory location 54FF16 contains A516.
and Carry is O. After execution of
RLC (HL)
memory location 54FF16 will contain 4B16. and Carry will be 1:
Before After
Memory Carry Memory Carry
Non-zero resu It. set Z to 0
@]
osets S to O__J
4 ones. set P/0 to 1
RLC (IX+disp)

11 010010
1
1
Rotate memory location (specified by the su m of the contents of Index register IX and
displacement integer d) left one bit. copying bit 7 into Carry.
Suppose the IX register contains 400016. Carry is 1. and memory location 400716 con-
tains 2F16. After the instruction
RLC (IX+7)
3-134
has executed. memory location 400716 will contain 5E16. and Carry will be 0:
Before After
--- --
Memory Carry Memory Carry
OJ
10 0 1 0 1 1 1 11
osets S to 0
5 ones, set PIO to 0
RLC (IY+disp)
~ - . -
~
This instruction is identical to RLC (IX+displ. but uses the IY register instead of the IX
register.
RLCA - ROTATE ACCUMULATOR LEFT CIRCULAR
Data
Memory
Program
Memory
-
S Z AC
P/0N
0
FI I 101 101
B,C
D.E
H,L
SP
- ~ V
PC
mmmm
~ m m m + 1
IX
IY
I I
R I
07 mmmm
mmmm+ 1
r---t mmmm + 2
r---t mmmm+3
RLCA
----
07
Rotate Accumulator contents left one bit copying bit 7 into Carry.
Suppose the Accumu lator contains 7A16 and the Carry status is set to 1. After the in-
struction
RLCA
has executed. the Accumulator will contain F416 and the Carry status will be reset to 0:
Before After
Accumulator Carry
1011110101 OJ
RLCA should be used as a logical instruction
Accumulator Carry
1111101001 @]
3-135
RLD - ROTATE ONE BCD DIGIT LEFT BETWEEN
THE ACCUMULATOR AND MEMORY LOCATION
Data
m
m+ 1
...-__ mmmm + 2
...-__ mmmm + 3
x
I
y r 5 ppqq
t
pp qq

mmmm
-
Program
Memory
I ED mmm
I 6F
mmm
S Z AC p/O N C

A
B.C
D.E
HL
SP
PC
IX
IV
I
R
RLD
---
ED 6F
The fou r low-order bits of a memory location (specified by the contents of register pair
HU are copied into the four high-order bits of the same memory location The previous
contents of the fou r high-order bits of that memory location are copied into the four
low-order bits of the Accumulator The previous four low-order bits of the Accumulator
are copied into the four low-order bits of the specified memory location.
Suppose the Accumulator contains 7F, 6, HL register pair contains 4000, 6. and memo-
ry location 4000'6 contains 1216 After execution of the instruction
RLD
Memory
Non-zero result. set Z to 0 high-order bit=O, set S to 0
4 ones, set P10 to ,
the Accumulator will contain 7116 and memory location 400016 will contain 2F16:
Before After
Accumulator Memory Accumulator

\ /'
\ -"
", ,"
........
3-136
RR reg - ROTATE CONTENTS OF REGISTER RIGHT THROUGH
CARRY
Data
Memory
Program
Memory
5 Z AC P/O N ~

FIXIXlotxtO\
-.-
~
A
~ . ~
D,E
H,L
SP
- /" !)
PC mmmm ~ m m m + 2
IX
IY
I
I
R
I
CB mmmm
00011001 mmmm + 1
mmmm +2
1-----1mmmm + 3
The illustration shows execution of RR C:
-L\
CB 00011 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register right one bit through Carry
Suppose Register H contains OF 16 and Carry is set to 1, After the instruction
RR H
has executed. Register H wi II contain 8716. and Carry wi II be 1:
Before After
-- --
Register H Carry Register H Carry
1000011111 IT] 10000111
1 sets S to 1
4 ones. set P/0 to 1
LNon-zero result. set Z to a
3-137
RR (HL) - ROTATE CONTENTS OF MEMORY LOCATION
RIGHT THROUGH CARRY
RR (Ix+disp)
RR (lY+disp)
q+d
m
m + 1
m +2
m+3
m+4
-
s Z AC P '0 N C
Data
rXIXIOIXIOIl
,. Memory I
..
ppq
l"
_/ 9
mmmm ...;,-- -. mmmm + 4
Program
Memory
ppqq
1
I FD mmm
I CB
C;pqq + d'"""'-
mmm
d
mmm
~ -
1E
mmm
mmm
F
A
B.C
DE
HL
SP
PC
IX
IY
I
R
The illustration shows execution of RR (lY+disp):
~ + d i ~ . e l
J;;h
Rotate contents of memory location (specified by the sum of the contents of the IY
register and the displacement value d) right one bit through Carry
Suppose the IY register contains 450016. memory location 450F16 contains 1016_ and
Carry is set to 0 After execution of the instruction
RR (IY+OFH)
memory location 450F16 will contain OE16. and Carry will be 1:
Before After
Memory Carry Memory Carry
100011101\ [Q] [j]
Non-zero result set Z to 0 osets S to 0
3 ones. set P/O to 0
RR (IX+disp)
~ -..-
J;;h
This instruction is identical to RR (lY+displ. but uses the IX register instead of the IY
register.
3-138
RR (HU

CB 1E
Rotate contents of memory location (specified by the contents of the HL register pair)
right one bit through Carry
RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY
Program
Memory
Data

1F mmmm
I-__-Immmm + 1
I-__-Immmm + 2
1-__-1mmmm + 3
s
F I I 101 101
1
'"
s.c
D.E
H.L
SP
- PC mmmm
1
IX
IY
I
I
R I
RRA
1F
Rotate Accumu lator contents rig ht one bit through Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1. After the in-
struction
RRA
has executed, the Accumulator will contain BD16 and the Carry status will be reset to
0:
Before
Accumulator Carry
1011110101 OJ
After
Accumulator Carry
1101 1 1 1 01l @]
3-139
RR (HU

CB 1E
Rotate contents of memory location (specified by the contents of the HL register pair)
right one bit through Carry
RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY
Program
Memory
Data

1F mmmm
I-__-Immmm + 1
I-__-Immmm + 2
1-__-1mmmm + 3
s
F I I 101 101
1
'"
s.c
D.E
H.L
SP
- PC mmmm
1
IX
IY
I
I
R I
RRA
1F
Rotate Accumu lator contents rig ht one bit through Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1. After the in-
struction
RRA
has executed, the Accumulator will contain BD16 and the Carry status will be reset to
0:
Before
Accumulator Carry
1011110101 OJ
After
Accumulator Carry
1101 1 1 1 01l @]
3-139
RRC (HL)-
RRC (IX+disp)
RRC (ly+disp)
ROTATE CONTENTS OF MEMORY LOCATION
RIGHT CIRCULAR
C
Data
Memory
pqq
m
m+ 1
mmmm+2
t-----t mmmm + 3
p
t
pp qq
-
--
Program
mmmm mmmm+2
-
....... Memory
i I CB mmm
I DE mmm
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of RRC (HU:
RRC (HU
~
CB OE
Rotate contents of memory location (specified by the contents of the HL register pair)
right one bit circularly, copying bit 0 into the Carry status,
Suppose the HL register pair contains 450016. memory location 450016 contains
3416. and Carry is set to 1. After execution of
RRC (HU
memory location 450016 will contain 1A16' and Carry will be 0:
Before After
Memory Carry Memory Carry
1001101001 OJ 0011010
lNon-zero result. set Z to 0 osets S to 0
3 ones, set P/0 to 0
RRC (IX+disp)
~
Rotate contents of memory location (specified by the sum of the contents of the IX
3-141
register and the displacement value d) right one bit circularly, copying bit 0 into the Ca-
rry status.
RRC (IY+disp)
'Xh
This instruction is identicaf to the RRC (IX+disp) instruction, but uses the IY register in-
stead of the IX register.
RRCA - ROTATE ACCUMULATOR RIGHT CIRCULAR
Program
Memory
Data
~
OF mmmm
mmmm+ 1
~ - - - I mmmm + 2
~ __-I mmmm + 3
s Z AcP/ON C

r
F I I 101 10 I
s,c
D,E
H,L
SP
--
PC mmmm -'w mmmm + 1
IX
.......
IV
I I
R
I
RRCA
----
OF
Rotate Accumulator contents right one bit circularly, copying bit 0 into the Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1 After the in-
struction
RRCA
has executed, the Accumulator will contain 3016 and the Carry status will be reset to
0:
Before
Accu mu lator Carry
1011110101 OJ
After
Accumulator Carry
1001111011 [Q]
RRCA should be used as a logical instruction.
3-142
RRD - ROTATE ONE BCD DIGIT RIGHT BETWEEN THE
ACCUMULATOR AND MEMORY LOCATION
S Z AC Plo N C Data
q
mm
mm+ 1
mmmm+2
1----"""'1mmmm + 3

I
x
I V
r I s
Of
-r=
pp qq
-, V Program
mmmm
I. mmmm+2
- -
Memory
I
ED mm
I
67 mm
F
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
RRD
--.....--
ED 67
The four high-order bits of a memory location (specified by the contents of register pair
HL) are copied into the four low-order bits of the same memory location. The previous
contents of the four low-order bits are copied into the four low-order bits of the Ac-
cumu lator. The previous four low-order bits of the Accumulator are copied into the four
high-order bits of the specified memory location.
Suppose the Accumulator contains 7F16. HL register pair contains 400016. and memo-
ry location 400016 contains 1216. After execution of the instruction
RRD
the Accumu lator will contain 7216 and memory location 400016 will contain F116:
Before After
-- --
Accumu lator Memory
7,'" F' ,
\ \ I
\ I
" '.(
, ... _" ,-"
High-order bit=O. set S to 0
4 ones. set P/0 to 1
Accumulator Memory
lIID
LNon-mo ,.sult
set Z to 0
3-143
RST n - RESTART
S Z AC p/o N C Data
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
o::::r::n:I:l
Memory
j mm+ 1
""1 mm
(PPQQ-2)
~ ........
ppqq
V"_ ~ m m m +y.
mmmm
Program
Memory
I
I
COOOOOOOOOOxxxOOO
11 xxx 111
I
ppqq-2
ppqq-1
ppqQ
mmmm
mmmm+ 1
mmmm+2
mmmm+3
SUBROUTINE
CALL USING
RST
R
11 xxx 111
Call the subroutine origined at the low memory address specified by n
When the instruction
RST 18H
has executed. the subroutine origined at memory location 001816 is called, The pre-
vious Program Counter contents are pushed to the top of the stack.
Usually. the RST instruction is used in conjunction with interrupt processing. as de-
scribed in Chapter 12,
If your application does not use all RST instruction codes to service
interrupts. do not overlook the possibility of calling subroutines
using RST instructions. Origin frequently used subroutines at ap-
propriate RST addresses. and these subroutines can be called with
a single-byte RST instruction instead of a three-byte CALL instruction
3-144
SBC A.data - SUBTRACT IMMEDIATE DATA FROM
ACCUMULATOR WITH BORROW
s Z AC PIO N J 1
Data
~
ft
~ X - Y Y - C r
Memory
xx
-, V Program
mmmm _ - ..",:.mmm + 2
Memory
I DE
I
"-
YY
F
mmmm
R mmmm+l
mmmm+2
mmmm+3
A
B,C
D,E
H,L
SP
PC
IX
IY
SBC A data
--...- -.-
DE yy
Subtract the contents of the second object code byte and the Carry status from the Ac-
cumulator
Suppose xx=3A16 and Carry=l, After the instruction
SBC A7CH
has executed, the Accumulator will contain B016.
3A
Twos camp of 7C
Twas camp of Carry
1 sets S to 1
Borrow. set C to 1
1¥ 1=0. set P/O to 0
0011 1010
1000 0100
1111 1111
1011 1101
fJ LNon-ze,o <esult. set Z to a
-----Borrow. set AC to 1
Subtract instruction. set N to 1
The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.
3-145
SBC A,reg - SUBTRACT REGISTER WITH BORROW
FROM ACCUMULATOR
A
B.C
D.E
HL
SP
PC
IX
IY
I
R
r
i S Z AC plO N C
~
xx-yy-C
t
}-Coo,"o:t A B
xx
C. D, E. H or L
is yy
, - ~ m m m + v mmmm
I
I
Data
Program
Memory
l00llxxx mmmm
mmmm+ 1
1------1mmmm + 2
1--__....... mmmm +3
reg SBC A.
-.--'
10011
--.-
xxx
--.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Subtract the contents of the specified register and the Carry status from the Accumu la-
tor.
Suppose xx=E316' Register E contains A016. and Carry=l. After the instruction
SSC A,E
has executed. the Accumulator will contain 4216
E3
Two' s camp of AO
Two's comp of 1
asets S to 0
No borrow. set C to a
1¥1 =0. set P/O to a
1 1 1 0 001 1
0110 0000
1 1 1 1 1 1 1 1
0100 0010
r LNoo-,em '"'"'I. ,et Z to a
"------No borrow. set AC to a
Subtract instruction. set N to 1
The Carry flag is set to 1 for a borrow and reset to aif there is no borrow.
3-146
sac A,(HL)-
sac A,UX+disp)
sac A,UY+disp)
SUBTRACT MEMORY AND CARRY FROM
ACCUMULATOR
S Z AC P/O N C
Data
m
m+ 1
mmmm+2
1-----1 mmmm + 3
IXIXIXIXllIX.
Memory
.1
xx
yy
PO;
pp qq
-
-
mmmm 1
Program
Memory
I 9E mmm
I mmm
F
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SSC A. (HU:
SSC A,(HU
-.,--
9E
Subtract the contents of memory location (specified by the Contents of the HL register
pair) and the Carry from the Accumulator,
Suppose Carry=O. ppqq=400016. xx=3A16. and memory location 400016 contains
7C16. After execution of the instruction
SSC A,(HU
the Accumulator will contain BE16.
3A a01 1
Two'S comp of 7C 1 aa0
Two's comp of Carry
1 010
0100
o
1 sets S to 1
Borrow. set C to 1
O¥O=O. set P/O to a
1011 1110
}.J L Non-2O'o 'esult. set Z to a
L... Borrow. set AC to 1
Subtract instruction. set N to 1
The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.

DD 9E d
Subtract the contents of memory location (specified by the sum of the contents of the
IX register and the displacement value d) and the Carry from the Accumulator
SBC A,{IY+disp)

FD 9E d
This instruction is identical to the SSC A, {IX+displ instruction, except that it uses the IY
register instead of the IX register,
3-147
SBC HL,rp - SUBTRACT REGISTER PAIR WITH CARRY
FROM HAND L
Data
Memory
Program
Memory
ED mmmm
01xxOO10 mmmm + 1
1-__ mmmm + 2
1-__ mmmm + 3
,
I
Be. DE. HL or SP
contains yyyy
xx xx
J

mmmm
-
I
I
S Z AC PIO N C

B.C
D.E
H.L
SP
PC
IX
IV
I
R
K
01 xx 0010
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Subtract the contents of the designated register pair and the Carry status from the HL
register pair.
Suppose HL contains F4A216. BC contains A03416. and Carry=O. After the instruction
SBC HL,BC
has executed. the HL register pair will conta in 546E16:
Two's camp of F4A2
Two's camp of A034
Two's camp of Carry
1111 0100 1010
010111111100
0010
1100
o
osets S to 0
No borrow. set C to 0
OWl 01 00 0 11 0 111 0
... L__ set Z to 0
1 ¥ 1=0. set P/O to 0 Subtract instruction. set N to 1
The Ca rry flag is set to 1 for a borrow and reset to 0 if there is no borrow.
3-148
SCF - SET CARRY FLAG
Program
Memory
Data
Memory
37 mmmm
1------.. mmmm + ,
1-__...... mmmm + 2
1------4 mmmm + 3
S Z AC P/O N C
~
r I I I I I
,
- ' ~ m m m + v
mmmm
I
I
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
F
SCF
37
When the SCF instruction is executed. the Carry status is set to 1 regardless of its pre-
vious value. No other statuses or register contents are affected.
3-149
SET b.reg - SET INDICATED REGISTER BIT
S Z AC PIO N C
FCIIIIIJ
Data
Memory
A
B.C
O.E
H.L
SP
PC
IX
IY
I
R
r
1
"-

yyyy yyyy
-'-
mmmm mmmm + 2
-
........
I
I
l l ~ ~
CB 11 bbb xxx
-.- --
Bit bbb xxx Register
-
a 000 000 B
1 001 001 C
2 010 010 0
3 011 011 E
4 100 100 H
5 101 101 L
6 110 111 A
7 111
Program
Memory
CB mmmm
11bbbxxx mmmm + 1
mmmm+2
......----1mmmm + 3
SET indicated bit within specified register. After the instruction
SET 2.L
has executed, bit 2 in Register L will be set. (Bit a is the least significant bit.)
3-150
SET b,(HL} - SET BIT b OF INDICATED MEMORY POSITION
SET b, (IX+disp)
SET b, (lY+disp)
S Z AC P/O N C
FCI:IIIJ:]
qq
mm
mm+ 1
mmmm+2
t-----t
mmmm
+ 3
yyyy yyyy
P
f
pp qq
- ~
Program
mmmm
-
I mmmm + 2
......... Memory
I CB mm
I 11bbbl10 mm
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SET b.(HU. Bit 0 is the least significant bit
1 1 ~ ~
CB 11 bbb 110
Bit Set bbb
o 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Set indicated bit within memory location indicated by HL.
Suppose HL contains 400016. After the instruction
SET 5.(HU
has executed. bit 5 in memory position 400016 will be 1.
SET b,(IX+disp)
bbb is the same as in SET b,(HU
Set indicated bit within memory location indicated by the sum of Index Register IX and
displacement
3-151
Suppose Index Register IX contains 400016. After execution of
SET 6.0X+5Hl
bit 6 in memory location 400516 will be 1.
~
FD CB d 11 bbb 110
bbb is the same as in SET b.(HU
This instruction is identical to SET b.(lX+disp), except that it uses the IY register instead
of the IX register
SLA reg - SHIFT CONTENTS OF REGISTER LEFT ARITHMETIC
Data
Program
Memory
CB mmmm
00100001 mmmm + 1
t------4 mmmm + 2
t------4 mmmm + 3
s Z ACP/O N 1.
FIXIXIOIXIOI'I
A
r
u.v
'"
° D.E
H.L
SP
~ m m m + ~
PC mmmm
IX
IV
I I
R
I
The illustration shows execution of SLA C:
SLA reg
I ~
CB 00100 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift contents of specified register left one bit. resetting the least significant bit to O.
Suppose Register B contains 1F16. and Carry= 1 After execution of
SLA B
Register B will contain 3E16 and Carry will be zero
3-152
Before
Register B Carry
1000111111 m
After
Register B Carry
0111110 [Q]
osets S to 0
5 ones, set P/0 to 0
Non-zero result set Z to 0
SLA (HL)-
SLA (lX+disp)
SLA (lY+disp)
SHIFT CONTENTS OF MEMORY LOCATION
LEFT ARITHMETIC

Data
Memory
Program
Memory
CB mmmm
26 mmmm +'
mmmm+2
t-----t mmmm + 3
A

D,E
H,L J- PP qq


mmmm
IX --__p-
lY ------....-------i
I
R
The illustration shows execution of SLA (HL):
SLA (HL)

CB 26
Shift contents of memory location (specified by the contents of the HL register pair} left
one bit resetting the least significant bit to O.
Suppose the HL register pair contains 450016, memory location 450016 contains
8416. and Carry=O. After execution of
SLA (HL)
memory location 450016 will contain 0816, and Carry will be 1.
Before After
-- --
Memory Carry Memory Carry
110000100\ IT] 0001000 ill
osets S to 0
one. set P/0 to 0
l Non-zero resu It set Z to 0
3-153
SLA (IX+disp)
li
Shift contents of memory location (specified by the sum of the contents of the IX
register and the displacement value d) left one bit arithmetically. resetting least signifi-
cant bit to 0
SLA (IY+disp)
' ~
This instruction is identical to SLA (IX+disp). but uses the IY register instead of the IX
register.
SRA reg - ARITHMETIC SHIFT RIGHT CONTENTS OF
REGISTER
S Z ACP/ON C
F
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
IxrXIOlxlOI
-
~
{
141
'-
mmmm
~ m m m + v
-
I
I
Data
Memory
Program
Memory
CB mmmm
00101111 mmmm + 1
mmmm+2
I-----t mmmm + 3
The illustration shows execution of SRA A:
SRA reg
I ~
CB 00101 xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift specified register right one bit Most significant bit is unchanged,
Suppose Register H contains 5916. and Carry=O. After the instruction
SRA H
has executed. Register H will contain 2C16 and Carry will be 1.
3-154
Before
Register H
10 1 0 1 1 00 11
C
@]
After
Register H
00101100
C
OJ
osets S to 0
3 ones, set P/0 to 0
L.Non-zero result. set Z to 0
SRA (HL)-
SRA (IX+disp)
SRA (ly+disp)
ARITHMETIC SHIFT RIGHT CONTENTS OF
MEMORY POSITION
Data
Memory
m
m+ ,
m+2
m+3
m+4
+d
L
ppqq

- ~ ~
Program
mmmm mmmm+4
ppqq I- "-
Memory
I DO mmm
I - CB mmm
~ p q q + d ~ d
mmm
~ -
2E mmm
mmm
R
A
Be
D.E
H.L
5P
PC
IX
IY
The illustration shows execution of SRA (IX+disp)
SRA (IX+disp)
~ - . -
~
Shift contents of memory location (specified by the sum of the contents of Register IX
and the displacement value d) right Most significant bit is unchanged.
Suppose Register IX contains 340016. memory location 34AA16 contains 2716. and
Carry=l After execution of
SRA (IX+OAAH)
memory location 34AA16 will contain 1316. and Carry will be 1.
Before After
Memory Carry Memory Carry
[001001111 00010011
OJ
osets S to 0
3 ones. set P/0 to 0
L..Non-zero result. set Z to 0
3-155
SRA (IY+displ
'-;R
This instruction is identical to SRA (IX+displ. but uses the IY register instead of the IX
register.
SRA (HLl
~
CB 2E
Shift contents of memory location (specified by the contents of the HL register pair)
right one bit. Most significant bit is unchanged.
SRL reg - SHIFT CONTENTS OF REGISTER RIGHT
LOGICAL
,
0
~
-
s Z AC P/O N C
FlolxlOlxlOI
- ,
A j
S.C
~ . L
H.L
SP
_/
PC mmmm mmmm+2
IX -
~
IY
I I
R I
Data
Memory
Program
Memory
CB mmmm
00111011 mmmm+ 1
mmmm+2
1-----1mmmm + 3
The illustration shows execution of SRL E:
SRL reg
l ~
CB 00111 xxx
--.-
000 for reg=B
001 for reg=C
010 for reg=D
011 forreg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift contents of specified register right one bit. Most significant bit is reset to O.
Su ppose Register 0 contains 1F16' and Carry=O. After execution of
SRL 0
Register 0 will contain OF, 6, and Carry will be 1.
3-156
Before
Register D Carry
1000111111 @]
4 ones, set P/0 to 1
After
Register D Carry
10000 1 1 1 11 [JJ
~
L...Non-zero result. set Z to 0
SRL (HL)-
SRL (IX+disp)
SRL (IV+disp)
SHIFT CONTENTS OF MEMORV LOCATION
RIGHT LOGICAL
Data
m
m+1
mmmm+2
1---....... mmmm + 3
t
pp
I
qq
mmmm
~ m m m + v
Program
Memory
I CB mmm
I 3E mmm
S Z AC PIO N C
: ~ x o X 0 ....
B.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SRL (HL):
SRL (HL)
-...,.-...-
CB 3E
Shift contents of memory location (specified by the contents of the HL register pair)
right one bit. Most significant bit is reset to O.
Suppose the HL register pair contains 200016, memory location 200016 contains 8F16.
and Carry=O. After execution of
SRL (HU
Carry
4 ones, set P/0 to 1
memory location 200016 will contain 4716. and Carry will be 1.
Before After
Memory Carry Memory
1100011111 [Q] 1010001111 OJ
~
L.. Non-zero result. set Z to 0
SRL (IX+disp)
~
Shift contents of memory location (specified by the sum of the contents of the IX
register and the displacement value d) right one bit. Most significant bit is reset to O.
3-157
SRL (IY+disp)
' ~
This instruction is identical to SRL (IX+displ. but uses the IY register instead of the IX
register
SUB data -SUBTRACT IMMEDIATE FROM ACCUMULATOR
- ~ J.
xx
___ xx-yy
-, "D Program
mmmm
~ m m m + 2
Memory
I 06
I
.....
yy
A
B.C
D.E
H.L
SP
PC
IX
IY
I mmmm
R mmmm + 1
mmmm+2
mmmm+ 3
S Z AC P/O N C Data
F ~ Memory
SUB data
-,.-. --.-
06 yy
Subtract the contents of the second object code byte from the Accumulator.
Suppose xx=3A16. After the instruction
SUB 7CH
Subtract instruction. set N to 1
has executed. the Accumulator will contain BE16·
3A 001 1 1 0 1 0
Two's comp of 7C = 1 000 01 00
1011 1110
1 sets S to 1 t-J LNon.zem ,esult. set Z to a
Borrow. set C to 1 L Borrow. set AC to 1
o¥ 0=0. set P/O to 0
Notice that the resulting carry is complemented.
3-158
SUB reg - SUBTRACT REGISTER FROM ACCUMULATOR
Program
Memory
Data
Memory
10010xxx mmmm
1-__--1 mmmm + 1
I-__--Immmm + 2
1-__--1 mmmm + 3
, C,
y
S Z AC PIO N C
. ~ ")
mEIEIEJIIE]
f.
-'....... xx-yy
}-CM"I. '" ,
xx
D, E, H or L is y
~ - . ~ m m m + ~
mmmm
1
I
F
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
reg SUB
----
10010 xxx
--.-
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg =L
111 for reg=A
Subtract the contents of the specified register from the Accumulator.
Suppose xx=E3 and Register H contains A016 After execution of
SUB H
Subtract instruction, set N to 1
osets S to 0
No borrow, set C to 0
the Accumulator will contain 4316-
E3 =:: 1 1 1 0 0 0 1 1
Two's comp of AD = 0 1 1 0 0000
0100 0011
fJ LNon-,em ,.sult, s.t Z to a
.... - -----No borrow, set AC to 0
1 ¥ 1=0. set P/0 to 0
Notice that the resu Iting carry is complemented.
3-159
SUB (HL) - SUBTRACT MEMORY FROM ACCUMULATOR
SUB (Ix+disp)
SUB (lY+disp)
m
m+ 1
m+2
m+3
+d
Data
x X X X 1 X
Memory
-" J.- xx _ 1,,- xx-yy yy ppqq

- V mmmm
_ 1 mmmm +3 Program
ppqq I-- ......... Memory
I DD mmm
I 96

mmm
d mmm
mmm
A
RC
D.E
H.L
SP
PC
IX
IY
I
R
S Z AC PIO N C

The illustration shows execution of SUB (IX+dl:
SUB (IX+disp)

DO 96 d
Subtract contents of memory location (specified by the su m of the contents of the IX
register and the displacement value d) from the Accumulator.
Suppose ppqq=400016. xx=FF16. and memory location 40FF16 contains 5016 After
execution of
1¥ 1=0. set P/O to 0
Notice that the resu Iting carry is complemented.
SUB (IY+disp)

Su btract instruction. set N to 1
1111 1111
101 1 0000
1010 1111
fJ LNon-zero 'esult, set Z to a
",- No borrow. set AC to 0
1 sets S to 1
No borrow, set C to 0
SUB (IX+OFFH)
the Accumulator will contain AF16·
FF
Two's comp of 50 =
FD 96 d
This instruction is identical to SUB (IX+disp). except that it uses the IY register instead
of the IX register.
SUB (HU

96
Subtract contents of memory location (specified by the contents of the HL register pair)
from the Accumulator
3-160
XOR data - EXCLUSIVE-OR IMMEDIATE WITH ACCUMULATOR
S ZACP/ON C
F ~
Data
Memory
A
B,C
D,E
H.L
SP
PC
IX
IV
I
R
- ~ > xx ........ xx¥yy
- ,,-
Program
mmmm mmmm+2
.......
Memory
I EE
I
"- yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
XOR data
EE yy
Exclusive-OR the contents of the second object code byte with the Accumulator.
Suppose xx=3A16. After the instruction
XOR 7CH
has executed, the Accumulator will contain 4616
3A 001 1
7C = 01 1 1
-------
0100
osets S to O ~
1 0 1 0
1 1 00
01 1 0
LNon-zero resu It set Z to 0
LThree 1 bits, set Pia to 0
The Exclusive-OR instruction IS used to test for changes in bit status.
3-161
XOR reg - EXCLUSIVE-OR REGISTER WITH ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
s Z AC P/O N C
- ~ ~
I!IEIIImI[)
f,
I......... xx¥yy
~ Co,,,LA'
C, 0, E, H or L
is yy
-,
mmmm mmmm + 1
--
I
I
Data
Memory
Program
Memory
lO1Olxxx mmmm
1-----1mmmm + 1
mmmm+2
1-----1mmmm + 3
reg XOR
-..-
10101 xxx
-..-
000 for reg= B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Exclusive-OR the contents of the specified register with the Accumulator.
Suppose xx=E316 and Register E contains A016. After the instruction
XOR E
has executed, the Accumulator will contain 4316.
E3 1 1 1 a
AO = 1 a 1 a
-------
a 1 aa
osets S to o..J
001 1
0000
001 1
L Non-zero resu It set Z to a
LThree 1 bits. set PIO to 0
The Exclusive-OR instruction is used to test for changes in bit status.
3-162

8080A
UNUSED
OPERATION
CODES
8080A/Z80
COMPATIBILITY
FEATURES
8080A/Z80
ASSEMBLY
LEVEL
CONVERSION
2-BYTE
OPERATION
CODES
8080A/Z80
INCOMPATIBILITIES
8080A!Z80 COMPATIBILITY
Although the Z80 microprocessor can certainly be used on
its own merits. one of its important characteristics is its
compatibility with the 8080A microprocessor. This com-
patibility has the following features:
1) All BOBOA machine language instructions are also l80 machine language instruc-
tions
2) All B080A registers are also l80 registers (see Table 3-6l.
3) Almost all 80BOA programs will run on a l80. with some minor differences to be
noted later.
4) The l80 has instructions. registers. and other features not present on the 8080A,
so l80 programs will not generally run on B080A processors.
Note that this compatibility does not extend to assembly
language source statements since l80 assemblers and B080A
assemblers use different operation code mnemonics. Table 3-7
contains a list of the 8080A mnemonic codes and the corres-
ponding Z80 code•. while Table 3-8 Is the same list organized
by Z80 code•.
Readers should note the binary coding limitations that this com-
patibility places on the extra features of the Z80 microprocessor.
The 8080A has some unused operation codes (see Table 3-9) that
are used for some of the l80's extra instructions. But there are
simply not enough such codes to cover the large number of
features in a simple form.
Thus. many of the added Z80 instructions require a 2-byte opera-
tion code. The first byte is CB. DO. ED. or FD. Note the following
meanings of these codes from Table 3-9:
CB - a register or bit operation
DO - an operation involving register IX
ED - a miscellaneous non-8080A instruction not covered elsewhere
FD - an operation involving register IY
The second byte of the operation code describes the actual operation to be performed.
The end result is that these multi-byte instructions execute rather FASTER AND
slowly (and use more memory) because an additional memory SLOWER
access is required The reader should be aware of this variation in EXECUTING
execution times and try to use faster executing instructions when INSTRUCTIONS
possible. This warning particularly applies to the extra shift
instructions (RLC, RRC, RL. RR. SRA, SRL) and to instructions involving the index
registers IX and IY.
There are a few minor incompatibilities between the
8080A and the Z80. These are:
1) The Z80 uses the P (or P/O) flag to indicate twos com-
plement overflow after arithmetic operations. The 8080A always uses this flag for
parity.
2) The l80 and 8080A execute the DAA instruction differently. On the l80, this in-
struction will correct decimal subtraction as well as decimal addition. On the
8080A, it will correct only decimal addition
3) The l80 rotate instructions clear the AC flag. The 8080A rotate instructions do
not' affect the AC flag.
3-164
Table 3-6. Register and Flag Correspondence between
laO and 8080A
Z80 Regl'ter
A
A'
B
B'
C
C'
o
0'
E
E'
F
F'
H
H'
I
IX
IY
L
L'
R
PC
SP
Z80 Regl'ter Pair,
BC
DE
HL
AF
Z80 Fleg.
C (Carryl
104 (Half -Carry)
N (Subtract)
P/O (Parity/Overflow)
S ISign)
Z (Zero)
8080.\ Regi,ter
A
None
B
None
C
None
o
None
E
None
Least S ~ n i f i c a n t Half of PSW
None
H
None
None
None
None
L
None
None
PC
SP
8080.\ Regl'ter Pel,.
B
o
H
PSW
8080" Fleg,
C (Carry)
AC (Auxiliary Carry)
None
P (Parity)
5 (Sign)
Z (Zero)
The l80 is not compatible with the extra features of
the 808& microprocessor. The codes used for RIM and
SIM on the 8085 are used for relative jumps (Nl and NC) on
the l80.
808&!l80
INCOMPATIBILITIES
TIMING
INCOMPATIBILITIES
Instruction timings on the 8080A, 808&, and Z80 all
differ. Programs that depend on precise instruction tim-
ings will therefore execute properly only on the pro-
cessor for which they were written.
The N flag on the l80 occupies bit 2 of the F register: the corresponding bit in the
Processor Status Word of the 8080A is always a logic "'.
3-165
Table 3-7 Correspondence between 8080A and Z80 Mnemonics
8080A Mnemonic l80 Mnemonic
ACI data ADC A,data
ADC reg or M ADC A,reg or (HLl
ADD reg or M ADD A,reg or (HL)
ADI data ADD A,data
ANA reg or M AND reg or (HLl
ANI data AND data
CALL addr CALL addr
CC addr CALL C,addr
CM addr CALL M,addr
CMA CPL
CMC CCF
CMP reg or M CP reg or (HLl
CNC addr CALL NC.addr
CNZ addr CALL NZ.addr
CP addr CALL P.addr
CPE addr CALL PE.addr
CPI data CP data
CPO addr CALL PO.addr
CZ addr CALL Z.addr
OM
.
OM
f DAD rp ADD HL,rp
OCR reg or M DEC reg or (HLl
DCX rp DEC rp
01 01
EI EI
HLT HALT
IN port IN A.(port)
INR reg or M INC reg or (HLl
INX rp INC rp
JC addr JP C,addr
JM addr JP M.addr
JMP addr JP addr
JNC addr JP NC,addr
JP addr JP P.addr
JNZ addr JP NZ.addr
JPE addr JP PE.addr
JPO addr JP PO,addr
JZ addr JP Z,addr
LOA addr LD A.laddr)
LOAX B or 0 LD A.(BCI or (DEI
8080A Mnemonic laO Mnemonic
LHLO addr LD HL.(addrl
LXI rp.data16 LD 'P.data16
MOV reg.reg or M LD reg.reg or (HL)
MOV reg or M,reg LD reg or (HLl.reg
MVI reg or M.data LD reg or (HLl.data
NOP NOP
ORA reg or M OR reg or (HLl
ORI data OR data
OUT port OUT (port), A
PCHL JP (HLl
POP pr POP pr
PUSH pr PUSH pr
RAL RLA
RAR RRA
RC RET C
RET RET
RLC RLCA
RM RET M
RNC RET NC
RNZ RET NZ
RP RET P
RPE RET PE
RPO RET PO
RRC RRCA
RST n RST n
RZ RET Z
SBB reg or M SBC A,reg or (HLl
SBI data SBC A,data
SHLD addr LD (addrl,HL
SPHL LD SP.HL
STA addr LD laddrl,A
STAX B or 0 LO (BC) or (DE},A
STC SCF
SUB reg or M SUB reg or (HLl
SUI data SUB data
XCHG EX OE,HL
XRA reg or M XOR reg or (HLl
XRI data XOR data
XTHL EX (SPl.HL
3-166
Table 3-8 Correspondence between Z80 and 8080A Mnemonic"
zeo Mnemonic eOeOA Mnemonic
ACC A,data ACI data
ADC A,(HU ADC M
ADC A,reg ADC reg
ADC + displ
-
ADC HL,rp -
ADD A,data ADI data
ADD A,(HLl ADD M
ADD A,reg ADD reg
ADD A,(xv + disp) -
ADD HL,rp DAD rp
ADD IX,PP
-
ADD IY,rr -
AND data ANI data
AND (HU ANA M
AND reg ANA reg
AND (xv + disp) -
BIT b,lHU
-
BIT b,reg -
BIT b,lxV + displ
-
CALL addr CALL addr
CALL C,addr CC addr
CALL M,addr CM addr
CALL NC,addr CNC addr
CALL NZ,addr CNZ addr
CALL P,addr CP addr
CALL PE,addr CPE addr
CALL PO,addr CPO addr
CALL Z,addr CZ addr
CCF CMC
CP data
Cpt data
CP (HLI CMP M
CP reg CMP reg
CP (XV + displ
-
CPO -
CPDR
-
CPI -
CPIR

CPL CMA
DAA DAA
DEC IHU DCR M
DEC reg DCR reg
DEC rp DCX rp
DEC XV -
DEC (XV + displ
-
01 01
DJNZ disp -
EI EI
EX AF,AF'
-
EX DE,HL XCHG
EX (SPI.HL XTHL
EX (SPl.xv
-
EXX
-
HALT HLT
1M m -
IN A,(port) IN port
IN reg,lCI -
INC INR M
INC reg INR reg
Z80 Mnemonic B080A Mnemonic
INC rp INX rp
INC XV

INC (XV + disp) -
IND -
INOR
-
INI -
INIR -
JP addr JMP addr
JP C,addr JC addr
JP (HU PCHL
JP M,addr JM addr
JP NC,addr JNC addr
JP NZ,addr JNZ addr
JP P,addr JP addr
JP PE,addr JPE addr
JP PO,addr JPO addr
JP Z,addr JZ addr
JP xv
-
JR C,disp -
JR disp -
JR NC,disp -
JR NZ,disp -
JR Z,disp -
LD A,(addr) LDA addr
LD A,(Be) or (DE) LDAX B or D
LD A,I -
LD A,R -
LD (addd,A STA addr
LD (addr),BC or DE -
LD SHLD addr
LD (addr),SP -
LD (addr),xv -
LD (Be) or IDEI.A STAX B or D
LD BC or DE,laddrl -
LD HUaddr) LHLD addr
LD (HU,data MVI M,data
LD IHU,reg MOV M,reg
LD I.A -
LD R,A -
LD reg, data MVI reg,data
LD reg,(HU MOV '8g,M
LO reg, reg MOV rag,reg
LO + displ -
LO rp,data16 LXI rp,data16
LO SP.laddr) -
LO SP,HL SPHL
LO SP,xv -
LD xV,data 16 -
LO
-
LO (XV + disp),data -
LO (xV + disp),reg -
LOD -
LOOR -
LDI -
LOIR -
NEG -
NOP NOP
OR data ORI data
- ,nd,cates that there IS no correspondong ,nstructlon.
3-167
Table 3-8. Correspondence between Z80 and 8080A Mnemonics (Continued)
Z80 Mnemonic 8080A Mnemonic
OR (HLI ORA M
OR reg ORA reg
OR (XV + disp) -
OTDR -
OTIR -
OUT (C),reg
~
OUT (port).A OUT port
aUTO -
OUTI -
pop pr pop pr
POP XV -
PUSH pr PUSH pr
PUSH XV -
RES b,(HL) -
RES b,reg -
RES b,(xv + disp} -
RET RET
RET C RC
RET M RM
R ~ T NC RNC
RET NZ RNZ
RET P RP
RET PE APE
RET PO RPO
AET Z RZ
RET! -
RETN
-
RL (HL) -
RL reg -
AL (XV + displ -
RLA RAL
RLC (HL) -
RLC reg -
RLC (XV + disp)
~
RLCA RLC
ALD -
Z80 Mnemonic 8080A Mnemonic
RR (HL) -
RR reg
-
RR (XV + disp) -
RRA RAR
RRC (HL) -
RRC reg
-
RRC (XV + disp) -
RRCA RRC
RRD -
RST n RST n
SBC A,data SBI data
SBC A,IHL) SBB M
SBC A,reg SBB reg
SBC A,(xV + displ -
SBC HL,rp -
SCF STC
SET b,IHL) -
SET b,reg
-
SET b,lxv + disp) -
SLA (HL) -
SLA reg -
SLA (XV + disp) -
SRA (HL) -
SRA reg -
SRA (XV + disp) -
SRL (HL) -
SRL reg
-
SRL (XV + disp) -
SUB data SUI data
SUB (HL) SUB M
SUB reg SUB reg
SUB (XV + disp) -
XOR data XRI data
XOR (HL) XRA M
XOR reg XRA reg
XOR (XV + disp) -
- indicates that there is no corresponding instruction
3-168

In this PDF: Chapter 3 page 1-42

. H. some important differences in the functions of Registers B. the shortest and fastest data transfers between the CPU and 1/0 devices are performed through the Accumulator. For example. It ohen takes fewer bytes of object code and less instruction cycles to perform operations with it. C. more Memory Reference instructions move data between the Accumu later and memory than between any other register and memory All 8-bit arithmetic and Boolean instructions take one of the operands from the Accumulator and return the result to the Accumulator. E. The Z80 programmer should try to address data memory via Registers Hand L whenever possible. and L registers are all secondary registers. you will normally use these two registers to hold the 16-bit memory address of data being accessed.Carry . always reserve Registers Hand L to hold a data memoryaddress. D. E. An instruction must therefore load the Accumulator before the laO can perform any abit arithmetic or Boolean operations.r S IZ I • IAct A C E L • I r r Flags Accumulator } Secondary Data Counters IPloi N I c B Secondary { Accumulators 0 H S'I Primary Data Counter IP!c)'1 N'I C' Alternate Flags Alternate Accumulator Alternate Secondary } Data Counters Alternate Primary Data Counter Stack Pointer Program Counter z'l lAd A' C' E' L' Alternate { Secondary Accumulators B' 0' H' SP PC IX IV I R Index Register Index Register Interrupt Vector Register Refresh Register The Accumulator is the primary source and destination for one-operand and twooperand instructions. There are. H. and L Registers Hand L are the primary Data Pointer for the laO. C. D. The B. Data may be transferred between any registers and the memory location addressed by Hand L Since HL is the primary Data Pointer. however. Data stored in any of these six registers may be accessed with equal ease: such data can be moved to any other register or can be used as the second operand In two-operand instructions. 3-2 . Within your program logic. In addition.CPU REGISTERS AND STATUS FLAGS The CPU registers and status flags for the laO may be illustrated as follows: Sign Zero Auxiliary Carry Parity 10verfiow ~ Subtract ro. That is to say.

The Carry status flag holds carries out of the most significant bit in any arithmetic operation. The alternate registers can be reserved for use when a fast interrupt response is required. D and E. But these instructions move data between memory and the Accumulator only.) There are a limited number of instructions that treat Registers Band C. and Boolean operations. Just two single-byte Exchange instructions select and deselect all alternate registers. as 16-bit Data Pointers. C. There are a number of instructions that handle 16 bits of data at a time. The Parity/Overflow flag is a multiple use flag. it is a parity flag. A'. B'. depending on the operation being performed. one instruction exchanges AF and the alternate AF' as a register pair.R instruction is executed.I or LD A. The Zero flag is set to 1 when any arithmetic or Boolean operation generates a zero result. and L' provide a duplicate set of general purpose registers. and E provide secondary data storage. Registers IX and IV are index registers. all subsequent register operations are performed on the active set until the next exchange selects the inactive set. or D and E. and E as temporary storage for data or addresses. For arithmetic operations. rotate. which is also the destination for the result. it is an overflow flag. Or. This flag is set to 1 for all Subtract instructions and reset to 0 for all Add instructions. treated as a 16-bit unit. DE. During block transfer and search operations. C. E/• H'. they may be used in any desired way by the programmer. They provide a limited indexing capability of the type described in An Introduction to Microcomputers: Volume 1 for short instructions. frequently. D. 0'. and HL' Once selected. with 1 = even parity and 0 = odd parity. For input. (The first operand is stored in the Accumulator. the second operand for two-operand instructions is stored in one of these fou r registers. These instructions refer to pairs of CPU registers as follows: F B D H F' B' D' H' ~ and and and and and and and and A C E L A' C' E' L' ~ Highorder byte Loworder byte The combination of the Accumulator and flags. and HL with the alternate BC'. In your program logic you should normally use Registers B. and one instruction exchanges BC. D.Registers B. or Hand L as 16-bit data units. The Subtract flag is designed for internal use during decimal adjust operations. The Carry flag is also included in Shift instructions: it is reset by Boolean instructions. 3-3 . C'. is used only for Stack operations and alternate register switches Arithmetic operations access Band C. The alternate registers F'. The Zero status is set to 0 when such an operation generates a nonzero result. DE'. it remains set until the byte counter decrements to zero: then it is reset to zero It is also set to the current state of the interrupt enable flip-flop (IFF2) when a LD A.

For example. depending on how it was loaded at the last LD RA instruction. You should use the Stack for accessing subroutines and processing interrupts. The Auxiliary Carry status flag holds any carry from bit 3 to 4 resulting from the execution of an arithmetic instruction. The Interrupt Vector register is used to store the page address of an interrupt response routine: the location on the page is provided by the interrupting device. The Refresh register contains a memory refresh counter in the low-order seven bits. The size of the Stack is limited only by the amount of addressable memory present In reality you will rarely use more than 256 bytes of memory for your Stack. lao MEMORY ADDRESSING MODES The · • • · · • • • • zeo provides extensive addressing modes. if the Zero flag is set. that causes the Accumulator to acquire a nonzero value: the value of the Zero flag remains unchanged. this is the standard use of an Auxiliary Carry status flag as described in An Introduction to Microcomputers: Volume 1. These Include: Implied Implied Block Transfer with Auto-Increment/Decrement Implied Stack Indexed Direct Program Relative Base Page Register Indirect Immediate 3-4 . Chapter 3. All of the above status flags keep their current value until an instruction that modifies them is executed. and a load immediate to the Accumulator is executed. This scheme allows the address of the interrupt response routine to be changed while still providing a very fast response time for the interrupting device. A Push decrements the Stack Pointer contents. The high-order bit of the Refresh register will remain set or reset.The Sign status flag acquires the value of the most significant bit of the result following the execution of any arithmetic or Boolean instruction. The 16-bit Stack Pointer allows you to Implement a Stack anywhere in addressable memory. a Pop increments the Stack Pointer contents The Interrupt Vector register and the Refresh register are special-purpose registers not normally used by the programmer. Merely changing the value of the Accumulator will not necessarily change the value of the status flags. The purpos'e of this status flag is to simplify Binary-Coded-Decimal (BCD) operations. The zao Stack is started at its highest address. This is not very efficient within the limitations of the zao instruction set. This counter is incremented automatically after each instruction fetch and provides the next refresh address for dynamic memories. Do not use the Stack to pass parameters to subroutines.

.-. E..Implied In implied memory addressing. the instruction LD C. C.(HU loads the C register with the contents of the memory location currently pointed to by HL.. H. For example. or L.. the Hand L registers hold the address of the memory location being acces. (HU EE:EE:EEEEl ~ 76543210 [ .L o a d Implied via HL C Register 1:1 3-5 . mmmm + 3 LD C..E H. B. Data may be moved between the identified memory location and anyone of the seven CPU registers A.l SP pp mmmm r ~mmm+~ yy qq Program Memory 4E 1 mmmm m mmm+ 1 q PC IX IV I R I I 1 .. mmrnm + 2 1..ed. This is illustrated as follows: s F Z AcP/O N C Data Memory c:::I:IJ:I:] A S. D..C D..

.. These instructions move data between the Accumu lator and the memory location addressed by Registers Band C or Registers D and E. 6 ~ --LD (BCl.. " " ..A S:-4 3 2 1 0' J T Store Implioed from A via BC 3-6 . _.A limited number of instructions use Registers Band C or 0 and E as the Data Pointer.L -~ ~mmm+ 1 ppqQ j SP PC IX IY I mmmm V1 Program MemOry I 02 m mmm R I m mmm+1 mmmm+2 1-----4 mmmm + 3 r.. . ..A ~_ _.. ... -.E H. The instruction LD (BCLA stores the contents of A into the memory location currently addressed by Register Pair Be... This is illustrated as follows: SZACPONC F A CIIIIIl vv pp qql Data Memorv B.".C O.

. auto-decrementing HL and DE instead of auto-incrementing.. a byte of data is moved from the memory location addressed by HL to the memory location addressed by DE. Memory is addressed by HL.---e:::c~ ...+o......O-+-:.. 4111... with the programmer supplying the loopback.--':"'" Spt.... D.. Data transfer continues until BC reaches zero. .... then HL and DE are incremented and Be is decremented..1 mmmrri + 3 ED mmmm LOIR . and a complementary set of Block Search instructions that compare the memory byte addressed by HL with the contents of the A register. .-.. The I/O port nu mber is taken as the contents of the C register.... Increment.--4---. and Repeat instruction LDIR is illustrated as follows: Set if BC... .. .... .. setting a flag if a match is found..~ IV .1." .-..... 3-7 ..l..C I-__... at which point the Instruction is terminated..-. ..L ~_.::!y... } load...-..-+.... In this form of addressing.. The Load..J. with the sing Ie B reg ister used as the byte counter.. Increment. mmmm + 1 mmmm+2 1 . .eS8t otherwise S Z AcP'ON C Fo:::EI:E:I2IJ Ar-_ _..r=---~~--~ PC I L=====~ IX ... and Repeat instruction A similar group of Input/Output instructions is provided.E 1-__~IT..__.....~ o.-_ _...--~q~q--....-----==80._ mmmm R ........t~t---..uu.. . ... Variations include allowing other instructions to follow each data transfer......£!pp~-. ~':-l B. allowing a block of data to be input or output between memory and an I/O device... ........ss~--..Implied Block Transfer With Auto-Increment/Decrement Block Transfer and Search instructions operate on a block of data whose size is set by the programmer as the contents of the BC register pair.._--.....

o. 76543210 ~~. Pu.~ .2 pp I ssss .Implied Stack Since the Stack is part of ReadIWrite memory.gl.truction.ddr••••d Stack Polnt. The instruction PUSH is illustrated as follows: 5 F A DE ZAcP/ON C Data r::IJ:IJ:IJ pp qq Memorv B.h and Pop in..t.e.- _ PUSH instruction . i..E H.r location.r pair and the .. PUSH DE I mmmm mmmm+ 1 oImmmm + 2 -tmmmm + 3 R I . current topof-stack.o. The Z80 Stack address is decremented with each Push and incremented with each Pop..Register Pair DE 3-8 .I- ~X. we must consider Stack instructions as Memory Reference instructions.C D.tw••n a r.. move two byt•• of data b.l SP JA ssss-2 ssss mmmm PC IX IV /'/' ~-~ ~ :mmm+l ~ -• C qq I ssss .1 ssss - Program Memory 05 .

.L yy • --- : qq pp ssss ssss + 1 ssss + 2 SP PC IX IV I ssss mmmm -" +':v mmmm Program Memory mmmm mmmm+ 1 mmmm+2 .The laO allo hal instructions that exchange the two top-of-stack bytes with a 16-blt register ...C D.HL or one of the two index registers.HL Z Ac Pia N C Data DIIIIJ M" xx Memory B.t mmmm + 3 R I I E3 3-9 ...E H..... The instruction EX is illustrated as follows: S F A (SPl.

ln the instruction ADD A.E H. (IX +40H) the memory address is the sum of the contents of the IX register and 40 16.rs. This may be illustrated as follows: S Z Ac P/O N C F~ A B.nt valu.d to the ind.rand includ•• a di.x op.m.t. ppqQj 40 mmmm ppqq I .plac. I • yy J • • ppqq . ADD - .:L mmmm mmmm+ 1 mmmm+2 mmm m+3 3-10 . The difference between implied addressing using HL and indexed addressing using IX and IY is that the ind. All memory reference operations for which (HU can be specified can alternatively be specified as an indexed operation.x r. They may be used interchangeably. call.gl.OX + 40) . two 16-bit Ind.x addr•••.~mmm+~ ~pqq+40~ JI' - Program Memory DO 86 40 R I A. that i.d IX and IV.C xx -~ I XX+YY Data Memory D. zao ha.l SP PC IX IV -- . add.Indexed Th.

IX. This may be illustrated as follows: 16 S Z FCIIIID A Ac P/O N C Data Memory S. or IV with any 16-bit memory value."- mmmm + 3 Program Memory mmmm mmmm+ t 1 mmmm+2 1-----1 mmmm + 3 2A I R I I '-. load BC. HL. and jump or call subroutines direct at any memory location.(NETX) loads the A register with the contents of the memory location addressed by the label NETX. DE. 1 0 1 1 1 0 1 . The 16-bit direct address is stored in the last two bytes of the instruction.C D. YV YV xx OIFF 0200 SP PC IX IV mmmm '" . ) FF 01 LD HL.l1 FFH) loads the L register with the contents of memory location 01 FF 16 and the H register with the contents of memory location 0200 . The i nstructi on LD A.L 6 xx . both unconditional and conditional. SP.High byte 0 0 0 0 0 0 0 The direct Jump instructions provide jumps and jumps-to-subroutines. as shown above for Load Direct. The instruction LD HL. base page.. 1 0 1 1 Load HL Direct instruction Direct address .Direct Direct addressing can be used to load the Accumulator with any 8·bit value from memory. and register indirect. zao 3-11 .low byte Direct address .!IFFH) 76543210 0 1 0 1 . These are all 3-byte instructions. in low-byte high-byte order (this is the reverse of the standard high-low schemel. In general. Branch instrucThere are three additional addressing modes used by tions: program relative.E H. with the direct address stored in the second and third bytes of the instruction. they are shorter and/or faster than direct jumps but may have more limited addressing capabilities.

.... e. loop control. There .C D.. with 1'fte signed displacement value stored in the second byte of the instruction.slng In the renge -128. Given the instruction JR SRCH assume that SRCH is a label alltdressing a location 5A 16 bytes up in memory from the JR op-code byte. uaaonditlonel end conditioneI re.on may be illustrated as follows: 5 Z AcP/O N C FCIIIIIJ A Data Memory B. well ••• Decrement end Jump " Not Zero in.E H. from the first byte of ~Program Relative instruction.. These instructions are all 2-byte instructions. +129 byte.L SP PC IX IV I R mmmm I I - 'mmmm:f) """SA Program Memory 18 ~.. mmmm mmmm+l mmmm+2 mmmm+3 ~~+-+-+-+-+-+-I ~ ....etive eddre. Jump Relative iAStruction Displacement "'--"'--"'--"""-"'-- . The operati.Program Relative Jump Re.truction (DJNZ) thet fecllltete.etlve instructions pro'ltde pregrem re. SA JR SRCH --..etive jump. o 3-12 .

_ R e s t 8 r t instruction code 76543210 RST OOH ~---Address 3-13 . fl ssss ..1 ssss B..c c T .. the instruction RST is illustrated as follows: OOH s F A Z AcP/O N C Data CIII:ID ssss . ~ mmmm mmmm+ 1 mmmm+2 mmmm+3 ~ ~ . ~ ~mmm+V000 Memory mm+l mm ssss ..E H.Base Page The Z80 has a modified base page addressing mode for the Restart instruction.2 ssss ....C D.. This is a special Call instruction that allows a single-byte instruction to jump to one of eight subroutines located at specific points in lower core. the high-order byte of the Program Counter is set to zero... t:.....L SP PC ----.2 mmmm IX IV I Program Memory C7 R I I ... For example. The effective address is calculated from a 3-bit code stored in the instruction... as follows: Lower Core Address 3-Bit Code OOH 08H 10H 18H 20H 28H 30H 38H 000 001 010 all 100 101 110 111 The decoded address value is loaded into the low-order byte of the Program Counter.-.

JP (HLl ~JUmpViaHL 3-14 .L pp mmmm qq SP PC IX IV I D Program Memory I R I E9 mmmm 1-_ _. This is a form of indirect addressing.E H.... .. In register indirect addressing. mmmm + 3 r:. However. while most microcomputers have implied addressing.. 7654 --:x.----a. and the instruction specifies which of the registers contains the effective address Note that for a Load..C D.....~ 3 2 1 0 :0-. a register contains the effective address.. the l80 has Jump instructions that allow a jump to the memory location whose address is contained in the specified register.. . and the instruction specifies the address of the memory location containing the effective address. The instruction JP (HL) directs that a jump is to be taken to the memory location whose address is contained in HL This may be illustrated as follows: S Z AC P/O N C FCCIIIIJ A Data Memory B..-. and is described separately because.. . very few have register indirect jumps...-----. mmmm+2 1 . a memory location contains the effective address.Register Indirect In standard indirect addressing. for instance. this is just another way of describing implied addressing. mmmm + .

3-. M ROO'• • "'.. or 4-byte instruction in which the last one or two bytes hold fixed data that is loaded into a register or memory location.. mmmm SP PC IX IV I ~mmm+9 Program Memory 01 I I R BC '- 00 mmmm mmmm + 1 mmmm+2 mmmm+3 LD BC. 08CH 76543210 ~ '4T 1 0 76543210 -~-----Reglster 1 0 """ Om"""'.low-order byte o I Immediate data .E H. The Z80 provides Immediate instructions to: load 8-bit data into any of the 8-bit registers.l .OBCH loads the immediate data value BC 16 into Register Pair BC.C D.. An Immediate instruction is a 2-. perform arithmetic and logical operations using the Accumulator and 8-bit immediate data..high-order byte 3-15 . The instruction LD BC. load 16-bit data into any of the register pairs or 16·bit registers.Immediate Some texts identify Immediate instructions as Memory Reference instructions. store 8-bit data into any memory location using implied or indexed addressing. Pair BC 0 0 1 0 1 0 1 0 0 0 o I Immediate data . This may be illustrated as follows: S Z AcP/O N C FCD:IIIJ A Data Memory B.

addr cond.(addr) data (HL).(HL) A.addr reg.Table 3-1. Frequently Used Instructions of the zeo Instruction Code ADC ADD AND CALL CALL CP DEC DJNZ IN INC JR JR LD LD LD LD LD LD OUT POP PUSH RET RET RLA RRA SLA SRL SUB A Meaning Add with Carry to Accumulator Add Logical AND Call Subroutine Call Conditional Compare Decrement Decrement and Jump If Not Zero Input Increment Jump Relative Jump Relative Conditional Load Register Load Accumulator Direct Load Immediate Store Register Store Accumulator Direct Move Register-ta-Register Output Pop from Stack Push to Stack Return from Subroutine Return Conditional Rotate Accumulator Left Through Carry Rotate Accumulator Right Through Carry Shift Left Arithmetic Shift Right Logical Subtract addr cond.A dst.src cond 3-16 .reg (addrl.

Table 3-2.CPDR CPI.data {xy+displ. (l\epeat) Reset !i'it Retu rn from Interru pt Rotate Left ThrouQh Carry Rotate Left Circular Rotate Accumulator Left Circular Rotate Right Throullh Carry Rotate RiQt1t Circll'tar Rotate Accumu"tor Right Circular Set Bit Shift Right Arithmetic Logica~ Exclursi-ve OR 01 EI EX HALT IND.xy (HL). OTIR RES RETI RL RLC RLCA RR RRC RRCA SET SRA XOR addr cond.(addr) xy. lRepeat) Output. CPIR CPL DAA Meaning Test Bit Compare. [)ecrement. Decrement. (Repeat) Compare. (BC) or (DE) HL. (Repeat) Jump Jump Conditional Load Accumulator Secondary Load Hl Direct Load Register Indexed Load ~egister Pair Direct Load Index Register Direct Store Accu mu lator Secondary Store Hl Direct Store Regfster Indexed Store R-egis1'er Pair Direct Store Index Register Direct Store Immediate to Memory Store Immediate to Memory Indexed Load.A (addr). Decrement.rp (addd. LDIR NEG NOP OR OUTD.addr A. (Repeat) Input. Increment. (Repeat) Complement A<:cumulator Decill11itl Adj ust Accu mu lator Disa~ IMerrupts Enable Interrupts Exchange Halt Input. Increment. INIR JP JP LD LD LD LD LD LD LD LD LD LD LD LD LDD. (xy+d isp) rp. Decrement.data 3-17 . Occasionally Used ~nstrlJ'Ctions of the laO Instruction Code BIT CPD. LDDR LD!.(addd reg.reg (addr).INDR IN!.HL (xy+disp). Increment. (Repeat) Load. IncremtiHlt.(addr) (BC) or (DE).OTDR OUTI. (Retlleat) Negate (Twos Complement) Accumulator No Operation Logical OR Output.

BC'. Conditions are: NZ .A SP.Parity Even (P = 1) P .Non-carry (C = 0) C .Negative Sign (S = 1) An 8-bit binary data unit A 16-bit binary data unit An 8-bit signed binary address displacement The high-order 8 bits of a 16-bit quantity xx Interrupt Vector register (8 bits) The Index registers (16 bits each) A 16-bit instruction memory address The low-order 8 bits of a 16-bit quantity xx Least Sig nificant Bit (B it 0) Most Significant Bit (Bit 7) Program Counter An 8-bit I/O port address data data16 disp xx(HI) I IX IY label xx(LO) LSB MSB PC port 3-18 .F. The alternate register pairs A 16-bit memory address Bit b of 8-bit register or memory location x Condition for program branching.HL SP.Parity Odd (P = 0) PE .Non-Zero (Z = 0) Z -Zero(Z=l) NC .Positive Sign (S = 0) M .E.Table 3-3 Seldom Used Instructions of the Z80 Instruction Code ADC CCF EXX 1M RETN RLD RRD RST SSC SCF LD LD LD LD LD LD HLrp Meaning Add Register Pair with Carry to HL Complement Carry Flag Exchange Register Pairs and Alternatives Set Interrupt Mode Return from Non-Maskable Interrupt Rotate Accumulator and Memory Left Decimal Rotate Accumulator and Memory Right Decimal Restart Subtract with Carry (Borrow) Set Carry Flag Load Accumulator from Interrupt Vector Register Load Accumulator from Refresh Register Store Accu mu lator to I nterru pt Vector Register Store Ac{'u mu lator to Refresh Register Move HL to Stack Pointer Move Index Register to Stack Pointer n AI AR I.A R.HL' addr x(b) cond The 8-bit registers.DE'.H.L AF'.Carry (C = 1) PO . A is the Accumulator and F is the Flag Word.D.C.xy ABBREVIATIONS These are the abbreviations used in this chapter: A.B.

pr Any of the following register pairs: BC DE HL AF The Refresh register (8 bits) Any of the following registers: R reg A B C D E H L rp Any of the following register pairs: BC DE HL SP Stack Pointer (16 bits) Either one of the Index registers (IX or lY) bbb eec Bit number 000 (LSB) to 111 (MSB) Condition code 000 001 010 011 100 101 110 111 = non-zero SP xy Object Code = = = = = zero no carry carry parity odd parity even = positive sign = negative sign ddd Destination register - same coding as rrr ppqq A 16-bit memory address rrr Register 111 000 001 010 011 100 101 = A = B = C D = E = H = L = sss x xx Source register Index reg ister Register pair same coding as rrr 0 = IX 1 =IY 00 = BC 01 = DE 10 = HL 11 = SP (rp) or AF (pr) Restart code (000 to 111) An 8-bit binary data unit A 16-bit binary data unit xxx yy yyyy 3-19 .

flag shows interrupt enabled/disabled status o - [[ ]] Memory addressing: 1) the contents of the memory location whose address is contained in the designated register.Carry status l .Parity/Overflow status AC .flag is unknown after operation P .Subtract status The following symbols are used in the status columns: X . A V 41- Logical AND Logical OR Logical Exclusive-OR Data is transferred in the direction' of the arrow ---+ Data is exchanged between the two locations designated on either side of the arrows.flag is affected by operation (blank) .Auxiliary Carry status N . whereas: [HL] +- [HL] + 1 indicates that the contents of the HL register itself are incremented.Sign status P/O .flag shows overflow status I . The contents of a register or memory location.lero status S . For example: ([HLll +- [] [[HLll + 1 indicates that the contents of the memory location addressed by the contents of HL are incremented.Statuses The l80 has the following status flags: C . 3-20 .flag is set by operation flag is reset by operation U .flag is not affected by operation 1 .flag shows paritY status o . 2) an I/O port whose address is contained in the designated register.

..g•• 3F).e.hown as eight binary digits (e..... The OPERAND column shows the operands.. For arithmetic.. 0 for nonzero) . examples of the format entry LD are: LD LD rp.... INSTRUCTION EXECUTION TIMES Table 3-4 lists the instruction execution times in clock periods.....t 7) . 0 for odd parity......75 microsecond execution time.001).... The variable part (Immediate data......... register name.INSTRUCTION MNEMONICS Table 3-4 summarizes the leO instruction set.... For example. For other instruction bytes with variation. are represented as two hexadecimal digits (e.. Real time can be obtained by dividing the given number of clock periods by the clock frequency..Zero status (1 for zero. For instruction bytes with variations in one of the two digits... The first time is for "condition not met...These bits are not used .(DAT2) IX.(addr) BC. 1 for ellen.g... LD).g.hown in lower case. if any.. 5/11)...--t--+--. Table 3-5 lists the object codes in numerical order. aftar subtract operation. When two possible execution times are shown (j. For instance... 1 for overflow) 10. are shown in Table 3-4 for each instruction variation.Parity/Overflow (for logical operations. For closely related operands. a 4 MHz clock will result in a 1... for an instruction that requires 7 clock periods.. For instruction bytes without variations....- Auxiliary Carry status (carry out of bit 3) ... the object code is .. The fixed part of an assembly language instruction is shown In UPPER CASE. I/O device number. used with the instruction mnemonic. OUT. object code..(addr) xy. The MNEMONIC column shows the instruction mnemonic UN...Carry status (carry out of bi.Sign status (vatue of bit 7) 3-21 ." whereas the second is for "condition met. 0 otharwise) " " .. it indicates that the number of clock periods depends on condition flags." STATUS The six status flags are stored in the Flag register (F) as follows: --+-.... 0118. label or address) is .... each type is listed separately without repeating the mnemonic.Subtract stetus (. the object code is shown as one 4-bit binary digit and one hexadecimal digit le.(MEM) INSTRUCTION OBJECT CODES The object code a"d instruction length in byte.• 11 x 1 D) in Table 3-5.

A 0 identifies a status that is always cleared. STATUS CHANGES WITH INSTRUCTION EXECUTION 3-22 . A 1 identifies a status that is always set. A question mark (?) means the status is not known. the effect of instruction execution on status is illustrated as follows: s Z AC Pia N C 171 ~ !ll x l o l x l l j~ ~ ~ I Modified to reflect results of execution Unconditionally reset to 0 Unconditionally set to 1 Unchanged Unknown An X identifies a status that is set or reset. A blank means the status does not change.In the individual instruction descriptions.

Address Bus: AO-A 7: port AS-A15 [AI [regl.[[ C]] [B)-[BJ .1 [ HLI .[(Cll [BJ-[Bl.[[ Cll Input to register from 1/0 port addressed by the contents of C.[HLJ .[HLI + 1 Transfer a block of data from 1/0 port addressed by contents of C to memory location addressed by contents of HL. going from high addresses to low." IN A." Repeat until [ BJ = 0: [[HL1J-[[Cll [B)-[B].ICl ED 01dddOOO 2 11 X X P X 0 INIR ED B2 2 20/15" 1 ? ] ] 1 (." If second byte is 70 only the flags will be affected.1 Transfer a block of data from 1/0 port addressed by contents of C to memory location addressed by contents of HL." [[ HLI. Contents of B serve. 0 INDR ED BA 2 20/15" 1 7 ] ? 1 INI ED A2 2 15 X ? ] ? 1 .[ HLI + 1 Transfer a byte of data from 1/0 port addressed bv contents of C to memory location addressed by contents of HL Decrement byte count and increment destination address.as a count of bytes remaining to be transferred.J I (.•• Address Bus: AO-A7: [e) AS-A1S: [B) Taole 3-4. Status C Z Type Mnemonic S PIO AC N [AJ.1 [ HLJ .(portl DB yy 2 IN reg. Contents of B serve as a count of bytes remaining to be transferred. A Summary of the Operend Object Code Bytes Clock Cycles 10 zao Instruction Set Operation Performed. 16 Repeat until [ BJ = 0: [[ HLI).1 [ HLI .[pertJ Input to Accumulator from directly addressed 1/0 port. going from low addresses to high.J "" ::.

15 C Z X S ? PIO A C ] N I [[ HU] .[BI.I Transfer a byte of data from I/O port addressed by contents of C to memory location addressed by contents of HL.I HU . Transfer a block of data from memory location addressed by contents of Hl to I/O port addressed by contents of C. going from high memory to low.[HLI .[[ CII (BJ . Operation Performed Typa. Address Bus: AO-A 7: port A8-A1S: [Al 11 C]).[A] Output from Accumulator to directly addressed I/O port..I t HL] .•• INO EDAA ? OUT (portl.reg EO 01555001 ED B3 2 2 12 20/15·· 1 ] ? ] 1 ~ 'ij . A Summary of the Operand Object Code zao Instruction Set (Continued) Statu.[reg] Output from register to I/O port addressed by the contents of C.··Address Bus: AO-A7: IC] A8-A1S: IB) Table 3-4.·· Repeat until [BI = 0: [[C])-[[HL]) [BI-IBJ -.5 • ::> g OTOR ED BB 2 ~ e 0 20/15·· I 7 7 ? 1 . Decrement both byte count and destination address.[BI . Contents of B serve as a count of bytes remaining to be transferred. Mnemonic Byte.A 03 yy 2 II OUT OTIR Co) I (Cl. Contents of B serve as a count of bytes remaining to be transferred ." Repeat until ( BI = 0: ([C])-([HL]) [8]." [port] . [ HLI . going from low memory to high.1 (HU-[HU+ 1 Transfer a block of date from memory location addressed by contents of HL to I/O port addressed by contents of C. 2 Clock Cycle.

Decrement both byte count and source address.(addd HL.I addr + 1l.t LD 4 4 A.IBC) A.[Hl.·· [[C)]-[(HL)] [B]. [ addr + 1] .laddd xy. [ HI . [addrl ..HL laddrl.(addd rp. [ addr + 1] . [ Ll .[[ BC]l or [ Al . c 0 :::I • OUTD ED AB 2 15 H X 7 7 7 1 g w C1l N • LD LD A..[[HLlJ [Bl. II: LD 4 4 • Ii >LD LD LD laddd.[AI Store Accumulator contents in directly addressed memory location.[ addrl load Hl from directly addressed memory.[ addrl Load register pair or Index register from directly addressed memory.§ .[addrl load Accumulator from directly addressed memory location... [ rpllOI) .rp (addd. A Summary of the Clock Cycles 15 zao Instruction Set Status (Continued) Mnemonic Operand Object Code Bytes Operation Performed C Z X S PIO 7 AC 7 N 1 [[ClI .1 [HLJ .[ xy(lOll Store contents of register pair or Index register to directly addressed memory. [ rplHIlJ . [addrl.[Bl . >- .( L] Store contents of Hl to directly addressed memory location.[ xy(HIIl.[ rplLO)] or [ addr + 11 . • u c • . [addr] .a. [ Al . (C) AS-A15: [B) Type Table 3-4. Address Bus: AO-A7.[rp(HIlI.[BI.[ addr + 1L [xy(LOII .IDEI OA 1A 1 1 7 7 ..A !addd.[HLl + 1 Transfer a byte of data from memory location addressed by contents of Hl to 1/0 port addressed by contents of C. Decrement byte count and increment source address.·· OUli ED A3 2 ? 'ii c .(addrl 3A ppqq 2A ppqq ED 01xx1011 ppqq 1hl11012Appqq 3 3 13 16 20 20 [Al.[[ DEli load Accumulator from memory location addressed by the contents of the specified register pair.1 [HLl-[HLl-1 Transfer a byte of data from memory location addressed by contents of HL to 110 port addressed by contents of C.xy 32 ppqq 22 ppqq ED 01xxOOll ppqq 1 hl1101 22 ppqq 3 3 13 16 20 20 ~ II E II . [addrl .[ addrl or [ xy(HIl] ..[ addr + 1l.

[ reg] .A (DEl.I HLl + 1 [ BC] . going from high addresses to low.I[ HLII Load register from memory location addressed by contents of HL.[[ HLl] I DEI .[ DE) . A Summary of the Type Mnemonic Operand Object Code Byte.(HU (Bel. zao Instruction Set (Continued) Status Operation Performed Z C S PIO AC N LD to reg.[ BC] .[[ HLl] I DEl . 0 0 0 Repeat until [ BCl ~ 0: [[ DEll . (J) !'oJ LDIR ED BO 2 20116·· ~ !! I II -0 ~ 0- '" • ~ '" -! ~ ~ LDDR ED B8 2 20/16·· 0 0 0 u 0 iii . Contents of BC serve as a count of bytes to be transferred. Repeat until [ BC] = 0: I[ DEll . going from low addresses to high.1 IHLl-IHLl-1 [ BC] .. Contents of BC serve as a count of bytes to be transferred.I reg] Store register to memory location addressed relative to contents of Index reg ister.I reg) Store register contents to memory location addressed by the contents of HL. ~ LD LD LD reg. [I HLII .I Alar [[ DEll . ~ 11:-0 '0_ ! to LD ~~ ~ Co) I .reg 11x1110101110sss disp 3 3 19 19 I reg] .[BCl .Table 3-4. 'E " ~ > • 6 .[[ xy] + disp] Load register from memory location using base relative addressing. II BClI .1 Transfer a block of data from the memory location addressed by the contents of HL to the memory location addressed by the contents of DE.(xy+disp 11x1110101ddd110 disp xy +displ. [[ xy] + displ .[ A) Store Accumulator to memory location addressed by the contents of the specified register pair.1 Transfer a block of data from the memory location addressed by the contents of HL to the memory location addressed by the contents of DE.I DEI + 1 I HLI .A (HLl. Clock Cycle..~ E .reg 01ddd110 02 12 01110sss 1 1 1 1 7 7 7 7 ..

Stop when a match is found or when the byte count becomes zero.1 Compare contents of Accumulator with those of memory block addressed by contents of HL.[[ HLll (only flags are affected) [ HLI ~ [HLI + 1 [ BCI ~ [BCI ... going from high addresses to low. Repeat until [AI = [[ HLll or [ BCI = 0: [A] .1 Transfer one byte of data from the memory location addressed by Ihe conlents of HL to Ihe memory location addressed by the contents of DE.t:.! I- ..1 Transfer one byte of data from the memory location addressed by the contents of HL to the memory location addressed by the contents of DE.S! CPDR ED B9 2 20/16" X X X X 1 [ BCI ~ [ BCI . I I) Iii • 'C ...1 Compare contents of Accumulator with those of memory block addressed by contents of HL. Repeat until [AI = [[ HLll or [ BCI = 0: I A] . Increment source and destination eddresses and decrement byte count. N . . [[ DEll ~[[HLll [ DE] . going from low addresses to high.1 [HLI~[HLI-1 LDI EO AO 2 LDD ED AS 2 16 X 0 0 'ii ~ c 0 Co) I • :l l.Table 3-4. ~ II c: c: CPIR ED B1 2 20/16" X X X X 1 l! III u '" .[ DEI .[[ HLlI (only flags are affected) [ HLl ~ [ HLI .) ~ . A Summary of the Z80 Instruction Set (Continued) Clock Cycles 16 Status Operation Performed C Z Type Mnemonic Operand Object Code Bytes S PIO AC X 0 N 0 [[ DEll ~ [[ HLlI [ DEl ~ [DEI + 1 [ HLI ~ [HLI + 1 [ BCI ~ [ BCI . Decrement source and destination addresses and byte count. Stop when a match is found or when the byte count becomes zero.1 IBCI ~IBCI.

Table 3-4. A Summary of the lSO Instruction Set (Continued)
Clock Cycles 16 Stetus Operation Performed C

Type

Mnemonic

Operand

Object Code

Byte.

Z
X

S
X

PIO
X

AC
X

N
1

CPI

ED Al

2

· .... ·.".r. -.
t: '0
~

..,t: ~

C •

!!~
u
~

0 t:

CPO

ED A9

2

16

X

X

X

X

1

~

u

o • CIIU1

r Al - II HLIl (onlV flags are affected) [ HLl - [HLl + 1 I BC) - ! Bel - 1 Compare contents of Accumulator with those of memory location addresslid bv contllnts of HL. Increment addrllss and dllcrement byte count. I Al - [[ HLII (onlV flags are affected I [ HL] - [HLl - 1 [ BCI - [ BCI - 1 Compare contents of Accumulator with those of memory location addressed bV contents of HL. Decrement address and byte count
[ Al - [AI + II HLlI or [ Al - ( Al + [( xvI + disp] Add to Accumulator using implied addressing or base relative addressing. [ Al - [AJ + II HLlJ + C or [ AI - ( Al + [[ xvi + disp! + C Add with Carry using implied addressing or base relative addressing. I Al - rAI - II HLlI Or I Al - [ AI - [( xvI + displ Subtract from Accumulator using implied addressing or base relative addressing. I Al - [ Al - [I i'lL]) - C or [ Al ~ [A] • II xvi + disp] - C SUbtract with Carry using implied addressing or base relative addressing. [ Al - I Al A [[ HLlI or ( Al ~ [AI A [[ xvi + displ AND with Accumulator using implied addressing or base relative addressing. r Al - [ Al V II HLlJ or [AI ~ [ Al V rr xyJ + disp! OR with Accumulator using implied addressing or base relative addressing.

ADD

CtJ
I

A.(HLI A.(xV +disp) A.IHLI A,(xV +disp) IHLI + disp)

86 l1xll101 86 disp 8E l1xl11018Edisp 96 l1xl1101 96 disp 9E llxl11D19Edisp A6 l1xl1101 A6 disp 86 l1x11101 B6 disp

1

7
19

X

X

X

0

X

D

3
1

N

.
I

CD

ADC

7
19

X

X

X

0

X

0

i•
IZ:
0

• u t:

3
1

SUB (XV SBC

7
19

X

X

X

0

X

3
1

~

• :!
'0 e: 0

e
>-

A.IHLI A,(xV+disp) IHLI (XV + disp~ (HL) (XV + displ

7
19

X

X

X

0

X

1

3
1

lii

AND

7
19

0

X

X

P

1

0

3
1

UI

u •

OR

7
19

0

X

X

...

I

0

3

Table 3-4. A Summary of the Z80 Instruction Set (Continued)
Clock Cycle. Statu. Operation Performed C 0

Type

Mnemonic

Operend

Object Code

Byte.

Z
:,(

S
X

P/O AC
P 1

N
0 I A] - I AI :!J-II HlJl or ( Al - I Al :!J- [[ xy] + displ Exclusive-OR with Accumulator usin9 implied addressing or base relative addressing. [ Al - [[ HlJl or [ Al - [[ XV) + disp] Compare with Accumulator using implied addressing or base relative addressing. Onlv the flags are affected. II Hlll -II HlJl + 1 or II XV] + disp) - II xy) + disp) + 1 Increment using implied addressing or base relative addressing. [[ Hlll - II HLII - 1 or II xvI + disp] - [( XV) + disp] - 1 Decrement using implied addressing or base relative addressing.

• ... " • c c o • u .. •• Ul';
II:

::i S >-y

. ·.. ..
E

>-'ii .. o

XOR
(XV

IHU + disp) (HU + disp)

AE 1 h1 1101 AE disp BE 11x11101 BE disp 34 11x1110134disp 35 11x1110135disp

1 3 1 3 1 3 1 3

7
19

.=

:I

CP
(XV

7
19 11 23 11 23

X

X

X

0

X

1

INC DEC

(HU + disp) (HU (XV + disp) (xy

X X

X X

0 0

X X

0 1

ff

RlC
(XV

(HU

CB 06 11x11101 CB disp 06

2 4

15 23

X

X

X

P

0

0

~

&y

7

~

oj:] oJ:]

+ disp)

0 II:

..•.•.
Rl (xy (Hll CB 16 11x11101 CBdisp 16 2 4 15 23 X X X P 0 0

II Hlll or [[ XV] + displ Rotate contents of memory location (implied or base relative addressing) left with branch Carry

c " • ::

+ disp)

:c Ul
::i

II Hl)J or [I xvI + disp] Rotate contents of memory location left through Carry.
X

LEJ..
7

I

7

..

E

Ii

>RRC
{XV

(Hll

CB OE 11xl1101 CB disp OE

2

15 23

X

X

P

0

0

lj

+ disp}

4

.. o~
+ dispJ

[( Hl)J or [( XV]

Rotate contents of memory location right with branch Carry.

Table 3-4. A Summary of the laO Instruction Set (Continued)
Type Clock Cyc'e. C Statu. Operation Performed

Mnemonic

Operlnd

Object Code

Bytes

2

S

P/O

AC

N

RR

IHLI Ixy + displ

CB1E lhlll0l CBdisp IE

2 4

15 23

X

X

X

P

0

0

l:f7

~

o

f

[[ HLlI or [[ xv1 + disp] Rolale conlenls of memory location right through Carry

·EJJ
O~O
C

'i;

SLA

W I W

;: 0 g :l
.:l
0

.5

II ::I

(HLI (XV + disp)

CB 26 lhlll0l CB disp 26

2 4

15 23

X

X

X

P

0

0

EJ.. I 7
I
7

-4

[[ HLll or [[ xvI + disp] Shift contenlS of memory location lefl and clear LSB !Arithmelic Shift)

o

... c
II:

SRA

::
I/)

co

(HLI (XV + disp)

CB 2E 1hll101 CB disp 2E

2 4

15 23

X

X

X

P

0

0

.- o

I I

[( HLlI or [( XV] + disp)

:E

;;

>-

~

II

E
(HLl
(xV + disp) CB 3E llxll101 CBdisp 3E 2 4 15 23
X X X
p

Shift contents of memory location right and preserlle MSB (Arithmetic Shift).

SAL

0

0

o

-.J 7

... 0

[( HLlJ or I[ xvI + disp) Shift contents of memory location right and clear MSB (logical Shift)

I -8

A Summary of the Clock Cycles zao Instruction Set Status Z (Continued) Operation Performed Type Mnemonic Operand Object Code Bytes C S PIO AC N [reg] -data load immediate into register.I SPJ + 2 Return from subroutine.[SP] . [ PCILO)) .Table 3-4. W I W JR JP I PC) -label Jump to instruction at address represented by label.2) .data rp. continue in sequence. [[SP] -l)-[PCIHU] II SP) . Return from subroutine if condition is satisfied. I PC] . E :::I 'ij .data (xy+ displ...2 [PCl -label Jump to subroutine starting at address represented by label. 0 . II HLl] . (rp) .datal 6 or [xy] .. otherwise.I[ SPJI [PCIH1lJ .• c: :::I III CAll RET cond.I PCI + 2 + (disp-2) Jump relative to p~esent contents of Program Counter.data16 (HLI.~ ell c: " 10 • RET cond 11 cccOOO 1 5/11 ~ :::I S .data16 xv.[[ SP] + 1] [ SP] . CAll 17 a: .label 11 cccl 00 ppqq C9 3 1 10/17 .data or [[ xy] + disp] . .data load immediate into memory location using implied or base relative addressing • E E a.[ PC(lOI] [ SP] .I HLI or [PC) .. Jump to subroutine if condition is satisfied.datal 6 load 16 bits of immediate data into register pair or Index register. I PC] . . otherwise. continue in sequence.• 01 LD LD lD reg. data label disp (HLI (xy) label OOdddllO VV OOxxOOOl yyyy 1 hlll0l 21 Vyyy 36 yy 1 h11l01 36 disp VY 2 3 1 10 14 10 19 4 2 4 JP C3 ppqq 18Idisp-2) E9 1hlll01 E9 CD ppqq 3 2 1 2 3 10 12 4 8 .I XV] Jump to address contained in Hl or Index register.

label 11 cccO 10 ppqq 3 10 JR C.disp Z.disp NC. A Summary of the laO Instruction Set (Continued) Type Mnemonic Operand Object Code Clock Cycles Status Operation Performed C Z Bytes S X X X X PIO AC N 0 0 1 1 0 0 0 1 ( Al ~ I A] + data Add immediate to Accumulator. If cond.2) Jump relative to contents of Program Counter if Carry flag is set.data Subtract immediate from Accumulator . [ A] .. then (PC] + 2 + (disp -21 Decrement contents of B and Jump relative to contents of Program Counter if result is not O.. then I PCI ~ [PC] + 2 + (disp -2) Jump relative to contents of Program Counter if Zero flag is reset.C Subtract immediate with Carry.(PC) + 2 + Idisp -2) Jump relative to contents of Program Counter if Carry flag is reset. { Al ~ I A] + data + C Add immediate with Carry. then I PCI ~ [PCl + 2 + (disp -2) Jump relative to contents of Program Counter if Zero flag is set. If Z = 1. • I> I> I> ~ SUB SBC AND OR XOR 0 a. X 1 1 1 • :s I> .Table 3-4.data .> I to) .data A. If C = 1. E . [AI . only the flags are affected." 0.data data A.disp disp 38 (disp-21 30 (disp-21 28 (disp-2) 20 (disp-2) 10 {disp-2l 2 2 2 2 2 7/12 7/12 7/12 7/12 8/13 :8 :s c 0 0 c JR JR JR DJNZ c 0 .I A] .data Compare immediate data with Accumulator contents. If Z = O.1 If [B] .data data data data data C6 yy CE yy 06 yy DE yy E6 yy F6 yy EE yy FE yy 2 2 2 2 2 2 2 2 7 7 7 7 7 7 7 7 X X X X 0 0 0 X X X X X X X X 0 0 0 0 P P P X X X . [ A] ~ I A] . then (PC) . IB] ~(BI.. then (PCI ~ (PC) + 2 + (disp .. If C = 0.5 c. [A] ~ I A] -¥Odata Exclusive-OR immediate with Accumulator. then I PCI ~ label Jump to instruction at address represented by label if the condition is true.disp NZ. [ A] ~ I A] A data AND immediate with Accumulator [ A] ~ { A] V data OR immediate with Accumulator. ADD ADC A. :::l a... X X E X X N CP X 0 X JP cond.

A SP. 08 09 . [SP). 0. A Summary of the Type Mnemonic Operand Object Code Clock Cycles 4 zao Instruction Set (Continued) Status Operation Performed Bytes C Z S P/O Ac N [ dstl .Table 3-4... > 'iii LD LD EX EX EXX 6 10 4 4 4 W W . C.~ CBC') [DEl [ DE'l [ HLl [HL') Exchange register pairs and alternate register pairs.A R. E.HL SP. H or L.AF' ED 57 ED SF ED 47 ED 4F F9 11x11101 F9 EB 2 2 2 2 1 9 9 9 9 X X X X I 0 0 0 0 I W I . Register designations src and dst may each be A. B..[HLl Move contents of HL to Stack Pointer.~ [ AF'I Exchange program status and alternate program status. [DEI.... [ AF] .HL AF. CBC) .[ srcl Move contents of source register to destination register. ~ :E .~ [HLl Exchange contents of DE and HL. [AJ-II] Move contents of Interrupt Vector register to Accumulator.xy OE.[xy] Move contents of Index register to Stack Pointer. . lD dstsrc 01 dddsss 1 LD LD LD LD A. [Il-[A) Load Interrupt Vector register from Accumulator.R I. [R)-[A] Load Refresh register from Accumulator. [AI-[R) Move contents of Refresh register to Accumulator. [SP].I A. 0 2 1 1 1 'iii Cl: ..

[ AI .[ reg] .[ Al . a: . A Summary of the laO Instruction Set (Continued) Type Mnemonic Object Code Bytes Clock Cycles Status Operation Performed C X X X X 0 0 0 X Z Operand 5 X X X X X X X X PIO AC X X X X 1 1 1 X N ADD AOC SUB SBC AND OR XOR CP A.C Subtract contents of register and Carry from Accumulator. DE. ~ '0.rp 00nl00l ED Olxxl0l0 ED Olxx0010 1 11 15 15 X } 0 0 1 2 2 X X X X X X 0 0 } } ADD IX.[ HLl . Only the flags are affected. . '0.[ HLl + [rp] + C 16-bit add with Carry register pair contents to contents of HL.[ HLl + [rpl 16-bit add register pair contents to contents of Hl..[ AI . DE.. [ HLl . 10011". [ AI .reg reg A. [ Al .[ reg] Subtract contents of register from Accumulator. 10000rrr 10110rrr 10101". Q.Table 3-4. 0 ADD ADC SBC HL.reg reg reg reg reg 10000rrr 10001 rrr 10010".reg A.[ IV] + [ rrl 1B-bit add register pair contents to contents of Index register IV (n ~ BC.[AI A [ regl AND contents of register with contents of Accumulator. [ HLl . SPI Co) I . IV. .rp HL. SPI [ IV] .• . [A] . IX.[AI + [ reg] + C Add contents of register and Carry to Accumulator. [ AI .pp DO 00xxl00l 2 15 X ? 0 ADD IV.." FD 00nl00l 2 15 X ? 0 . [ HLl .[AI + [reg] Add contents of register to Accumulator...[rp] .rp HL. [A] .[ IX) + [ pp] 16-bit add register pair contents to contents of Index register IX (pp ~ BC.•. [ Al .[reg] Compare contents of register with contents of Accumulator. 0 Co) ~ ! • .C 16-bit subtract with Carry register pair contents from contents of HL.[AI-¥-[ reg] hclusive-OR contents of register with contents of Accumulator. [ IX] . 10111rrr 1 1 1 1 1 1 1 1 4 4 4 4 4 4 4 4 X X X X X X X X 0 0 0 0 P P P 0 0 1 1 0 0 0 1 l AI .[ AI V [ reg] OR contents of register with contents of Accumulator.

. 4 4 zao Instruction Set (Continued) 5t.[ rp) + .( XV) + . [A)-[AJ Complement Accumulator (ones complement).[ reg] + 1 Increment register contents ...[rpl .. C Z PIO AC P X 1 N DAA CPL NEG INC INC DEC reg rp xy reg rp xv 27 2F ED 44 OOm'OO OOxxOO'1 '1xlll0l 23 OUrrr101 00xx10'1 llxl11012B 1 1 2 1 1 X X X a. A Summary of the Clock Cycle.. ( rpJ . 2 1 4 X X 0 X 1 Co) Co) .. [ regl . [rp] ..• II II II 1 8 4 X X X X 0 0 X X .c RLA 17 1 4 X 0 0 LE]4 q7 I • 7 II: 'co II RRCA OF . Oper. or! xVJ .. or [ XV] . o~ . 0 qj :c i II ::: "" . [A)-[AJ +' Negate Accumulator (twos complement).1 Decrement register contents.tion Performed 5 Type Mnemonic Operand Object Code Byte. II Rotate Accumulator left with branch Carry. assuming that Accumulator contents are the sum or difference of BCD operands.[ reg) .. Increment contents of register or Index register. . Decrement contents of register pair or Index register. ! reg] .Table 3-4. DEC 6 10 2 U1 RLCA 07 1 4 X 0 0 &y 7 4 [A] op oj:] [AJ II: . Rotate Accumulator left through Carry 1 4 X 0 0 [AJ Rotate Accumulator right with branch Carry.[xy] .tu. 0 Decimal adjust Accumulator. .. X 6 10 . 0 II 'iiI II: II ..

E}J [ reg! Rotate contents of register right through Carry. A Summary of the Type Mnemonic Operand Object Code Byte. RR reg CB 0001 1m 2 8 X X X p 0 0 l:j7 . C Z - S Ip/O "c 0 N RRA IF 1 4 X 0 l:f7 (AJ . oI .- 0 .... o J. C8 ‫סס‬oo1 rrr 2 8 X X X P 0 0 • O~ • Rotate contents of register right with branch Carry. • 'a.. l:j7 [ reg) t7 • oiJ 0 II: 'I::J i: .Table 3-4.l: C/) • RRC reg c [ reg] Rotate contents of register left through Carry. I I: . . RlC ~ ~ reg CB OOOOOrrr 2 8 X X X P 0 0 &y17 I IRotate .I 7 .• ~ 2 B X X X P 0 0 L£]. SlA reg CB 00100rrr 2 8 X X X P 0 0 [reg] Shift contents of register left and clear lSB (Arithmetic ShiftJ. oI :§J of:J 'Rotate Accumulator right through Carry.. Set (Continued) Operation Performed Clock Cycle.:: • c g Rl reg CB 00010rrr [ reg] contents of register left with branch Carry. zao Instruction Statu. El.•... W I Co) 9 0) ..

Contents of the upper half of the Accumulator are not affected. 0 2 18 X X P 0 0 I I3 [Al I 'tl • ::: :c III J RRD ED 67 a Rotate one BCD digit left between the Accumulator and memory location (implied addressingl. I --EJ o • RLD ED 6F Shift contents of register right and clear MSB (Logical Shiftl. SRL reg CB 00111rrr 2 8 X X X P 0 0 -..Contents of the upper half of the Accumulator are not affected.. c: . A Summary of the laO Instruction Set (Continued) Type Mnemonic Operand Object Code Byte..... .Table 3-4. Operation Performed C Z S PIO Ac 0 N SRA reg CB 00101rrr 2 8 X X X P 0 Cj 0 [ reg] . • I o I I 7 4 I 3 I ~ I 4 • o I 2 18 X X P 0 0 I 7 4 I3 [AI Rotate one BCD digit right between the Accumulator and memory location (implied addressingl. W I W . I "0 o Shift contents of register right and preserve MSB (Arithmetic Shift).1 7 4 7 . Clock Cycle.. Statu.•..:: c: 0 tJ :::I [ reg] . • o I I • • 7 I 3 [[ HLlJ I o I ...• a:: c: .

(xV" disp) b. reg(b) .1 Set indicated bit of memory location (implied addressing or base relative addressing/. Z .[ pdHIIl (( SPl-21. [ pr(LOll .[ SPl-2 Put contents of register pair or Index register on top of Stack and decrement Stack Pointer.. [ HI . . [( HLlJlb) . RES RES 8 15 23 to) I (0) 4 co PUSH pr xv 1'u0101 1h11101 E5 1 2 11 15 POP .! :::l a.[[ SPI + 1I [ SP] . Operation Performed Z Mnemonic Object Code C S ? ? PIO ? Ac 1 1 N BIT BIT b.1 or [[ XV] + dispJlb) . reglbl . II u lhxOO01 1 h11101 E1 1 2 10 14 EX ISPl.(xV + displ CB 01bbbrrr CB 01bbbllO 1 lx11101 CB disp 01bbb110 CB 11 bbbrrr CB 11bbb1 10 1h11101 CB disp 11bbb110 CB 10bbbrrr CB 10bbbll0 1 lx11 101 CB disp 10bbb110 2 2 8 12 20 X X 0 0 ? 4 2 2 .[[ SP] + 1] [Ll .. zao Instruction Set (Continuedl Statu. SET SET 8 15 23 iii .0: pr xv (/) .[SP] + 2 Put contents of top of Stack in register pair or Index register and increment Stack Pointer.. II 4 2 2 Z .0 Reset indicated register bit..[[ xvI + displlb) Zero flag contains complement of selected bit of the memory location (implied addressing or base relative addressing). A Summary of the Type Operand Byte.reg b.xv E3 llxlllOl E3 1 2 19 23 ([ SP]-ll .[[ HLlJlbl or Z .IHlI b.(HU b.reg b.Table 3-4.[ pr(LOl] [ SP).reglbl Zero flag contains complement of the selected register bit.reg b. Clock Cycle.[[ SPII [ pr(HIlI .[[ SPII Exchange contents of HL or Index register and top of Stack.1 Set indicated register bit.0 or [[ XV] + dispJlbl .0 Reset indicated bit in memory location limplied addressing or base relative addressing). [[ HLlJlbl .(HU b.g 'i: ~ e: .HL (SPl.lxV + disp) b.

[PCIHIIl [[ SP)-2J . et) II • a SCF CCF 37 3F 1 X 0 ? 0 0 C-1 Set Carry flag. RETI RETN ED ED ED ED ED 40 45 46 56 5E 2 2 14 14 1M 0 1 2 2 2 2 1 1 B B B 4 4 CAl CAl CD ..6 Restart at designated location.[ SPI-2 [PCl -18. CPU halts.[ PCILOI) [ SP] . Enable interrupts. [[ SP)-1] . C-C Complement Carry flag. No operation . Set interrupt mode O. Return from interrupt.volatile memories are refreshed. Return from nonmaskable interrupt. i a. executes NOPs to refresh volatile memories. 01 EI RST n F3 FB 1 lxxx1 1 1 1 1 1 S .nl. or 2. 1. . NOP HALT 00 76 1 1 4 4 "Execution time shown is for one iteration. A Summary of the Clock Cycles 4 4 11 zao Z Instruction Set (Continued) Status Operetion Performed C Type Mnemonic Operand Object Code Bytes S P/O Ac N DiSable interrupts.Table 3-4.

{HLl reg (HU A.A DE Af.(HU A.data16 (addrl.reg A.reg E.datal€ (addr).lHU L.disp SP.rr CB06 ca 0 iHU (HU.lBC) BC C C C.addr reg (HU reg (HU reg {HLI reg C9 CA ppqq CB 0 Orr.reg H.addt addr NZ.laddr) SP A A A.reg C.(HLI A.addr BC A.data16 (BCl.OE A.(HU O.A SP (HU 16 vv 17 18 disp-2 19 lA 18 lC to RLA JR ADD LD DEC INC DEC LO RRA JR LO LO INC INC DEC 10 IE vv 1f 20 disp-2 21 yyyy 22 ppqq 23 24 25 26 27 28 disp-2 29 2A ppqq 28 2C 20 2E 2f 30 disp-2 31 yyyy 32 ppqq 33 34 35 36 37 38 9 lrrr 9E AOm A6 A 1m AE BOrn sac SBC AND AND XOR XOR OR OR CP CP RET B6 B 1m BE CO Cl C2 ppqq C3 ppqQ C4 ppqQ C5 C6 C7 C8 vv LO OM JR ADO LO DEC INC DEC LO CPL JR LO LO INC INC DEC pop JP JP CALL PUSH ADD RST RET RET JP RLC RLC RRC RRC RL RL RR vv OOH Z Z.SP A.reg O.data OBJECT CODE 39 3A ppqq 38 3C 3D 3E 3F 46 4 lsss 4E 5 Osss 56 5 lsss 5E 6 Osss 66 6 lsss 6E 7 Osss 76 7 lsss 7E 80m 86 8 1m 8E 90m 96 INSTRUCTION ADO LO DEC INC DEC HL.disp HL.A BC B B B. 1.reg A.data disp HL. Instruction Object Codes in Numerical Order OBJECT CODE INSTRUCTION NOP LD LD INC INC DEC LD RLCA EX ADD LD DEC INC DEC LO RRCA OJNZ Lo LO INC INC DEC disp oE.disp CB Of CB 1 Orrr CB 16 CB 1 1m vv LO SCF JR 3-40 .(HLJ E.reg B.AF HL.data NC.data Z.laddr) HL L L L.data 00 01 yyyy 02 03 04 05 06 VV 07 08 vv LD CCf LO LO LO LO LD LO LO LO LO LO LO LO LO HALT LO LO ADD ADD ADC AOC SUB SU8 4 Osss 09 OA OB DC DO OEvv OF 10 disp-2 II yyyy 12 13 14 15 0 0 o.HL HL H H H.disp HUiL HL.Table 3-5.data NZ.{HU reg (HU reg (HU reg (HLI reg (HU NZ BC NZ.(OE) DE E E E.reg A.BC A.reg A.(HLJ C.reg A.data16 (DEI.data BC.(HU IHU.data C.lHU H.reg L.data B.

reg b.dllta16 (addrl.addr DE data 10H C C.Table 3-5.(addrl IX (IX + displ (IX + diep) (IX + displ.IHU b.reg HL. Instruction Object Codes in Numerical Order (Continued) OBJECT CODE CB IE CB 2 Om CB 26 CB21m CB 2E CB 31m CB 3E CB 01bbbm CB 01bbbl10 • CB IObbbm CB IObbbl10 CB l1bbbm CB llbbbllO CC PPQq CO PPQq CE yy CF 00 01 02 PPQq 03 yy D4 PPQq 05 Deyy 07 INSTRUCTION RR SLA SLA SRA SRA SRL SRL BIT BIT RES RES SET SET CALL CALL ADC RST RET pop JP OUT CALL PUSH SUB RST RET EXX JP IN CALL ADD LD LO INC Lo DEC INC DEC Lo LD Lo ADD ADC SUB SBC AND XOR OR CP RLC RRC RL RR SLA SRA SRL BIT (HU reg (HU reg (HLI reg (HLI b.reg A.addr reg.(lX+displ b.rp (addrl.A A.data ISH PO HL PO.data 08H NC DE NC.(lX+displ IX (SPI.A HL.addr addr A.reg b.A NC.(lX + displ OBJECT CODE DO CB disp lObbbl10 DO CB disp l1bbb110 DO El DO E3 DO E5 DO E9 DO F9 DE yy OF EO E1 E2 PPQq E3 E4 PPQq E5 E6 yy E7 E8 E9 EA PPQq EB EC ppqq EO 01dddOOO ED 01sss001 EO 01xx 2 EO 01xx 3 ppqq EO 44 ED 45 ED 01Onnl10 EO 47 ED 01xx A ED 01xx B ppqq ED 40 ED 4F EO 57 ED 5F ED 67 EO 6F EO AO ED Al ED A2 ED A3 EO AS ED A9 EO AA ED AS ED SO ED B1 ED 82 ED B3 ED 88 ED B9 EO SA EO Be EE yy EF INSTRUCTION RES SET pop EX PUSH JP LD SBC RST RET pop JP EX CALL PUSH AND RST RET JP JP EX CALL IN OUT b.(lX + diapl (IX + displ.rp sse LD NEG RETN D8 09 DA PPQq DB yy DC ppqq DO OOxx 9 DO 21 yyyy DO 22 PPQq DO 23 DO 2A PPQq DO 2B DO 34 disp 00 35 disp DO 36 disp yy DO 01ddd 110 disD 00 I Oass disD DO S6 disp DO SE disp DO 96 disp DO 9E disp DO A8 disp DO AE disp DO B6 disp DO BE disp 00 CB disp 06 00 CB disp DE DO CB disp 16 DO CB disp 1E DO CB disp 26 DO CB disp 2E DO CB disp 3E DO CB disp 01bbbl 10 1M LD ADC LD RETI Lo Lo Lo RRO RLO LDI CPl INI m I.reg b.addr IX.HL PO.addr (SP).IX A.(IX + diap) (IX +disp) A'(lX+disp) (IX + disp) (IX + displ (IX + disp) (lX+disp) (lX+disp) (IX +displ IIX +disp) (IX +diap) (IX +disp) (IX +disp) (lX+displ b.addr OE.IHL) Z.addr (portl.pp IX.(addrl R.(lX+disp) A.HL PE.rp rp.(port) C.dlltl reg.I A.lX IX IX.addr A.IHU b.addr HL data 20H PE IHLI PE.R OUTI LOO CPO iND OUTO LDIR CPlR INIR OTIR LDDR CPOR INDR OTOR XOR RST dIIta 2SH 3-41 .(CI (CI.IX IX (IX) SP.

.

set C to 0 f.ADC A. After the instruction A..data .C D. - CE yy mmmm mmmm+ 1 mmmm+2 mmmm+ 3 -. and Carry=O.. Suppose xx=3A16.If 1= 1. yy= 7C 16.E H. the Accumulator will contain 8616: 3A 7C Carry o1 1 1 1011 001 1 1 010 1 1 00 1 sets S to 1 No carry.ADD IMMEDIATE WITH CARRY TO ACCUMULATOR s F A Z AC Pia N ~ xx ~ . I Data Memory B.-CE yy ADC data Add the contents of the next program memory byte and the Carry status to the Accumulator.J o 0110 LNon~zem . set AC to 1 a. set N to 0 "'-------Carry. '" mmmm+2 """"- R • I ADC A. 3-43 .7CH has executed. set P/0 to 1 The ADC instruction is frequently used in multibyte addition for the second and subsequent bytes.esult set Z to 0 Addition instruction.L ~+xx+~ Program Memory SP PC IX IV I mmmm .

ADC A.mo .. D..C D..... the Accumulator will contain 8416: E3 AO Carry 1 1 10 1010 1000 1 1 sets S to 1 Carry.. i Data Memory }-l ~ contents of A._ _--1mmmm + 2 1-_ _. H or L and the Carry status to the Accumulator... Suppose xx=E316. B..D. mmmm + 3 ADC A -.. Register E contains A016. C.reg - ADD REGISTER WITH CARRY TO ACCUMULATOR -~ ~ ~x+vy+c SZACP/ON! F A S.10001 -reg xxx -..E ~ xx r. E.H H. set P/0 to 0 t u 01 00 LNon... set N to 0 The ADC instruction is most frequently used in multibyte addition for the second and subsequent bytes.B....sult._ _--1mmmm + 1 .No carry.. set AC to 0 Addition instruction...000 001 010 011 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Add the contents of Register A.C.. set C to 1 1 ¥ 1=0. Program Memory I R I 10001 xxx mmmm . 3-44 .". After the instruction ADC AE 001 1 0000 has executed.E.L orLisvy mmmm + 1 SP PC IX IV I mmmm . and Carry=l...... Sol Z to 0 .

x. After the instruction ADC A(HU ---ADC A(HU 8E has executed..L PP mmmm QQ ..(HU: Add the contents of memory location (specified by the contents of the HL register pair) and the Carry status to the Accumu lator Suppose xx=E316.ADC A.- ADC A(lX+disp} DO d Add the contents of memory location (specified by the sum of the contents of the IX register and the displacement digit d) and the Carry to the Accumulator ~-.o cesult. set N to 0 ~---- ~-.+ C -~ YV + ~ l A YV PPQQ B. the Accumulator will contain 8416: E3 AO Carry 1110 1010 1000 1 sets S to 1 Carry. set Z to a No carry.. set AC to 0 Addition instruction.(IY+disp) S ZAcP/ON C F IxlXIXlxlOIX ~X Data Memory _ I. set P/O to 0 .E H.fJ BE BE 0011 0000 1 0100 LNon.C D.- ADC A(lY+disp) FD d This instruction is identical to ADC A(lX+displ. set C to 1 1 ¥ 1=0.. yy=A016..(IX+disp) ACCUMULATOR ADC A.. 3-45 .(HL) .:. except that it uses the IY register instead of the IX register The ADC instruction is most frequently used in multibyte addition for the second and subsequent bytes. and Carry=l.ADD MEMORY AND CARRY TO ADC A. SP PC IX -~ ~mmm+ 1 V Program Memory mmm m mm mm+l mmmm+2 ~---t mmmm + 3 IV I I BE R I The illustration shows execution of ADC A.

HL or SP : " contain yyyy xx mmmm xx ~ - ~xx+yyyy .E H.. BC contains 104416. to the HL register pair. set N to 0 The ADC instruction is most frequently used in multibyte addition for the second and subsequent bytes.. set AC to 0 Addition instruction..Ncncmc result. DE. set P!O to 0 V 1 t. Suppose HL contains A53616.L Memory Be.ADD REGISTER PAIR WITH CARRY TO HAND L S Z AC P/O N C Data F~ A B. set Z to 0 No carry."""" SP PC IX IY I +C Program ~mmm+v Memory I R I mmmm mmmm + 1 mmmm+2 t . After execution of HLBC the HL register pair will cqrtain: A536 1044 Carry 1010{)101 0011 0110 0001 000001000100 1 1011010101111011 1 sets S tc 1 No carry. and the Carry status. and Carry=l.C D. HL register pair or the Stack Pointer.rp . set C to 0 011-0=0.- for for for for rp rp rp rp is is is is register pair BC register pair DE register pair HL Stack Pointer Add the 16-bit value from either the BC.. 3-46 ...ADC HL. DE.t mmmm + 3 ED 01xxl010 E DOlxxl010 K 00 01 10 11 ADC -.

-C6 -. 3-47 .C D. set AC to 1 Addition instruction.E H. and Carry=O.7CH has executed.ADD A. set C to 0 t - LNon-ze""esu. the Accumulator will contain 8616: 3A 001 1 7C = 0 1 1 1 1 01 0 1 10 0 110 101U 1 sets S 10 1 No carry. C6 YV mmmm mmmm+ 1 mmmm+2 mmmm+3 ADD A. yy=7C16. set N to 0 o¥ 1= 1: set P/0 to 1 This is a routine data manipulation instruction. After the instruction ADD A..L xx :xx+vvr " mmmm """"'+ SP PC IX IY I mmmm 2 Program Memory I R I .ADD IMMEDIATE TO ACCUMULATOR F (E[E[[IE]]JEJ 5 Z AcP/O N C Data Memory to S... Suppose xx=3A16.yy Add the contents of the next program memory byte to the Accumulator.tset Z to 0 Carry...data . data ---.

C D. set C to 1 1 ¥ 1=0. D.E the Accumulator will contain 8316: E3 AO = 1 1 10 10 10 1000 1 sets S to 1 Carry... B. ... . set Z to a .D.. r 3> ~A. After execution of ADD A.C..reg S Z ADD CONTENTS OF REGISTER TO ACCUMULATOR N C Ac P/O F A ~ xx r..E H.B. Suppose xx=E316. - 10000 xxx 000 001 010 011 100 101 111 for for for for for for for reg=B reg=C reg""-D reg=E reg =H reg=L reg=A Add the contents of Register A.. H or L is yy _ ~..ADD A..No carry. set PIO to 0 r 00 1 1 0000 0011 LNon-wo msull....1 mmmm + 2 l0000xxx R I I t-----1 mmmm+3 ADD reg -v-" . H or L to the Accumulator.L SP PC IX IY I mmmm } 0001. Register E contains A016...E...::mmm + 1 Program Memory mmmm mmmm+ 1 t . set N to 0 This is a routine data manipulation instruction 3-48 . xx+yy~ Data Memory B. C. set AC to 0 Addition instruction... E.

set AC to 0 Addition instruction.. lA = 0001 50 = 0 1 0 1 1010 0000 101 0 o1 10 o sets S to 0 No carry.C D. set P/O to 0 ~-.. Program Memory R I I ~pqq+d)== 00 86 d mmm m mmm m+ 1 mmm m +2 mmm m + 3 The illustration shows execution of ADD A.. to the Accumulator. The ADD instruction is a routine data manipulation instruction 3-49 ..L -~ I-- "" xx+yy ~ """" yy ppqq+ d ~ SP PC IX IV I mmmm ppqq ~ mmmm+3 . set C to 0 fJ .(IX+disp).em . specified by the contents of the HL register pair.. except that it uses the IY register instead of the IX reg ister.(IX+disp} --..""It. xx= 1A 16..- ADD A(lY+disp) FD d This instruction is identical to ADD A(lX+disp).(lY+disp} S X ZACP/ON C X X X 0 X F~ A Data Memory xx B..E H. ADD A(HL) ~ This version of the instruction adds the contents of memory location. (IX+disp) ADD A.-. After the instruction ADD A(lX+OFH) has executed.ADD A. and memory location 400F16 contains 5016. set N to 0 o¥O=O.. 86 86 LNon-.. ADD A. set Z to 0 No carry.(HL) .ADD MEMORY TO ACCUMULATOR ADD A. the Accumulator will contain 6A 16.-DO 86 d Add the contents of memory location (specified by the sum of the contents of the IX register and the displacement digit d) to the contents of the Accumulator Suppose ppqq=4000 16.

= 0000 0011 0100 1010 0010 0001 0100 1100 00 1 100 100 1 11 aa No carry. DE.l xx mmmm SP PC IX IY I xx ~ -. Suppose HL contains 034A16 and BC contains 214C16. set C to 0.. set N to a a a The ADD HLHL instruction is equivalent to a 16-bit left shift. After the instruction has executed. DE.rp - ADD REGISTER PAIR TO HAND L Data Memory A Be.J ~"'''''P-------NOcarry. HL or SP B.. II.E H.ADD HL.C D. 3-50 . the HL register pair will contain 249616..J Program Memory xxxx + VYYY - ~mmm+l I R I mmmm mmmm+ 1 1------1 mmmm + 2 mmmm+3 1------1 OOxxl001 1K --00 xx 1001 00 01 10 11 for for for for rp rp rp rp ADD HLBC 034A 214C is is is is register pair BC register pair DE register pair HL Stack Pointer Add the 16-bit value from either the BC."~ YVVY v. HL register pair or the Stack Pointer to the HL register pair. ~ =t. set AC to a Addition instruction.

.. -~ mmmm +~ 2 .100 1 00 01 10 11 for for for for register=IX 1 for Index register=IY rp rp rp rp is is is is register pair BC register pair DE specified Index register Stack Pointer Add the contents of the specified register pair to the contents of the specified Index register.L rr 55 SP PC IX IV I R mmmm ppqq t'--....DE...ADD xy.. Program Memory -....I ........rp \l..... Index Register IY will contain 4FFF16 3-51 . 11 ADD xi. mmmm + 3 The illustration shows execution of ADD IX. Suppose IY contains 4FF016 and BC contains 000F16 After the instruction ADD IY....BC has executed...rp - ADD REGISTER PAIR TO INDEX REGISTER Data Memory A B..... o for Index /Xk "'_-----J. ... "Gqq+rr5~ llvl1101 mmmm OOxx 1001 mmmm + 1 1-_ _---1mmmm + 2 1-_ _. 11 a1 OO-¥.C D...E H.

.E H.AND data -AND IMMEDIATE WITH ACCUMULATOR S Z AC P/O N C Data Memory F~ A B.. 3A 7C = 001 1 0 111 0011 10 10 1 10 0 1000 o sets S to o. set PIO to 0 LNon-zero result. the instruction AND 7FH will unconditionally set the high order Accumulator bit to 0.E6 data -yy LThree 1 bits..-r.L SP PC IX IV mmmm "mmmm+ 2 .. the Accumulator will contain 3816.. Program Memory O.. Suppose xx=3A16..J This is a routine logical instruction: it is often used to turn bits "off' For example. set Z to 0 AND the contents of the next program memory byte to the Accumulator....C xx _ -~ xx·yy -I~ "). 3-52 .After the instruction AND 7CH has executed.. '- I R I I E6 yy mmmm mmmm+1 mmmm+2 mmmm+3 AND --.

.C Z ACP/O N C ~ xx f..oJ'OI _ Jt' Il A. and Register E contains A016 After the instruction AND E has executed. 0...t mmmm + 2 mmmm+3 t .B.C. C. H or L. B. the Accumulator will contain A016 E3 AO = ----. Suppose xx=E316... se1 P/O 10 1 Non-zero result set Z to 0 AND is a frequently used logical instruction 3-53 .L SP PC IX IY I }-... I R I mmmm mmmm+ 1 t ... H or L is yy mmmm + 1 mmmm Program Memory ..- reg for for for for for for for reg=B reg=C reg =0 reg=E reg =H reg=L reg=A AND the Accumulator with the contents of Register A. 10100xxx AND ~ 10100 000 001 010 011 100 101 111 -.. -.D.... Jt' xx'vy Data Memory "- D........ E..E H.-J 1== Two 1 bit>. Save the resu It in the Accumulator..-101 0 0000 1 1 10 1010 001 1 0000 sets S to 1....-.-xxx -.AND reg -AND REGISTER WITH ACCUMULATOR s F A B...E...

-..- yy ppqq +d ~ SP PC IX IY I mmmm ppqq .""'--1 mmmm + 3 R I I ppqq+dJ- FD A6 The illustration shows execution of AND (IY+disp)..... and memory location 400F16 contains A016..J LTWO AND (IX+disp) DD A6 1 bits... ppqq=400016.the displacement digit d) with the Accumulator Suppose xx=E316.AND (HL) . 3-54 .- d This instruction is identical to AND (lY +displ. A6 AND the contents of the memory location (specified by the contents of the HL register pair) with the Accumulator. ~ AND (IY +disp) -:-rFD A6 d AND the contents of memory location (specified by the sum of the contents of the IY register and..AND MEMORV WITH ACCUMULATOR AND (lX+disp) AND (IV +disp) S Z AC P/O N C x X 1 X 0 0 F~ A B. the Accumulator will contain A016 E3 AO = ------- 111a 1 01 0 10 10 o1 1 1 0000 0000 sets S to 1.. except that it uses the IX register instead of the IY register.C D... AND (HL) --.E H. set PIO to 1 LNon-zero result. After the instruction AND (IY+OFH) has executed.. .•.. mmmm+3 Program Memory mmm m mmmm+ 1 d mmmm+2 1--.L Data Memory xx . AND is a frequently used logical instruction. ~ xxoyy ... set Z to 0 ~-...

while bit 4 in Register Cremains O.... t AC P/O N C r 1 b Data Memory B..t mmmm + 3 CB 01bbbxxx R I I -... a 3-55 .~ PC IX IV I mmmm .BIT b.C D. mmmm + 2 Program Memory mmmm mmmm + 1 mmmm+2 I .. Bit is the least significant bit...C will then set the Z flag to 1..- b.CB 01 BIT --.E H..L SP _. Suppose Register C contains 1110 1111.. bbb -.reg - TEST BIT b IN REGISTER reg s F A ~ yyy yyyy. The instruction BIT 4.xxx Bit Tested a 000 1 001 2 010 all 3 100 4 101 5 110 6 111 7 --reg 000 001 010 all 100 101 111 Register B C 0 E H l A Place complement of indicated register's specified bit in Z flag of F register.

and place bit's complement in Z flag of the F register. Bit BIT -. while bit 3 in memory location 4000H remains 1. (HL) .BIT b.- least significant bit b. The instruction BIT 3.(lX+disp) BIT b.b is the same as in BIT b..E H.(HL) Examine specified bit within memory location indicated by the sum of Index Register IX and disp.TEST BIT b OF INDICATED MEMORY POSITION BIT b.CB 01 -.. 3-56 . Place the complement in the Z flag of the F register.L SP PC IX IV I PP mmmm Pi q qq -~ ~mmm+2 :V Program Memory I R I mm mm CB 01bbbll0 mmmm+l mmmm+2 1 .- a is the -. 2KDD CB dOl bbb 110 bb. (HL) Bit Tested bbb a 000 001 1 2 010 all 3 4 100 101 5 6 110 111 7 --bbb 110 Test indicated bit within memory position specified by the contents of Register HL.1 mmmm + 3 The illustration shows execution of BIT 4.-/- yyyByyyy D. (lY+disp) 5 Z AC Pia N C F~ A Data Memory b B.(HL)....C .. Suppose HL contains 4000H and bit 3 in memory location 4000H contains 1.(HL) will then set the Z flag to O.

. except that it uses the IY register instead of the IX register..the low-order half of the address......L SP -C:.- CD ppqq Store the address of the instruction following the CALL on the top of the stack: the top of the stack is a data memory byte addressed by the Stack Pointer Then subtract 2 from the Stack Pointer in order to address the new top of stack. The instruction labeled SUBR will be executed next 3-57 . and the third byte is the high-order byte...E H..C D.Suppose Index Registel' IX contains 4000H and bit 4 of memory location 4004H is O. mmmm I I mm+3 mm xxxx-2 Program Memory xxxx-2 xxxx-l xxxx '# ~ PC IX ~mmm+3 IY ~ R I I mmmm mmmm+ 1 { .q~q_-I mmmm + 2 1------4 mmmm + 3 pp CD CALL "'-v-' label -. (Ix +displ. The Stack Pointer is decremented by 2.(IY+disp) Fo~ CALL label 5 Z Ac PIO N c bbb is the same as in BIT b.. CALL THE SUBROUTINE IDENTIFIED IN THE OPERAND Data Memory FCIIIIIJ A S. Move the 16-bit address contained in the second and third CALL instruction object program bytes to the Program Counter..(HU This instruction is identical to BIT b.. while bit 4 of memory location 4004H remains 0 BIT b. Consider the instruction sequence: CALL AND SUBR 7CH SUBR After the instruction has executed. (IX +4H) will then set the Z flag to 1. the address of the AND instruction is saved at the top of the stack.. The second byte of the CALL instruction is. The instruction BIT 4. xxxx.

SUBR condition not satisfied 7CH SUBR If the condition is not satisfied. the AND instruction will be executed after the CALL COND.CALL condition. If the condition is satisfied. label T~I 11 xxx 100 pp qq CALL T all -'- 000 001 010 100 101 110 111 Condition NZ Non-Zero Z Zero NC Non-Carry C Carry PO Parity Odd PE Parity Even P Sign Positive M Sign Negative Relevant Flag Z Z C C PIO PIO S S This instruction is identical to the CALL instruction. except that the identified subroutine will be called only if the condition is $atisfied. 3-58 . the instruction sequentially following the CALL condition instruction will be executed. The instruction labeled SUBR will be executed next. label - CALL THE SUBROUTINE IDENTIFIED IN THE OPERAND IF CONDITION IS SATISFIED condition. Consider the instruction sequence: I _------1 AND condition satisfied CALL : COND. and the Stack Pointer is decremented by 2.SUBR instruction has executed. otherwise. the address of the AND instruction is saved at the top of the stack.

CCF S COMPLEMENT CARRY FLAG Z AC P/O N C Fc:r::r::I:IJEJ. --- Program Memory I R I I 3F mmmm I-_ _-Immmm + 1 mmmm+2 I ...-. mmmm + 1 .E H. A S. .. -------~~C:X . No other status or register contents are affected 3-59 .L J Data Memory SP PC IX IY mmmm .I mmmm + 3 CCF 3F Complement the Carry flag.C D...

E H. ie.N o borrow.. but modify the status flags to reflect the result of the subtraction...e. set C to 0 1¥1 =0. the Accumulator will still contain E316. treating both numbers as simple binary data. set PIO to 0 t u LNoo-mo .. set Z to 0 '--. set N to 1 Notice that the resulting carry is complemented.. Suppose xx=E316 and the second byte of the CP instruction object code contains AD 16 After the instruction CP OAOH has executed. set AC to 0 Subtract instruction. leave the Accumulator alone. 3-60 .l - Xx-VY~ ~mmm+v Program Memory SP PC IX IV I R mmmm I FE yy I mmmm mmmm+ 1 mmmm+2 mmmm+3 CP FE data yy Subtract the contents of the second object code byte from the contents of the Accumulator. Discard the result.C D.CP data ."lt.COMPARE IMMEDIATE DATA WITH ACCUMULATOR s F Z AC Pia N C t ~ xx Data Memory A B. but statuses will be modified as follows: E3 AO 1110 1010 0100 0011 0000 0011 o sets S to 0 No borrow.

t Z AC P/O N C" tEIEIEIEIIEl xx I - 1 XX. set N to 1 a a . but modify status flags to reflect the result of the subtraction. After the instruction CP B has executed..yy ') Data Memory } Contents of or Lis yy ____ A. leave the Accumulator alone.I mmmm I I +3 CP --.... Discard the result.CP reg - COMPARE REGISTER WITH ACCUMULATOR I's F A B.C D.l .suit set Z to 0 Subtract instruction..~mmm+v Program Memory mmmm mmmm+ 1 ~----1 mmmm + 2 10111xxx ~_ _.C.E H. treating both numbers as simple binary data.... the Accumulator will still contain E316. set AC to 0 Notice that the resulting carry is complemented.. B.em ". Suppose xx=E316 and Register B contains A016.E.10111 xxx 000 001 010 all 100 101 111 -reg -. H or L from the contents of the Accumulator. set PIC to fJ 0011 0000 0011 LNon~.- for reg=B for reg=C for reg=D for reg=E forreg=H forreg=L for reg=A Subtract the contents of Register A.. set C to 1 ¥ 1=0.No borrow.D. E..B.H l SP PC IX IY I R mmmm - . i. 3-61 . C D..e.. but statuses will be modified as follows: E3 = AO 1110 1010 0100 a sets S to a No borrow.

leave the Accumulator alone.em . treating both numbers as simple binary data Discard the result: ie. set N to 1 a a Notice that the resu Iting carry is complemented..L pp qq mmmm SP PC IX IV I -~ I.CP (HL) . LNOn".esult..-- DO BE d 3-62 .. set Z to 0 No borrow.C D. but statuses will be modified as follows: E3 1 1 10 AO = 0 1 1 0 0100 00 1 1 000 0011 a a sets S to a No borrow. set P/O to U t .xx-yy .-.-..:. but modify status flags to reflect the resu It of the subtraction Suppose xx=E316 and yy=A016· After execution of CP (HL) the Accumulator will still contain E316.. CP (IX+disp) ---./ _ ""'" yy B..mmm +' V 1 mmmm mmmm+1 mmmm+2 qq Program Memory I BE R I t-----t mmmm + 3 The illustration shows execution of CP (HL): CP (HL) ~ BE Subtract the contents of memory location (specified by the contents of the HL register pair) from the contents of the Accumulator. set C to 1 ¥ 1=0.E H. set AC to-O Subtract instruction.COMPARE MEMORY WITH ACCUMULATOR CP (lX+disp) CP (lY +disp) ..' S Z AC pia N C F A t ~ xx Data Memory _r _ ' .

.....t I R mmmm mmmm+ 1 mmmm+2 .:_.-' ED A9 Compare the contents of the Accumu lator with the contents of memory location (specified by the HL register pairl. i.l .==~-.. ~ reset otherwise Data Memol')! xx uu t-----::'::""""--t------:~--f_::::::::. CPO-COMPARE ACCUMULATOR WITH MEMORY.e...... Discard the result. ~ CP (IY+disp) FD BE --d This instruction is identical to CP (IX+displ... yy ppqq D... except that it uses the IY register instead of the IX register.Subtract the contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) from the contents of the Accumulator....J mmmm Program Memol')! IV I .. leave the Accumulator alone...C fXT'XTXT'"J'i'n tt 5 Z Ac P/O N C 5et if 8C-l ~ O.. DECREMENT ADDRESS AND BYTE COUNTER F A B... SP PC IX t:==~p~p==~~::=:q~q~==f=----=:::=::::~-...... set Z flag...1 mmmm + 3 A9 ED CPD '-.E H. treating both numbers as simple binary data. (BC is used as the Byte Counter) 3-63 .. If A is equal to memory.. but modify status flags to reflect the result of the subtraction.. Decrement the HL and BC register pairs.

interrupts will be recognized and two refresh cycles will be executed.. the Accumu lator contains F916' and memory has contents as follows: Location 5000 16 4FFF16 4FFE16 4FFD16 4FFC16 4FFB16 After execution of CPOR the P/O flag will be 1. and yy=A016.-ED B9 This instruction is identical to CPO. After each data transfer. the BC register pair contains 00FF16. ppqq=400016. the HL register pair will contain 4FFB 16. Contents AA16 BC16 1916 7A16 F916 0016 3-64 . BC contains 000116.N o borrow. J fJ 0011 LNon-mo 'e...". but statuses will be modified as follows: E3 AO 1 1 10 1 01 0 001 1 0000 0100 o sets S to O . After the instruction CPO has executed.. the Z flag will be 1. the Accumulator will still contain E316. and the BC register pair will contain 00FA16. DECREMENT ADDRESS AND BYTE COUNTER. The HL register pair will contain 3FFF16. CONTINUE UNTIL MATCH IS FOUND OR BYTE COUNTER IS ZERO CPOR --.. set Z to 0 '--. set N to 1 Carry not affected..Suppose xx=E316. except that it is repeated until a match is found or the byte counter is zero. Suppose the HL register pair contains 500016. and BC=O CPDR-COMPARE ACCUMULATOR WITH MEMORY. set AC to 0 The P/O flag will be reset because BC-1 =0 Subtract instruction involved.

... and BC will contain 003116..----1 mmmm + 2 ..-. ~eset otherwise XX Memory B.L SP PC IX IY mmmm Program Memory ED I R . Increment the HL register pair and decrement the BC register pair (BC is used as Byte Cou nter) Suppose xx=E316. Subtract instruction involved. BC contains 003216. DECREMENT BYTE COUNTER..- The HL register pair will contain 400116. ppqq=400016.E tt PP uu QQ YY PPQQ H. set Z to 1 No borrow.. 3-65 . the Accumulator will still contain E316.. set N to 1. INCREMENT ADDRESS S Z AC P/O N C F~ A Data ~tifBC-l ~O. set the Z flag._ _--1 mmmm + 3 CPI ~ Al mmmm mmmm+ 1 ED A1 Compare the contents of the Accumulator with the contents of memory location (specified by the HL register pair). but statuses will be modified as follows: E3 -E3 1111 0000 0000 0 11 1 10 1 0000 a o sets S to 0--1 fJ LResult is O. set AC to 0 The PIO flag will be set because BC-1 l' O...C D... and yy=E316 After the instruction CPI has executed.. Carry not affected 1.CPI-COMPARE ACCUMULATOR WITH MEMORY. If A is equal to memory.

and the BC register pair will contain OOFC16. and memory has contents as follows: Location 4500 16 4501 16 4502 16 After execution of CPIR the P10 flag will be 1. the Accumulator contains F916. and the Z flag will be 1.CPIR - COMPARE ACCUMULATOR WITH MEMORY. the BC register pair contains 00FF16. INCREMENT ADDRESS. Suppose the HL register pair contains 450°16. After each data transfer interrupts will be recognized and two refresh cycles will be executed. The HL register pa ir will conta in 450316. CONTINUE UNTIL MATCH IS FOUND OR BYTE COUNTER IS ZERO ---CPIR ED B1 This instruction is identical to CPI. except that it is repeated until a match is fou nd or the byte counter is zero. Contents AA16 15 16 F916 3-66 . DECREMENT BYTE COUNTER.

....1 mmmm + 1 I---.t mmmm + 3 CPL 2F Complement the contents of the Accumu lator..COMPLEMENT THE ACCUMULATOR S F A Z ACP/O N C CI:IIIIrIJ xx Data Memory -~ xx B.. Suppose the Accumu lator contains 3A 16.C D... You need not use it for binary subtraction.E H.....L """- ~ Program Memory 2F mmmm SP PC IX IV I R mmmm " mmmm+ 1 """- I I 1 .CPL . SBC) 3-67 . After the instruction CPL has executed. the Accumulator will contain C516· 3A = Complement = 001 1 1 1 00 o 1 01 10 10 This is a routine logical instruction. there are special subtract instructions (SUB...t mmmm + 2 I---. No other register's contents are affected.

DAA - DECIMAL ADJUST ACCUMULATOR
S Z AC P/O N C Data

F~
A

Memory

xx

-

~onvert?
""-decimal

B.C
D,E H,L

SP

PC
IX

mmmm

_

-~ I....:,mmm + 1

V

Program Memory mmmm mmmm+ 1 1 - - - - - 1 mmmm + 2 27

IY
I

I

R

I

1--_ _-1 mmmm + 3

DAA

27
Convert the contents of the Accumulator to binary-coded decimal form. This instruction should only be used after adding or subtracting two BCD numbers: ie, look upon ADD DAA or ADC DAA or INC DAA or SUB DAA or SBC DAA or DEC DAA or NEG DAA as compound, decimal arithmetic instructions which operate on BCD sources to generate BCD answers. Su ppose the Accu mu lator contains 3916 and the B reg ister conta i ns 4716 After the instructions ADD B DAA have executed, the Accumulator will contain 8616, not 8016 Z80 CPU logic uses the values in the Carry and Auxiliary Carry, as well as the Accumulator contents, in the Decimal Adjust operation.

3-68

DEC reg -

DECREMENT REGISTER CONTENTS
Data
Memory

SZACP/ONC

F~
A

B.C D.E
H.L SP PC IX IV I R

~ Coo,"""E.ofH.Po, B. C. D.
or Lis yy

mmmm

-~

...,::mmm + 1

V

Program
Memory

I

I

mmmm mmmm+ 1 t - - - - 1 mmmm + 2 mmmm+3

OOxxxl01

t----t

_&
00

-..000 001 010 011 100 101 111

xxx

101 for reg=B for reg=C forreg=D for reg=E for reg= H for reg=L for reg=A

Subtract 1 from the contents of the specified register. Suppose Register A contains 5016. After execution of DEC A Register A will contain 4F16

3-69

DEC rp DEC IX DECIY
S

DECREMENT CONTENTS OF SPECIFIED REGISTER PAIR
C Data Memory

Z AC P/O N

Fc::o:IIIl
A

RC
D.E
H.L

~ Co,..,,, of Be
DE, HL or SP is yyyy

SP

PC
IX IY I R

mmmm

~mmm+3>

Program Memory

I I

mmmm mmmm+ 1 I - - - - - f mmmm + 2
I - - - - - f mmmm + 3

OOxxl0ll

The illustration shows execution of DEC rp:

]X
00 xx 1011 00 01 10 11 for for for for rp rp rp rp is is is is register pair BC register pair DE register pair HL Stack Pointer Subtract 1 from the 16~bit value contained in the specified register pair. No status flags are affected Suppose the Hand L registers contain 2F001 6 After the instruction DEC HL has executed. the Hand L registers will contain 2EFF16. DEC IX

-.---

DD 28 Subtract 1 from the 16-bit value contained in the IX register DEC IY
FD 28

--....-

Subtract 1 from the 16-bit value contained in the IY register. Neither DEC rp. DEC IX nor DEC IY affects any of the status flags. This is a defect in the Z80 instruction set. inherited from the 8080. Whereas the DEC reg instruction is used in iterative instruction loops that use a counter with a value of 256 or less. the DEC rp (DEC IX or DEC IY) instruction must be used if the counter value is more than 256. Since the DEC rp instruction sets no status flags. other instructions must be added to simply

3·70

set AC to a Subtract instruction. MOVE D TO A .E H.D E NZ.LOOP JP . This is a typica I loop form: LD LOOP DE.TO TEST FOR ZERO...C D... Suppose ppqq=450016.L SP PC IX IY I R pp Cqq yy-1 yy P f mmmm ~mmm+~ Program Memory I 35 I mmmm mmmm+1 mmmm+2 .FIRST INSTRUCTION OF LOOP DEC LD OR DE A.DECREMENT MEMORY CONTENTS DEC (lX+disp) DEC (IV +disp) S Z AC P/O N C Data F~ A S.RETURN IF NOT ZERO DEC (HL) .DECREMENT COUNTER .------1 The illustration shows execution of DEC (HL): DEC (HL) '-v-" mmmm + 3 35 Subtract 1 from the contents of memory location (specified by the contents of the HL reg ister paid. set N to 1 3-71 .LOAD INITIAL 16-81T COUNTER VALUE .test for a zero resu It. 5F = -01 = 0 10 1 1111 ~ ~ a sets S to O. yy=5F16 After execution of DEC (HL) memory location 450016 will contain 5E16.DATA . set PIO to 0 I?]1 0 1 r - 1111 1111 1 1 10 LNoo-mo 'esult. set Z to a No borrow.THEN OR A WITH E .jJ 1 ¥ 1=0.

.._ _-1 mmmm + 3 F3 When this instruction is executed.... the maskable interrupt is automatically disabled The maskable interrupt request remains disabled until it is subsequently enabled by an EI instruction....L SP . No registers or flags are affected by this instruction 3-72 .- DEC (IY+disp) FD 35 d This instruction is identical to DEC (IX+disp).... the maskable interrupt request is disabled and the INT input to the CPU will be ignored.._ _-1 mmmm + 1 .----1 mmmm + 2 01 -.E H. mmmm mmmm+ 1 ..C D. Remember that when an interrupt is acknowledged..... PC IX IY ~ Program Memory I R I F3 mmmm I .... except that it uses the IY register instead of the IX register 01 S DISABLE INTERRUPTS Z AC P/O N C Data FCIIIID A B..DEC (IX+disp) '-v-' -- DD 35 d Subtract 1 from the contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) ~-.-' .

DJNZ disp - JUMP RELATIVE TO PRESENT CONTENTS OF PROGRAM COUNTER IF REG B IS NOT ZERO xx-l j F A c::a::r::co xx' mmmm s Z ACPIO N C ~ Data Memory B.E H. The Assembler automatically adjusts for the twice-incremented PC. add the contents of the DJNZ instruction object code second byte and 2 to the Program Counter.L SP PC IX IV I R mmmm """""I I -- mmmm + 1 Program Memory mmmm mmmm+ 1 t .......C D....l SP PC IX IV ~ R - . Program Memory I • L 10 dd-2 mmmm mmmm+ 1 mmmm+2 mmmm+3 DJNZ ~ 10 dd-2 -- disp Decrement Register B If remaining contents are not zero.t mmmm + 3 3-73 . since the one instruction replaces the typical "decrement-then-branch on condition" instruction seQuence.E H.. The jump is measured from the address of the instruction operation code. The DJNZ instruction is extremely useful for any program loop operation.ENABLE INTERRUPTS S Z AC PIO N C F~ A Data Memory B.. EI.C D.m mmm+ ·~dd-2)+ 2..t mmmm + 2 FB t . the next sequential instruction is executed. and has a range of -126 to +129 bytes... If the contents of B are zero after decrementing.

EI FB Execution of this instruction causes interrupts to be enabled.ENABLEINTERRUPTS . Most interrupt service routines end with the two instructions: EI RET . Interrupts are processed serially: Lt'""""s ~ Lt'""'rus: ~ Interrupt service routine Interrupt service routine 3-74 .RETURN FROM INTERRUPT It is not uncommon for interrupts to be kept disabled while an interrupt service routine is executing.and unnecessarily consume stack memory space. but not until one more instruction executes.RETURN TO INTERRUPTED PROGRAM If interrupts are processed serially.ENABLE INTERRUPTS . This may be illustrated as follows: Interrupt Interrupt service routine By inhibiting interrupts for one more instruction following execution of EI. Under these circumstances. the ensures that the RET instruction gets executed in the sequence: zeo CPU EI RET . then for the entire duration of the interrupt service routine all maskable interrupts are disabled . If interrupts were acknowledged as soon as the EI instructions had executed. then the Return instruction would not be executed. returns would stack up one on top of the other .which means that in a multi-interrupt application there is a significant possibility for one or more interrupts to be pending when any interrupt service routine completes execution.

L' Program Memory D. ~mmm+ 1 V I R I mmmm mmmm + 1 mmmm +2 t------4I mmmm + 3 DB EX AF.AF' ~ 08 The two-byte contents of register pairs AF and AT are exchanged.E' H'. Suppose AF contains 4F9916 and A'F' contains 10AA16.E H.C I -if I F' A' B'. 3-75 .AF' AF will contain 1OAA16 and AF' will contain 4F9916.EX AF. A S. After execution of EX AF.C' D'.AF'-EXCHANGE PROGRAM STATUS AND ALTERNATE PROGRAM STATUS S Z ACP/O N C FI I I I I I - Alternate "\ Regis t er Set .L SP PC IX IV I mmmm -.

. H will contain 0316.) mmmm+ 1 Program Memory I EB mmmm mmmm+2 R I I--_ _---tmmmm + 1 t .(HL) has no single instruction equivalent. L will contain 2A16.HL S EXCHANGE DE AND HL CONTENTS C Data Memory Z AC P/O N Fco:IID A S.HL LD A.(DE) but if you want to load data addressed by the 0 and E register into the B register.- EB The 0 and E registers' contents are swapped with the Hand L registers' contents Suppose pp=0316. """'" .. qq=2A16.EX DE.L pp xx qq yy mmmm SP PC IX IY I . EX DE...E H.(HU are eq uiva lent to: LD A..HL has executed.HL LD B. 0 will contain 4116 and E will contain FC16· The two instructions: EX DE.t mmmm + 3 EX DE. xx=4116 and yy=FC 16· After the instruction EX DE....C D. 3-76 .HL ---.

H will contain 3A 16.L K xx ssss mmmm YV •" -.C D. EX (SP).HL ~ E3 Exchange the contents of the L register with the top stack byte.IY S EXCHANGE CONTENTS OF REGISTER AND TOP OF STACK Data Memory Z AC P/O N C Fo:r:IIIJ A B.HL instruction is used to access and man ipu late data at the top of the stack EX (SP). Exchange the IX register's high-order byte with the byte below the stack top. Exchange the contents of the H register with the byte below the stack top. The EX (SP).IX ~ DO E3 Exchange the contents of the IX register's low-order byte with the top stack byte. pp=3A16' qq=E216 After the instruction EX (SP). ~mmm+ 1 - - qq pp ssss ssss + 1 ssss + 2 SP PC IX IV I R V Program Memory I I E3 I-------t mmmm + 3 mmmm mmmm+ 1 mmmm+2 The illustration shows execution of EX (SP). but uses the IY register instead of the IX register.IY ~ FD E3 This instruction is identical to EX (SPl. Suppose xx=2116.IX. 3-77 . yy=FA16.HL EX (SP).E H.HL has executed.IX EX (SP). L will contain E216 and the two top stack bytes will contain FA 16 and 2116 respectively.HL EX (SP).EX (SP).

~mmm+~ R I I I--... 10FF16 and 333316 respectively After the execution of EXX the registers will have the following contents: BC: 000016....L }4 mmmm . and H'L'... DE and HL are swapped with the contents of register pairs B'C'.. 3-78 ..C D. HL: 333316...EXX - EXCHANGE REGISTER PAIRS AND ALTERNATE REGISTER PAIRS ZACP/ON C S F A c::r:::r::IIIJ Altemate Register Set B.f D·. F' I----+--.t .... B••C' { t . DE and HL contain 490116.. 5F0016 and 725116 respectively. and register pairs B'C DE.. mmmm + 1 mmmm+2 t ..t mmmm + 3 EXX 09 The contents of register pairs BC..... B'C': 490116. D'E': 5F0016. H'L' contain 000016... H'L': 725116 This instruction can be used to exchange register banks to provide very fast interrupt response times.........E·· H·• L Program Memory 09 mmmm A' SP PC IX IY I ...E H. D·E·.... DE: 10FF16.. Suppose register pairs BC....

.... memory refresh logic continues to operate...HALT S Z AC P/O N C FCIIIIIJ A S..t mmmm + 2 76 I I t .. mmmm+ 1 Program Memory mmmm mmmm+ 1 t .. No registers or statuses are affected: however.t mmmm + 3 76 When the HALT instruction is executed.L SP PC IX IV I R mmmm . HALT .C Data Memory D. 3-79 ......E H.. The CPU requ ires an interrupt or a reset to restart execution. program execution ceases...

1M 0 S

INTERRUPT MODE 0
C

Z AC PIO N

FO::C:O::O
A
B,C

Data
Memory

D.E
H,L

SP

PC
IX IY I

mmmm

- -. mmmm + 2

- .........
~

Program Memory

R

-.

r

ED
46

I -_ _~

I-_ _~

mmmm mmmm+ 1 mmmm + 2 mmmm + 3

IMO
'-..,,-'

ED 46

This instruction places the CPU in interrupt mode a In this mode. the Interrupting device will place an instruction on the Data Bus and the CPU will then execute that instruction No registers or statuses are affected

1M 1 -INTERRUPT MODE 1
1M 1
'-..,,-'

ED 56

This instruction places the CPU in interrupt mode 1 In this mode. the CPU responds to an interrupt by executing a restart (RST) to location 003816.

1M 2 -

INTERRUPT MODE 2

This instruction places the CPU in Interrupt mode 2 In this mode, the CPU performs an indirect call to any specified location in memory. A 16-bit address is formed using the contents of the Interrupt Vector (I) register for the upper eight bits, while the lower eight bits are supplied by the interrupting device. Refer to Chapter 12 for a full description of interrupt modes. No registers or statuses are affected by this instruction

--1M 2
ED 5E

3-80

IN A,(portl-INPUT TO ACCUMULATOR

s
F
A
B,C

Z Ac PIO N C

CIIIIIJ
mmmm

I

I/O port yy

t
I

j4--

Data Memory

D,E
H,L

SP
PC
IX

- .,

~mmm + 2

V

Program Memory

IV
I

I

DB
yy

R

I

mmmm mmmm+ 1 mmmm+2 mmmm+3

Load a byte of data into the Accumulator from the I/O port (identified by the second IN instruction object code byte) Suppose 3616 is held in the buffer of I/O port 1A16 After the instruction IN A,(1 AH) has executed, the Accumulator will contain 3616 The IN instruction does not affect any statuses Use of the IN instruction is very hardware dependent Valid I/O port addresses are determined by the way in which I/O logic has been implemented. It is also possible to design a microcomputer system that accesses external logic using memory reference instructions with specific memory addresses

--INA

(port)
'"-v-'

DB

yy

3-81

INC reg -INCREMENT REGISTER CONTENTS
S
F

Z AC

plo

N C

I:EIEIEIEI]D

Data Memory

A BC DE
H.L

~Co,,,,,,E.ofHA.or B, C. D,
Lis yy
mmmm
:-.0 -.~mmm

SP PC
IX

_/

+~ 1

Program Memory
OOxxx 100

IY
I R

I

mmmm

I

1-----1 mmmm + 1
mmmm+2 t - - - - - 1 mmmm + 3

INC reg

I~
00 xxx 100 000 001 010 all 100 101 111 for reg =8 for reg=C for reg=D forreg=E for reg =H for reg=L for reg=A

Add 1 to the contents of the specified register Suppose Register E contains A816 After execution of INC E Register E will contain A916

3-82

HL or SP ..isyyyy SP PC IX mmmm - I~mmm+v Program Memory IY I I R I mmmm mmmm+ 1 t .. INC IX nor INC IY affects any status flags This is a defect In the Z80 instruction set inherited from the 8080.C D.-.L Data Memory } Coo""" of DC. DE.INC rp INC IX INC IV S INCREMENT CONTENTS OF SPECIFIED REGISTER PAIR Z AC P/O N C FCIIII:IJ A B.E H...t mmmm + 2 ~----fmmmm + 3 OOxxOO 11 The illustration shows execution of INC rp ~ 0 0 xx 0011 rp rp rp rp 00 01 10 11 for for for for is is is is register pair BC register pair DE register pair HL Stack Pointer Add 1 to the 16-blt value contained in the specified register pair No status flags are affected Suppose the 0 and E registers contain 2F7 A16 After the instruction INC DE has executed...-- Add 1 to the 16-bit value contained in the IX register..-FD 23 Add 1 to the 16-bit value contained in the IY register... DEC IX and DEC IY. neither INC rp.. Just like the DEC rp.. INC IY . 3-83 . the D and E reg isters wi II contain 2F7B 16 INC IX DO 23 .-.

G INC (IX+disp) ~ Pqq + d )= 34 d m mmm m mmm+l m mmm+2 m mmm+3 The illustration shows execution of INC (IX+d): -.. 36 = 0011 001 1 o sets S to 0 Carry status not affected r 34 0 1 10 1 0 111 L d No.- FD 34 This instruction is identical to INC (IX+dispL except that it uses the IY register instead of the IX register../ ..INC (HL) .E H.. Suppose ppqq =400016 and memory location 400F16 contains 3616 After execution of the instruction INC (IX+OFH) memory location 400F 16 will contain 3716. set AC to a O¥ 0=0....- -... set Z to 0 No carry... set N to a --.-mo 'esult.L SP x X X X 0 []J]IEI]]]I] Data Memory C mmmm .. 3-84 ._- yy ppqq+d • Program Memory PC IX IY I R ppqq -- -~ • mmmm + 3 ..d DD 34 Add 1 to the contents of memory I"cation (specified by the sum of the contents of Register IX and the displacement value d).INCREMENT MEMORY CONTENTS INC (IX +disp) INC (lY+disp) S Z AC PIO N C F A B.. set P/O to ° INC (IY+disp) Addition instruction. • I DO -... yy+l ..C D. INC (HL) ~ Add 1 to the contents of memory location (specified by the contents of the HL register pair).

memory location 240016 will contain 1916. ~ . 3-85 . but is repeated until Register B=O... Suppose xx=0516.IND -INPUT TO MEMORY AND DECREMENT POINTER s F Z AC PIO N C C xx-1 cm::G:GIIIJ xx pp mmmm .-- the buffer of 1/0 port INDR -INPUT TO MEMORY AND DECREMENT POINTER UNTIL BYTE COUNTER IS ZERO --.-- INDR ED BA INDR is identical to IND. ppqq=240016.. and memory locations will have contents as follows: Location 2400 23FF 23FE Contents 17 16 59 16 AE16 This instruction is extremely useful for loading blocks of data from an input device into memory.r yy ~ I/O port yy A B. mmmm+'V I ED R I AA 1------1 ED AA Input from 1/0 port (addressed by Register C) to memory location (specified by HL) Decrement Registers Band HL.E H..C D.. The B register will contain 0416 and the HL reg ister pa ir 23FF 16 In IND --. and HL contains 240016 The following sequence of bytes is available at 1/0 port 1516: 17 16. Suppose Register B contains 0316..L • I I Data Memory - ppqq qq ~~Ppqq-1 • Program Memory mmm m mmm m+ 1 I -_ _---Immmm + 2 mmmm + 3 SP PC IX IV I . . 5916 and AE 16 After the execution of INDR the HL register pair will contain 23FD16 and Register B will contain zero. yy= 1516. Register C contains 1516... and 1916 is held 1516 After the instruction IND has executed.

... and HL contains 240016 The following sequence of bytes is available at I/O port 1516 1716.I mmmm + 3 ED A2 INI '-v-' ED A2 Input from I/O port (addressed by Register C) to memory location (specified by HL) Decrement Register B: increment register pair HL Suppose xx=:0516..E H..~ D. I/O port yy • I I Data Memory .INI-INPUT TO MEMORY AND INCREMENT POINTER s F A B.5916 and AE16 After the execution of INIR the HL register pair will contain 240316 and Register B will contain zero. and memory locations will have contents as follows: Location 2400 2401 2402 Contents 17 16 59 16 AE16 This instruction is extremely useful for loading blocks of data from a device into memory.L SP . memory location 240016 will contain 1916 The B register will contain 0416 and the HL register pair 240116 INIR - INPUT TO MEMORY AND INCREMENT POINTER UNTIL BYTE COUNTER IS ZERO INIR '-v-' EO B2 INIR is identical to INI.. Program Memory ppqq ....C Z AC PIO N C C xx-l ~ o:::o:::DJ xx pp • yy qq ~ .. but is repeated until Register 8=0... and 1916 is held in the buffer of I/O port 15 16 After the instruction INI has executed... Suppose Register B contains 0316. £Ppqq+l PC IX IY I mmmm ~ ~mmm+2 V I R I mmm m mmmm+ 1 t . ppqq=:240016.. yy=: 1516..I mmmm + 2 t . 3-86 .. Register C contains 1516.

(C) -INPUT TO REGISTER s F A Z AC PIO N C m:m::J]J]D \'y B. After the instruction IN D. making it pOSSible to extend the number of addressable 1/0 ports. the contents of Register B are placed on the top half of the Address Bus. H or L t --t Data I/O port vv I Memory PC IX IV I mmmm I I _ . D.C D. and Register C contains 3616. the 0 register will contain 4216 During the execution of the instruction.(C) has executed. Suppose 4216 is held In the buffer of 1/0 port 3616. C.\. E.::mmm ~ ~ 2 + Program Memory R mmmm mmmm + 1 mmmm+2 ~----fmmmm + 3 ED 01xxxOOO IN reg.IN reg. 3-87 . (C) K ED 01 xxx 000 000 001 010 011 100 101 111 110 for reg=B for reg =C for reg=D for reg=E for reg=H for reg=L for reg=A for setting of status flags without changing registers Load a byte of data into the specified register (reg) from the 1/0 port (identified by the contents of the C register).L SP ~Register A B.E H.

E H.JP label S JUMP TO THE INSTRUCTION IDENTIFIED IN THE OPERAND C Data Memory Z AC P/O N FCIIIIIJ A B. unless a Jump instruction somewhere else in the instruction sequence jumps to this instruction 3-88 . t C3 qq pp mmmm mmmm+ 1 mmmm+2 mmmm+3 -. The previous Program Counter contents are lost.'-v-' JP label C3 ppqq Load the contents of the Jump instruction object code second and third bytes into the Program Counter. In the following sequence JP AND NEXT 7FH NEXT CPL The CPL instruction will be executed after the JP instruction The AND instruction will never be executed..l SP PC IX IY I mmmm - r ppqq : ) Program Memory R I • I . this becomes the memory address for the next instruction to be executed.C O.

label instruction has executed. being the next sequential instruction. except that the jump will be performed only If the condition is satisfied: otherwise. label - JUMP TO ADDRESS IDENTIFIED IN THE OPERAND IF CONDITION IS SATISIFED JP condo label Kl 11 cc 010 ppqq I Condition NZ Z NC C PO PE P M Non-Zero Zero No Carry Carry Parity Odd Parity Even Sign Positive Sign Negative Relevant Flag Z Z C C 000 001 010 011 100 101 110 111 Pia Pia S S This instruction is identical to the JP instruction. if the condition is satisfied then the OR instruction will be executed If the condition IS not satisfied. IS executed 3-89 . the AND instruction. the Instruction sequentially followIng the JP condition instruction will be executed Consider the instruction sequence ---------'11 condition satisfied JP COND.LABEL condition not satisfied AND + 7CH LABEL OR B After the JP cond.JP condition.

The instruction sequence LD JP H.C Data D.-E9 The contents of the HL register pair are moved to the Program Counter: therefore.L pp mmmm qq SP PC IX IY I P JP (HL) Program Memory mmmm mmmm + . mmmm+2 J---~ mmmm + 3 ~_ _--1 R I I E9 The illustration shows execution of JP (HL): -..-' DD£9 This instruction is identical to the JP {HL) instruction.JP (HL) JP (IX) JP (IV) S JUMP TO ADDRESS SPECIFIED BV CONTENTS OF 16-BIT REGISTER Z Ac P!O N C FCIIIIIJ A S.. except that it uses the IX register 3-90 . if SUB executes without detecting error conditions.RETURN JP (IX) -...ADDR (HL) has exactly the same net effect as the single instruction JP ADDR Both specify that the Instruction with label ADDR is to be execu ted next The JP (HL) instruction is useful when you want to increment a return address for a subroutine that has multiple returns Consider the following call to subroutine SUB: CALL JP SUB ERR :CALL SUBROUTINE :ERROR RETURN :GOOD RETURN Using RET to return from SUB would return execution of JP ERR: therefore.E H. return as follows: POP INC INC INC JP HL HL HL HL {HL) :POP RETURN ADDRESS TO HL :ADD 3 TO RETURN ADDRESS . an implied addressing Jump is performed.

$+8 _---------'1 c=o 4000 4002 AND . the next instruction is executed In the following instruction sequence: JR C.$+8 instruction.. The AND instruction is executed if the Carry status equals 0 3-91 ..-' -. JR C. the OR instruction is executed if the Carry status equals 1.-' FD E9 This instruction is identical to the JP (HU instruction. except that it uses the IY register instead of the HL register pair.disp - JUMP RELATIVE TO CONTENTS OF PROGRAM COUNTER IF CARRY IS SET JR C.. disp '-.instead of the HL register pair. except that the jump is only executed if the Carry status equals 1: otherwise.- 38 dd-2 This instruction is identical to the JR disp instruction... JP (lY) '-. 7FH C=1 -~~4008 OR B After the JR (.

--..JR disp S JUMP RELATIVE TO PRESENT CONTENTS OF PROGRAM COUNTER C Z AC P/O N FCIIIIIJ A S. and has a range of -126 to + 129 bytes..18 dd-2 18 dd-2 mmmm mmmm+ .'mmmmD a. and 2. JR $+4 Result of this instruction is shown below: 3-92 . mmmm+2 mmmm+3 Add the contents of the JR instruction object code second byte. Load the sum into the Program Counter The jump is measured from the address of the instruction operation code.E H. the contents of the Program Counter.L SP PC IX IY I mmmm . The Assembler automatically adjusts for the twice-incremented Pc.~d-2)+2 Program Memory R I I 1 JR disp --. The following assembly language statement is used to Jump four steps forward from address 400016.C Data Memory D.

except that the jump is only executed if the Zero status equals 0: otherwise..' -v-' 20 dd-2 This instruction is identical to the JR disp instruction.0:.0:. the OR instruction is executed if the Carry status equals 1 The ADD instruction is executed if the Carry status equals O. In the following instruction sequence: I _--4.J.$+6 instruction.disp-JUMP RELATIVE TO CONTENTS OF PROGRAM COUNTER IF ZERO FLAG IS RESET JR NZ.. 3-93 .---II~ 4000 I 4001 I c=o I C~1 4002 I 4003 JR 4005 OR After the JR NC. except that the Jump is only executed if the Carry status equals 0: otherwise.disp '-. The AND instruction is executed if the Zero status equals 1.-.. the next instruction is executed. the OR instruction is executed if the Zero status equals O..:..0----::.' NZ...$-3 instruction. JR NZ...7FH .disp - JUMP RELATIVE TO CONTENTS OF PROGRAM COUNTER IF CARRY FLAG IS RESET JR NC....R-.JR NC..$+6 z=o :~~~ AND OR t z=~FH B 4005 '---'-4006 After the JR NZ... In the following instruction sequence I ADD I A.. the next instruction is executed.disp 30 ----- dd-2 This instruction is identical to the JR disp instruction.

-.........t l r ...0. the OR instruction is executed if the Zero status equals 1 The AND instruction is executed if the Zero status equals 0 LD A.J.MOVE CONTENTS OF INTERRUPT VECTOR OR LD A.---28 dd-2 This instruction is identical to the JR disp instruction. the next instruction is executed In the following instruction sequence I JR Z.-_ _ 4..JR l. The value of the interrupt flip-flop will appear In the Parity/Overflow flag.. and interrupts are disabled After execution of LD A. Suppose the Interrupt Vector register contains 7F16.0. 3-94 .I Register A will contain 7F16. and P/O will be 0 LD A.I: LD A...R -.....disp .I mmmm + 3 ED 57 The illustration shows execution of LD A..disp - JUMP RELATIVE TO CONTENTS OF PROGRAM COUNTER IF ZERO FLAG IS SET --...I ~ ED 57 Move the contents of the Interrupt Vector register to the Accumulator.. except that the Jump is only executed if the Zero status equals 1.. otherwise....R_ .....$+6 instruction.R REFRESH REGISTER TO ACCUMULATOR S Z AC Pia N C Data F~ A B.I.E H.0_--.. 1 4002 4004 4005 ' .4006 Z=l Z....L SP PC IX IY I mmmm -~ xx ~mmm+2 V Pro~ram Memory R I I mmmm mmmm + 1 mmmm + 2 t .. $+6 7FH z=o AND: t OR B After the JR Z..' ED 5F Move the contents of the Refresh register to the Accumulator.. and reflect interrupt enable status in Parity/Overflow flag.C xx D..

The instruction LD A.. 3-95 .C D.--.--3A ppqq Load the contents of the memory byte (addressed directly by the second and third bytes of the LD A.(Iabell is equivalent to the two instructions LD LD HL...label..(addrl instruction object code) into the Accumulator Suppose memory byte 084A 16 contains 2016 After the instruction label EQU 084AH LD A(label) has executed. the LD A(label) instruction is preferred: it uses one instruction and three object program bytes to do what the LD HL.label.(HL} When you are loading a single value from memory.. LD A (HL} combination does in two instructions and four object program bytes.(addr) S Z ACP/ON LOAD ACCUMULATOR FROM MEMORY USING DIRECT ADDRESSING C Data Memory F D:IIIIJ yy A yy ppqq B. the Accumulator will contain 2016 Remember that EQU is an assembler directive rather than an instruction: It tells the Assembler to use the 16-bit value 084A16 wherever the label appears. Also..--.L SP PC IX IV I R .label A. which LD A (label) does not.I' mmmm mmmm+3 ...E H.LD A. Program Memory I I I mmmm mmmm+ 1 PP mmmm +2 't----'--'-----1 mmmm + 3 3A qq LD A (addr) --.. the LD HL. LD A (HLI combination uses the Hand L registers.

(rp) and LD rp..C yy Data Memory } ..... the LD A. and memory byte 084A 16 contains 3A 16 After the instruction has executed. Suppose the B register contains 0816.. since the LD rp.E H. the Accumulator will contain 3A16 Normally..data instruction loads a 16-bit address into the BC or DE registers as follows: 3-96 .mmm.data will be used together.t mmmm + 3 OOOx1010 LD A(rp) :Ilw o if LD A(BC) LD LD BC.L SP PC IX IY mmmm C:--:-::.1 .(rp) -LOAD ACCUMULATOR FROM MEMORY LOCATION ADDRESSED BY REGISTER PAIR S Z ACP/0N C FCIIIIIJ A B. ~ l I yy ppqq Program Memory ..084AH A(BCI register pair=BC 1 if register pair=DE Load the contents of the memory byte (addressed by the BC or DE register pair) Into the Accumu lator. . the C register contains 4A16. BC or DE contain ppqq D.LD A... I R I mmmm mmmm+ 1 mmmm+2 I .

"" A. Data Memory R...I mmmm + 2 1-_ _--1 mmmm + 3 01dddsss III 01 ddd sss '-v-' 000 001 010 all 100 101 111 for for for for for for for dst dst dst dst dst dst dst or or or or or or or src=B src=C src=D src=E src=H src=L src=A The contents of any designated register are loaded into any other register For example LD A.L }l tD...l Register A..E H.. C D. B.. src mmmm+ 1 Program Memory R I I mmmm mmmm+ 1 I . LD dst.C D. B. since the C register has been specified as both the source and the destination 3-97 . E.H. H..S loads the contents of Register B into Register A. C. L ~ SP PC IX IV I mmmm ..LD dst. LD LD loads the contents of Register D into Register L LD C....E...C does nothing.src S MOVE CONTENTS OF SOURCE REGISTER TO DESTINATION REGISTER C Z AC PIO N FDIIIIJ A B.

. (addr) LOAD REGISTER PAIR OR INDEX REGISTER FROM MEMORY USING DIRECT ADDRESSING S Z AC P/O N C FCIIIIIJ A Data Memory B. LD lX. the HL register pair will contain 12AD16..--.L yy • mmmm I xx ..:.(addr) rp.(addr) 3-98 ...E H. --. . Suppose memory location 400416 contains AD16 and memory location 400516 contains 1216 After the instruction LD HL(4004H) has executed.~ ".LO LD LD LD HL.(addr) IY...---.C D.-..-DD 2A ppqq Load IX register from directly addressed memory.-.2A ppqq Load the HL register pair from directly addressed memory location. (49FFH) has executed.. After the instruction LD DE. the DE register pair will contain 33BE16. LD HL..mmm +3 Xl( ppqq ppQ1 yV SP PC IX IY Program Memory I R 2A I 1 ~ QQ pp mmm m mmmm + 1 mmmm+2 mmmm+3 The illustration shows execution of LD HL(ppqq): --.- 00 01 10 11 for for for for rp rp rp rp is is is is register pair Be register pair DE register pair HL Stack Pointer Load register pair from directly addressed memory.addr 1fL ED 01 dd 1011 ppqq --. Suppose memory location 49FF16 contains BE16 and memory location 4A0016 contains 3316.. (addr) IX.

the Refresh register will contain 7F 16· LO I. After the instruction LO IX.C D.. Suppose the Accumulator contains 7F16· After the instruction LO R. the IX register will contain 56FF16· ---...A has executed.(addrl LD I.A '-'v-' J-----1 mmmm + 2 mmmm+3 ED 47 Load Interrupt Vector register from Accumulator..A '"-v-' ED 4F Load Refresh register from Accumulator.1 The illustration shows execution of LD R.(D111H) has executed... Affects IY register instead of IX. Otherwise identical to LO IX(addr)..A LD R. LO IY.Suppose memory location 011116 contains FF16 and memory location 011216 contains 5616.-FO 2A ppqq Load IY register from directly addressed memory.---.-. 3-99 ..L SP PC IX IY IV R JJ' mmmm -- mmmm + 2 Program Memory I I ED 4F mmmm mmmm+ 1 .A 5 F LOAD INTERRUPT VECTOR OR REFRESH REGISTER FROM ACCUMULATOR C Data Z AC P/O N o::::r::r:IIJ xx A B...A LO R.E H.

..data S Z AC P/O N LOAD IMMEDIATE INTO REGISTER C Data F A o::::I::IIIJ } -0.C D.... 3-100 .LD reg... When the instruction LD A. Program Memory I I OOxxx 11 0 mmmm YY I .. B..- 000 001 010 all 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Load the contents of the second object code byte into one of the registers.. D.2AH has executed.E H.I mmmm + 3 mmmm+ 1 mmmm+2 00 xxx 110 yy -...L SP PC IX IV I R - -~ ~ mmmm + 2 .. Register A...... C. 2A16 is loaded into the Accumulator. H or L mmmm B. E..

data S LOAD 16 BITS OF DATA IMMEDIATE INTO REGISTER Z Ac P/O N C FD:IIIIJ A Data B. After the instruction has executed.""".data: _Jt1 -00 xx 0001 ppqq 00 01 10 11 for for for for rp rp rp rp is is is is LD SP.E H.data LD IX... mmmm+3 ~ Program Memory emorY I OOxxOOOl I \ qq pp mmmm mmmm+ 1 mmmm+2 mmmm+3 The illustration shows execution of LD rp.032AH LD IX..data instruction is equivalent to two LD reg...eC'D< mmmm HL or SP.data LD IV. data -..C D. FD 21 ppqq Load the contents of the second and third object code bytes into the Index Register IY.03H L.DD 21 ppqq Load the contents of the second and third object code bytes into the Index register IX..2AH HL.- 3-101 . data -- ---- LD IY. Notice that the LD rp...217AH register pair Be register pair DE register pair HL Stack Pointer Load the contents of the second and third object code bytes into the selected register pair.data instructions For example: LD is equivalent to LD LD H. Load ppqq into ::cted destination PC IX IV I R .L SP y.LD rp. the Stack Pointer will contain 217A 16· ---...

(lX+displ. (Iv + disp) ~J FD 01 xxx 110 d l"------I. Olxxx110· d mmm m mmm m+ 1 mmm m+2 mmm m+3 The illustration shows execution of LD reg.. (IX +disp) LD reg.(IX+disp) LD reg.E H. Program Memory R I I DO ~pqq+d)-. (HL) . ' " D. LD reg.L SP -. Register B will contain FF16."" A.LOAD REGISTER FROM MEMORY LD reg.C yy D. same as for LD reg. H or L ~ S Z AC P/O N C Data Memory A B....-Bog.. 3-102 .. (lY +disp) F o::r::::r:r::o } ... B.(IX+disp) This instruction is identical to LD reg.LD reg. +d PC IX IY I mmmm ppqq - mmmm+3 . E. except that it uses the IV register instead of the IX register. (IX + disp) ~J DD 01 xxx 110 d 000 001 010 011 100 101 111 for for for for for for for reg=B reg =C reg=D reg=E reg=H reg=L reg=A Load specified register from memory location (specified by the sum of the contents of the IX register and the displacement digit d) Suppose ppqq=400416 and memory location 401016 contains FF16 After the instruction LD B(IX+OCH) has executed. C ...

.. ~ mmmm+ 1 Program Memory mmmm mmmm+ 1 t .HL: LD SP. ~same as for LD reg.C D. LD reg..m -.IV S Z MOVE CONTENTS OF HL OR INDEX REGISTER TO STACK POINTER Ac P/O N C FCIIIID A Data B.IX LD SP.IX ~ DO F9 Load contents of Index Register IX into Stack Pointer LD SP..L pp mmmm qq SP PC IX IY I ::>.lY ~ FD F9 Load contents of Index Register IY into Stack Pointer. 3-103 .E H.... LD SP .f mmmm + 2 t -_ _--fmmmm + 3 I I F9 R The illustration shows execution of LD SP......l..OX+disp) Load specified register from memory location (specified by the contents of the HL register pair).. the Stack Pointer will contain 083F16 LD SP.HL has executed.HL LD SP.HL ~ F9 Load contents of HL into Stack Pointer Suppose pp=0816 and qq=3F16· After the instruction LD SP..(HU 0 1xxxll0 .

Also. while the LD (labell. Suppose the Accumulator contains 3A16 After the instruction label EQU 084AH LD (label).A When you are storing a single data value in memory.C D. The instruction LD (addrl. the LD Oabell.A combination does in two instructions and four object program bytes. Remember that EQU is an assembler directive rather than an instructio~ it tells the Assembler to use the 16-bit value 084AH whenever the word "label" appears. the LD H(labell. LD (HL). LD (HL).E H. memory byte 084A16 will contain 3A16.label LD (HL).A is equivalent to the two instructions LD H.L SP PC cr:IIIIJ yy Data Memory ~mmm+v I yy ppqq mmmm IX IY I Program Memory I R I mmmm mmmm+ 1 mmmm+2 't----'-'----1 mmmm + 3 32 qq pp tY 3 2 ppqq Store the Accumulator contents in the memory byte addressed directly by the second and th ird bytes of the LD (addrLA instruction object code.A instruction is preferred because it uses one instruction and three object program bytes to do what the LD H(label). 3-104 .A S Z ACP/ON STORE ACCUMULATOR IN MEMORY USING DIRECT ADDRESSING C F A S.A has executed.LD (addr).A instruction does not.A combination uses the Hand L registers.

memory byte 084A16 will contain 2A16 Memory byte 084B16 will contain3C16 Remember that EOU is an assembler directive rather than an instruction.BC has executed.lD (addr).. Suppose the BC register pair contains 3C2A16.xy ADDRESSING S Z ACP/ON C Data Memory F A CIIIIlJ xx yy B.Hl.. -- Program Memory I ED 01010011 R I qq pp mmmm mmmm+ 1 mmmm +2 mmmm+3 The illustration shows execution of LD (ppqql.rp REGISTER IN MEMORY USING DIRECT lD (addr)...HL 3·105 ..C D...E H..L SP xx . ~ 22 ppqq This is a three-byte version of LD (addrl.... it tells the Assembler to use the 16-bit value 084A16 whenever the word "label" appears. LD (addrl. 00 01 10 11 for for for for rp rp rp rp is is is is register pair BC register pair DE register pair HL Stack Pointer Store the contents of the specified register pair in memory.DE: ~ ED 01 xx 0011 ppqq . ppqq ~ ppqq + 1 " mmmm I I yy PC IX IY mmmm+4 .. After the instruction label EQU 084AH LD (labell. The high-order byte is written into the next sequential memory location. The third and fourth object code bytes give the address of the memory location where the low-order byte is to be written.rp which directly specifies HL as the source register pair..STORE REGISTER PAIR OR INDEX lD (addr) .

1X DO 22 ppqq Store the contents of Index register IX in memory. except that it uses the IY register instead of the IX register. 3-106 .lX instruction. ~ FD 22 ppqq This instruction is identical to the LD (addrl. The third and fourth object code bytes give the address of the memory location when'! the low-order byte is to be written The high-order byte is written into the next sequential memory location.

--. LD (HL).. memory location 540916 will contain FA16 ----FD 36 LD (IY+disp).-----.data -.-. ----... LD (IX+disp).L SP PC IX IY I mmmm ppqq ~mmm+~ ~pqq+d~.data -..d xx DD 36 Load Immediate into the Memory location designated by base relative addressing..LD (HL)..data.. Suppose ppqq=540016 After the instruction LD (IX+9).-' d xx This instruction is identical to LD (IX+disp).-._ Program Memory I DO 36 d '-- R I xx mmm m mmm m+ 1 mmmm+2 mmm m+3 The illustration shows execution of LD (IX+&xx: -.data -.FAH has executed.data -LOAD IMMEDIATE INTO MEMORY LD (Ix +disp) .".-' 36 xx Load Immediate into the Memory location (specified by the contents of the HL register pair) The Load Immediate into Memory instructions are used much less than the Load Immediate into Register instructions 3-107 . but uses the IY register instead of the IX register.data S Z AC P/O N C F A CIIIIIJ ~ Data Memory xx ppqq +d I B..C D.data LD (lY+disp) .".E H.

reg Load memory location (specified by the sum of the contents of the IX register and the 3-108 .C D.E H. memory location 450016 will contain F916. D.reg S ZACP/ON C Data F A B.C has executed. l~ DDOll10xxxa T ~ same as for LD (HU.LOAD MEMORY FROM REGISTER LD (lX+disp). qq SP 1 PC IX IY I ~mmm+~ Program Memory R I I m mmm mm mm+l mmmm+2 1------1 mmmm + 3 01110xxx The illus1ration shows execution of LD (HU.L o::::r::rIIl ~isyy pp mmmm Contents of A.LD (HL).reg: 'II 01110xxx 000 001 010 011 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Load memory location (specified by the contents of the HL register pair) from specified register.reg . H or L yy c. Suppose ppqq=450016 and Register C contains F916 After the instruction LD (HU. E. B.reg LD (ly +disp).

A S LOAD ACCUMULATOR INTO THE MEMORY LOCATION ADDRESSED BY REGISTER PAIR Data Memory Z AC plO N C F A B. (HU.C co:::IIIJ yy . Suppose the BC register pair contains 084A16 and the Accumulator contains 3A16 After the instruction has executed. :LY FD01110xxxa LD (lY +dispLreg T... } • D.. since the LD rp....084AH LD (BCl.displacement value d) from specified register. except that it uses the IY register instead of the IX register. I -- + 1 Program Memory 1 OOOxOO10 mmmm mmmm+ 1 mmmm+2 t------t mmmm + 3 I m '-' LD (BCLA LD BC. memory byte 084A 16 will contain 3A 16· The LD (rp). LD (rp).E H.t l.L SP Be or DE contain ppr q I yy ppqq PC IX IV I R mmmm - -..data will normally be used together.A o if register pair=BC 1 if register pair=DE Store the Accumulator in the memory byte addressed by the BC or DE register pair. same as for LD ..data instruction loads a 16-bit address into the BC or DE registers as follows: 3-109 . --" mmmm .A and LD rp.reg This instruction is identical to LD (IX+dispLreg.A LD (rpl.

Decrement contents of register pairs BC.. Suppose register pair BC contains 004F16... DECREMENT DESTINATION AND SOURCE ADDRESSES ....u:...... M": t~t ~_ _.LDD - TRANSFER DATA BETWEEN MEMORY LOCATIONS.q:....p ss . DE.Lt-_ _..:u:..---~~.:...--~_--It--~::-:---..:P.. --LDD ED A8 3-110 . q. DE will contain 454416..... Iy I A -I ....- ~===~~rrss ----..C IA .... reset otherwise Z AC P/G N C t Data FaTID:§!] B. memory location 454516 will contain 1816... register pair BC will contain 004E16.. After the instruction LDD has executed.-_ _ rrss.... PC IX ~~=----mmmm .-----. ...E rr ..1 Sp ........ .... and memory location 201216 contains 1816.. and HL. and HL will contain 201116.. t::E::j • ----Program Memory ~ ppqq-1 ppqq • D. HL contains 201216............ DE contains 454516..~A""8-..I! Set if BC-1 5 0... ~..:.-"'oo... mmmm + 1 1-------41 mmmm + 3 ED mmmm mmmm+2 Transfer a byte of data from memory location addressed by the HL register pair to memory location addressed by the DE register pair.

Suppose we have the following contents in memory and register pairs: Register/Contents HL --LDDR LDDR Location/Contents DE BC After execution of 201216 454516 000316 201216 1816 201116 AA16 2010162516 register pairs and memory locations will have the following contents: Register/Contents HL Location/Contents Location/Contents DE BC 200916 454216 000016 201216 201116 201016 1B16 AA16 2516 454516 454416 454316 1816 AA16 2516 This instruction is extremely useful for transferring blocks of data from one area of memory to another. DECREMENT DESTINATION AND SOURCE ADDRESSES ED B8 Th is instruction is identical to LDD.LDDR - TRANSFER DATA BETWEEN MEMORY LOCATIONS UNTIL BYTE COUNTER IS ZERO. except that it is repeated until the BC register pair contains zero After each data transfer. 3-111 . interrupts will be recognized and two refresh cycles will be executed.

C D. Increment contents of register pairs HL and DE Decrement contents of the BC register pair Suppose register pair BC contains 004F16. HL contains 201216_ and memory location 201216 contains 1816._ _-1 mmmm + 2 . DE contains 454516.L uu ss QQ mmmm Program Memory ED SP PC IX IY I R mmmm AO mmmm+ 1 . reset otherwise S F Z ACP'O N C c:::c:I:§I]IIJ tt rr pp A B. register pair BC will contain 004E16..._ _-1 mmmm + 3 LDI ~ ED AO Transfer a byte of data from memory location addressed by the HL register pair to memory location addressed by the DE register pair.. DE will contain 454616_ and HL will contain 201316 3-112 . memory location 454516 will contain 1816. INCREMENT DESTINATION AND SOURCE ADDRESSES ~ Set if BC-1 0.E ... After the instruction LDI has executed.LDI - TRANSFER DATA BETWEEN MEMORY LOCATIONS....

.. After each data transfer.44 Negate contents of Accumulator. interrupts will be recognized and two refresh cycles will be executed Suppose we have the following contents in memory and register pairs: Register/Contents HL OE BC After execution of LDIR register pairs and memory will have the following contents: Register/Contents HL OE BC 201516 454816 000016 Location/Contents 2012161816 201316 C016 201416 F016 Location/Contents 4545161816 454616 C016 454716 F016 201216 454516 000316 Location/Contents 201216 1816 201316 CD16 201416 F016 This instruction is extremely useful for transferring blocks of data from one area of memory to another.E H... INCREMENT DESTINATION AND SOURCE ADDRESSES ED BO LOIR -... NEG S NEGATE CONTENTS OF ACCUMULATOR ZACP/ON C Data F~ A B.. After the instruction NEG has executed.- This instruction is identical to LDI. except that it is repeated until the BC register pair contains zero.L xx __ ~" xx +' ~ SP PC IX mmmm "mmmm + 2 .. Program Memory IV I R I I mmmm mmmm+ 1 1-----1 mmmm + 2 I . This is the same as subtracting contents of the Accumulator from zero.. BOH will be left unchanged Suppose xx=5A16.t mmmm + 3 . The result is the two's complement...LDIR-TRANSFER DATA BETWEEN MEMORY LOCATIONS UNTIL BYTE COUNTER IS ZERO. the Accumulator will contain A616· 5A 01 01 Two's complement = 1 0 1 0 1 01 0 0 1 10 3-113 .ED .C D..

L SP PC IX IY I mmmm _ --·(~"mmm +~ ~ Program Memory R I I 00 mmmm 1--_ _--1mmmm + 1 1--_ _--1mmmm + 2 t-_ _--fmmmm + 3 This is a one-byte instruction which performs no operation. Each NOP instruction adds four clock cycles to a delay.C Data D. --NOP 00 NOP is not a very useful or frequently used instruction.E H. The NOP instruction allows you to give a label to an object program byte: HERE NOP To fine-tune delay times. except that the Program Counter is incremented and memory refresh continues. This instruction is present for several reasons: 1) 2) 3) A program error that fetches an object code from non-existent memory will fetch 00. 3-114 .NOP S NO OPERATION Z AC PIO N C FCIID:D A B. It is a good idea to ensure that the most common program error will do nothing.

the Accumulator will contain 7E16· 3A 001 1 0111 1 01 0 1 10 0 1110 LSiX 1 bits.L SP PC IX IV I mmmm '" .. mmmm+2 Program Memory F6 I R I yy mmmm mmmm+ 1 mmmm+2 mmmm+3 OR F6 data yy OR the Accumulator with the contents of the second instruction object code byte...OR data S OR IMMEDIATE WITH ACCUMULATOR Data Memory ZAcP/ON C F~ A S. 3-115 .. the instruction OR 80H will unconditionally set the high-order Accumulator bit to 1. Suppose xx=3A 16. After the instruction OR 7CH has executed.... For example. it is often used to turn bits "on".. set PIO to 1 7C = 0 1 1 1 o sets S to O~ L Non-zero resu It set Z to 0 This is a routine logical instruction.C xx --' OR yy~ ..E H.:x D.

the Accumulator will contain EB16 E3 A8 = ------ 1 1 10 101 0 1 1 10 001 1 1000 10 1 1 sets S to 1...J L L Six 1 bits. } -~ xx OR yy --.C D. set Z to 0 3-116 .. -- mmmm + 1 Program Memory I R I I 10110xxx mmmm 1-------1 mmmm + 1 mmmm+2 I . After the instruction OR E has executed. set PIO to 1 Non-zero resu It. Co"JOfA is yy B.. Store the result in the Accumulator. H or L... Data Memory . H or L SP PC IX IY mmmm -.t mmmm + 3 --OR reg 10110 -.. D.. D. Suppose xx=E316 and Register E contains A8l6. C.OR reg S F OR REGISTER WITH ACCUMULATOR C 2 AC Pia N ~ xx A B..xxx 000 for reg=B 001 010 011 100 101 111 for for for for for for reg=C reg=D reg=E reg=H reg=L reg=A Logically OR the contents of the Accumulator with the contents of Register A B.E H.c... E.L r. E.

C -..OR (HL) .--... yy P qq D.E H. set Z to 0 OR (IX+disp) -. 3-117 .J 00 1 1 1000 1011 LSix 1 bits..xx OR yy~ . the Accumulator will contain EB 16· E3 AS = 1 110 1010 1110 1 sets S to 1.L SP qQ f ~mmm+~ Program Memory PC IX IY I I B6 R I 1-------.. ppqq=400016.. and memory location 400016 contains A816' After the instruction OR (HU has executed...OR MEMORY WITH ACCUMULATOR OR (IX+disp) OR (IY+disp) S Z AC PIO N C F ~ xx pp mmmm Data Memory A B. except that it uses the IY register instead of the IX register.-.d This instruction is identical to OR (IX+displ.DD B6 d OR contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) with the AccumulatoL OR (IY+disp) FD 86 --- -.. set PIO to 1 LNon-zero result. The illustration shows execution of OR (HU: mmmm mmmm+1 mmmm+2 mmmm + 3 OR (HU ~ 86 OR contents of memory location (specified by the contents of the HL register pair) with the AccumulatoL Suppose xx=E316..

- 000 001 010 all 100 101 111 for reg=B for reg=C for reg=D forreg=E for reg=H for reg=L for reg=A Suppose yy= 1F16 and the contents of Hare AA 16 After the execution of OUT (C)...H AA16 will be in the buffer of I/O port 1F16' 3-118 .E H.OUT (C) . H or LB SP PC IX IV I mmmm " mmmm+ 2 Program Memory mmmm mmmm + 1 mmmm+2 t ... + Data Memory vv }--""...C D.reg 5 OUTPUT FROM REGISTER Z AC PIO N C F A B. E.L CIIIIIJ I I - I/O port vv I c..1 mmmm + 3 ED 01xxxOO1 I R I 1)[ ED 01 xxx 001 -...J" .. D..

and memory location 500016 contains 7716 After the instruction OUTD has executed. DECREMENT ADDRESS xx-1 s F A B. Register C contains FF 16. Register 8 will contain zero. but is repeated until Register B contains O. CONTINUE UNTIL REGISTER 8=0 ---. ppqq=500016. 1816. This instruction is very useful for transferring blocks of data from memory to output devices...L I pp I mmmm SP PC IX IV I -- ~ppqq-1 ~ • + I Data Memory ppqq ~~ r--.OUTD - OUTPUT FROM MEMORY.J' ~ ~mmm+2 Program Memory m mmm m mmm+ 1 mmmm+2 t . Registers Band HL are decremented. Suppose xx=OA16. .. and HL contains 500016 Memory locations 4FFE16 through 500016 contain: Location/C ontents 4FFE16 4FFF16 5000 16 After execution of OTDR register pair HL will contain 4FFD16. Suppose Reg ister B contains 0316. The B register will contain 0916. CA16 1816 F116 OTDR 3-119 . and the sequence F116.t mmmm + 3 I ED R I AS OUTD ~ ED AB Output from memory location specified by HL to I/O port addressed by Register C..E H.-ED 88 OTDR is identical to aUTO. DECREMENT ADDRESS. CA16 will have been written to 1/0 port FF16.C Z AC P/O N C ~ I xx • qq ~ Vy ~ ~ I/O port yy D. 7716 will be held in the buffer of I/O port FF16. and the HL register pair 4FFF16· OTDR - OUTPUT FROM MEMORY. . yy=FF16......

..l qq mmmm SP PC IX IY I ~ .- OUTI OTIR-OUTPUT FROM MEMORY.. INCREMENT ADDRESS s F A S. Suppose xx=OA 16.t ! mmmm + 3 ED A3 Output from memory location specified by HL to I/O port addressed by Register C Register B is decremented and the HL register pair is incremented. 1B16' B116 and AD16 will have been written to I/O port FF16 This instruction is very useful for transferring blocks of data from memory to an output device.E H.OUTPUT FROM MEMORY. except that it is repeated until Register B contains 0 Suppose Register B contains 0416. 7716 wi II be held in the buffer of I/O port FF16 The B register will contain 0916 and the HL register pair will contain 500116.r + ppqq+ 1 Program Memory -- ~mmm+2 R I ED A3 I mmmm mmmm+1 mmmm+2 I . and memory location 500016 contains 7716 After the instruction OUTI has executed. CA16 1B16 81 16 AD16 --OTIR ED B3 3-120 . INCREMENT ADDRESS.. -...OUTI. Register C contains FF 16.C Z Ac Pia N C GEGEIIJ xx pp C J xx-1 II ~ yy I/O port yy + J Data Memory ppqq D. and HL contains 500016 Memory locations 500016 through 500316 contain: Location/Contents 5000 16 5001 16 5002 16 5003 16 After execution of OTIR register pair HL will contain 500416. CONTINUE UNTIL REGISTER 8=0 OTIR is identical to OUTI. yy=FF16' ppqq =500016. Register B will contain zero and the sequence CA16..

C D.OUTPUT FROM ACCUMULATOR s F Z AC PIO N C CIIIID I I/O port yy ~ + Data Memory A B. After the instruction OUT (lAHl. Valid I/O port addresses are determined by the way in which I/O logic has been implemented.... Program Memory SP PC IX IV I R .L + mmmm+2 . 3616 will be in the buffer of I/O port 1A16 The OUT instruction does not affect any statuses Use of the OUT instruction is very hardware-dependent.OUT (port).t' mmmm I I 03 '- mmmm yy mmmm+ 1 mmmm+2 mmmm+3 U 03 yy Output the contents of the Accumulator to the I/O port identified by the second OUT instruction object code byte Su ppose 3616 is held in the Accumu lator..E H...A ..A has executed. It is also possible to design a microcomputer system that accesses external logic using memory reference instructions with specific memory addresses OUT instructions are frequently used in special ways to control microcomputer logic external to the CPU 3-121 .

the Carry status will be set to 1 and other statuses will be cleared... The POP instruction is most frequently used to restore register and status contents which have been saved on the stack: for example. POP IX ~ DD E1 POP the two top stack bytes into the IX register POP IY -.POP rp POP IX POPIY S READ FROM THE TOP OF THE STACK Z AC Pia N C F A S.. while servicing an interrupt.L ~ :.(-SSSS+2 ssss mmmm • I qq pp SSSS SSSS + 1 SSSS + 2 SP PC IX IY I' ~-" -immmm + 1 /7 - -- Program Memory I 11000001 R I mmmm mmmm+ 1 .. Execution of the instruction POP AF loads 01 into the status flags and 2A16 into the Accumulator Thus..C D:IIIIJ Data Memory D_E H..._ _~mmmm+2 ..Execution of POP HL loads 01 16 into the L register and 2A16 into the H register. 3-122 ...FD El POP the two top stack bytes into the IY register.._ _--1mmmm + 3 The Illustration shows execution of POP BC: POP rp lZ11 xx 0001 00 01 10 11 for for for for rp rp rp rp is is is is reg ister register register register pair pair pair pair BC DE HL A and F POP the two top stack bytes into the designated register pair_ Suppose qq=0116 and pp=2A16..

for example. before servicing an interrupt 3-123 . PUSH IX ~ DO E5 PUSH the contents of the IX register onto the top of the stack LK 11 -.L ssss-2 ssss-1 ssss SP SSSS PC IX IY I ... then FF16 onto the top of the stack.E H. The PUSH instruction IS most frequently used to save register and status contents. LsSSS-2 ) // mmmm ppqq I ~mmm+v Program Memory mmmm mmmm+ 1 mmmm+2 t . Suppose the IY register contains 45FF16' Execution of the instruction PUSH IY loads 4516..00 01 10 11 xx 0101 rp rp rp rp for for for for is is is is register register register register pair Be pair DE pair HL pair A and F PUSH contents of designated register pair onto the top of the stack Execution of the instruction PUSH AF loads the Accumulator and then the status flags onto the top of the stack.PUSH rp PUSH IX PUSHIY S WRITE TO THE TOP OF THE STACK Z AC Pia N C FCIIIIIJ A Data Memory ----I I qq pp B..C D..1 mmmm + 3 R I FD E5 The illustration shows execution of PUSH IY PUSH IY ~ FD E5 PUSH the contents of the IY register onto the top of the stack.

L SP T PC IX IV I R mmmm mmmm+2 . 0 ) Program D..bbb xxx 000 000 001 001 010 010 Register B a 1 2 C D 3 4 5 6 7 Reset I ndicated bit within specified register.. bit 6 in Register H will be reset (Bit a is the least significant bit) 3-124 .reg S RESET INDICATED REGISTER BIT C Data FCI:IJIIJ A B..H has executed...t mmmm + 3 ~l\ CB 10 bbb xxx - Bit -. mmmm+2 t .RES b...-..& c ... After the instruction all all 100 100 101 101 110 111 111 E H L A RES 6... Memory CB 10bbbllllll mmmm I I mmmm + ..E H.C Z AC Pia N Memory yyyyyyyy ...

0 T ~ yyyyyyyy ppqq+ d a Program Memory H.RESET BIT b OF INDICATED MEMORY POSITION RES b. Bit a is the least significant bit.(IX+7) has executed..L $P PC IX IV '...C D.. (lY +disp) F o:r:r::r:o 5 Z AC P/O N C mmmm ppqq Data Memory A B. a is execution of SET ~ DD CB d 10 bbb 110 bbb 000 001 010 011 100 101 110 111 Bit Reset a 1 2 3 4 5 6 7 Reset ind icated bit within memory location indicated by the sum of Index Register IX and d.{IX+disp) RES b. except that it uses the IY register instead . bit 0 in memory location 411716 will be O..(IX+disp). ~ --.mmm+4 I R I I 0 1 pqq + d ) : : : mmm m mmmm+1 mmmm+2 d 10bbb110 mmm m+3 DD CB mmm m+4 The illustration shows execution of SET b. Bit b.(IX+disp).{HL) .3-125 FD CB d 10 bbb 110 bbb is the same as in RES b.E c .RES b.. Suppose IX contains 411016 After the instruction RES 0.. (IX+disp).(IX+disp) This instruction is identical to RES b.

and causes execution to return to the calling program.(IX+disp) Reset indicated bit within memory location indicated by HL.(HL) bit 7 in memory location 444416 will be 0 RET S Z F A S.of the IX register RES b. Suppose HL contains 444416· After execution of RES 7. 3-126 . to add ress the new top of stack.E H.' 2 I R I L( RET ppqq r- Program Memory mmmm mmmm+ 1 mmmm+2 t-----4 mmmm + 3 C9 C9 Move the contents of the top two stack bytes to the Program Counter: these two bytes provide the address of the next instruction to be executed.. Increment the Stack Pointer by 2. Previous Program Counter contents are lost. .. Every subroutine must contain at least one Return (or conditional Return) instruction: this is the last instruction executed within the subroutine.C D.(HL) III CB10bbb110 bbb is the same as in RES b.. I Data Memory qq pp xxxx xxxx + 1 xxxx + 2 SP PC IX IY I .-Il xxxx'.L RETURN FROM SUBROUTINE Ac P/O N C CCIIII:l xxxx mmmm .

. being the next sequentia I instruction. except that the return is not executed unless the condition is satisfied: otherwise.. the OR instruction. the instruction sequentially following the RET cond Instruction will be executed Consider the instruction sequence: CALL AND SUBR 7CH~ 1 I I I SUbl+--. is executed. If the condition is not satisfied..RET cond - RETURN FROM SUBROUTINE IF CONDITION IS SATISFIED K 000 001 010 11 xxx 000 Condition NZ Z NC C PO PE P M Non-Zero Zero Non-Carry Carry Parity Odd Parity Even Sign Positive Sign Negative Relevant Flag all 100 101 110 111 Z Z C C Pia Pia S S This instruction is identical to the RET instruction. 3-127 ..First subroutine instruction I I condition satisfied I R T ---------" cond I condition not satisfied a SOH After the RET cond is executed. . if the condition is satisfied then execution returns to the AND instruction which follows the CALL.

if the condition is satisfied then execution returns to the AND instruction which follows the CALL.. except that the return is not executed unless the condition is satisfied: otherwise.. being the next sequentia I instruction.. If the condition is not satisfied. is executed. . the instruction sequentially following the RET cond Instruction will be executed Consider the instruction sequence: CALL AND SUBR 7CH~ 1 I I I SUbl+--.RET cond - RETURN FROM SUBROUTINE IF CONDITION IS SATISFIED K 000 001 010 11 xxx 000 Condition NZ Z NC C PO PE P M Non-Zero Zero Non-Carry Carry Parity Odd Parity Even Sign Positive Sign Negative Relevant Flag all 100 101 110 111 Z Z C C Pia Pia S S This instruction is identical to the RET instruction. 3-127 . the OR instruction..First subroutine instruction I I condition satisfied I R T ---------" cond I condition not satisfied a SOH After the RET cond is executed.

E H. in addition to returning control to the interrupted program.RETI. This instruction is used at the end of an interrupt service routine. and address the new top of stack.-..RETURN FROM INTERRUPT S Z AC Pia N C F A B. and.C o:::I:IIIJ Data Memory qq pp xxxx xxxx +' xxxx + 2 D. it is used to signal an I/O device that the interrupt routine has been completed.L SP xxxx mmmm ~ PC IX IY I . Previous Program Counter contents are lost Increment the Stack Pointer by 2. The I/O device must provide the logic necessary to sense the instruction operation code: refer to An Introduction to Microcomputers: Volume 2 for a description of how the RETI instruction operates with the Z80 family of devices --RETI 3-128 . I ~ xxxx+2 Program Memory R • I ppqq~ ED 4D mmmm mmmm+ 1 mmmm+2 mmmm+3 ED 4D Move the contents of the top two stack bytes to the Program Cou nter: these two bytes provide the address of the next instruction to be executed.

xxxx + 2) t. II _ Data Memory qq pp B. Restore the interrupt enable logic to the state it had prior to the occurrence of the nonmaskable interrupt. these two bytes provide the address of the next instruction to be executed. This instruction is used at the end of a service routine for a non-maskable interrupt..L mmmm mmmm+ 1 mmmm +2 SP PC IX xxxx mmmm -.E H. Previous Program Counter contents are lost Increment the Stack Pointer by 2 to address the new top of stack. IV I! R I I Ii-< --.RETN S RETURN FROM NON-MASKABLE INTERRUPT C ZACP/ON FOIIIlJ A .C D..1 mmmm + 2 Move the contents of the top two stack bytes to the Program Counter.-ED 45 RETN ppqq =>- Program Memory ED 45 t-----t mmmm mmmm+ 1 mmmm+3 1 . 3-129 .. and causes execution to return to the program that was interrupted..

~ t -~ ~mmm + 2 D.\ Data Memory A u. Suppose 0 contains A916 and Carry=O After the instruction RL 0 has executed...E H. 0 will contain 5216 and Carry will be 1: Before Register 0 11010 100 11 Carry After Register 0 Carry OJ a Non-zero resu It.t mmmm + 3 CB 00010001 The illustration shows execution of RL C: l\ CB 00010 xxx 000 001 010 all 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Rotate contents of specified register left one bit through Carry.. set P/0 to a a 3-130 . set Z to 0 sets S to 3 ones.L SP PC IX IY I mmmm V Program Memory R • I mmmm mmmm + 1 mmmm+2 t ..RL reg - ROTATE CONTENTS OF REGISTER LEFT THROUGH CARRY s FI ~ Z AC Pia N 1 • x I x I 0\ x \ 0.

..E t ...... memory location 400716 contains 2f 16..... R 3-131 . .Non-zero result.. and Carry is set to 1. J 6 ones.RL (HL) ROTATE CONTENTS OF MEMORY LOCATION RL (IX+disp) LEFT THROUGH CARRY RL (IY+disp) Memory Data ..I H.Jppqq A +d D. After execution of the instruction RL (lX+7~ memory location 400716 will conta in 5F 16.. and Carry is 0 Before Memory Carry After Memory Carry ~ 1001 0 1 1 1 1] OJ ~ [Q) sets S to 0 .........---~I:RFFJ=R=:R-.........-........" ..... Suppose the IX reg ister contains 400016..........t .~~---------....... R _ _-- Program Memory .....- Rotate contents of memory location (specified by the sum of the contents of Index Register IX and displacement integer d) left one bit through Carry. mmmm mmmm+ 1 d mmmm+2 _ _ _.....J~-"1-~1~6--Immmm + 3 DO CB 1---"""'1 mmmm+4 The illustration shows execution of RL (IX+disp) RL (IX+disp) --..I IX I PC r::====::!m~m~m~m======l......C _-----t--------i SP t .... set Z to 0 This instruction is identical to RL (IX+dispL but uses the IY register instead of the IX register. set P10 to 1 RL (IY+disp) o L..~~ ppqq IY .L B..

RL (HL) ~ CB 16 Rotate contents of memory location (specified by the contents of the HL register pair) left one bit through Carry RLA - ROTATE ACCUMULATOR LEFT THROUGH CARRY Z AC PIO N s 1 FI I 101 loP s.L Data Memory SP PC IX IV I mmmm ~mmm+~ Program Memory R I I 17 mmmm +1 I -_ _~mmmm + 2 I -_ _~mmmm + 3 ~_ _--1mmmm RLA 17 Rotate Accumu lalor contents left one bit through Carry status Suppose the Accumulator contains 2A16 and the Carry status is set to 1 After the instruction RLA has executed.E H.c D. the Accumulator will contain F516 and the Carry status will be reset to 0: Before Accu mu lator 1011110101 Carry After Accumulator Carry OJ 111110101\ @] 3 -132 .

..... set P/0 to 1 o 3-133 .- ArB.. Suppose Register 0 contains A916 and Carry is 1.....------tl The illustration shows execution of RLC E: mmmm mmmm + 1 mmmm +2 mmmm + 3 1-1 CB 00000 xxx 000 001 010 011 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Rotate contents of specified register left one bit. SP .. H.~ """4 .. After execution of RLC 0 Register 0 will contain 5316 and Carry will be 1.RLC reg S ROTATE CONTENTS OF REGISTER LEFT CIRCULAR ) Z AC-P/0 N C Data Memory FIXIXIOIXlol.L ~~ t------m==m:":m::':m=------i-_---4-.-------t I CB 00000011 ....:rrmmmm IV I: ..C .-------"'-----------t +'9 Program Memory R ------r-. copying bit 7 into Carry. set Z to 0 sets S to 0 4 ones. Before Reg ister 0 Carry After Register 0 Carry 11 01010011 OJ OJ Non-zero result.

After the instruction RLC (IX+7) 3-134 .E H. Carry is 1. copying bit 7 into Carry. set Z to 0 RLC (IX+disp) '~6 Rotate memory location (specified by the su m of the contents of Index register IX and displacement integer d) left one bit. copying bit 7 into Carry. set P/0 to 1 Non-zero resu It.h::Q. and Carry will be 1: Before Memory Carry After Memory Carry 11 010010 11 @] J o sets S to O_ _ 4 ones. After execution of RLC (HL) memory location 54FF16 will contain 4B16. and memory location 400716 contains 2F16. Suppose register pair HL contains 54FF16 Memory location 54FF16 contains A516.RLC (HL)ROTATE CONTENTS OF MEMORY LOCATION RLC (Ix +disp) LEFT CIRCULAR RLC (lY +disp) c Data ~]]TIaJarI::J~-------------1 A S. and Carry is O. Suppose the IX register contains 400016.iiIi++U-_J ppqq Memory • pp D.C L_.L qq mmmm SP PC IX IY I ~mmm+3) Program Memory mmm m mmm m+ 1 mmmm+2 t--------I mmmm + 3 CS I R I 06 The illustration shows execution of RLC (HL): RLC ~HL) ~ CB 06 Rotate contents of memory location (specified by the contents of the HL register pair) left one bit.

After the instruction RLCA has executed.C 0 I Data Memory D. but uses the IY register instead of the IX register. and Carry will be 0: Before --Memory Carry After -Memory Carry 10 0 1 0 1 1 1 11 OJ sets S to 0 5 ones.L SP PC IX IY I mmmm -~ V ~mmm+ 1 Program Memory 07 mmmm mmmm+ 1 mmmm + 2 mmmm+3 R I r---t r---t Rotate Accumulator contents left one bit copying bit 7 into Carry. Suppose the Accumu lator contains 7A 16 and the Carry status is set to 1.- o This instruction is identical to RLC (IX+displ.E H. memory location 400716 will contain 5E16.has executed. the Accumulator will contain F416 and the Carry status will be reset to 0: Before Accumulator 1011110101 Carry After Accumulator 1111101001 Carry ---RLCA 07 OJ @] RLCA should be used as a logical instruction 3-135 . ~ RLCA S ROTATE ACCUMULATOR LEFT CIRCULAR Z AC P/0N FI I 101 101 B. set PIO to 0 RLC (IY+disp) ~-.

.. and memory location 4000'6 contains 1216 After execution of the instruction --RLD ED 6F RLD the Accumulator will contain 7116 and memory location 400016 will contain 2F16: Before Accumulator Memory After Accumulator Memory 71IF~~2 \ \ ". Suppose the Accumulator contains 7F. set Z to 0 3-136 .C x I qq y r 5 ppqq D. set S to 0 4 ones..-_ _ R I mmm m mmm m+ 1 mmmm + 2 mmmm + 3 The fou r low-order bits of a memory location (specified by the contents of register pair HU are copied into the four high-order bits of the same memory location The previous contents of the fou r high-order bits of that memory location are copied into the four low-order bits of the Accumulator The previous four low-order bits of the Accumulator are copied into the four low-order bits of the specified memory location.-_ _ . .. 6. set P10 to ." high-order bit=O.. HL register pair contains 4000....RLD S ROTATE ONE BCD DIGIT LEFT BETWEEN THE ACCUMULATOR AND MEMORY LOCATION Z AC p/O N C Data F~ A B. _---~' -" / ' . 6..E HL pp mmmm SP PC IX IV I t ~mmm+) Program Memory I ED 6F . _~-J Non-zero result...

Register H wi II contain 8716.~ D. and Carry wi II be 1: Before -HRegister 1000011111 Carry After -Register H 10000111 Carry IT] 1 sets S to 1 4 ones. set P/0 to 1 LNon-zero result.L SP PC IX IY mmmm .RR reg - ROTATE CONTENTS OF REGISTER RIGHT THROUGH CARRY 5 Z AC P/O N • ~ -./" ~mmm+2 !) Program Memory I R I I mmmm mmmm + 1 mmmm +2 1-----1 mmmm + 3 00011001 CB The illustration shows execution of RR C: -L\ CB 00011 xxx 000 001 010 all 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Rotate contents of specified register right one bit through Carry Suppose Register H contains OF 16 and Carry is set to 1.E H.~ FIXIXlotxtO\ A Data Memory ~. set Z to a 3-137 . After the instruction RR H has executed.

.C DE HL l" mmmm . and Carry will be 1: Before Memory 100011101\ Carry After Memory Carry [Q] [j] Non-zero result set Z to 0 sets S to 0 3 ones.-..el J.pqq + d'"""'- CB 1E d The illustration shows execution of RR (lY+disp): ~+di~.. set P/O to 0 RR (IX+disp) ~ o J.. -..h Rotate contents of memory location (specified by the sum of the contents of the IY register and the displacement value d) right one bit through Carry Suppose the IY register contains 450016. Data Memory I ppq q+d B. mmmm + 4 SP PC IX IY I 9 ~- Program Memory FD mmm m mmm m + 1 mmm m +2 mmmm+3 mmm m+4 ppqq I R I 1 C.ROTATE CONTENTS OF MEMORY LOCATION RIGHT THROUGH CARRY RR (Ix +disp) RR (lY+disp) RR (HL) - s A Z AC P '0 N C F rXIXIOIXIOIl .- 3-138 .h This instruction is identical to RR (lY+displ.... memory location 450F16 contains 1016_ and Carry is set to 0 After execution of the instruction RR (IY+OFH) memory location 450F16 will contain OE16. _/ - .. but uses the IX register instead of the IY register.-.

Suppose the Accumulator contains 7A16 and the Carry status is set to 1.L 1 ~ --"'~mmm+ 1 SP PC IX IY I mmmm -~ ~ Program Memory I I R 1F mmmm I -_ _-Immmm + 1 I -_ _-Immmm + 2 1-_ _-1 mmmm + 3 RRA 1F Rotate Accumu lator contents rig ht one bit through Carry status.c D. After the instruction RRA has executed. the Accumulator will contain BD16 and the Carry status will be reset to 0: Before Accumulator 1011110101 Carry After Accumulator 1101 1 1 1 01l Carry OJ @] 3-139 .RR (HU ~ CB 1E Rotate contents of memory location (specified by the contents of the HL register pair) right one bit through Carry RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY Data s Z~P/ONl FI I 101 101 '" s.E H.

the Accumulator will contain BD16 and the Carry status will be reset to 0: Before Accumulator 1011110101 Carry After Accumulator 1101 1 1 1 01l Carry OJ @] 3-139 . Suppose the Accumulator contains 7A16 and the Carry status is set to 1.RR (HU ~ CB 1E Rotate contents of memory location (specified by the contents of the HL register pair) right one bit through Carry RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY Data s Z~P/ONl FI I 101 101 '" s.c D.L 1 ~ --"'~mmm+ 1 SP PC IX IY I mmmm -~ ~ Program Memory I I R 1F mmmm I -_ _-Immmm + 1 I -_ _-Immmm + 2 1-_ _-1 mmmm + 3 RRA 1F Rotate Accumu lator contents rig ht one bit through Carry status. After the instruction RRA has executed.E H.

RRC (HL)RRC (IX+disp) RRC (ly +disp) C ROTATE CONTENTS OF MEMORY LOCATION RIGHT CIRCULAR Data Memory p pqq A B.. t Program Memory mmm m mmm m+ 1 mmmm+2 t . memory location 450016 contains 3416. After execution of RRC (HU memory location 450016 will contain 1A16' and Carry will be 0: Before Memory 1001101001 Carry After Memory 0011010 Carry OJ sets S to 0 3 ones.E H. set P/0 to 0 RRC (IX+disp) o lNon-zero result..t mmmm + 3 mmmm+2 I R I CB DE The illustration shows execution of RRC (HU: RRC (HU ~ CB OE Rotate contents of memory location (specified by the contents of the HL register pair) right one bit circularly.L pp qq SP PC IX IY Ii mmmm -. and Carry is set to 1.. set Z to 0 Rotate contents of memory location (specified by the sum of the contents of the IX ~ 3-141 .........C D. copying bit 0 into the Carry status.. Suppose the HL register pair contains 450016.

.L SP PC IX mmmm -'w mmmm + 1 . 'Xh This instruction is identicaf to the RRC (IX+disp) instruction. the Accumulator will contain 3016 and the Carry status will be reset to ---RRCA OF 0: Before Accu mu lator Carry After Accumulator Carry 1011110101 OJ 1001111011 [Q] RRCA should be used as a logical instruction. copying bit 0 into the Carry status. Suppose the Accumulator contains 7A16 and the Carry status is set to 1 After the instruction RRCA has executed.E H. 3-142 .. copying bit 0 into the Carry status.register and the displacement value d) right one bit circularly. but uses the IY register instead of the IX register. -- ~ Program Memory IV I R I I mmmm mmmm+ 1 ~---I mmmm + 2 ~_ _... RRC (IY+disp) RRCA - ROTATE ACCUMULATOR RIGHT CIRCULAR Z AcP/ON C r s F I I 101 10 I • Data s.c D.I mmmm + 3 OF Rotate Accumulator contents right one bit circularly...

.I. _" ...~ r I s q V -r= Of pp mmmm SP PC IX IY I -.sult set Z to 0 3-143 . and memory location 400016 contains 1216. ~2 \ I I lIID ".L ~ x I I qq M~ry bY-. The previous contents of the four low-order bits are copied into the four low-order bits of the Accumu lator..RRD S ROTATE ONE BCD DIGIT RIGHT BETWEEN THE ACCUMULATOR AND MEMORY LOCATION Z AC Plo N C Data F A B. HL register pair contains 400016. . After execution of the instruction RRD RRD the Accumu lator will contain 7216 and memory location 400016 will contain F116: Accu mu lator Before -Memory Accumulator After -Memory 7.C D.( High-order bit=O. The previous four low-order bits of the Accumulator are copied into the four high-order bits of the specified memory location.'" \ \ F' . Suppose the Accumulator contains 7F16. set P/0 to 1 L Non-mo . set S to 0 4 ones.. V . mmmm+2 Program Memory I R I mm mm mm mm+ 1 mmmm+2 1----"""'1 mmmm + 3 ED 67 --.-" ~ '.E H..-ED 67 The four high-order bits of a memory location (specified by the contents of register pair HL) are copied into the four low-order bits of the same memory location..

as described in Chapter 12.. (PPQQ-2 ) PC IX IY I R V"_ ~mmm + y... If your application does not use all RST instruction codes to service SUBROUTINE CALL USING interrupts... do not overlook the possibility of calling subroutines using RST instructions. the RST instruction is used in conjunction with interrupt processing. The previous Program Counter contents are pushed to the top of the stack. Origin frequently used subroutines at apRST propriate RST addresses.L SP .RST n F A RESTART Data Memory j S Z AC p/o N C o::::r::n:I:l ~ ""1 ppqq mmmm mm+ 1 mm ppqq-2 ppqq-1 ppqQ B. the subroutine origined at memory location 001816 is called. Usually. I I C I Program Memory 11 xxx 111 OOOOOOOOOOxxxOOO mmmm mmmm+ 1 mmmm+2 mmmm+3 R When the instruction 11 xxx 111 Call the subroutine origined at the low memory address specified by n RST 18H has executed.C D.E H. and these subroutines can be called with a single-byte RST instruction instead of a three-byte CALL instruction 3-144 ...

3A Twos camp of 7C Twas camp of Carry 0011 1000 1111 1011 1 sets S to 1 Borrow. set C to 1 1 ¥ 1=0. V .L ft _ - ~X-YY-Cr 1 Data Memory SP PC IX IY mmmm -..yy Subtract the contents of the second object code byte and the Carry status from the Accumulator Suppose xx=3A16 and Carry=l. set Z to a ..C D...data - SUBTRACT IMMEDIATE DATA FROM ACCUMULATOR WITH BORROW s F Z AC PIO N J xx ~ A B.mmm + 2 "- Program Memory DE mmmm mmmm+l mmmm+2 mmmm+3 R I I YY SBC A DE --.Borrow..".:.E H.. the Accumulator will contain B016.- data -.SBC A. 3-145 . set P/O to 0 1010 0100 1111 1101 fJ LNon-ze. After the instruction SBC A7CH has executed. set AC to 1 Subtract instruction.. set N to 1 The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.o <esult.

-~mmm+v Program Memory I I mmmm mmmm+ 1 1------1 mmmm + 2 l00llxxx 1--_ _.. After the instruction SSC A.xxx --....E has executed..reg - SUBTRACT REGISTER WITH BORROW FROM ACCUMULATOR S Z AC plO N C r xx ~ A B.et Z to a a " .. set P/O to a r 001 1 0000 1111 0010 LNoo-. E. set C to a 1¥1 =0. the Accumulator will contain 4216 E3 Two' s camp of AO Two's comp of 1 1 1 10 0110 1111 0100 a sets S to 0 No borrow. H or L SP PC IX IY I R mmmm . . set N to 1 The Carry flag is set to 1 for a borrow and reset to a if there is no borrow. D. Suppose xx=E316' Register E contains A016.--' --..em '"'"'I. -. 3-146 . set AC to Subtract instruction.C i t xx-yy-C Data D.SBC A....N o borrow.."o:t is yy A B C.000 001 010 all 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A reg 10011 Subtract the contents of the specified register and the Carry status from the Accumu lator.E HL }-Coo. mmmm + 3 SBC A. and Carry=l.

(HU a 01 1 aa0 1 1 010 0100 o Non-2O'o 'esult. set C to 1 O¥O=O..E) DD 9E d The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.{IY+disp) 3-147 . (HU: -. After execution of the instruction SSC A. and memory location 400016 contains 7C 16.sac A.UY+disp) S Z AC P/O N C SUBTRACT MEMORY AND CARRY FROM ACCUMULATOR F IXIXIXIXllIX. {IX+displ instruction.C D.UX+disp) sac A. pp mmmm qq PC IX IY I -~ - ..J L L .1 xx :Xx-yy-C~ yy PO. set AC to 1 Subtract instruction. xx=3A16. ppqq=400016. Subtract the contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) and the Carry from the Accumulator ~--FD 9E d This instruction is identical to the SSC A. Suppose Carry=O. 1110 a a ~+di. 3A Two'S comp of 7C Two's comp of Carry SSC A.~mmm+ 1 ~ Program Memory I R I mmm m mmm m+ 1 mmmm+2 1-----1 mmmm + 3 9E The illustration shows execution of SSC A. SBC A. set P/O to }.E H. except that it uses the IY register instead of the IX register.-9E Subtract the contents of memory location (specified by the Contents of the HL register pair) and the Carry from the Accumulator. set N to 1 1011 1 sets S to 1 Borrow.(HL)sac A.(HU the Accumulator will contain BE16..L SP Data Memory . set Z to Borrow. A B.

I contains yyyy xx Be.BC has executed. set C to 0 1 ¥ 1=0.. 01 00 0 11 0 111 0 L_ ~::::::~~SUIt. _ Subtract instruction. After the instruction SBC HL. set N to 1 The Ca rry flag is set to 1 for a borrow and reset to 0 if there is no borrow.rp S SUBTRACT REGISTER PAIR WITH CARRY FROM HAND L Data Memory Z AC PIO N C B.SBC HL. DE. BC contains A03416.L J SP PC IX IV I .C ~~ xx mmmm .E H. and Carry=O. 3-148 . HL or SP D. set P/O to 0 ~ . the HL register pair will conta in 546E 16: 1111 0100 1010 0010 010111111100 1100 OWl o set Z to 0 o sets S to 0 No borrow.·1l~mmm+J) Program Memory I ED R I 01xxOO10 1-_ _ 1-_ _ mmmm mmmm + 1 mmmm + 2 mmmm + 3 K 01 00 01 10 11 Two's camp of F4A2 Two's camp of A034 Two's camp of Carry xx 0010 for for for for rp rp rp rp is is is is register pair BC register pair DE register pair HL Stack Pointer Subtract the contents of the designated register pair and the Carry status from the HL register pair. Suppose HL contains F4A216.

~ -'~mmm+v Data Memory B.. the Carry status is set to 1 regardless of its previous value. 3-149 ... mmmm + .L SP PC IX IY I R mmmm Program Memory 37 I mmmm I 1------..C D. No other statuses or register contents are affected.. mmmm + 2 1------4 mmmm + 3 SCF 37 When the SCF instruction is executed.E H.SCF F A SET CARRY FLAG I I I I I S Z AC P/O N C r . 1-_ _..

E H. Program Memory mmmm mmmm + 1 mmmm+2 ... (Bit a is the least significant bit.) 3-150 ..1 mmmm + 3 11bbbxxx R I CB I ll~~ CB 11 bbb xxx -.reg S SET INDICATED REGISTER BIT C Data Memory Z AC PIO N FCIIIIIJ A B..Bit bbb xxx - -000 001 010 011 100 101 111 a 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 Register B C 0 E H L A SET indicated bit within specified register. After the instruction SET 2.SET b....L yyyy yyyy mmmm • r "- 1 SP PC IX IY I - -'mmmm + 2 .....C O..... bit 2 in Register L will be set.L has executed..

.(HL} .... bit 5 in memory position 400016 will be 1.....E H.L pp mmmm qq SP PC IX IY I .t mmmm + 3 mm mm mmmm+ 1 mmmm+2 The illustration shows execution of SET b.(HU Set indicated bit within memory location indicated by the sum of Index Register IX and displacement 3-151 .SET BIT b OF INDICATED MEMORY POSITION SET b. (IX +disp) SET b. Suppose HL contains 400016. Bit 0 is the least significant bit CB 11 bbb 110 Bit Set bbb 000 001 010 011 100 101 110 111 11~~ o 1 2 3 4 5 6 7 Set indicated bit within memory location indicated by HL.(HU. After the instruction SET 5.(HU has executed. I f ~ mmmm + 2 Program Memory R I CB I 11bbbl10 t ...C D...SET b. SET b.. (lY +disp) S Z AC P/O N C FCI:IIIJ:] A yyyy yyyy P qq B..(IX+disp) bbb is the same as in SET b.

resetting the least significant bit to O.0X+5Hl bit 6 in memory location 400516 will be 1. After execution of SET 6. ~ FD CB d 11 bbb 110 bbb is the same as in SET b.(lX+disp).(HU This instruction is identical to SET b. r Data FIXIXIOIXIOI'I D.v Z ACP/O N 1.Suppose Index Register IX contains 400016. except that it uses the IY register instead of the IX register SLA reg - SHIFT CONTENTS OF REGISTER LEFT ARITHMETIC s A u.E H. Suppose Register B contains 1F16. and Carry= 1 After execution of SLA B Register B will contain 3E16 and Carry will be zero 3-152 .L SP PC IX IV I '" mmmm ° Program Memory ~mmm+~ I R I CB 00100001 mmmm mmmm + 1 t------4 mmmm + 2 t------4 mmmm + 3 The illustration shows execution of SLA C: SLA reg I~ CB 00100 xxx 000 001 010 all 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Shift contents of specified register left one bit.

. memory location 450016 contains 8416.E pc mmmm SPt===~~~===::J:.L D..-..-_ _pProgram Memory mmmm mmmm +' mmmm+2 t . Memory Before -Carry Memory After -Carry 110000100\ IT] 0001000 ill sets S to 0 one.. and Carry will be 1.ii~( IX lY .. and Carry=O...C~-----t-----~ A L----tl:B:HHr~Ppqq H..J .i I R JPP qq t-:==:££:=:t:=~c:=t----==:--~----=---.Before Register B 1000111111 Carry After m Register B 0111110 Carry [Q] o sets S to 0 5 ones..t mmmm + 3 CB 26 The illustration shows execution of SLA (HL): SLA (HL) ~ CB 26 Shift contents of memory location (specified by the contents of the HL register pair} left one bit resetting the least significant bit to O. set P/0 to 0 o l 3-153 Non-zero resu It set Z to 0 . Suppose the HL register pair contains 450016..... After execution of SLA (HL) memory location 450016 will contain 0816...... set P/0 to 0 ~ Non-zero result set Z to 0 SLA (HL)SHIFT CONTENTS OF MEMORY LOCATION SLA (lX+disp) LEFT ARITHMETIC SLA (lY +disp) Data Memory B...

SRA reg S ARITHMETIC SHIFT RIGHT CONTENTS OF REGISTER C Z ACP/ON Data F IxrXIOlxlOI A 141 ~ Memory B. Suppose Register H contains 5916. 3-154 . but uses the IY register instead of the IX register. resetting least significant bit to 0 SLA (IY+disp) li '~ This instruction is identical to SLA (IX+disp).t mmmm + 3 CB 00101111 IY I R I I The illustration shows execution of SRA A: SRA reg I~ CB 00101 xxx 000 001 010 011 100 101 111 for for for for for for for reg=B reg=C reg=D reg=E reg=H reg=L reg=A Shift specified register right one bit Most significant bit is unchanged..C D.. After the instruction SRA H has executed. Register H will contain 2C16 and Carry will be 1..L SP PC IX - ~mmm+v Program Memory mmmm mmmm + 1 mmmm+2 I . and Carry=O.E { 'mmmm H.SLA (IX+disp) Shift contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) left one bit arithmetically..

and Carry=l After execution of SRA (IX+OAAH) memory location 34AA16 will contain 1316.Non-zero result. memory location 34AA 16 contains 2716. set P/0 to 0 o L.L L mmmm ppqq mmmm+4 -~ ~ ppqq +d • Program Memory 5P PC IX IY R I- "- I I ~pqq+d~ ~ DO CB d 2E mmm m mmm m+ . Suppose Register IX contains 340016.E H. mmm m+2 mmm m+3 mmmm+4 The illustration shows execution of SRA (IX+disp) SRA (IX+disp) ~-.Before Register H 10 1 0 1 1 00 11 C After Register H 00101100 C @] OJ sets S to 0 3 ones. set P/0 to 0 L. and Carry will be 1. set Z to 0 3-155 .Non-zero result. Before Memory [001001111 Carry After Memory 00010011 Carry ~ OJ o sets S to 0 3 ones..- Shift contents of memory location (specified by the sum of the contents of Register IX and the displacement value d) right Most significant bit is unchanged. set Z to 0 SRA (HL)SRA (IX +disp) SRA (ly +disp) ARITHMETIC SHIFT RIGHT CONTENTS OF MEMORY POSITION Data Memory A Be D.

L H. and Carry will be 1. s Z AC P/O N - . Most significant bit is reset to O. but uses the IY register instead of the IX register.C ~.000 001 010 011 100 101 111 for reg=B for reg=C for reg=D forreg=E for reg=H for reg=L for reg=A Shift contents of specified register right one bit. Su ppose Register 0 contains 1F16' and Carry=O. Most significant bit is unchanged. SRL reg - SHIFT CONTENTS OF REGISTER RIGHT LOGICAL C .'-. SRA (HLl ~ SRA (IY+displ CB 2E Shift contents of memory location (specified by the contents of the HL register pair) right one bit. 6. 0 FlolxlOlxlOI j ~ Data Memory A S.R This instruction is identical to SRA (IX+displ. After execution of SRL 0 Register 0 will contain OF.L SP PC IX IY mmmm - _/ mmmm+2 Program Memory mmmm mmmm+ 1 mmmm+2 1-----1 mmmm + 3 CB 00111011 ~ I I R I The illustration shows execution of SRL E: SRL reg CB 00111 xxx l~ --. 3-156 .

.. After execution of SRL (HU memory location 200016 will contain 4716. memory location 200016 contains 8F16..CB 3E Shift contents of memory location (specified by the contents of the HL register pair) right one bit.. and Carry=O. Most significant bit is reset to O.-..Non-zero result.. set Z to 0 SRL (HL)SRL (IX+disp) SRL (IV +disp) S Z AC PIO N C SHIFT CONTENTS OF MEMORV LOCATION RIGHT LOGICAL Data :~xo .. X 0 B. Non-zero result. ~ 3-157 SRL (IX+disp) .. Before Memory Carry After Memory Carry SRL (HL) 1100011111 [Q] 1010001111 ~ OJ 4 ones.C D... set Z to 0 Shift contents of memory location (specified by the sum of the contents of the IX register and the displacement value d) right one bit..E H. Suppose the HL register pair contains 200016.. set P/0 to 1 L.. and Carry will be 1... mmmm + 3 CB 3E The illustration shows execution of SRL (HL): -..L pp SP I mmmm qq t ~mmm+v Program Memory PC IX IY I R I I mmmm mmm m+1 mmmm+2 1 .-... set P/0 to 1 L. Most significant bit is reset to O.Before Register D Carry After Register D Carry 1000111111 @] 10000 1 1 1 11 ~ [JJ 4 ones..

--. set C to 1 t-J L LNon....-.L SP PC IX IY mmmm -. D. set Z to a Borrow.yy data 06 Subtract the contents of the second object code byte from the Accumulator. the Accumulator will contain BE16· 3A 001 1 Two's comp of 7C = 1 000 1011 10 10 01 00 1110 1 sets S to 1 Borrow. ~mmm+2 "D .. set N to 1 o¥ 0=0. Suppose xx=3A16. set AC to 1 Subtract instruction. Program Memory I R I I 06 yy mmmm mmmm + 1 mmmm+2 mmmm+ 3 SUB -.C xx -~ ___ xx-yy J. 3-158 .SRL (IY+disp) '~ This instruction is identical to SRL (IX+displ.esult. set P/O to 0 Notice that the resulting carry is complemented.zem .E H. After the instruction SUB 7CH has executed. but uses the IY register instead of the IX register SUB data -SUBTRACT IMMEDIATE FROM ACCUMULATOR S Z AC P/O N C Data Memory F~ A B..

L }-CM"I. set N to 1 Notice that the resu Iting carry is complemented. set AC to 0 Subtract instruction. s. E.. xx-yy ") ~ Data Memory S. C.. ..SUB reg S SUBTRACT REGISTER FROM ACCUMULATOR C Z AC PIO N F mEIEIEJIIE] xx A f.No borrow. set C to 0 1 ¥ 1=0. H or L is y y SP PC IX mmmm Program Memory IY I 1 R I 10010xxx mmmm 1-_ _--1 mmmm + 1 I -_ _--Immmm + 2 1-_ _--1 mmmm + 3 ---SUB 10010 reg xxx --......000 001 010 011 100 101 111 for for for for for for for reg=B reg =C reg=D reg=E reg=H reg =L reg=A Subtract the contents of the specified register from the Accumulator.sult. ~-.'" ..t Z to a . 3-159 ... D. -'.C D.E H... set P/0 to 0 fJ LNon-.~mmm+~ . Suppose xx=E3 and Register H contains A016 After execution of SUB H the Accumulator will contain 4316E3 =:: 1 1 1 0 Two's comp of AD = 0 1 1 0 0100 00 11 0000 0011 o sets S to 0 No borrow.em ...

SUB (HL) - SUBTRACT MEMORY FROM ACCUMULATOR SUB (Ix +disp) SUB (lY+disp)
S Z AC PIO N C

Data
Memory xx

x X X X 1 X F~
A

_

RC
D.E
H.L

-" J.1,,xx-yy

yy

ppqq +d


Program Memory

SP PC
IX IY I

mmmm

_

ppqq

I--

-~
1

mmmm +3

.........

V

R

I I

~pqq+d)-:=

DD 96
d

mmm m mmm m+ 1 mmmm+2 mmmm+3

The illustration shows execution of SUB (IX+dl:
~-.-

SUB (IX+disp) DO 96 d

Subtract contents of memory location (specified by the su m of the contents of the IX register and the displacement value d) from the Accumulator. Suppose ppqq=400016. xx=FF16. and memory location 40FF16 contains 5016 After execution of SUB (IX+OFFH) the Accumulator will contain AF16· FF Two's comp of 50 = 1111 101 1 1010

1 sets S to 1 No borrow, set C to 0 1 ¥ 1=0. set P/O to 0

fJ
",-

1111 0000 1111

LNon-zero 'esult, set Z to a
No borrow. set AC to 0 Su btract instruction. set N to 1

Notice that the resu Iting carry is complemented. SUB (IY+disp)
~--

FD 96

d

This instruction is identical to SUB (IX+disp). except that it uses the IY register instead of the IX register. SUB (HU
~

96 Subtract contents of memory location (specified by the contents of the HL register pair) from the Accumulator

3-160

XOR data S

EXCLUSIVE-OR IMMEDIATE WITH ACCUMULATOR
C

ZACP/ON

F~
A B,C
D,E H.L

xx

-~ xx¥yy ........

>
"-

Data Memory

SP
PC IX IV I

mmmm

- ,,.......

mmmm+2

Program Memory

I

EE
yy

R

I

mmmm mmmm+ 1 mmmm+2 mmmm+3

XOR

data yy

EE
Suppose xx=3A16. After the instruction

Exclusive-OR the contents of the second object code byte with the Accumulator.

XOR 7CH has executed, the Accumulator will contain 4616 3A 7C =

o sets S to O~
The Exclusive-OR instruction
IS

------0100
LNon-zero resu It set Z to 0 LThree 1 bits, set Pia to 0

001 1 01 1 1

10 10 1 1 00 01 1 0

used to test for changes in bit status.

3-161

XOR reg - EXCLUSIVE-OR REGISTER WITH ACCUMULATOR s Z AC P/O N C Data -~xx¥yy~ I......... Memory
F

I!IEIIImI[)

f,

A

B.C
D.E H.L SP

~ Co,,,LA'
C, 0, E, H or L is yy

PC
IX IY I

mmmm

-,

--

mmmm + 1

Program Memory lO1Olxxx mmmm

R

I I

1 - - - - - 1 mmmm + 1 mmmm+2 1 - - - - - 1 mmmm + 3

-..10101

XOR

reg

-..000 001 010 011 100 101 111

xxx

for for for for for for for

reg = B reg=C reg=D reg=E reg=H reg=L reg=A

Exclusive-OR the contents of the specified register with the Accumulator. Suppose xx=E316 and Register E contains A016. After the instruction XOR E has executed, the Accumulator will contain 4316. E3

AO =

------001 1

o

sets S to

o..J

1 1 1a 1a1a a 1 aa

001 1

0000

L

Non-zero resu It set Z to

a

LThree 1 bits. set PIO to 0 The Exclusive-OR instruction is used to test for changes in bit status.

3-162

.

RL. FASTER AND The end result is that these multi-byte instructions execute rather slowly (and use more memory) because an additional memory SLOWER access is required The reader should be aware of this variation in EXECUTING execution times and try to use faster executing instructions when INSTRUCTIONS possible.a miscellaneous non-8080A instruction not covered elsewhere FD . There are a few minor incompatibilities between the 8080A and the Z80. The l80 has instructions. The l80 and 8080A execute the DAA instruction differently.an operation involving register IX 8080A/Z80 ASSEMBLY LEVEL CONVERSION 8080A UNUSED OPERATION CODES 2-BYTE OPERATION CODES ED . The 8080A always uses this flag for parity. with some minor differences to be noted later. Note the following meanings of these codes from Table 3-9: CB . and other features not present on the 8080A. one of its important characteristics is its compatibility with the 8080A microprocessor. 3) 3-164 . DO. SRL) and to instructions involving the index registers IX and IY. Almost all 80BOA programs will run on a l80. SRA. this instruction will correct decimal subtraction as well as decimal addition. The 8080A has some unused operation codes (see Table 3-9) that are used for some of the l80's extra instructions. On the 8080A. RR. On the l80. registers.8080A!Z80 COMPATIBILITY Although the Z80 microprocessor can certainly be used on its own merits. so l80 programs will not generally run on B080A processors. RRC. But there are simply not enough such codes to cover the large number of features in a simple form. many of the added Z80 instructions require a 2-byte operation code. Thus. The first byte is CB.an operation involving register IY The second byte of the operation code describes the actual operation to be performed. or FD.a register or bit operation DO . This warning particularly applies to the extra shift instructions (RLC. 2) 3) 4) Note that this compatibility does not extend to assembly language source statements since l80 assemblers and B080A assemblers use different operation code mnemonics. Table 3-7 contains a list of the 8080A mnemonic codes and the corresponding Z80 code•. These are: 1) 8080A/Z80 INCOMPATIBILITIES 2) The Z80 uses the P (or P/O) flag to indicate twos complement overflow after arithmetic operations. while Table 3-8 Is the same list organized by Z80 code•. The 8080A rotate instructions do not' affect the AC flag. This compatibility has the following features: 1) 8080A/Z80 COMPATIBILITY FEATURES All BOBOA machine language instructions are also l80 machine language instructions All B080A registers are also l80 registers (see Table 3-6l. it will correct only decimal addition The l80 rotate instructions clear the AC flag. Readers should note the binary coding limitations that this compatibility places on the extra features of the Z80 microprocessor. ED.

ter A None B None B' C C None C' o 0' o None E E' F F' H H' I E None Least S~nificant Half of PSW None H None None None None IX IY L L' L None None R PC SP PC SP Z80 Regl'ter Pair. Programs that depend on precise instruction timings will therefore execute properly only on the processor for which they were written. and Z80 all differ.\ Regl'ter Pel. The codes used for RIM and SIM on the 8085 are used for relative jumps (Nl and NC) on the l80. 8080. C (Carry) AC (Auxiliary Carry) None P (Parity) 5 (Sign) Z (Zero) The l80 is not compatible with the extra features of the 808& microprocessor. 808&!l80 INCOMPATIBILITIES TIMING INCOMPATIBILITIES The N flag on the l80 occupies bit 2 of the F register: the corresponding bit in the Processor Status Word of the 8080A is always a logic "'. 808&. B BC DE HL AF o H PSW Z80 Fleg.. Register and Flag Correspondence between laO and 8080A Z80 Regl'ter A A' B 8080.\ Regi. 3-165 .Table 3-6. Instruction timings on the 8080A. C (Carryl 104 (Half -Carry) N (Subtract) P/O (Parity/Overflow) S ISign) Z (Zero) 8080" Fleg.

addr P.data reg or (HLl data (port).HL SP.rp reg or (HLl rp reg or (HLl NC.data16 reg.addr M.data reg or (HLl data addr C.reg or (HL) reg or (HLl.A reg or (HLl data OE.reg reg or M.addr data PO.data (addrl.reg or (HLl A.addr NZ.laddr) A.reg or M reg or M.addr PE.A (BC) or (DE}.Table 3-7 Correspondence between 8080A and Z80 Mnemonics 8080A Mnemonic ACI ADC ADD ADI ANA ANI CALL CC CM CMA CMC CMP CNC CNZ CP CPE CPI CPO CZ OM DAD OCR DCX reg or M addr addr addr addr data addr addr rp reg or M rp data reg or M reg or M data reg or M data addr addr addr l80 Mnemonic ADC ADC ADD ADD AND AND CALL CALL CALL CPL CCF CP CALL CALL CALL CALL CP CALL CALL OM ADD DEC DEC 01 EI HALT HL.data A.HL IN INC INC JP JP JP JP JP JP JP JP JP LD LD A.addr A.HL reg or (HLl data (SPl.addr P.reg or (HLl A.addr Z.addr NZ.addr M. A (HLl pr pr C . M NC NZ P PE PO f 01 EI HLT IN INR INX JC JM JMP JNC JP JNZ JPE JPO JZ LOA LOAX port reg or M rp addr addr addr addr addr addr addr addr addr addr B or 0 Z A.reg reg or (HLl.(port) reg or (HLl rp C.HL laddrl.data16 reg.addr PO.data reg or M data port pr pr HL.reg or (HL) A.addr Z.(BCI or (DEI SBB SBI SHLD SPHL STA STAX STC SUB SUI XCHG XRA XRI XTHL reg or M data addr addr B or 0 reg or M data reg or M data 3-166 .addr A.addr 8080A Mnemonic LHLO LXI MOV MOV MVI NOP ORA ORI OUT PCHL POP PUSH RAL RAR RC RET RLC RM RNC RNZ RP RPE RPO RRC RST RZ n laO Mnemonic LD LD LD LD LD NOP OR OR OUT JP POP PUSH RLA RRA RET RET RLCA RET RET RET RET RET RET RRCA RST RET SBC SBC LD LD LD LO SCF SUB SUB EX XOR XOR EX n addr rp.addr PE.addr addr NC.(addrl 'P.

data16 LD LD LO LO LO LO LO LO LD LO LO LO LOD LOOR LDI - + displ rp. data reg.reg I.xv xV.BC or DE (a~dr).A (addr).A R.addr PE.AF' DE.HL SP.~xV eOeOA Mnemonic ACI ADC ADC data M reg Z80 Mnemonic INC INC INC IND INOR rp XV (XV + disp) B080A Mnemonic INX ~ rp - + displ HL.addr PE.data A.HL (SPl.addr P.rp IX.(port) reg. 3-167 .laddr) SP.addr xv C.rr data (HU reg (xv + disp) b.cates that there no correspondong .(HU A.reg - ~ CMA DAA IHU reg rp XV (XV + displ disp AF.SP (addr).~xV STAX LHLD MVI MOV B or D addr M.data A.addr PO.disp Z.A BC or DE.addr data (HLI reg (XV + displ ADI ADD ADD data M reg rp INI INIR JP JP JP JP JP addr C.data M.data (xV + disp).lxV + displ addr C.reg - - HLT m IN port M reg - A.rp A.xv DCR DCR DCX M reg rp MVI MOV MOV LXI reg.disp A.addr (HU M. reg .A reg.nstructlon.reg b.addr NC.(xv + disp) HL.addr NC.~addr} 01 SPHL - EI XCHG XTHL - - (XV + disp).xv (Be) or IDEI.(addr) A.laddrl HUaddr) (HU.Table 3-8 Correspondence between Z80 and 8080A Mnemonic" zeo ACC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD AND AND AND AND BIT BIT BIT CALL CALL CALL CALL CALL CALL CALL CALL CALL CCF CP CP CP CP CPO CPDR CPI CPIR CPL DAA DEC DEC DEC DEC DEC 01 DJNZ EI EX EX EX EX EXX HALT 1M IN IN INC INC - Mnemonic A.addr Z.lHU b.(Be) or (DE) A.PP IY.disp NZ.data '8g.addr PO.lCI ~HU LOIR NEG NOP OR data INR INR IS NOP ORI data reg .data16 SP.data IHU.M rag.addr Z.HL (SPI.data 16 xv.eg.(HU reg.addr NZ.nd.reg rp.I A.disp disp NC.R (addd.addr NZ.reg A.addr M.reg A.HL - JMP JC PCHL JM JNC JNZ JP JPE JPO JZ - addr addr addr addr addr addr addr addr addr DAD - ANI ANA ANA data M reg JP JP JP JP JP JP JR - - - CALL CC CM CNC CNZ CP CPE CPO CZ CMC Cpt CMP CMP - addr addr addr addr addr addr addr addr addr data M reg JR JR JR JR LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD - LDA LDAX addr B or D - STA SHLD - addr addr (addr).addr P.(HLl A.

lxv + disp) (HL) reg (XV + disp) (HL) reg (XV + disp) (HL) reg (XV + disp) data (HL) reg (XV + disp) data (HL) reg (XV + disp) RST SBI SBB SBB n data M reg pop POP PUSH PUSH RES RES RES RET RET RET R~T pop pr pr RST SBC SBC SBC SBC SBC SCF SET SET SET SLA SLA SLA SRA SRA SRA SRL SRL SRL SUB SUB SUB SUB XOR XOR XOR XOR PUSH - - STC RET RC RM RNC RNZ RP APE RPO RZ - - - RET RET RET RET AET RET! RETN RL RL AL RLA RLC RLC RLC RLCA ALD - P PE PO Z - - - - (HL) reg (XV + displ (HL) reg (XV + disp) - SUI SUB SUB data RAL M reg data M reg ~ XRI XRA XRA RLC - - indicates that there is no corresponding instruction 3-168 .IHL) b.Table 3-8. Correspondence between Z80 and 8080A Mnemonics (Continued) Z80 Mnemonic OR OR OR OTDR OTIR OUT OUT aUTO OUTI (C).reg (port).reg b.reg b.(xv + disp} C M NC NZ n A.data A.IHL) A.(xV + displ HL.(HL) b.rp b.reg A.A (HLI reg (XV + disp) 8080A Mnemonic ORA ORA ~ Z80 Mnemonic RR RR RR RRA RRC RRC (HL) reg (XV + disp) (HL) reg (XV + disp) 8080A Mnemonic M reg - RAR - OUT - port RRC RRCA RRD RRC pr XV pr XV b.

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