By B.

Baha Eddine

Exemple de Programme en VHDL

Fonctions asynchronies: Bascule RS :
LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.std_arith.all; entity RS_ASYNC is port (R,S :in std_logic; Q :out std_logic); end RS_ASYNC; architecture ARCH_RS_ASYNC of RS_ASYNC is signal X :std_logic; begin X <= '0' when R='1' and S='0' else '1' when R='0' and S='1' else X when R='0' and S='0' else '-'; Q <= X; end ARCH_RS_ASYNC;

Fonctions synchrones :
Bascule D :
LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.std_arith.all; entity D_FF is port (H,R,D :in std_logic; Q :out std_logic); end D_FF; architecture ARCH_D_FF of D_FF is signal X :std_logic; begin process(H,R) begin if R='1' then X <= '0'; elsif (H'event and H='1') then X <= D; end if; end process; Q <= X; end ARCH_D_FF;

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USE work. 2 . else X <= '-'. begin process(H) begin if (H'event and H='1') then if R='1' and S='0' then X <= '0'. elsif R='0' and S='1' then X <= '1'. end ARCH_RS_SYNC. Exemple de Programme en VHDL Comme pour la bascule RS asynchrone. Q <= X. USE ieee. architecture ARCH_RS_SYNC of RS_SYNC is signal X :std_logic.R. end if.std_logic_1164.all. end RS_SYNC.By B. elsif R='0' and S='0' then X <= X.std_arith. Ceci correspond au schéma suivant. end if.all. le logiciel a choisi Q = 1 pour l'état R = S = 1.S :in std_logic. end process.Baha Eddine Bascule RS synchrone : LIBRARY ieee. entity RS_SYNC is port (H. Q :out std_logic).

elsif (H'event and H='1') if K='1' and J='0' then elsif K='0' and J='1' elsif K='1' and J='1' else X <= X. architecture ARCH_JK_FF of JK_FF is signal X :std_logic. end if.R) begin if R='1' then X <= '0'.J. end ARCH_JK_FF.K :in std_logic. then X <= not X. Q <= X. entity JK_FF is port (H. 3 . USE work. end JK_FF. USE ieee.std_logic_1164.R.Baha Eddine Bascule JK : LIBRARY ieee. Exemple de Programme en VHDL then X <= '0'. end if.By B.all.std_arith. then X <= '1'. begin process(H. end process. Q :out std_logic).all.

all. end if. begin process(H.By B. Les équations obtenues se traduisent par le schéma donné ci-contre. Q :out std_logic). sinon. On voit clairement apparaître le rôle du OU exclusif. end T_FF. end process. elseif (H'event and H='1') then if T='1' then X <= not X. USE work. Exemple de Programme en VHDL architecture ARCH_T_FF of T_FF is signal X :std_logic. en D on obtient !Q. on obtient Q.R) begin if R='1' then X <= '0'. Si T vaut 1. Q <= X.Baha Eddine Bascule T : LIBRARY ieee.R. end if.T :in std_logic. USE ieee.std_arith. entity T_FF is port (H.all. end ARCH_T_FF. 4 . else X <= X.std_logic_1164.

std_logic_1164.By B. end ARCH_DECOMPT4. end if. architecture ARCH_DECOMPT4 of DECOMPT4 is signal X :std_logic_vector(3 downto 0).R) begin if R='1' then X <= "0000". end if. end COMPT_4. elsif (H'event and H='1') then X <= X .all. elsif (H'event and H='1') then X <= X + 1. entity DECOMPT4 is port (H. end ARCH_COMPT_4. entity COMPT_4 is port (H. Q <= X.R) begin if R='1' then X <= "0000". Décompteur synchrone : LIBRARY ieee. begin process(H.all. USE ieee. end process. Q <= X. end DECOMPT4.R :in std_logic.all.R :in std_logic. architecture ARCH_COMPT_4 of COMPT_4 is signal X :std_logic_vector(3 downto 0).all.Baha Eddine Exemple de Programme en VHDL Fonctions de comptage : Compteur synchrone : LIBRARY ieee. end process.std_arith.std_arith. 5 . Q :out std_logic_vector(3 downto 0)).1. USE work. USE work. Q :out std_logic_vector(3 downto 0)). begin process(H. USE ieee.std_logic_1164.

6 . entity MODULO10 is port (H. architecture ARCH_MODULO10 of MODULO10 is signal X :std_logic_vector(3 downto 0). USE work.all. end MODULO10.By B.R.Baha Eddine Compteur décompteur synchrone : LIBRARY ieee.R) begin if R='1' then X <= "0000". end if. architecture ARCH_UPDOWN4 of UPDOWN4 is signal X :std_logic_vector(3 downto 0). end ARCH_UPDOWN4. else X <= X + 1. begin process(H. Q :out std_logic_vector(3 downto 0)).all. USE ieee.all.UD :in std_logic. begin process(H. end if.1.std_logic_1164. USE ieee. Q <= X. elsif (H'event and H='1') then if X >= 9 then X <= "0000". end process. elsif (H'event and H='1') then if UD='0' then X <= X .all. Exemple de Programme en VHDL Compteur synchrone modulo N : LIBRARY ieee. USE work.R) begin if R='1' then X <= "0000". else X <= X + 1.std_arith. end UPDOWN4. Q <= X. end process.R :in std_logic. Q :out std_logic_vector(3 downto 0)).std_logic_1164. entity UPDOWN4 is port (H. end if. end if. end ARCH_MODULO10.std_arith.

all. OUT_SERIE :out std_logic). else Q <= Q.std_arith. elsif (H'event and H='1') then if EN = '1' then Q <= Q(2 downto 0) & IN_SERIE. end DECAL_D. entity DECAL_DE is port (H. begin process(H. USE ieee. USE ieee. end if.all. USE work.R) begin if R='1' then Q <= "0000".all. OUT_SERIE :out std_logic). end process. end if.R.R) begin if R='1' then Q <= "0000". elsif (H'event and H='1') then Q <= Q(2 downto 0) & IN_SERIE.EN. entity DECAL_D is port (H.IN_SERIE :in std_logic. end process. end ARCH_DECAL_DE.IN_SERIE :in std_logic. architecture ARCH_DECAL_D of DECAL_D is signal Q :std_logic_vector(3 downto 0).std_arith. USE work. OUT_SERIE <= Q(3). OUT_SERIE <= Q(3). begin process(H.R.std_logic_1164.all.std_logic_1164.By B. 7 . architecture ARCH_DECAL_DE of DECAL_DE is signal Q :std_logic_vector(3 downto 0). end DECAL_DE. end if.Baha Eddine Exemple de Programme en VHDL Registres à décalage : Registre à décalage à droite : LIBRARY ieee. end ARCH_DECAL_D. Registre à décalage à droite à autorisation d'horloge : LIBRARY ieee.

IN_OUT. end process. end DECAL_DG. OUT_IN <= Q(3) when SENS = '1' else 'Z'. IN_OUT <= Q(0) when SENS = '0' else 'Z'.std_arith. USE work.std_logic_1164. Exemple de Programme en VHDL architecture ARCH_DECAL_DG of DECAL_DG is signal Q :std_logic_vector(3 downto 0).SENS :in std_logic. end if.R) begin if R='1' then Q <= "0000".all. USE ieee.OUT_IN :inout std_logic). begin process(H.all.By B.R. else Q <= OUT_IN & Q(3 downto 1).Baha Eddine Registre à décalage à droite ou à gauche : LIBRARY ieee. elsif (H'event and H='1') then if SENS = '1' then Q <= Q(2 downto 0) & IN_OUT. entity DECAL_DG is port (H. 8 . end if. end ARCH_DECAL_DG.

IN_SERIE :in std_logic. USE ieee. OUT_SERIE <= Q(3). end ARCH_DECAL_DE. begin process(H. 9 . end process. OUT_SERIE :out std_logic).By B.R.std_logic_1164. end if. USE work. entity DECAL_DE is port (H.std_arith. elsif (H'event and H='1') then if EN = '1' then Q <= Q(2 downto 0) & IN_SERIE. else Q <= Q.all.Baha Eddine Registre à décalage à droite à autorisation d'horloge : LIBRARY ieee.R) begin if R='1' then Q <= "0000". end if.all. end DECAL_DE. Exemple de Programme en VHDL architecture ARCH_DECAL_DE of DECAL_DE is signal Q :std_logic_vector(3 downto 0).EN.

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