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Introduction

Power dissipation of digital systems have been continued

**to be focused on hardware design.
**

The manner in which software uses and directs the

**hardware can have a substantial impact on the power dissipation.
**

No efficient and accurate tools to estimate overall effect of

**software design on power dissipation.
**

2

Gokul B S

Program’s energy dissipation is proportional to the number of execution cycles of the program. Gokul B S 3 .Sources of SPD Memory system takes 1/10t to 1/4th fraction of the power budget. Control logic and clock distribution. Data paths in ALUs and FPUs. System buses with large switching activity. More sensitive DSP power applications such as video processing.

> Too slow for low power optimization.Use gate level simulation and power estimation tools. Gate level Power Estimation > Most accurate method available assuming detailed gate level description is available. but more important in evaluating the power dissipation behavior of a processor design.Software Power Estimation Lower level approach . Higher level approach – Estimate power based on frequency of execution of instruction sequence. Gokul B S 4 .

. Gokul B S 5 . input data to a program. > Less precise but much faster > Is implemented in a Power Estimation Simulator called ESP(Early design Stage Power and performance simulator). > Requires knowledge about architecture of processor. opcodes for instruction set. etc.Software Power Estimation Architectural Level Power Estimation contd.. Bus Switching Activity > Bus activity is assumed to be representative.

.. for( i=0. i<n. With the help of for loop. 2. for ( i=0. Gokul B S 6 . i+=2) sum_even+=i. i++) if(i % 2 == 0) sum_even+=i. 1. i<n.Software Power Estimation Instruction Level Power Analysis contd.

a typical problem is to structure software in a way that maximizes the available parallelism.Software Power Optimizations A prerequisite to optimizing a program for low power must always be to design an algorithm that maps well to available hardware and is efficient for the problem at hand in terms of both time and storage complexity. Gokul B S 7 . Algorithm Computations to match Computational Resources In parallel processor applications.

Gokul B S 8 . In low-power DSP synthesis. a typical problem is to design an algorithm to allow a circuit implementation that minimizes power dissipation given throughput and area constraints.Algorithm Computations to match Computational Resources Parallel computing resources can then be used to speed up program execution. Often a low-power DSP design will also exploit parallelism in an algorithm. but the objective is to shorten critical paths so that supply voltages can be lowered while maintaining overall performance.

1 is a sensible approach. Parallelizing the summation would only force us to use additional registers to store intermediate sums. Gokul B S 9 . then Figure 8. If only one adder is available. Algorithm Computations to match Computational Resources .

One Adder Gokul B S 10 .

Gokul B S 11 .2 makes sense because it permits two additions to be performed simultaneously. then the algorithm illustrated in Figure 8.Algorithm Computations to match Computational Resources If two adders are available.

Two Adders Gokul B S 12 .

the principle is still applicable. However. The basic principle is to try to match the degree of parallelism in an algorithm to the number of parallel resources available. Gokul B S 13 . one cannot manipulate the parallelism of an algorithm quite so conveniently.Algorithm Computations to match Computational Resources In the general case.

Minimizing Memory Access Costs Gokul B S 14 .

Minimizing Memory Access Costs Gokul B S 15 .

Minimizing Memory Access Costs Gokul B S 16 .

Minimizing Memory Access Costs Gokul B S 17 .

Instruction Selection and Ordering Similar to gate input reordering Gokul B S 18 .

Kaushik Roy and Sharat C Prasad. Low-Power CMOS VLSI Circuit Design.com/files/get/39f8aa41/ Gokul B S 19 .Reference 1. 2009 2. http://uploading. Wiley Student Edition.

THANK YOU Gokul B S 20 .

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