PUNJABI UNIVERSITY, PATIALA

REVISED SCHEME AND SYLLABI FOR

MASTER OF TECHNOLOGY (ELECTRONICS AND COMMUNICATION ENGG.) REGULAR / PART TIME (SEMESTER SYSTEM) YEAR 2010-2011

(Electronics & Comm. Regular/Part-Time. BOS: 15. LAB SELF STUDY & SEMINAR PROJECT DISSERTATION MEC-401 DISSERTATION Page 2 of 7 . Patiala. Year 2010-2011 LIST OF CORE COURSES MEC-101 MEC-102 MEC-103 MEC-104 MEC-105 MEC-106 WIRELESS AND MOBILE DATA COMMUNICATION OPTICAL COMMUNICATION SYSTEM VLSI DESIGN MICROCONTROLLERS AND EMBEDDED SYSTEMS ADVANCED DIGITAL SIGNAL PROCESSING RESEARCH METHODOLOGY LIST OF ELECTIVE COURSES MEC-201 MEC-202 MEC-203 MEC-204 MEC-205 MEC-206 MEC-207 MEC-208 MEC-209 MEC-210 MEC-211 MEC-212 MEC-213 MEC-214 MEC-215 MEC-216 MEC-217 MEC-218 MEC-219 MEC-220 MEC-221 MEC-222 ANTENNA SYSTEM ENGINEERING DIGITAL IMAGE PROCESSING AND ANALYSIS INFORMATION THEORY AND CODING EMI AND EMC TECHNIQUES SEMICONDUCTOR DEVICES AND MODELING ARTIFICIAL NEURAL NETWORKS AND FUZZY SYSTEMS MEMS AND MICROSYSTEMS TECHNOLOGY TELECOMMUNICATION SWITCHING SYSTEMS AND NETWORKS PROGRAMMABLE LOGIC CONTROLLER NANOELECTRONICS DEVICES ENGINEERING PARALLEL COMPUTING FUNDAMENTALS SPEECH PROCESSING COMPUTER SYSTEM ARCHITECTURE MICROELECTRONICS TECHNOLOGY ADVANCED DIGITAL SYSTEM DESIGN ADVANCED MICROPROCESSORS AND INTERFACING MULTIMEDIA COMPRESSION TECHNIQUES MICROWAVE INTEGRATED CIRCUITS GLOBAL TRACKING AND POSITIONING SYSTEMS COMMUNICATION NETWORK SECURITY RF SYSTEM DESIGN DATA AND COMPUTER COMMUNICATION NETWORKS SEMINAR AND MINOR PROJECT MEC-301 MEC302 MEC-303 ELECTRONICS ENGG.Punjabi University.).2010 M.2.Tech. Engg.

Design Cycle. Lectures to be delivered: 45-55 Instructions for paper-setter: The question paper will consist of five sections A. CAN. Engg. B. SECTION-A Introduction: The Overview of 8051 Microcontroller Family. References: 1. Assembly Language Programming: communication.Tech. Serial and Parallel Communication Between Networked Multiple Devices Using I2C. C and D of the question paper and the entire section E. Timer and Counting Devices.2010 M. Issues in Embedded System Design. Patiala. C and D will have two questions from the respective sections of the syllabus. Processor and Memory Organization: Structural Units in a Processor. ISA.Kenneth J. C. Interrupts Programming. Section E will have one question with 10 short answer objective type parts. “Embedded Systems. Design Issues in system Development Process. Instructions for candidates: Candidates are required to attempt one question each from sections A. I/O instructions. SECTION-B I/O Programming. Raj Kamal. Instruction Set: Arithmetic. The Inside of 8051 Microcontroller. Mazidi. which will cover the entire syllabus uniformly.” Tata McGraw Hill 3. All questions will carry same marks. (Electronics & Comm. Software. Pearson 2. Pin Description of the 8051. Processor in the System. SECTION-D Devices and Buses: I/O Devices. Use of Target System and In-Circuit Emulator. Case Studies. and Embedded System Examples. Year 2010-2011 MEC-104 MICROCONTROLLERS AND EMBEDDED SYSTEMS LT P 3 1 0 Maximum Marks: 70 Minimum Pass Marks: 40% Maximum Time: 3 Hrs. Interfacing Processor. Hardware-Software Co-design in an Embedded System: Embedded System Project Management.Punjabi University. D and E.2. Hardware Units. etc.). “The 8051 Microcontroller. B. PCI and advanced I/O Buses. Processor Selection for Embedded System. BOS: 15. B. Serial SECTION-C Introduction to Embedded Systems: An Embedded System. Software tools for Development of Embedded System. Memories and I/O Devices. Ayala. Addressing Modes. “The 8051 Microcontroller and Embedded Systems.” Penram International Page 3 of 7 . Timer/Counter Programming. Regular/Part-Time. Sections A. Memory Map. Logic and Single Bit Instructions.

Digital Signal Processing By Mitra 5. Quantization of filter co. Oppenheim & Schafer. Palan.” PHI 4.). classification of signals and systems. Sections A. equations. Analysis and Digital Filter Design. Frequency analysis of discrete time signals and LTI Systems.efficients. B. Johan G. Section E will have one question with 10 short answer objective type parts. N. References: 1. Using windows methods. “Digital Signal Processing Principles. B. “ Digital Signal Processing: Theory. Nair. Fourier and Z Transforms: Properties of Fourier and Z transforms. Engg. Matched-z Transformation and Approximation of Derivatives Methods Characteristics of commonly used Analog Filters.2. Lectures to be delivered: 45-55 Instructions for paper-setter: The question paper will consist of five sections A. Bilinear Transformation.” PHI Page 4 of 7 . G. Architecture TMS 320C54X and ADSP 2100 DSP processors. “Digital Signal Processing. Patiala. D and E. convolution. C. SECTION-B Discrete Fourier Transform: Definition and properties of DFT. Fast Fourier Transform: FFT algorithms and their applications. which will cover the entire syllabus uniformly. Algorithms and Applications. BOS: 15. Linear filtering methods using DFT. linear filtering approach to computation of the DFT. C and D of the question paper and the entire section E. Proakis and Dimitris G. SECTION-A Introduction: Review of.Tech. Applications of DSP: Applications of DSP in Communications. IIR Filter Design: IIR filter design by Impulse invariance. Manolakis. All questions will carry same marks. SECTION-C Implementation of Discrete Time systems: Structure of IIR and FIR systems. FIR Filter Design: Symmetric & Antisymmetric FIR filter design by Frequency Sampling. Year 2010-2011 MEC-105 Maximum Marks: 70 Minimum Pass Marks: 40% ADVANCED DIGITAL SIGNAL PROCESSING L T P 3 1 0 Maximum Time: 3 Hrs.Punjabi University. Biomedical and in Radars with case studies. difference correlation.2010 M. Instructions for candidates: Candidates are required to attempt one question each from sections A. state space analysis and structures. Frequency analysis of signals using the DFT. (Electronics & Comm. C and D will have two questions from the respective sections of the syllabus. image processing. SECTION-D DSP Processors: Introduction to DSP Processors. speech processing. B. “Digital Signal Processing.” Tech Max Publications Pune 3. Regular/Part-Time.” PHI 2.

B. Instructions and arithmetic pipelines. CPU Structure. M. Year 2010-2011 MEC. Memory interleaving. CPU.1. computer System Buses. “Computer Architectures". DMA. Hardwired and Micro programmed Control. McGraw-Hill 2. ALU. Section E will have one question with 10 short answer objective type parts. SECTION-A Basic Computer Organization: Introduction.213 COMPUTER SYSTEM ARCHITECTURE LTP 3. registers & stacks. Sections A.2. “Computer Organization and Architecture". RISC and Superscalar Processors. Parallelism in uniprocessor system. (Electronics & Comm. B. Hayes.2010 M. Addressing modes and Formats. SECTION-C Memory and I/O Devices: Internal & External memory. D and E. M. B. BOS: 15. Mano. Patiala. Organization & Architectural classification. parallel processing algorithms. Virtual & High-Speed memories. “Computer System Architecture". SECTION-B CPU Instruction Sets: Characteristics.0 Maximum Marks: 70 Minimum Pass Marks: 40% Maximum Time: 3 Hrs. C and D will have two questions from the respective sections of the syllabus. Processor & Register Organization. C. All questions will carry same marks. I/O Devices & Modules. Morgaon Kauffman Page 5 of 7 . which will cover the entire syllabus uniformly. Lectures to be delivered: 45-55 Instructions for paper-setter: The question paper will consist of five sections A. References: 1. PHI 4. Functions. Array processor. Regular/Part-Time. Stallings.). Patterson and Hennessy. Control Unit. Engg.Punjabi University. Computer Evolution and Performance.Tech. PowerPC. Pearson Education 3. Computer Arithmetic: Integer & Floating Point Arithmetic. Instructions for candidates: Candidates are required to attempt one question each from sections A. Pentium processors etc. Pipelining and vector processing. Programmed & Interrupt driven I/O. C and D of the question paper and the entire section E. John P. SECTION-D Parallel Processing and Pipelining: Introduction. “Computer Architecture and Organization".

security associations. Sections A. SECTION-D SECURITY SYSTEM: Intruders. (Electronics & Comm.0 Maximum Time: 3 Hrs. Viruses. William Stallings. Engg. Trusted systems. "TheRC5.Prentice Hall of India. SECTION-A CONVENTIONAL ENCRYPTION: Introduction.TC5-CBC-PAD and RC5-CT5 Algorithms. Encryption algorithms. RSA algorithm.2010 M. PUBLIC KEY ENCRYPTION AND HASHING: Principles of public key cryptosystems. confidentiality. Diffie-Hellman Key Exchange. All questions will carry same marks. SECTION-C WEB SECURITY: Web security requirement. which will cover the entire syllabus uniformly. Lectures to be delivered: 45-55 Instructions for paper-setter: The question paper will consist of five sections A.October1996. BOS: 15. antivirus techniques. block cipher. References: 1. Data Encryption Standard. Regular/Part-Time. 1999 2. Steganography. transport layer security. New Delhi. D and E. firewall design. Worms. Digital signatures. Patiala. R. Key Management. Year 2010-2011 MEC-220 COMMUNICATION NETWORK SECURITY Maximum Marks: 70 Minimum Pass Marks: 40% LTP 3. secure sockets layer. Conventional encryption model."Cryptography and Network security". Baldwin R and Rivest. 2nd Edition . digital Immune systems. SECTION-B IP SECURITY: IP Security Overview.). C and D of the question paper and the entire section E. B. B.RC5-CBC. B.Tech.RFC2040".1. Page 6 of 7 . secure electronic transaction. Instructions for candidates: Candidates are required to attempt one question each from sections A. authentification Header. Elliptic curve cryptology.Punjabi University. Key distribution. C. Section E will have one question with 10 short answer objective type parts.2. dual signature. Security payload. IP security Architecture. C and D will have two questions from the respective sections of the syllabus. Hash and Mac algorithms. message authentification and Hash functions.

quality of service. shortest path. Internet transport protocols. Virtual Circuits Network Reference Models: OSI and TCP/IP. SECTION-A Data Communication Techniques: Synchronous-Asynchronous Transmission. All questions will carry same marks. Davie. L. Pearson Education 4. Session layerDialogue management. K. Ross. SECTION . NFS E.S. W. Data encoding Techniques Communication Networks: Circuit switching.L. BOS: 15. multiplexing. Engg. Pearson Education 2. CIDR. Telnet. Message switching. B. LAN Technologies. C. Section E will have one question with 10 short answer objective type parts. “Computer Networks: A Systems Approach”. (Electronics & Comm. Congestion control. Transmission Media. flow control and buffering. addressing.connection oriented and connectionless.25. Regular/Part-Time. B. Year 2010-2011 MEC. token bucket. Kurose. traffic shaping. APR. “Computer Networking: A Top-Down Approach featuring the Internet". data link layer in the Internet (SLIP. Layered architecture SECTION . synchronization and remote procedure call.” Data and Computer Communications". SNMP. Peterson. SECTION . B. SMTP and World Wide Web References: 1. OSPF.Punjabi University. connection management.D Presentation Layer: date representation. framing.). Patiala. data compression. J. which will cover the entire syllabus uniformly. TFTP. Sections A. Lectures to be delivered: 45-55 Maximum Marks: 70 Minimum Pass Marks: 40% Instructions for paper-setter: The question paper will consist of five sections A. flow control.B Data Link Layer: Design issue. D and E. RARP. Packet Switching. ICMP.mail. S. C and D of the question paper and the entire section E. SDLC. load shedding. IP protocol. Link state routing. B. fragmentation. internet architecture and addressing. Tanenbaum. PPP) Network Layer: Routing Algorithms. Impairments. PHI 3. and multicast routing. error control. Digital Transmission.TCP and UDP. Stallings. "Computer Networks". X. network security and cryptography. C and D will have two questions from the respective sections of the syllabus. IPv6. Pearson Education Page 7 of 7 .C Transport and Session Layer: Transport Service. Application Layer: DNS.2010 M. A. Instructions for candidates: Candidates are required to attempt one question each from sections A. BGP.2. distance vector routing. HDLC. internetworking.1.W.0 Maximum Time: 3 Hrs. leaky bucket. choke packets.F.Tech.222 DATA AND COMPUTER COMMUNICATION NETWORKS LTP 3.

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