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C. Efstathiou' & H. T. V e r g ~ s * , ~

'Department o Informatics, TEI o Athens, Ag. Spyridonos St., 12210 Egaleo, Athens, Greece. f f 2 Computer Engineering & Informatics Dept., University of Patras, 26 500 Greece 3 Computer Technology Institute, 3 Kolokotroni Str., 262 21 Patras, Greece

Abstract

In this paper we derive a novel modified Booth multiplier architecture which is based on 1's complement arithmetic. We also extend our theory to the design of modulo 2"-1 multipliers. The proposed 1's complement modified Booth multipliers have an execution latency which is approximately the same as that offered by their 2's complement counterparts with a completely regular structure. Therefore, pipelined implementations of them can be derived in a straightforward manner. The proposed modified Booth modulo 2"-1 multipliers can find great applicability in Residue Nvmber System applications.

1. Introduction

Multipliers are met in almost all modern special and general purpose processors. They can be implemented either as strictly serial or serial-parallel or all parallel [ 11. The advances in VLSI implementation technology, as well as the need for higher throughput and shorter latencies have made the parallel multipliers the only attractive alternative for contemporary integrated circuits. In a parallel multiplier all partial products are generated in parallel and then added successively until the final product is derived. The techniques that have been presented for speeding up the multiplication process aim towards two main directions : 1) The reduction of the number of the generated partial products. The Modified Booth algorithm [2, 31 reduces the number of the partial products that need to be added to approximately the half. 2) The speed-up of the summation of the partial products. Carry-Save Adder (CSA) arrays, Wallace trees [4] and Dadda parallel counters [ 5 ] are among the most commonly used structures. However, when the multiplier operands are wide enough (for example in floating-point multiplication) the above techniques may not be adequate for effective reduction of the multiplier's latency. For spreading and "hiding" the latency of the multiplication over more CPU cycles pipelining is commonly used. However, the intrinsic architecture of the modified Booth algorithm which is based on 2's complement arithmetic is not suitable for pipelined implementations [6]. The main reasoning behind this claim is the 2's complement nature of the algorithm. That is, the generation of the 2's complement of a number A requires its inversion and the addition of 1. The addition of 1 at each stage may make the time to generate the partial products unaffordable. Therefore, a common solution often employed when a multioperand CSA is used, is to pass the addition of these 1s-to the 637 0-7803-6542-9/00/$10.000 2000 IEEE

final stage adder. The resulting architecture however, is hard to pipeline without significant area and performance penalties. The problem of pipelining a Booth multiplier is examined in [6] but focus is mostly given on the power - performance ratio. When Wallace trees or Dadda counters are used for the addition of the partial products, the resulting multiplier can neither be easily pipelined nor has a regular layout. Motivated by the above, we present a new modified Booth architecture for 1's complement arithmetic. Our design is based on the following observations : 0 In 1's complement arithmetic the addition of 1 is not required to get the complement of a number and 1's complement addition can be done as fast as that of 2's complement arithmetic [7, 81. The proposed 1's complement multipliers have completely regular structure and can be pipelined straightforwardly. Pipelined versions of the proposed 1's complement multipliers can be used as a core for the multiplication of floating-point numbers. In the vast majority of modern computer systems the IEEE standard [9] for the representation of floating-point numbers is used. Since each mantissa in this representation is at least 23 bits wide the execution latency of the multiplier will be long even when the speed up techniques mentioned earlier are used. Therefore, a simple to derive pipelined implementation of the proposed 1's complement Booth multipliers can be used effectively in this case. Modulo arithmetic is used in several applications of the computer systems. Modulo 2"-1 multipliers are used today in digital signal processors which are based on the residue number system (RNS) [lo-121 and cryptography [ 13, 141. For modulo multiplication various ROM-based solutions using look-up tables have been proposed and compared [15]. Modulo multipliers which are based on CSA or adder trees have been presented in [16]. The only attempt for applying a Booth algorithm to modulo 2"-1 multipliers was presented in [ 171. In this paper we give the formal foundation for modified Booth modulo 2"-1 multipliers as well as indicative results when these are used in RNS arithmetic. In the RNS system multiplication is performed in parallel among three channels that usually are chosen to perform modulo 2", 2"-1 and 2"+1 multiplication. In such a system, the proposed multipliers are highly applicable.

2. Preliminaries

In an unsigned representation the n-bit binary vector X,.~X,.~ ... xlx0 represents the integer value X = Cxi2'

+(2"-I)].1-2bn) + (-bn. al % b e a signed binary number in 1's complement representation.~X.. .. In the case where the 1's complement multiplier is used as a block of a floatingpoint multiplier.. The latter can be expressed as : B =-b. + b12 + b o + b n = + = 2"(bn+b. a.. = =-bn2"+I+ b..+b.(2"+'-1) + b.12"-' + bn-22"-' + .2" + b.l) .+. 3..a. ..lbn..2b21+1) be viewed as an element can of the set {-2. the product AB can be ) expressed as : AB = A c 2 " (bzl-.. namely the all 0 and the all 1 vector.2. 2"-21..2 .2 .l-2b.. Relation ( I ) reveals that a modified Booth 1's complement multiplier can be designed following the block diagram of Fig... 81.. an. Sign (a) a.which lies within the range [0. Since 1's complement arithmetic is used here. b.2bzi+. 11 1 11 0 I 11 1.= =2"(b.12" .2"+' + b. and (bZ1. . a final 1's complement adder with single representation of zero [7..-. b. I .2" + b. Let A be the multiplicand and B the multiplier. According to the above.32n-2) 638 b21-lyp b..+b. b.. 1 presents a block diagram of any multiplier implementing the modified Booth's algorithm..... a. The comparison of the proposed structure against a 2's complement multiplier structure reveals that both require T . denote the sign of the corresponding operand). Consider the signed binary numbers A = anan.b.111 or 000 . AB = I PP..12"-' + bn-22n-2 . 1 as an element of the set {-2.. Mulhplicant A b. These partial products are then reduced to two by the Partial Products Addition Array block. a. .-2bl) That is.2"-' + + bn.+ b21. blbo in 1's complement representation to be multiplied (a. 8.. ) .. Figs 2a and 2b present sample implementations. We have to note that very efficient 1's complement adder designs have been proposed in [7. + I . The addition of the partial products can be done as in the 2's complement multipliers by either a CSA or tree structures.. +1. + b12 + bo + b..1 = I .. +(2"-l)].12"-' + . where b. (1) Partial Products Addition Array Final Result Forming Adder where PPI = A221(b21. B = c 2 " (bZi-' + b.2" + b.2" + Cxi2' E [-2". To this end we utilize the following Lemma (the proofs of the Lemmas are given in [IS]): Lemma 1. the same vector represents the value X = -x..a. 3 presents a 8x8 modified Booth 1's complement multiplier with a CSA...+l. + b22* + b12 +bo= = -b.l-2b... . . 0.1)+...bn.2+b..a. . Product P Fig. Then : M =a...) + 2"-2(b.... -1..(2"-1) + bn.. Fig.That is.l-2bn) .-2b21+I) the partial are products which are derived according to Lemma 1 and summarized in Table I (x' is used to denote the complement of bit x). 1's complement modified Booth multipliers For introducing our 1's complement modified Booth multipliers we will show that the number of partial products in a 1's complement arithmetic multiplication can be reduced. Sign (b) b..aD pp. Fig.32"-' + . 171 must be used. In the widely used 2-bit recoding form of the algorithm successive triplets of the bits of multiplier B are examined and encoded by the Booth encoder block of Fig..+2}. + + (bo+b.... xlxo represents the value X = -xn(2"1) + Cxi2' E [-(2"-I)..O. -1. + b12 +bo+ b. a. I . = + .. Encoder (a) and selector (b) blocks.). 2"-I].a. In a modulo 2"-1 number system the same vector represents the value X Zn-1 = cxi2' Zn-1 which lies within the range [0.+ b. The Final Result Forming Adder adds the two remaining quantities and produces the final result.. therefore we will not consider this further in this work.3-2bn.. 2. whereas in 2's complement representation. every carry-out bit must be fed back as a carry-in to the adder array. + + + b12 + bo+ b.. I I I I bn-32n-3 .~ . Let A = a. + b22' +bI2 + bo = =-b. the number zero has two representations. .+. 1. ..)+ 2"-2(bn-2+bn. ..= . The encoded information along with the multiplicand A are then used for forming the partial products by the Booth selector block.-..- = 2"(bn+b..12"-' + .12"-' + . +2}. =2"(b..+.2b.lan. + bo+ b.b. In 1's complement representation the (n+l)-bit binary vector X.l-2b.X... = I + = I A 2" (bZl-.% and B = bnbn. In the second case..a. 000 Area and time efficient implementations of the encoder and the selector circuits can be derived when a 3-bit bus approach is used for their interconnection...2b. Modified Booth multiplier's block diagram Fig.~+b2. 1.

To this end we utilize the following Lemma : Lemma 2.~ + ~ i ( " .2 xlx0 (x.lan. a ~ n -.alo+2i(n-ljn 2+~i(n-~~~ HallAdder 0 Selglor 0 Full Adder 1 Encodel Fig. B = Obn. = A 2" b2i-l + b. 4. Modulo 2"-1Modified Booth multipliers For high performance modulo multiplication dedicated multipliers are required which can be implemented as combinational or pipelined circuits. 1. as it is obvious from this figure the proposed multiplier has a completely regular structure.. We will present indicative results confirming this in Section 5. Selector .21i (b2i-l + bZi. the multiplier B U can be expressed as : B = [221(b~1. leading zero. therefore pipelined implementations can be derived easily. 11 1 0 0 1 +A2 ' a ~ " . which are derived according to Lemma 2 and summarized in Table 11. For introducing our modulo 2"-1 modified Booth multipliers we will firstly show that the number of partial products can be reduced..2b2. for applying it to unsigned binary numbers. B.2.. 3. b...~xn. n 1 I where b. .~+b~1-2b~l+~)1. Modified Booth modulo 255 multiplier... 639 . 000 or 1 1 1.~ ~ .2b2i+l 12"-1~2"-1 = PP.Fig... as for example PI Pa P.approximately the same area and should offer similar execution times.+]... al%. Table 11.+1 I ( jZn-. . However. b... Pa P1 Pz P> Po to the two modulo 2"-1 numbers A.lbn. As a sample we present in Fig. : Full Adder : Encoder As shown in the previous section. Then : 1 212" -1 = x1 n-l+i (n-1 )I x I x' n-2+1 (n-111 I I+i(n-ljn x I0+1(n-lj. bn = 0). = /21. Let X = x.are the partial products of the multiplication. Since the modified Booth multiplication algorithm is based on signed binary number representations.. 4. 4 the modulo 255 multiplier.?.. is the sign bit) . The value of the product AB in modulo 2"-1 can be expressed as : The above analysis indicates that a modified Booth modulo 2"-1 multiplier can be designed following also in this case the block diagram of Fig.. = 0. these should first be transformed to positive binary numbers by adding a Half Adder 0 . . Recoded artial roducts 2i+lb~ib~i-1 Partial Product (PPi) 000 . a signed binary number in 1's complement representation. 1's Complement 8 x 8 multiplier. 3 if the partial product generation and product reduction has a delay close to that of the final adder a simple 30-bit register before the 1's complement adder can be utilized to spread the overall latency in two consecutive shorter cycles. blbo (a. that is A = Oan.xn. For example in Fig.

al. T. D. We expect and we will verify by actual implementations that corresponding 1's and 2's complement multipliers will offer the same performance and similar implementation area. 1985. For all the designs a 2-bit recoding scheme and a CSA reduction was adopted. June 195I . October 1975. Zimmermann. of the 39'h Midwest Sym.. Vol. Results & Discussion In this paper we have presented a modified Booth 1's complement multiplier architecture. 34. "A suggestion for a Fast Multiplier". al. During synthesis the netlists were optimized for speed and as a secondary target the tool was instructed to try to recover as much area as possible. 14-17. vol. 8. 957-961. pp. in Proc. M. Rubinfield. 604-616. 2000/09/03. CAS-39.5 16. Capello and K. A.1180.5 17. Institute of Electrical and Electronics Engineers.64 12642. 'I. New York: IEEE. W. IEEE Trans. " 640 . G. July 1994. Computer Technology Institute Technical Report No. No. April 1999. on Circuits and Systems11. 1301-4.. 5. "Efficient VLSI Implementation of Modulo (2"+1) Addition and Multiplication". Modified Booth' 1's Complement and Modulo 2"-1 Multipliers". pp. Efstathiou and H.0V).95 12254.2 1 5. Kalamboukas. Area and Delay results of 2's and the proposed 1's complement multipliers 2's com lement 1's com lement Operands' Length Area Delay Area Delay (Bits) 4 1 353. Wang. March 1994. pp. et. 41 (7). K. following the procedure described earlier. Architecture and Design. Adelaide. A. Therefore we expect that the modulo 2"-1 multipliers will offer similar performance and implementation area. 41. Sonderstrand et. PhD. Wu. 1997 R. Rao. 1 have obtained for modulo 2"-1 multipliers with inputs of 4. vol. No. "Area-Time Efficient Modulo 2"-1 Adder Design". C. A. Efstathiou et. 16 and 32 bits. June 1998. L. IEEE Standard for Binary Floating-point Arithmetic. Hwang. "High-speed Regular-Layout Modulo 2". July 2000. vol. All results associated with circuit delay were gathered assuming worst case process parameters and are measured in ns. "Fast and Flexible :-. 4. August 1992. Vol.1 Adders". For realistic measures the conventional (integer) and the proposed 1's complement multipliers were described in HDL for operand lengths of 4.5. "A Look-Up Table VLSI Design Methodology for RNS Structures used in DSP Applications". EC-13. IEEE Press.7 10. of 14th IEEE Symp. 8. making them highly applicable in a RNS system. pp. May 1983. IEEE Trans.. pp. (4). 236 . on Circuits and Systems. P. on Circuits and Systems-11. pp. pp. All designs were mapped to the AMS CUB implementation technology (0. We also extended our developed theory for the design of modulo 2"-1 Booth multipliers.235. 673-680. B. Thesis. Steiglitz. as for example IEEE floating point mantissas multiplication. "A Proof of the Modified Booth Algorithm for Multiplication". VLSI Architectures f o r Computations in Finite Rings and Fields. "An algorithm for multiplication modulo 2N-l Proc.3 30. pp. 463467. vol. The proposed 1's complement multipliers however can be pipelined in a straightforward manner. A. pp. 1 179 . "A 177 Mbls VLSI Implementation of the International Data Encryption Algorithm".40 8 1130. al. L. Booth. Z.. P. Vol. 157 . M. ACM Trans. IEEE Trans. M.4 30. April 1992. Australia. C-24. C. Electronics Letters.lO 1180. S. A. al.33 1 370. 8. al. IEEE Trans.307. C. Miller. 303 . "New multipliers modulo 2"-I".240. IEEE Joumal of Solid-state Circuits. and Applied Mathematics. 1979. ~ 1 area results are in mils2. The structure of the proposed 1's complement modified Booth multipliers resembles that of the 2's complement ones but it is also completely regular. pp.7 10. Jullien.64 12642. J.2 I 5. CAS-34. vol. 2-metal layer. 29 (3). on Computers. June 1987. 3. "A Signed Binary Multiplication Technique". Vergos.6pm. John Wiley and Sons Publishers. on Computer Systems 1(2). 1014-1015..4 30. A. "Modified Booth pipelined multiplication". IEEE Trans. Bayoumi et. Computer Arithmetic : Principles. therefore they may be more applicable in cases of long operands in which spreading the multiplication latency among several cycles is imperative. Residue Number System Arithmetic : Modern Applications in Digital Signal Processing.3 30. on Computers. on Circuits and Systems. "A VLSI Layout for a Pipelined Dadda Multiplier". IEEE Standard 754-1985. References K. on Computers. pp. No. Mech.. A. New York. Results that completely verify our expectations are given in Table 111. et. 16 or 32 bits. R. 226 . pp. Skavantzos and P. Bayoumi. 158-167.42 32 12254. on Computers. Table IV presents the results that we [18] Architectures for RNS arithmetic decoding". vol. IEEE Trans. R. A. pp.09 3470. IEEE Trans. Wallace. Arithmetic. on Comp. Vol. C. Curiger. Swiss Federal Institute of Technology (ETH).42 I [13] [ 141 [15] Operands' Length Area Delay [16] [ 171 (Bits) 32 The structure of the proposed modulo 2"-1 multipliers also resembles that of the modulo 2" multipliers. 49. 1986. i [12] ~ ~ Table 111. Zurich 1993. Zimmermann et. Elleithy & M. 12. al.03 16 3170.174. February 1964.

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