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Chapter

2
System Hardware

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System Hardware
2.1 Overview Architecture Issues Bus Systems Memory Devices

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Overview
BSPs have responsibilities for all components in the hardware environment. Embedded hardware categories:
q

Architecture specic (caches, MMUs, interrupt controllers, and oating point hardware). Bus specic (Bus controllers, and bus bridges). Memory specic (memory controllers, and chips). Devices (architecture/bus/memory independent). Initialization. Access.

Support issues:
q q

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System Hardware
Overview 2.2 Architecture Issues Bus Systems Memory Devices

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BSPs and CPUs


Libraries for managing CPUs are part of the Tornado architecture module. Some CPU specics will be relevant for BSP development:
q q

MMU Support Cache Issues Interrupt Handling Floating-Point Support

Many of these specics will be important during the initialization phase of booting a VxWorks image.

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MMUs
Memory Management Units control memory access for:
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Allocating/de-allocating memory. Resolving cache coherency issues. Write protecting memory. Virtual memory swapping. Paging and segmentation. Garbage collection.

Requires RAM resident translation tables which map physical memory into a virtual memory address space. May be inappropriate for real-time applications due to latency increases and memory consumption. Unit is often on the same ASIC as the CPU.
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MMU Support
Booting VxWorks:
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MMU disabled until the wind kernel is activated. Build translation tables. Enable MMU.

In VxWorks a task does not include a translation table as part of its context:
q q

Tasks do not reside in virtual memory. Default virtual memory maps are global and at. Bundled MMU library. Optional virtual memory management product (provides programmatic access to MMU).
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MMU may be managed dynamically with:


q q

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Each translation table is a link list of physical memory containing its table and page descriptors. This why wind kernel must be running prior to initializing the MMU. The optional virtual memory management product is VxVMI. Will allow private memory contexts to be dened; and used on a per task basis if application requires this feature.

Caches
Fast memory interface between CPU and main memory. Reduces read/write access time for CPU and local bus activity. Most modern processors support separate data and instruction caches. Cache is accessed in quantized units called cache lines. Cache modes:
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Write through - Data written to cache by processor ushed to main memory. Copyback - Writes only to cache, conserves processor bandwidth.
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Caches - continued
Cache is located:
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On the same ASIC as the CPU - L1 cache External to the CPU ASIC - L2 cache Backside L2 cache - External L1 cache (with special bus to processor).

Some architectures provide cache management instructions, others bundle cache management with virtual memory support facilities. If cache is enabled, it is examined by the CPU for each memory access:
q q

If data is there - cache hit. If data is not there, access main memory- cache miss.
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Cache Issues
Cache coherency:
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Ideally cached information mirrors main memory. Bus master or device with DMA support may update main memory without updating cache. CPU may update cache without updating main memory, making information in main memory stale. Cache needs to be ushed when updated by CPU. Cache needs to be invalidated (and updated) when main memory is modied by bus master or DMA transfer. Snooping circuitry.

To maintain cache coherency:


q q

Copyback with snooping is fastest conguration.


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Cache Support
Booting VxWorks:
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Cache(s) disabled until the hardware environment is placed in a quiet state. Invalidate and congure cache mode. Enable cache(s) (before wind kernel is activated). Data cache / RAM - Bus master and DMA access to RAM. Instruction cache / data cache - Loader, debugger, and ISR connection routines. Shared cache lines - Multiple task access to cache.

Provide cache coherency for VxWorks:


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When MMU is enabled, cache management and mode control are supplied by an MMU library.
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Cache may be managed by bundled cache management library or optional virtual memory product.The optional virtual memory product is VxVMI.

Cache Support - continued


Cache coherency is maintained:
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Map off-board addresses as non-cacheable. MMU enabled - Routine to allocate cache aligned memory marked as non-cacheable (returned cacheable). MMU not enabled - Cache library support to ush and invalidate cache when necessary.

Architecture may have more than one cache implementation. Hardware environment could then support multiple cache systems.
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BSP must supply support for selecting the appropriate cache libraries. Linker must include needed cache library modules.
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Interrupt Handling
Hardware interrupt request and acknowledgment transactions are specic to:
q q

Hardware requesting interrupt service. CPU. System bus protocol(s). Determine which interrupt service is requested. Terminate device interrupt request upon IACK or device access.

Hardware device will:


q q

CPU will determine number of external interrupts and interrupt levels supported using external interrupt lines and/or interrupt controller.
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IACK - Interrupt Acknowledgment. Informs device that interrupt request has been received, usually tells device to stop requesting service, and provides interrupt number/vector to CPU. Device may be interrupt controller or device requesting service. Servicing a single hardware interrupt may require several IACKs or modifying device register bits. Internal interrupts (traps or exceptions) are an architecture module issue, not a BSP issue.

Interrupt Handling - continued


IACK cycles are a function of local bus protocol:
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Vectored - Automatic acknowledgment. Autovectored - Acknowledgment done in software. External interrupt line activated. Interrupt select register of interrupt controller. Interrupt select register on device. Combinations, often requiring interrupt service demultiplexing in software. Bits in a CPU status register. Interrupt mask on external interrupt controller.
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CPU will determine which ISR to execute based on:


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CPU will reset interrupt status info after ISR completes:


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Some hardware environments process interrupts through a cascaded chain of interrupt controllers requiring ISRs to reset or clear an interrupt controller at each stage.

Interrupt Handling Issues


Designing interrupt scheme for hardware environment:
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Interrupt priority levels. Association of interrupts with devices and/or device service requests. Number of ISRs - De-multiplex services in single ISR. CPU (and interrupt controller when present). Device specic (enable/disable, IACKs, etc.). Latency. Interrupt context and hardware negotiation. Connecting.
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Hardware support facilities:


q q

Interrupt service routines:


q q

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Interrupt Circuitry Guidelines


To minimize latency in handling interrupts, design efcient interrupt circuitry. Choose devices which provide interrupt vectors, with different vectors for each requested service. If not possible, one vector for device. Ability to enable/disable each interrupt source separately.
q q

Device interrupt control register. Interrupt controller.

Well documented and diagramed interrupt vector scheme.


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Interrupt Handling Support


VxWorks uses an interrupt table:
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ISRs must be connected to unique interrupt vectors after wind kernel is started. Table contains addresses for interrupt handlers.

VxWorks is interrupt aware, preventing the OS from providing blocking services at interrupt time. Device interrupts must be disabled before kernel is activated, and enabled after ISRs are connected. Architecture and device driver libraries:
q q

Provide ISR code. Provide hardware interrupt management code.


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A VxWorks interrupt handler is a small, fast code stub which saves the CPU interrupt context, calls a C language ISR, and restores the CPU context after the ISR returns. This handler also manages an interrupt context variable which allows VxWorks to be interrupt aware. Non Maskable Interrupts (NMI) are a special case:
q q

NMIs are usually only used to shutdown the system. NMIs must never make kernel calls - making kernel calls from a NMI service routine could jeopardize the integrity of the system.

Interrupt Handling Support continued


A BSP:
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Disables device interrupts at system start-up. Connects ISRs to interrupt table. Supplies interrupt level/vector bindings to devices. Supplies addresses and control values associated with hardware interrupt status and control registers. Supplies routine which transfers control to boot code if an ISR throws an exception.

BSP interrupt support should make device drivers as exible as possible so they can be reused in hardware environments with different interrupt structures.

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Floating Point Support


Support for oating-point operations:
q q

Floating-point/math co-processor(s). Software emulation.

VxWorks contexts do not save/restore oating-point registers by default:


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Tasks allow an optional context extension which will include oating point registers. ISRs and exception handlers use bundled routine to programmatically manage oating-point registers.

Architecture is responsible for oating-point support. Some BSPs will have conguration macros for FPU or software oating-point emulation.
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FPU is a Floating-Point Unit.

Additional Architecture Considerations


Additional architecture issues which may impact a BSP:
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Big-endian/little-endian byte ordering. Processor specic initialization. Register and memory alignment. Addressing mode constraints. TAS operations and external bus access.

Any of these issues may require BSP conguration macros to be dened.

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System Hardware
Overview Architecture Issues 2.3 Bus Systems Memory Devices

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Bus Systems
Buses are classied relative to the processor:
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Local bus (processor bus). External buses (all others). Multiple external bus systems. No external bus system. Cycles ((a)synchronous, multiplexed, etc.). Arbitration (bus-locking, priority levels, etc.). Data transfers (memory-mapped, I/O mapped, etc.). Data properties (width, big/little endian, etc.). Interrupt policies (generation, IACK, routing, etc.).
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Hardware environment may have:


q q

Bus system characteristics:


q q

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Local bus and external bus(es) comprise system buses.

Bus System Issues


BSP developer will need to be aware of bus protocols:
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Data transfer rates and formats. Bus requirements for DMA transfers. Interrupt protocols.

For hardware environments with multiple buses, bridge chips may connect the busses, and provide an interface for inter-operability:
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Data transfer. Interrupt services. Minimum initialization to boot VxWorks. Complete initialization to support application.
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Bus system initialization:


q q

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Bus System Support


Bus systems and bus bridges have device drivers. Generic device drivers should be decoupled from bus specic issues. A BSP provides conguration and access support for:
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Bus drivers. Bus bridge drivers. Generic drivers for bus resident devices. Bootstrap code identies local bus speed, initializes local CPU bus, and necessary bus bridges. Boot code/VxWorks completes initialization, particularly support for external buses.
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A BSP is responsible for bus initialization:


q

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System Hardware
Overview Architecture Issues Bus Systems 2.4 Memory Devices

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Memory Types
Memory types traditionally supported by embedded systems:
q q

RAM - Random Access Memory ROM - Read Only Memory Non-Volatile memory - NVRAM and Flash.

Memory types represent different technologies with different access characteristics, capabilities, and costs. Each memory type itself has multiple sub-types. Embedded systems will typically use some or all of these memory types.

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Non-volatile memory retains its contents after power is turned off. NVRAM - Non-Volatile RAM.

Memory Access
Memory is accessed via uniquely addressed locations (which may be mapped to a separate address space). A memory controller provides hardware support allowing the CPU to access memory. Provides:
q q

Address decode logic. Timing control. Memory bus interface support. Control of memory mapped devices.

To access memory mapped addresses in a different physical address space, the hardware environment may have a separate memory controller ASIC. Hardware environment may have multiple maps.
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ASIC - Application Specic Integrated Circuit.

Memory Access Issues


Memory access issues:
q q

Initialize memory hardware. Provide support for software access. Enable memory controller. Enable memory chips. Enable bridge/memory controller(s). Check integrity of memory. Initialize dynamic memory management facilities. Maintain integrity of system/application memory pools.
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Initializing memory hardware:


q q

Supporting software access:


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Memory Access Support


Memory access:
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Hardware support. Software support. Initialization to load ROM code into RAM performed at power-up. Remainder of memory hardware initialized by prekernel initialization code in VxWorks. Management of virtual memory maps. Initialize partition library after kernel is activated. Enable and initialize MMU after kernel is activated.
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Hardware support:
q

Software support:
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Memory partition management is implemented via a free list.

RAM
Random Access Memory:
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Dynamic RAM (DRAM) Static RAM (SRAM) Primary storage technology. Store/hold capacitor technology. Limited read/write cycle times. Refresh cycles required. Most often used for cache storage, often on CPU chip Flip-op technology, fast read/write cycle times. No refresh cycles.
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DRAM
q q

SRAM
q q

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Main memory will be RAM (or possible SRAM).

RAM Support
RAM conguration:
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Main memory. Cache memory. Zeroed at power-up for cold-boot to prevent parity errors. Congured and enabled by ROM code at system power-up. Usually disabled at power-up, enabled by VxWorks pre-kernel initialization code. Provide cache management libraries.
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Main memory RAM conguration:


q

Cache memory RAM conguration:


q

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For some architectures the instruction cache is enabled at power-up for faster VxWorks boots.

ROM
Read Only Memory types:
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Programmable ROM (PROM). Erasable Programmable ROM (EPROM). Electrically Erasable PROM (EEPROM). Non-volatile. Modied using a ROM programmer. Usually longer access times than DRAM/SRAM. Memory controller interfaces ROM to CPU. System boot code storage. Hardware environment congured to jump to a ROM address at power-up.
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ROM properties:
q q

Non-volatile property allows:


q q

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To program a ROM, it is removed from hardware environment and taken to a ROM burner.

Flash
Flash is non-volatile memory which can be modied programmatically. Used as a silicon hard disk:
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System boot code storage. Hardware environment congured to jump to a ash address at power-up. Maintaining data integrity during power-outs.

Access times slightly slower than DRAM but faster than ROM. Flash memory cells have a nite number of erase/ program cycles (~10,000 - 100,000).

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Flash vs. PROM


Flash and ROM use similar memory cell technology:
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Storage transistor employs transistor tunnelling. No battery to provide non-volatility. Access times are roughly the same.

Flash technology requires lower voltage to erase/ program than PROM. Flash power supply unit allows ash to be modied without being removed from hardware environment.
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Contents may be modied over a network interface. Contents may be modied by application code.

Many ash chips support congurable write protection.


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Many hardware environments use jumpers to congure:


q q

System to jump to a ash address or a PROM address at power-up. Size of on board ash/PROM.

Flash/PROM Support
Flash/PROM support facilities:
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At system start-up. For application code. Code executing out of ash/PROM in Tornado tree. Makele support to build boot code. Flash le system to load VxWorks from ash. Minimum capacity PROM. Code (driver/le system) to uniformly access ash. Large capacity PROM for ROM-resident and uncompressed VxWorks/boot code images.
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System start-up support:


q q

Application code support:


q q

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A minimum capacity PROM for boot code is typically 128K for a compressed CISC image, 256K for a compressed RISC image. For systems using ash a download path for boot code and/or VxWorks will be required.

NVRAM
Non-volatile RAM:
q q

Non-volatility usually provided by battery. May be implemented using CMOS RAM, batterybacked SRAM, or ash.

Units may contain a programmable time-of-day (TOD) clock:


q

TOD information is stored in NVRAM. VxWorks boot parameters may use up 255 bytes.

Used to store boot parameters for VxWorks image:


q

If a hardware environment does not have NVRAM, boot parameters are statically linked into boot code.

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CMOS - Complementary Metal Oxide Semiconductor. Capacitor storage technology with low power consumption characteristics.

System Hardware
Overview Architecture Issues Bus Systems Memory 2.5 Devices

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Embedded System Devices


Generic devices are independent of architecture, buses, and memory hardware. Typical devices:
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Timers. Serial Communication Controllers (SCC). Network interfaces. SCSI controllers. Custom ASICs (DSP chips, etc.) Read/write access. Any mandatory access timing requirements.
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Devices should support:


q q

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Many devices have Direct Memory Access (DMA) capabilities, however, separate DMA controllers are also a type of device. VxWorks is a exible RTOS allowing inclusion of custom ASICs with relative ease by following the templates of standard embedded devices. Hardware environment should also provide:
q

Reset button - Functionally equivalent to a power-on reset, should also reset any external busses. Abort button - Capable of generating a non-maskable-interrupt (NMI) allowing user to take control of hardware environment without a power-on reset.

Timers
Hardware timers are used for:
q q

System clock interrupt (mandatory). Auxiliary clock for high speed polling. Timestamp for WindView. TOD clocks (Real Time Clocks - RTCs). Periodic interrupt. One-shot interrupt. Timestamp.

Timers operate in one of three modes:


q q

Timer use dictated by mode(s) supported by hardware. Timers are initialized after the kernel is activated.
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Timers - cont.
The three modes for timer operation are:
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Periodic interrupt - Counts up/down to programmed terminal count, generates interrupt, resets counter. One-shot interrupt - Counts up/down to programmed terminal count, generates interrupt, disables counter. Timestamp - Counts up/down to maximum count, generates interrupt to log counter rollover, restarts count. Unlike periodic interrupt, counter is polled to obtain high-delity timestamp, interrupt is only used to mark counter rollover.

TOD clocks will also contain date information.

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Serial Communication Controllers


SCCs used as:
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Download/debug path during BSP/application development. Communication channel for application. System level debugging (pre/post kernel). Task level debugging (post kernel). Dual level debugging (post kernel).

Support for interrupt and polled mode operation:


q q

In polled mode, serial interface can be used for system level debugging prior to kernel activation. For pre-kernel system level debugging serial port is accessed by WDB agent.
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Target environments often under software ow control. Ignoring hardware ow control signals means only three lines need to be supported:
q q

Transmit. Receive. Signal ground.

A RS-232 interface dictates that a DCE (Data Communication Equipment) behaves like a modem, and a DTE (Data Terminal Equipment) behaves like a computer. Conguring the target environment as DCE allows a straightforward connection to standard computer terminals.

Network Interfaces
Provides support for:
q q

Application development using Tornado. Distributed applications. 4.3 BSD TCP/IP stack. SENS - Scalable Enhanced Network Stack. 4.4 BSD TCP/IP stack. A proprietary MUX interface between the link and protocol layers. END - Enhanced Network driver which decouples network driver from network protocols.
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VxWorks supports two network stacks:


q q

SENS supports:
q q

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SENS allow any network device to be used with an arbitrary network protocol (e.g. TCP/IP over ATM). END devices allow poll mode access but only after kernel is activated.

SCSI Controllers
Used to provide access to hard disks, tape drives, etc.:
q q

For booting VxWorks. Application data storage/retrieval. Architecture independent libraries. Architecture specic controller driver. Board specic device initialization code. File system (DOS or RAW) for block devices. Tape le system for sequential devices. Customized SCSI commands for unsupported device classes.
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VxWorks supports SCSI-2 systems. Support consist of:


q q

Devices accessed by application through:


q q

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Summary
A BSP will provide support for several hardware categories. Architecture specic:
q q

Caches. MMUs. Interrupt controllers. Floating point hardware. Bus controllers. Bus bridges.

Bus specic:
q q

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Summary
Memory specic:
q q

Memory controllers. Memory chips. Timers. Serial Communication Controllers. Network interfaces. SCSI controllers. Custom ASICs.

Devices:
q q

Support issues involve initialization and hardware access by application code.

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Hardware environment for example BSP discussed in Appendix A.

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