2010 International Conference on Reconfigurable Computing

FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System
Khaled Sobaihi, Akram Hammoudeh, David Scammell Faculty of Advanced Technology University of Glamorgan, UK Email: {ksobaihi, amhammou, dscammel}@glam.ac.uk

Abstract—Orthogonal Frequency Division Multiplexing (OFDM) has been adopted by most wireless and wired communication standards; these include wireless Local Area Networks (LANs) HyperLan2, 802.11a, broadband wireless (802.16) and lately the 802.15.3c for millimetre wave communications. In parallel, Field-Programmable Gate Arrays (FPGAs) have become an alternative for the implementation of those standards, due to their increased capabilities (speed and resources). This work introduces the design and performance evaluation of an OFDM transceiver, implemented on a FPGA platform for applications on a wireless millimetre wave radio system, operating around 60GHz. Keyword—FPGA, HDL, Millimetre Wave, Mobile Radio, OFDM, Xilinx System Generator.

I.

INTRODUCTION

only experience the effects of flat fading. The orthogonality of the subcarriers ensures the OFDM modulation scheme is spectrum efficient. In recent years, Field-Programmable Gate Arrays (FPGAs) have become a key component for implementing high performance digital signal processing (DSP) designs particularly for digital communication systems. The logic fabric of today’s FPGAs consists not only of look-up tables, registers, multiplexers, distributed and block memory, but also, dedicated circuitry for fast adders and multipliers. The memory bandwidth of modern FPGAs far exceed that of a microprocessor or a DSP processor running at clock rates two to ten times that of the FPGA. However, this DSP performance combined with the parallelism aspect of the FPGA allow the implementation of complex digital communication systems such as OFDM. II. RELATED WORKS

The interest in the unlicensed millimetre wave band, particularly the oxygen absorption zone around 60GHz, for wireless communication systems has increased dramatically. This is because of the large bandwidth available to accommodate high data-rates; and the fact that radiated power is limited to some tens of mW, lead to a good frequency reuse factor [1]. The task group TG3c under IEEE802.15.3c working group, responsible for of standardizing Wireless Personal Area Network (WPAN) systems, is now working on future WPAN systems, IEEE802.15.3c, which operates in the 60GHz millimetre-wave band. WPAN systems will support high data rate at least 1 Gbps for applications such as high speed internet access and a streaming content download (video on demand, home theatre, etc.) [2]. Orthogonal Frequency Division Multiplexing (OFDM) has been proposed for use in millimetre-wave transmission systems. This is due to OFDM having superior performance over single carrier system in multi-path wireless channels. The OFDM allows the transmission of the data over multiple orthogonal subcarriers, created by the mean of a Fourier Transform; each subcarrier is modulated independently resulting in a narrow band signal that will
978-0-7695-4314-7/10 $26.00 © 2010 IEEE DOI 10.1109/ReConFig.2010.40 185

There are limited publications related to the design and implementation of complete OFDM transceivers on FPGA platforms along with their performance evaluation over real wireless channels operating at millimetre waves. Work presented in [3] and [4] focused on the FPGA suitability and the resource availability to design an OFDM transceiver, without evaluating its performance under real conditions. Research published in [5] reported the implementation of an OFDM transceiver on a FPGA prototype to validate its suitability for implementation as an Application-Specific Integrated Circuit (ASIC). In contrast, work presented in [6], [7], [8] and [9] have reported the design and implementation of the transmitter part only of the OFDM system, by either using pure HDLs coding or System Generator block-set. The simulation of the OFDM system operating at millimetre waves has been emphasised in [10], [11], [12] and [13]. Those simulations demonstrated the possibility to use a high bit-rate communication system in a 60 GHz indoor wireless channel. The use of 16-QAM/OFDM for the transmission of Digital Terrestrial Broadcasting (ISDB-T) over 60GHz

was successfully transferred with a BER less than 10-6 without using forward error correction. Previous experience with Xilinx FPGAs or Hardware Description Languages (HDLs) is not required when using System Generator.. Basic OFDM Transceiver ADC fc DAC Figure 3. The “In-phase” and “Quadrature” signals are generated from the first and the last two bits respectively according to Table I. after down-conversion the signal is converted to digital format. characterised by a low bit-rate of 6. DAC1 I Re in Re out I I OFDM splits a data-bearing radio signal into multiple smaller signal sets and modulates each onto a different subcarrier. The Inverse Fourier Transform (IFFT) block takes N samples and performs the inverse Fourier transform. OFDM SIMULATION USING XILINX SYSTEM GENERATOR B0B1 00 01 10 11 In Phase (I) -3 -1 1 3 B2B3 00 01 10 11 Quadrature (Q) -3 -1 1 3 System Generator is a DSP design tool from Xilinx that enables the use of The Mathworks model-based design environment Simulink for FPGA design. 16-QAM Mapping scheme to get the correct samples. All of the downstream FPGA implementation steps including synthesis and place and route are automatically performed to generate an FPGA programming file [15].channel has been reported in [14]. the inverse process is applied. 4 bits for 16QAM etc. 16-QAM Mapping Table IV. The block diagram of 16-QAM mapping is demonstrated in Fig 3.. +1 and +3) are stored in a ROM memory block. transmitting them simultaneously at different frequencies. Those N point samples are serialised and converted to analogue format to be up-converted and sent through the channel. III. This OFDM has 64 subcarriers modulated with 16-QAM scheme.).39Mbps. At the receiver. System Generator implementation of an OFDM Transceiver Fig 2 shows the block diagram of the OFDM transceiver to be implemented on the FPGA board by using the Xilinx block-set. The four coding values (-3. Those points are framed in the same order as the ones sent. by using a number of parallel subcarriers spaced orthogonally as closely as possible in frequency without overlapping or interfering [1]. TABLE I. It has been shown that the ISDB-T signal. Those subcarriers are demodulated by using the corresponding de-mapping Up-Conversion fc In bits Stream Serial /Parallel QAM/PSK Mapping N Pts IFFT Parallel /Serial Re dout Tx s z -1 p B Q Im in Im out Q Q Serial to Parallel LFSR PSEUDO RANDOM GENERATOR Im 16QAM MAPPING Start 1 Start Done DAC2 IFFT Tx Tx Out Out Rx Tx Rx Error Rate Calculation Rx Sy stem Generator AWGN Channel AWGN 16QAM DEMAPPING I Re out Re in ADC1 I Re s p B QAM16_DEM Q Im out Im in Q Im Parallel to Serial Thrd 0. in order to apply an N point Fourier transform to recover the N subcarriers. The main blocks are: A. Designs are captured in the DSP friendly 186 . the result is N-Points time domain signal that sums up N subcarriers. the samples are serialised back to get the bits stream initially transmitted. the input bits stream are grouped into parallel format in order to be mapped into M-QAM or M-PSK constellation (Example: 2 bits for QPSK. Fig 1 shows the block diagram of a basic OFDM Transceiver. OFDM TRANSCEIVER ARCHITECTURE Simulink modelling environment using a Xilinx specific block-set. -1. 16-QAM Mapping Each four bits generated by the pseudo random generator are mapped using the 16-QAM constellation. The output of the mapping is a complex number that locates the sample on the I-Q constellation.32501220 threshold FFT dv Start ADC2 Figure 2. Transmitter Channel Down-Conversion 1 B [a:b] B2B3 addr z-1 Q ROM 2 Q [a:b] B0B1 addr z-1 I ROM 1 I Out bits Stream Parallel /Serial QAM/PSK DeMapping N Pts FFT Serial /Parallel Receiver Figure 1.

c. Bit Error Rate vs SNR Ratio Q 1011 X Threshold 1010 X +1 1001 X 1000 X 1111 X 1110 X +3 1101 X 1100 X VI. HARDWARE CO-SIMULATION The implementation of the OFDM system has been performed on Xilinx XtremeDSP Developement Kit (Fig 7). the main features of this development board are: I a. The performance of the simulated OFDM has been evaluated over Additive White Gaussian Noise (AWGN) channel to estimate the BER for a given Signal to Noise ratio. the FFT should be applied on the received samples which must have the same order as the ones transmitted. Figure 5. The floating point performs slightly better than fixed point. B0B1B2B3 0011 X 0010 X -3 0001 X 0000 X 0111 X +3 0110 X +1 -1 0101 X -1 0100 X -3 Bit Error Rate (BER) 1. Fig 4 shows an example using this IP core block. Fig 5 illustrates this principle. At the receiver. 1. b. SOFTWARE SIMULATION The input data stream is generated from a pseudo random generator implemented by a Linear Feedback Shift Register (LFSR) block. I and Q signals are compared to a predefined threshold defined at the mid-way between two neighbouring points. The same code is translated into equivalent behavioural HDL code when hardware is generated. and in order to recover the subcarriers. this is the result of the limited 16-bits word length compared to 64-bits floating point. Virtex-4 XC4VSX35 main FPGA which has a high amount of DSP blocks. 16-QAM De-Mapping 1. therefore.E-02 1. Direct/Inverse Fast Fourier Transform The FFT and IFFT are the most important blocks in the OFDM system and their performances have a big effect on the whole system. This IP core is well optimised for a given device and can be configured to work in pipelined streaming I/O which means that the input data and output results are continuously fetched in and out respectively. The M-Code block supports a limited subset of the MATLAB language (Finite state machines and control logic). Xilinx Intellectual Property (IP) Core is used to perform a 64 Point (number of subcarriers employed) FFT or IFFT. V.E-05 -20 -15 -10 -5 0 5 10 Signal To Noise Ratio SNR (dB) Figure 6.E-04 Matlab Floating Point FPGA Fixed Point 1. 2 channels DAC (14-bits up to 160 MSPS). Fig 6 compares the BER obtained from floating point simulation of the OFDM by using MATLAB Simulink and the 16-bits fixed point Xilinx block-set. To perform this synchronisation the “Done” output of the IFFT block is set high upon the completion of the inverse Fourier transform.B. The Xilinx “MCode” block contains MATLAB code to be executed within Simulink to calculate the block outputs during simulation.E+00 Figure 4.E-01 To perform the 16-QAM demodulation of the recovered sub-carriers the Xilinx “M-Code” is used. 16-QAM De-Mapping decision scheme 187 . therefore. IFFT/FFT Xilinx IP Core C. This is turn will set the “Start” input of the FFT block to start receiving the transmitted samples. The De-Mapping is performed by assigning the received I-Q signals location to the nearest point in the I-Q constellation. The results obtained from both simulations are very similar. 2 channels ADC (14-bits up to 105 MSPS).E-03 1.

CONCLUSION POWER AMP ISOLATOR TRIPLER LNA DOUBLER SPLITTER 10. Equalisation techniques will also be utilised to mitigate the effect of multipath fading. This I-Q constellation is very clean and errors-free transmission was achieved with a bit-rate up to 200Mbps. After the mapping and routing phase. simulate and implement an OFDM transceiver was achieved in this work by exclusively using System Generator block-set provided by Xilinx. the used area is summarised in Table II. During simulation. the OFDM transceiver will be further improved to allow a high order modulation scheme such as 256-QAM. except that the simulation data is processed in hardware instead of software. The received I-Q constellation with LOS Transmission and 1m distance VII. .4 GHz wireless radio system.5 Mbits of embedded memory.Once the simulation is verified. Such blocks are mandatory to make the system work in the real world. The upconversion of the baseband signal to the 64. a hardware cosimulation block along with a hardware configuration file are generated by the System Generator. In future work and in order to ensure the correct functionality of the OFDM system. the configuration file is loaded into the XtremeDSP developement board and the co-simulation block behaves exactly as the subsystem from which it generated. XtremeDSP development kit Tx I-Q Modulator I Q Rx DOWN CONVERTER LNA ISOLATOR TRIPLER LNA DOUBLER I-Q Demodulator I Q UP CONVERTER Figure 9. 3.4 GHz intermediate frequency.4 GHz radio system Fig 8 shows the integration of the OFDM baseband transceiver with a 62. OFDM baseband transceiver interfaced with 62.4GHz OSC LNA 100MHz CRYSTAL SPLITTER 2.2 GHz is done through a 2. The inverse process is performed in the down-conversion. The timing constraints reported in Table III do not show any conflict and the maximum estimated frequency is 228MHz. The design targets the Xilinx FPGA Virtex4 xc4sx35-10ff668 which packs 700 kgates. particularly over the 60 GHz wireless radio channel. In addition.4GHz OSC 10MHz CRYSTAL ITx FPGA Board Baseband OFDM IRx QTx QRx Control Figure 8. Figure 7. frame synchronisation would need to be implemented. This is directly related to the maximum achievable bit-rate of 228Mbps. This shows there are sufficient resources to improve the OFDM transceiver by adding the coding blocks. 192 dedicated DSP blocks. and up to 448 I/O lines. Fig 9 illustrates the received I-Q 16-QAM constellation for line of sight transmission with the transmitter and receiver 1m apart. transmitter and the receiver use common oscillators in order to achieve perfect frequency synchronization. synchronisation and carrier recovery blocks. where the 188 The capability to design.

2008. B. 3. “60 GHz band 64 QAM/OFDM terrestrial digital broadcasting signal transmission by using millimeter-wave selfheterodyne system”. 1-6. Poegel. 2004. in 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC 2008). pp. Vicedo.15 WPAN Task Group 3c (TG3c) Millimeter Wave Alternative PHY Friday. Decai. [10] D.N. Available: http://www. T. in IEEE Workshop on Signal Processing Systems. 114 – 117. Canet. K. S.xilinx. (ICC apos. B. in IEEE 4th International Symposium on Spread Spectrum Techniques and Applications Proceedings.720 2. F. [11] D. M. 2005. M. Available: http://www. Ochi.J. Fettweis. G. Sai. Shayan.833MHz Resources Slice FFs Slices RAMB16s DSP48s Utilisation 10% 15% 2% 22% [12] D.152ns Maximum frequency: 228. Takayama. Itho. vol. Haitao. 157 – 161. [6] A. Nagatsuka.com/support/sw_manuals/sysgen_gs. Manavi and Y.S. [14] Y. 2004.227-232 [4] F. J.pdf REFERENCES [1] S. “Fast frequency correction for DQPSK-OFDM in the 60 GHz indoor environment”. Dony. Fettweis “Coded OFDM at 60 GHz: System Aspects and Measurement Results”. Sommer. pp. [8] X. Jinsong.TABLE II. 1768-1772. 12. H. G. W. vol. System Generator for DSP.370ns Maximum path delay: 4. [15] Xilinx (2009). G. F. J. 50-54. Available: http://www.359 30. “Design and implementation of pipelined MBOFDM UWB transmitter backend modules on FPGA” in International Conference on Computing. Finger. [7] J.vodafonechair. [13] F.org/15/pub/TG3c. H. in 2nd International Conference on Electrical and Electronics Engineering. Hamaguchi. 1999. W. 3. Fettweis. Z.11a standard based on Xilinx Virtex-II FPGA” in 59th IEEE Vehicular Technology Conference ( VTC 2004) 2004. [5] S. [Online]. [Online]. 2008.360 4 192 44 192 TABLE III." Computer. 47.R. Prabakar. P. Sommer. Dec.ieee802.1. "OFDM: Back to the Wireless Future. “Fpga implementation of an if transceiver for OFDM-based WLAN”. R. “A pipelined implementation of OFDM transmission on reconfigurable platforms” in Canadian Conference on Electrical and Computer Engineering. Shoji. Vol. N. G. pp. vol. V. pp. 7-9 Sept. “300-Mbps OFDM transceiver for wireless communication with an 80MHz bandwidth” in Intelligent Signal Processing and Communication Systems (ISPACS 2005).html [3] M. Garcia. Ogawa. in IEEE International Conference on Communications. Yujing.1. Y. Zeisberg. Hirata. A. S. (CCECE 2008). N. Z. [Online]. pp.P. (SIPS 2004). Sommer. M. “Implementation of OFDM modem for the physical layer of IEEE 802. 2001. Finger. Valls. 2005 pp. 122 – 125.11a”. pp. 2002. IEEE Transactions On Broadcasting. (ICCCn 2008). pp. Hataoka. Timing Constraints Timing summary Minimum period: 4. FPGA Resources Utilisation Device Utilisation Summary Virtex4 xc4vsx35-10ff668 Used Available 3. Poegel. A. 213-216. Areibi. Santhi. no. No. Cumplido “On the design of an FPGA-Based OFDM modulator for IEEE 802. 99). “Coherent OFDM Transmission at 60 GHz”. 2008.Almenar.com/publications/1999/Sommer_d_ofdm_99. 26-28 May 2008. [9] M. Lakshminarayanan. 18-20 Dec. B. “Comparison of different coding schemes for high bit rate OFDM in a 60 GHz environment”.pdf 189 .393 15. 5 February 2010. Xiaochun. 35. 19-21 [2] IEEE 802. “Implementation of MB-OFDM Transmitter Baseband Based on FPGA”. pp. 218-227. in IEEE VTS 50th Vehicular Technology Conference (VTC 1999). pp. pp. Kumar. Getting Started Guide.P. 1545-1549. Xiaolong. Vol. 22-25 Sep 1996. Chaogang. Sghaier. Yoshizawa. Communication and Networking. 000801000804. Y. L. pp. Miyanaga. Vaughan-Nichols.