JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

JESD209-2E
APRIL 2011
JEDEC
STANDARD
Low Power Double Data Rate 2
(LPDDR2)
(Revision of JESD209-2D, December 2010)
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Special Disclaimer
JEDEC has received information that certain patents or patent applications
may be essential to this standard. However, as of the publication date of this
standard, no statements regarding an assurance or refusal to license such
patents or patent applications have been provided. Contact JEDEC for further
information.
JEDEC does not make any determination as to the validity or relevancy of
such patents or patent applications. Anyone making use of the standard
assumes all liability resulting from such use. JEDEC disclaims any
representation or warranty, express or implied, relating to the standard and its
use.
JEDEC Standard No. 209-2E
Contents
1 Scope ..................................................................................................................................1
2 Package ballout & addressing .........................................................................................2
2.1 LPDDR2 12x12 PoP 2-channel 2x32 package ballout .................................................. 2
2.2 LPDDR2 12x12 PoP 1-channel x32 package ballout using MO-273............................. 3
2.3 LPDDR2 14x14 PoP Dual x32 Channel ballout using MO-273 .................................... 4
2.4 LPDDR2 10x10 PoP 1-channel x32 package ballout ..................................................... 5
2.5 79-ball x16 LPDDR2 0.5mm pitch package ballout (Discrete/MCP) ........................... 6
2.6 2.5 134-ball x16/x32 LPDDR2 package ballout (Discrete/MCP) ................................. 7
2.7 162-ball x16/x32 LPDDR2 and SDR-Flash package ballout ........................................ 8
2.8 180-ball x16/x32 LPDDR2, SDR-Flash, and e-MMC package ballout ........................ 9
2.9 121-ball x16 LPDDR2, SDR Flash-NVM, and e-MMC package ballout ..................... 10
2.10 LPDDR2 Pad Sequence ............................................................................................... 11
2.11 Input/output functional description .............................................................................. 12
2.11.1 Pad Definition and Description ................................................................................. 12
2.12 LPDDR2 SDRAM Addressing .................................................................................... 14
2.13 LPDDR2 NVM Addressing ......................................................................................... 14
2.13.1 Three-Phase Addressing ........................................................................................... 14
3 Functional description .................................................................................................... 20
3.1 Simplified LPDDR2 Bus Interface State Diagram .........................................................21
3.2 Simplified LPDDR2-SX State Diagram .........................................................................23
3.3 Simplified LPDDR2-N Simplified Bus State Diagram ..................................................25
3.3.1 Power On and Resetting states .................................................................................... 25
3.3.2 Idle state ...................................................................................................................... 25
3.3.3 Active state .................................................................................................................. 26
3.4 Power-up, Initialization, and Power-Off .........................................................................28
3.4.1 Power Ramp and Device Initialization ....................................................................... 28
3.4.2 Initialization after Reset (without Power ramp): ......................................................... 30
3.4.3 Power-off Sequence .................................................................................................... 31
3.4.4.Uncontrolled Power-Off Sequence ............................................................................. 31
3.5 Mode Register Definition ................................................................................................32
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM ............ 32
4 LPDDR2-N Software Interface ...................................................................................... 47
4.1 Overlay Window ............................................................................................................ 47
4.1.1 Map of Control Registers (offsets and definitions) ..................................................... 48
4.1.1.1 Command Code Register .......................................................................................... 49
4.1.1.2 Command Data Register .......................................................................................... 49
4.1.1.3 Command Address Register ..................................................................................... 49
4.1.1.4 Multi-Purpose Register ............................................................................................ 49
4.1.1.5 Command Execute Register ..................................................................................... 50
4.1.1.6 Suspend Register ...................................................................................................... 50
4.1.1.7 Abort Register .......................................................................................................... 51
4.1.1.8 Status Register ......................................................................................................... 51
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JEDEC Standard No. 209-2E
Contents (cont’d)
4.1.1.9 Program-Buffer ........................................................................................................ 53
4.2 Data Byte Lane Assignment for Overlay Window Register .......................................... 53
4.3 LPDDR2-NVM Operations ........................................................................................... 54
4.4 Nomenclature ................................................................................................................. 55
4.5 Acronyms ....................................................................................................................... 56
4.6 Conventions ................................................................................................................... 57
4.7 Overlay Window Enable and Disable ............................................................................ 58
4.7.1 Block Lock Command ................................................................................................ 59
4.7.2 Block Unlock Command ............................................................................................. 61
4.7.3 Block Lock-Down Command ..................................................................................... 63
4.7.4 Block Erase Command ................................................................................................ 65
4.7.5 Single Word Program Command ................................................................................ 67
4.7.6 Single Word Overwrite Command ............................................................................. 69
4.7. 7Buffered Program Command ...................................................................................... 71
4.7.8 Buffered Overwrite Command .................................................................................... 73
4.7.9 Program/Erase Suspend .............................................................................................. 75
4.7.10 Program/Erase Resume Command ........................................................................... 77
4.7.11 Abort ......................................................................................................................... 78
4.7.12 Row Data Buffer Incoherency .................................................................................. 79
4.8 Dual operations and multiple partition architecture ....................................................... 80
5 LPDDR2 Command Definitions and Timing Diagrams .............................................. 81
5.1 Activate Command ........................................................................................................ 81
5.1.1 LPDDR2-SX: Activate Command .............................................................................. 81
5.1.2 LPDDR2-N: Activate Command ................................................................................ 82
5.2 LPDDR2 Command Input Signal Timing Definition .................................................... 83
5.2.1 LPDDR2 Command Input Setup and Hold Timing .................................................... 83
5.2.2 LPDDR2 CKE Input Setup and Hold Timing ............................................................ 84
5.3 Read and Write access modes ........................................................................................ 85
5.3.1 LPDDR2-SX: Read and Write access modes ............................................................. 85
5.3.2 LPDDR2-N: Read and Write access modes ............................................................... 85
5.4 Burst Read Command .................................................................................................... 86
5.4.1 Reads interrupted by a read ......................................................................................... 91
5.4.2 LPDDR2: Data Not Valid ........................................................................................... 92
5.5 Burst Write Operation .................................................................................................... 94
5.5.1 Writes interrupted by a write ...................................................................................... 97
5.6 Burst Terminate .............................................................................................................. 99
5.7 Write Data Mask ............................................................................................................ 103
5.8 LPDDR2-N: Preactive operation ................................................................................... 105
5.8.1 LPDDR2-N: Burst Read operation followed by Activate or Preactive ...................... 106
5.8.2 LPDDR2-N: Burst Write operation followed by Activate or Preactive ..................... 107
5.8.3 LPDDR2-N: Auto Precharge (AP) bit ........................................................................ 109
5.9 LPDDR2-SX: Precharge operation ................................................................................ 109
5.9.1 LPDDR2-SX: Burst Read operation followed by Precharge ...................................... 110
5.9.2 LPDDR2-SX: Burst Write followed by Precharge ..................................................... 112
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JEDEC Standard No. 209-2E
Contents
5.9.3 LPDDR2-SX: Auto Precharge operation .................................................................... 112
5.9.3.1 LPDDR2-SX: Burst Read with Auto-Precharge ...................................................... 113
5.9.3.2 LPDDR2-SX: Burst write with Auto-Precharge ...................................................... 114
5.10 LPDDR2-SX: Refresh command ................................................................................. 117
5.10.1 LPDDR2 SDRAM Refresh Requirements ................................................................ 118
5.11 LPDDR2-SX: Self Refresh operation .......................................................................... 124
5.11.1 LPDDR2-S2: Partial Array Self-Refresh: Bank Masking ........................................ 125
5.11.2 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking ........................................ 126
5.11.3 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking ................................... 126
5.12 Mode Register Read Command ................................................................................... 127
5.12.1 Temperature Sensor .................................................................................................. 129
5.12.2 DQ Calibration .......................................................................................................... 130
5.13 Mode Register Write Command .................................................................................. 132
5.13.1 LPDDR2-SX: Mode Register Write ......................................................................... 132
5.13.2 LPDDR2-N: Mode Register Write ........................................................................... 132
5.13.3 Mode Register Write Reset (MRW Reset) ............................................................... 134
5.13.4 Mode Register Write ZQ Calibration Command ...................................................... 135
5.13.4.1 ZQ External Resistor Value, Tolerance, and Capacitive Loading ......................... 137
5.14 Power-down ................................................................................................................. 138
5.15 LPDDR2-SX: Deep Power-Down ............................................................................... 145
5.16 Input clock stop and frequency change ........................................................................ 146
5.17 No Operation command ............................................................................................... 147
5.18 Truth tables .................................................................................................................. 147
5.18.1 Command Truth Table .............................................................................................. 148
5.19 LPDDR2-SDRAM Truth Tables ................................................................................. 150
5.20 LPDDR2-N: Truth Tables ............................................................................................ 155
5.21 Data Mask Truth Table ................................................................................................ 158
6 Absolute Maximum Ratings ........................................................................................... 159
6.1 Absolute Maximum DC Ratings .................................................................................... 159
7 AC & DC Operating Conditions ................................................................................... 160
7.1 Recommended DC Operating Conditions ...................................................................... 160
7.2 Input Leakage Current ................................................................................................... 161
7.3 Operating Temperature Range ....................................................................................... 161
8 AC and DC Input Measurement Levels ........................................................................ 162
8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................ 162
8.1.1 AC and DC Input Levels for Single-Ended CA and CS_n Signals ............................ 162
8.1.2 AC and DC Input Levels for CKE .............................................................................. 162
8.1.3 AC and DC Input Levels for Single-Ended Data Signals ........................................... 162
8.2 Vref Tolerances .............................................................................................................. 163
8.3 Input Signal .................................................................................................................... 164
8.4 AC and DC Logic Input Levels for Differential Signals ............................................... 166
8.4.1 Differential signal definition ....................................................................................... 166
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JEDEC Standard No. 209-2E
Contents (cont’d)
8.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe ........................ 166
8.4.3 Single-ended requirements for differential signals ..................................................... 168
8.5 Differential Input Cross Point Voltage .......................................................................... 169
8.6 Slew Rate Definitions for Single-Ended Input Signals .................................................. 170
8.7 Slew Rate Definitions for Differential Input Signals ..................................................... 170
9 AC and DC Output Measurement Levels ..................................................................... 171
9.1 Single Ended AC and DC Output Levels ....................................................................... 171
9.2 Differential AC and DC Output Levels ......................................................................... 171
9.3 Single Ended Output Slew Rate ..................................................................................... 172
9.4 Differential Output Slew Rate ........................................................................................ 173
9.5 Overshoot and Undershoot Specifications ..................................................................... 174
9.6 Output buffer characteristics .......................................................................................... 175
9.6.1 HSUL_12 Driver Output Timing Reference Load ..................................................... 175
9.7 RONPU and RONPD Resistor Definition ..................................................................... 176
9.7.1 RONPU and RONPD Characteristics with ZQ Calibration ........................................ 177
9.7.2 Output Driver Temperature and Voltage Sensitivity .................................................. 178
9.7.3 RONPU and RONPD Characteristics without ZQ Calibration .................................. 179
9.7.4 RZQ I-V Curve ........................................................................................................... 180
10 Input/Output Capacitance ........................................................................................... 182
10.1 Input/Output Capacitance ............................................................................................ 182
11 IDD Specification Parameters and Test Conditions ................................................. 184
11.1 IDD Measurement Conditions ..................................................................................... 184
11.2 IDD Specifications ...................................................................................................... 186
12 Electrical Characteristics and AC Timing ................................................................. 189
12.1 Clock Specification ..................................................................................................... 189
12.1.1 Definition for tCK(avg) and nCK ............................................................................ 189
12.1.2 Definition for tCK(abs) ............................................................................................ 189
12.1.3 Definition for tCH(avg) and tCL(avg) ..................................................................... 189
12.1.4 Definition for tJIT(per) ............................................................................................. 189
12.1.5 Definition for tJIT(cc) .............................................................................................. 190
12.1.6 Definition for tERR(nper) ........................................................................................ 190
12.1.7 Definition for duty cycle jitter tJIT(duty) ................................................................. 191
12.1.8 Definition for tCK(abs), tCH(abs) and tCL(abs) ...................................................... 191
12.2 Period Clock Jitter ....................................................................................................... 192
12.2.1 Clock period jitter effects on core timing parameters .............................................. 192
12.2.1.1 Cycle time de-rating for core timing parameters ................................................... 192
12.2.1.2 Clock Cycle de-rating for core timing parameters ................................................ 192
12.2.2 Clock jitter effects on Command/Address timing parameters ................................. 192
12.2.3 Clock jitter effects on Read timing parameters ........................................................ 193
12.2.3.1 tRPRE .................................................................................................................... 193
12.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) ......................................... 193
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JEDEC Standard No. 209-2E
Contents
12.2.3.3 tQSH, tQSL ........................................................................................................... 193
12.2.3.4 tRPST ..................................................................................................................... 193
12.2.4 Clock jitter effects on Write timing parameters ........................................................ 194
12.2.4.1 tDS, tDH ................................................................................................................ 194
12.2.4.2 tDSS, tDSH ............................................................................................................ 194
12.2.4.3 tDQSS .................................................................................................................... 194
12.3 LPDDR2-SX Refresh Requirements by Device Density ............................................. 195
12.4 AC Timings .................................................................................................................. 197
12.5 CA and CS_n Setup, Hold and Derating ...................................................................... 206
12.6 Data Setup, Hold and Slew Rate Derating ................................................................... 212
Annex A LPDDR2-NVM Software Application Notes ................................................... 218
A.1 Scope ............................................................................................................................. 218
A.2 Programming operations based on Programming Region ............................................ 218
A.2.1 Introduction ................................................................................................................ 218
A.2.2 Programming Modes .................................................................................................. 218
A.2.3 Programming Regions ................................................................................................ 218
A.2.4 Program Modes .......................................................................................................... 219
A.2.4.1 Control Mode ........................................................................................................... 219
A.2.4.2 Object Mode ............................................................................................................ 221
A.2.4.3 Programming Region Configuration ....................................................................... 222
Annex B LPDDR2-NVM Boot Procedure ....................................................................... 224
B.1 Booting From an LPDDR2-NVM Device ..................................................................... 224
B.1.1 Power Ramp and Initialization ................................................................................... 226
B.1.2 ZQ Initialization ......................................................................................................... 227
B.1.3 Determine the LPDDR2 bus width, memory type, RDB size and density ................ 227
B.1.4 Align controller and memory latency settings (RL, WL, tRCD) ............................... 227
B.1.5 Determining whether to boot from the LPDDR2 Bus ................................................ 227
B.1.6 Continued Boot Out Of the LPDDR2-NVM Device ................................................. 227
B.1.7 Output Drive Strength ................................................................................................ 227
B.1.8 Setting the Output Impedance Calibration Interval .................................................... 228
B.1.9 Increasing the Clock Rate ........................................................................................... 228
B.1.10 Controller Latency Settings for Higher Clock Rates ................................................ 228
B.1.11 Increasing the Clock Rate ......................................................................................... 229
B.1.12 Data Training ............................................................................................................ 229
B.1.13 Summary .................................................................................................................. 229
Annex C LPDDR2-N: Replay Protected Memory Block (RPMB) ................................ 230
C.1 Acronyms ...................................................................................................................... 230
C.2 Introduction ................................................................................................................... 230
C.3 Map of Control Registers (offsets and definitions) ....................................................... 230
C.3.1 Command Result Register .......................................................................................... 231
C.3.2 Nonce Register ........................................................................................................... 232
C.3.3 Write Counter Register ............................................................................................... 233
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JEDEC Standard No. 209-2E
Contents (cont’d)
C.3.4 Command Response Register...................................................................................... 234
C.3.5 MAC Register ............................................................................................................ 234
C.4 Authentication Key and RPMB Resource ..................................................................... 235
C.4.1 Authentication Key ..................................................................................................... 235
C.4.2 Authentication Key Configuration Register ............................................................... 235
C.4.3 RPMB ID, RPMB Start Address, RPMB End Address ............................................. 235
C.4.4 RPMB Configuration Register ................................................................................... 236
C.5 Message Authentication Code Calculation ................................................................... 237
C.6 LPDDR2-NVM RPMB commands ............................................................................... 239
C.6.1 Write Security Register Command ............................................................................. 240
C.6.2 Read Security Register ............................................................................................... 243
C.6.3 Write Counter Digest Command ................................................................................ 245
C.6.4 Memory Data Digest Command ................................................................................. 247
C.6.5 Authenticated Block Erase Command ....................................................................... 249
C.6.6 Authenticated Single Word Program Command ........................................................ 252
C.6.7 Authenticated Single Word Overwrite Command ..................................................... 255
C.6.8 Authenticated Buffered Program Command .............................................................. 258
C.6.9 Authenticated Buffered Overwrite Command ........................................................... 261
C.7 Dual operations with Authenticated Command ............................................................ 264
Annex D (informative) Differences between Document Revisions ................................ 266
D.1 Initial Release JESD209-2 ............................................................................................ 266
D.2 Updated Specification to JESD209-2A ......................................................................... 266
D.3 Updated Specification to JESD209-2B ......................................................................... 268
D.4 Updated Specification to JESD209-2C ......................................................................... 269
D.5 Updated Specification to JESD209-2D ......................................................................... 270
D.6 Updated Specification to JESD209-2E ......................................................................... 272
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JEDEC Standard No. 209-2E
Page 1
LOW POWER DOUBLE DATA RATE 2 (LPDDR2)
(From JEDEC Board ballots JCB-10-54, JCB-10-90, and JCB-10-91, formulated under the cognizance of
the JC-42.6 Subcommittee on Low Power Memory.)
1 Scope
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics,
packages, and ball/signal assignments. This specification covers the following technologies: LPDDR2-S2A,
LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this specification
is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32
SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. This specification was
created using aspects of the following specifications: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209),
and LPDDR-NVM (N07-NV1A). Each aspect of the specification were considered and approved by committee
ballot(s). The accumulation of these ballots were then incorporated to prepare the LPDDR2 specification.
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2 Package ballout & addressing
2.1 LPDDR2 12x12 PoP 2-channel 2x32 package ballout
NOTE 1 12x12 mm, 0.4mm pitch, 29 rows
NOTE 2 216 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A DNU VSSa/b VDD2_a/b DQ30_a DQ29_a VSSQ_a DQ26_a DQ25_a VSSQ_a DQS3_c_a VSSQ_a DQ14_a DQ13_a VSS_a VDD1_a VDD2_a DQ11_a DQ10_a DQ9_a DQS1_t_a DM_1_a VDDQ_a DQS0_t_a DQ7_a DQ6_a DQ4_a DQ3_a VSS_a/b DNU
B
VSSQ_b/
VSS
VACC DQ31_a VDDQ_a DQ28_a DQ27_a VDDQ_a DQ24_a VDDQ_a DQS3_t_a DM3_a DQ15_a VDDQ_a VSSQ_a Vref(DQ)_a VDD2_a DQ12_a VDDQ_a DQ8_a DQS1_c_a VSSQ_a DM_0_a DQS0_c_a VSSQ_a VDDQ_a DQ5_a DQ2_a VACC VSSQ_a
C VDD1_a/b DQ16_b VDD1_a VDD2_a/b
D DQ17_b VDDQ_b DQ1_a VDDQ_a
E DQ18_b DQ19_b VSSQ_a DQ0_a
F VSSQ_b DQ20_b DM2_a VDDQ_a
G DQ21_b VDDQ_b DQS2_t_a DQS2_c_a
H DQ22_b DQ23_b VSSQ_a DQ23_a
J VSSQ_b VDDQ_b VDDQ_a DQ22_a
K DQS2_c_b DQS2_t_b Channel b DQ20_a DQ21_a
L DM2_b DQ0_b Channel a DQ19_a VSSQ_a
M DQ1_b VSSQ_b Power VDDQ_a DQ18_a
N DQ2_b VDD1_b Ground DQ16_a DQ17_a
P VSS_b VSS_b Do Not Use VDD2_b VDD1_b
R VDD1_b Vref(DQ)_b ZQ VSS_b CA0_b
T VDD2_b VDD2_b Clock VDDCA_b CA1_b
U VDDQ_b DQ3_b Vref(CA)_b CA2_b
V DQ4_b VSSQ_b VSSCA_b CA3_b
W DQ6_b DQ5_b CA4_b CSB1_b
Y VDDQ_b DQ7_b CSB0_b CKE1_b
AA DQS0_t_b DQS0_c_b VSSCA_b CKE0_b
AB DM0_b VSSQ_b CK_t_b CK_c_b
AC VDDQ_b DM1_b VDDCA_b CA5_b
AD DQS1_c_b DQS1_t_b CA7_b CA6_b
AE DQ8_b VSSQ_b CA8_b VDDCA_b
AF DQ9_b VDDQ_b VSSCA_b CA9_b
AG DQ10_b DQ11_b VDD2_a/b ZQ_b
AH VSSQ_b VDD1_a/b VDD2_a/b DQ13_b VSSQ_b DQ15_b DM3_b DQS3_t_b VDDQ_b DQ26_b DQ27_b VDDQ_b DQ30_b VSSQ_b VDD2_a Vref(CA)_a CA9_a VSSCA_a CA7_a CA6_a CK_c_a VDDCA_a CKE0_a CSB0_a CA3_a CA2_a CA1_a VDD1_a/b VSSCA_a
AJ DNU VSS_a/b DQ12_b VDDQ_b DQ14_b VDDQ_b VSSQ_b DQS3_c_b DQ24_b DQ25_b VSSQ_b DQ28_b DQ29_b DQ31_b VDD1_a VSS_a ZQ_a CA8_a VDDCA_a CA5_a CK_t_a VSSCA_a CKE1_a CSB1_a CA4_a VDDCA_a CA0_a VSS_a/b DNU
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2.2 LPDDR2 12x12 PoP 1-channel x32 package ballout using MO-273
NOTE 1 12x12 mm, 0.5mm pitch, 23 rows
NOTE 2 168 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A DNU DNU
RDY,R/B
_n,
CLK
CLKm
ADQ11
DAT6m
VCCm
m
ADQ10
DAT4m
ADQ9
DAT2m
VCCQmm
ADQ8
DAT0m
VDD1 VSSQ DQ30 DQ29 VSSQ DQ26 DQ25 VSSQ DQS3_c VDD1 VSS DNU DNU
B DNU DNU VDD1
ADQ3
DAT7m
VSSm
m
ADQ2
DAT5m
ADQ1
DAT3m
VSSm
m
ADQ0
DAT1m
VSS VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_t VDDQ DM3 VDD2 DNU DNU
C VSS VDD2 DQ15 VSSQ
D ADQ12 ADQ4 VDDQ DQ14
E ADQ13 ADQ5
Flash Memory (eMMC/MuxOneNand/NAND/AAD-
MuxNOR) ADD/CTRL
Ball
Loca-
Mux
One-
eMMC
Raw
NAND
ADD-
Mux
Comment DQ12 DQ13
F
VCCQmm
VDDImm
VSSmm LPDDR2 DQ A3
RDY /
WAIT_n
CMDm R/B_n WAIT DQ11 VSSQ
G ADQ14 ADQ6 LPDDR2 CA A4 CLK CLKm NC CLK VDDQ DQ10
H ADQ15 ADQ7 Power K1 WE_n NC WE_n WE_n DQ8 DQ9
J VCCmm VSSmm Ground K2 OE_n NC RE_n OE_n DQS1_t VSSQ
K WE_n
OE_n/
RE_n
Do Not Use L1 RP_n
RST_n
(v4.4)
CLE
RST_n /
DPD
DPD must be con-
figured active high
VDDQ
DQS1_
c
L
RP_n,
RST_n,
AVD_n,
ADV_n,
ZQ L2 AVD_n NC ALE ADV_n VDD2 DM1
M CE_n VSS Clock N1 INT NC WP_n WP_n Vref(DQ) VSS
N INT,WP_n VDD1 VDD1 DM0
P ZQ Vref(CA) DQS0_c VSSQ
R VSS VDD2 VDDQ DQS0_t
T CA9 CA8 DQ6 DQ7
U CA7 VDDCA DQ5 VSSQ
V VSSCA CA6 VDDQ DQ4
W CA5 VDDCA DQ2 DQ3
Y CK_c CK_t DQ1 VSSQ
A
A
VSS VDD2 VDDQ DQ0
A
B
DNU DNU CS0_n CS1_n VDD1 CA1 VSSCA CA3 CA4 VDD2 VSS DQ16 VDDQ DQ18 DQ20 VDDQ DQ22 DQS2_t VDDQ DM2 VDD2 DNU DNU
A
C
DNU DNU CKE0 CKE1 VSS CA0 CA2 VDDCA VSSmm VDDmm VACC VSSQ DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ DQS2_c VDD1 VSS DNU DNU
J
E
D
E
C

S
t
a
n
d
a
r
d

N
o
.

2
0
9
-
2
E
P
a
g
e

4
2.3 LPDDR2 14x14 0.5 mm ball pitch Dualx32 ChannelPoP ballout using variation VEEBDC for MO-273
NOTE 1 14x14 mm, 0.5mm pitch, 27 rows
NOTE 2 240 Ball Count, internal row partially populated
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
A
DNU VSS_a/b VDD2_a/b DQ31_a VDDQ_a VSSQ_a DQ26_a DQ24_a DQS3_t_a DM3_a DQ15_a DQ13_a VSSQ_a VDDQ_a DQ8_a VSSQ_a Vref(DQ)_a VDD1_a/b VDDQ_a VSSQ_a DQ7_a DQ5_a VSSQ_a VDDQ_a VDD1_a/b VSSQ_a DNU
A
B
VSSQ_b VACC VSSQ_a DQ30_a DQ29_a DQ27_a VDDQ_a VSSQ_a DQS3_c_a VSSQ_a DQ14_a DQ12_a DQ11_a DQ9_a DQS1_c_a VDDQ_a VSS_a/b VDD2_a/b DQS0_c_a DM0_a DQ6_a DQ4_a DQ3_a DQ1_a DQ0_a VACC VSS_a/b
B
C
VDD1_a/b DQ16_b DQ28_a DQ25_a VDDQ_a VDDQ_a DQ10_a DQS1_t_a DM1_a DQS0_t_a VDDQ_a DQ2_a DM2_a VDD2_a/b
C
D
DQ17_b VDDQ_b VDDQ_a DQS2_c_a
D
E
DQ18_b DQ19_b VSSQ_b
14X14 mm, 0.5mm pitch, 27 rows
VSSQ_a DQS2_t_a DQ23_a
E
F
DQ20_b DQ21_b
240 Ball Count
DQ22_a VDDQ_a
F
G
VDDQ_b DQ22_b DQ23_b
Top View A1 in Top Left Corner
DQ21_a DQ20_a VSSQ_a
G
H
VSSQ_b DQS2_t_b DQ19_a DQ18_a
H
J
DQS2_c_b VDDQ_b DM2_b
Channel b
VDDQ_a DQ17_a DQ16_a
J
K
VSSQ_b DQ0_b
Channel a
VSSQ_a VDD2_a/b
K
L
DQ1_b VDDQ_b DQ2_b
Power
CA0_b VDD1_a/b VSS_a/b
L
M
DQ3_b VSSQ_b
Ground
CA1_b VSSCA_b
M
N
DQ4_b DQ5_b VDDQ_b
Do not use
CA3_b CA2_b VDDCA_b
N
P
DQ6_b DQ7_b
ZQ
CA4_b CSB1_b
P
R
VDDQ_b DQS0_t_b DQS0_c_b CKE0_b CSB0_b CKE1_b
R
T
VSSQ_b VSS_a/b CK_c_b CK_t_b
T
U
Vref(DQ)_b VSS_a/b DM0_b VDD2_a/b VDDCA_b VSSCA_b
U
V
VDD1_a/b VDD1_a/b VSS_a/b Vref(CA)_b
V
W
DM1_b VDD2_a/b VDD2_a/b CA5_b VDDCA_b VSSCA_b
W
Y
VDDQ_b VSSQ_b CA7_b CA6_b
Y
AA
DQS1_c_b DQS1_t_b DQ8_b VDD2_a/b CA9_b CA8_b
AA
AB
VDDQ_b DQ9_b VSS_a/b ZQ_b
AB
AC
DQ10_b DQ11_b VSSQ_b DNU DNU VDD1_a/b
AC
AD
DQ13_b DQ12_b DNU DNU
AD
AE
VDD1_a/b DQ14_b VSSQ_b DQ27_b DQ30_b VDD2_a/b CA6_a CA5_a VDD2_a/b CA4_a VSS_a/b DNU DNU DNU
AE
AF
VSSQ_b VDDQ_b DQ15_b VDDQ_b DQS3_t_b DQ25_b DQ26_b DQ28_b VDDQ_b VSSQ_b VSS_a/b CA9_a CA7_a VDDCA_a VSS_a/b VDDCA_a CK_t_a CKE0_a CSB0_a CA2_a VSSCA_a CA0_a VDD2_a/b DNU DNU DNU DNU
AF
AG
DNU VSS_a/b VDD2_a/b DM3_b DQS3_c_b DQ24_b VDDQ_b VSSQ_b DQ29_b DQ31_b VDD1_a/b ZQ_a CA8_a VSSCA_a Vref(CA)_a VSSCA_a CK_c_a CKE1_a CSB1_a CA3_a VDDCA_a CA1_a VDD1_a/b DNU DNU DNU DNU
AG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
JEDEC Standard No. 209-2E
Page 5
2.4 LPDDR2 10x10 PoP 1-channel x32 package ballout using variation VAABCB for MO-273
NOTE 1 10x10 mm, 0.5mm pitch, 19 rows
NOTE 2 136 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A DNU DNU VSS VSSQ DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_c DM3 VSSQ DQ14 DQ13 DQ11 VSS DNU DNU
B DNU DNU VSS VDD2 DQ30 DQ29 VSSQ DQ26 DQ25 VSSQ DQS3_t VDDQ DQ15 VDDQ DQ12 VDD2 VSS DNU DNU
C ZQ VDD1 VDD1 DQ10
D CA9 CA8 DQ9 VDDQ
E VSSCA VDDCA VSSQ DQ8
F CA7 CA6 LPDDR2 DQ DQS1_t DQS1_c
G CA5 VDD2 LPDDR2 CA VDDQ DM1
H VDD1 Vref(CA) Power VDD2 VSSQ
J VSS VDDCA Ground VSS VDD2
K CK_t CK_c Do Not Use Vref(DQ) VSS
L VSS VSSCA ZQ VDD1 VDD1
M CKE1 CKE0 Clock VDD2 VSSQ
N CS1_n CS0_n VDDQ DM0
P CA3 CA4 DQS0_t DQS0_c
R VDDCA CA2 VSSQ DQ7
T CA1 VSSCA DQ6 VDDQ
U CA0 VDD1 VDD1 DQ5
V DNU VACC VSS VDD2 DQ17 DQ18 VSSQ DQ21 DQ22 VSSQ DQS2_t VDDQ DQ0 VDDQ DQ3 VDD2 VSS DNU DNU
W DNU DNU VSS VSSQ DQ16 VDDQ DQ19 DQ20 VDDQ DQ23 DQS2_c DM2 VSSQ DQ1 DQ2 DQ4 VSS DNU DNU
JEDEC Standard No. 209-2E
Page 6
2.5 79-ball x16 LPDDR2 0.5mm pitch package ballout (Discrete/MCP)
NOTE 1 0.5mm pitch, 11 rows
NOTE 2 79 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 The ZQ-ball used when operating above 200 MHz is limited to a 5pF load (typically 2 die using CKE0,1
and CS0,1)
NOTE 5 See JESD21-C, Section 3.12.1
1 2 3 4 5 6 7 8 9
A NC CA9 VDD2 VDD1 VSSQ DQ14 DQ12 VDD2 NC
B CA7 CA8 ZQ VSS DQ15 DQ13 VDDQ VSSQ DQ11 LPDDR2 DQ
C CA5 CA6 DQ10 DQ9 LPDDR2 CA
D VDDCA VSSCA
CKE2
CS3_n
VSSQ DQS1_t DQ8 VDDQ Power
E VDD2 Vref(CA) CKE1 VDDQ DQS1_c DM1 VSS Ground
F VSS VSSCA CKE0 VSS VDD1 VDD2 Vref(DQ) Do Not Use/No Connect
G VDDCA CK_t CS1_n VSSQ DQS0_c DM0 VDD1 ZQ
H CK_c CS0_n CS2_n VDDQ DQS0_t DQ7 VDDQ Clock
J CA4 CA3 DQ5 DQ6
K CA2 CA1 VACC VSS DQ0 DQ2 VDDQ VSSQ DQ4
L NC CA0 VDD2 VDD1 VSSQ DQ1 DQ3 VDD2 NC
JEDEC Standard No. 209-2E
Page 7
2.6 134-ball x16/x32 LPDDR2 package ballout (Discrete/MCP)
NOTE 1 0.5mm (x32) or 0.65mm pitch (x32, x16), 17 rows
NOTE 2 134 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.1
1 2 3 4 5 6 7 8 9 10
A DNU DNU NB NB NB NB NB NB DNU DNU
B DNU NC VACC NB VDD2 VDD1
DQ31
NC
DQ29
NC
DQ26
NC
DNU
Ball Definition where
2 labels are present
C VDD1 VSS ZQ1 NB VSS VSSQ VDDQ
DQ25
NC
VSSQ VDDQ
1st Row
2nd Row
x32 device
x16 device
D VSS VDD2 ZQ0 NB VDDQ
DQ30
NC
DQ27
NC
DQS3_t
NC
DQS3_c
NC
VSSQ
E VSSCA CA9 CA8 NB
DQ28
NC
DQ24
NC
DM3
NC
DQ15 VDDQ VSSQ
F VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ
G VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ
H VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB
J VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB
K CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB LPDDR2 DQ
L CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ LPDDR2 CA
M CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ Power
N VSSCA VDDCA CA1 NB
DQ19
NC
DQ23
NC
DM2
NC
DQ0 VDDQ VSSQ Ground
P VSS VDD2 CA0 NB VDDQ
DQ17
NC
DQ20
NC
DQS2_t
NC
DQS2_c
NC
VSSQ Do Not Use/NC/No Ball
R VDD1 VSS VACC NB VSS VSSQ VDDQ
DQ22
NC
VSSQ VDDQ ZQ
T DNU NC NC NB VDD2 VDD1
DQ16
NC
DQ18
NC
DQ21
NC
DNU Clock
U DNU DNU NB NB NB NB NB NB DNU DNU
JEDEC Standard No. 209-2E
Page 8
2.7 162-ball x16/x32 LPDDR2 and SDR-Flash package ballout
NOTE 1 0.5mm (x32, x16) or 0.65mm pitch (x32, x16), 20 rows
NOTE 2 162 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.1
1 2 3 4 5 6 7 8 9 10
A DNU DNU
WP_n
WP_n
DAT0
CLE
CLE
DAT6
VCCN
VCCN
VDDIm
IO4
DQ4
DAT5
IO7
DQ7
DAT3
VCCN
VCCN
VCCm
DNU DNU
B DNU
VCCN
VCCN
VCCm
IO11
DQS
DAT1
NB
ALE
ALE
DAT7
NB
RE_n
RE_n
CLKm
NB
IO5
DQ5
DAT4
NB
IO14
NC
DAT2
IO15
NC
VCCQm
VSS DNU
C
IO10
NC
RST_n
IO1
DQ1
NC
IO3
DQ3
VSSQm
WE_n
WE_n
NC
R/B_n
R/B_n
CMD
IO6
DQ6
NC
NB NB NB NB
SDR NVM Ball Definition
where 3 labels are present
D
IO8
NC
NC
IO0
DQ0
NC
IO2
DQ2
NC
CE_n
CE_n
NC
IO12
NC
NC
IO13
NC
NC
NB NB NB NB
1st Row
2nd Row
3rd Row
NVM device
ONFI device
eMMC device
E VSS
IO9
NC
NC
VACC NB VDD2 VDD1
DQ31
NC
DQ29
NC
DQ26
NC
DNU
LPDDR2 Ball Definition
where 2 labels are present
F VDD1 VSS ZQ1 NB VSS VSSQ VDDQ
DQ25
NC
VSSQ VDDQ
1st Row
2nd Row
x32 device
x16 device
G VSS VDD2 ZQ0 NB VDDQ
DQ30
NC
DQ27
NC
DQS3_t
NC
DQS3_c
NC
VSSQ
H VSSCA CA9 CA8 NB
DQ28
NC
DQ24
NC
DM3
NC
DQ15 VDDQ VSSQ
J VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ
K VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ
L VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB
M VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB
Flash Memory
(eMMC/NVM/ONFI) ADD/CTRL
N CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB LPDDR2 DQ
P CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ LPDDR2 CA
R CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ Power
T VSSCA VDDCA CA1 NB
DQ19
NC
DQ23
NC
DM2
NC
DQ0 VDDQ VSSQ Ground
U VSS VDD2 CA0 NB VDDQ
DQ17
NC
DQ20
NC
DQS2_t
NC
DQS2_c
NC
VSSQ Do Not Use/NC/No Ball
V VDD1 VSS VACC NB VSS VSSQ VDDQ
DQ22
NC
VSSQ VDDQ ZQ
W DNU NC NC NB VDD2 VDD1
DQ16
NC
DQ18
NC
DQ21
NC
DNU Clock
Y DNU DNU NB NB NB NB NB NB DNU DNU
JEDEC Standard No. 209-2E
Page 9
2.8 180-ball x16/x32 LPDDR2, SDR-Flash, and e-MMC package ballout
NOTE 1 0.5mm (x32, x16) or 0.65mm pitch (x32, x16), 22 rows
NOTE 2 180 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.1
1 2 3 4 5 6 7 8 9 10
A DNU DNU WP_n CLE VCCN
IO4
DQ4
IO7
DQ7
VCCN DNU DNU
B DNU VCCN
IO11
DQS
ALE RE_n
IO5
DQ5
IO14
NC
IO15
NC
VSS DNU
C
IO10
NC
IO1
DQ1
IO3
DQ3
WE_n R/B_n
IO6
DQ6
NB NB NB NB
SDR NVM Ball Definition
where 2 labels are present
D
IO8
NC
IO0
DQ0
IO2
DQ2
CE_n
IO12
NC
IO13
NC
NB NB NB NB
1st Row
2nd Row
NVM device
ONFI device
E VSS
IO9
NC
VACC NB VDD2 VDD1
DQ31
NC
DQ29
NC
DQ26
NC
DNU
LPDDR2 Ball Definition
where 2 labels are present
F VDD1 VSS ZQ1 NB VSS VSSQ VDDQ
DQ25
NC
VSSQ VDDQ
1st Row
2nd Row
x32 device
x16 device
G VSS VDD2 ZQ0 NB VDDQ
DQ30
NC
DQ27
NC
DQS3_t
NC
DQS3_c
NC
VSSQ
H VSSCA CA9 CA8 NB
DQ28
NC
DQ24
NC
DM3
NC
DQ15 VDDQ VSSQ
J VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ
K VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ
L VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB
M VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB
N CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB
P CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ
Flash Memory
(eMMC/NVM/ONFI) ADD/CTRL
R CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ LPDDR2 DQ
T VSSCA VDDCA CA1 NB
DQ19
NC
DQ23
NC
DM2
NC
DQ0 VDDQ VSSQ LPDDR2 CA
U VSS VDD2 CA0 NB VDDQ
DQ17
NC
DQ20
NC
DQS2_t
NC
DQS2_c
NC
VSSQ Power
V VDD1 VSS VACC NB VSS VSSQ VDDQ
DQ22
NC
VSSQ VDDQ Ground
W VCCm VDDIm NC NB VDD2 VDD1
DQ16
NC
DQ18
NC
DQ21
NC
DNU Do Not Use/NC/No Ball
Y VSS DAT2 CMD DAT6 DAT1 NB NB NB NB NB ZQ
AA DNU VCCQm DAT4 CLKm DAT0 VCCm NB NB NB DNU Clock
AB DNU DNU DAT3 DAT5 DAT7 VCCQm RST_n VSS DNU DNU
JEDEC Standard No. 209-2E
Page 10
2.9 121-ball x16 LPDDR2, SDR Flash-NVM, and e-MMC package ballout
NOTE 1 0.5mm pitch, 15 rows
NOTE 2 121 Ball Count
NOTE 3 Top View, A1 in Top Left Corner
NOTE 4 See JESD21-C, Section 3.12.2
1 2 3 4 5 6 7 8 9 10 11
A NC NC
DAT2
ADQ9
DQ2
DAT5
ADQ2
DQ5
VDDI
VCCQ
VCC VDD2 VSS VDDQ NC NC
B NC VSSx
DAT3
ADQ1
DQ3
DAT6
ADQ11
DQ6
DAT7
ADQ3
DQ7
VSSx VDD1 DQ15 DQ14 VSSQ NC
SDR NVM Ball Definition
where 3 labels are present
C VCCQ
DAT0
ADQ8
DQ0
DAT4
ADQ10
DQ4
CLK e
CLK o,f
DQS i
CMD e
RDY o
WAIT f
R/B_n n,i
RST_n e,f
RP_n o
CLE n,i
DQ11 DQ12 DQ13
1st Row
2nd Row
3rd Row
eMMC (e)
OneNAND (o) / AAD Nor (f)
Raw NAND (n) / ONFI2 (i)
D VDD2
DAT1
ADQ0
DQ1
DQ10 VSSQ
E VSS ZQ CA9 DQ8 DQ9 VDDQ
Flash Memory
(eMMC/Raw NAND/OneNAND)
F VDD1 CA8 VCCn VSSx
WE_n
CLK i
DQS1_t VSSQ LPDDR2 DQ
G VSSCA CA7 CA6
-
ADQ12
DQ12
OE_n o,f
RE_n n,i
W/R_n i
CE_n DQS1_c DM1 VDDQ LPDDR2 CA
H VDDCA CA5
-
ADQ13
DQ13
-
ADQ6
DQ11
-
ADQ4
DQ9
Vref(DQ) VDD2 Power
J VDD2 Vref(CA) VSS
-
ADQ14
DQ14
-
ADQ7
DQ10
-
ADQ5
DQ8
DQS0_c DM0 VDD1 Ground
K CK_t CK_c
-
ADQ15
DQ15
VSSx VCCn DQS0_t VDDQ Do Not Use/NC/No Ball
L CS0_n CS1_n CS2_n DQ7 DQ6 VSSQ ZQ
M CA4 CA3 DQ5 VDDQ Clock
N VDDCA CA2 CA1 CKE0
AVD_n o
ADV_n f
ALE n,i
-
INT o
WP_n f,n,i
DQ3 DQ2 VSSQ
P NC VSSCA CA0 CKE2 CKE1
VACC
VPP
DQ0 DQ1 DQ4 VSSQ NC
R NC NC VSS VDD2 VDD1 VSS VDD2 VSS VDDQ NC NC
Ball eMMC (e)
OneNAND (o)
AAD NOR (f)
NAND (n)
NAND
DDR (i)
- DAT[7:0] ADQ[15:0] DQ[15:0] DQ[15:0]
C5 CLK CLK - DQS
C6 CMD RDY / WAIT R/B_n R/B_n
C7 RST_n RP_n/RST_n CLE CLE
F7 - WE_n WE_n WE_n, CLK
G6 - OE_n RE_n RE_n, W/R_n
G7 - CE_n CE_n CE_n
N6 - AVD_n/AVD_n ALE ALE
N7 - INT / WP_n WP_n WP_n
VSSx represents common Flash VSS
JEDEC Standard No. 209-2E
Page 11
2.10 LPDDR2 Pad Sequence
NOTE 1 Pads with (*1) are optional.
NOTE 2 Ordering of DQ bits shall be maintained in the system, including within the package and on the PCB.
DQ byte swapping and DQ bit Swapping are not allowed in the system.
NOTE 3 CA pads and DQ pads shall be separated on opposite sides of die from top of silicon view.
Table 1 — LPDDR2 Pad Sequence
CA Pad Sequence DQ Pad Sequence
x32 x16 x8
S4 S2A S2B N-A N-B S4 S2A S2B N-A N-B S4 S2A S2B N-A N-B S2A S2B N-A N-B
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
VDD2 VDD2 VDD2 VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ
DQ31 DQ31 DQ31 DQ31 DQ31
DQ30 DQ30 DQ30 DQ30 DQ30
VDDQ VDDQ VDDQ VDDQ VDDQ
DQ29 DQ29 DQ29 DQ29 DQ29
DQ28 DQ28 DQ28 DQ28 DQ28
VSSQ VSSQ VSSQ VSSQ VSSQ
DQ27 DQ27 DQ27 DQ27 DQ27
DQ26 DQ26 DQ26 DQ26 DQ26
VDDQ VDDQ VDDQ VDDQ VDDQ
DQ25 DQ25 DQ25 DQ25 DQ25
DQ24 DQ24 DQ24 DQ24 DQ24
VSSQ VSSQ VSSQ VSSQ VSSQ
DQS3_t DQS3_t DQS3_t DQS3_t DQS3_t
DQS3_c DQS3_c DQS3_c DQS3_c DQS3_c
VDDQ VDDQ VDDQ VDDQ VDDQ
DM3 DM3 DM3 DM3 DM3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DQ15 DQ15 DQ15 DQ15 DQ15 DQ15 DQ15 DQ15 DQ15 DQ15
DQ14 DQ14 DQ14 DQ14 DQ14 DQ14 DQ14 DQ14 DQ14 DQ14
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQ13 DQ13 DQ13 DQ13 DQ13 DQ13 DQ13 DQ13 DQ13 DQ13
DQ12 DQ12 DQ12 DQ12 DQ12 DQ12 DQ12 DQ12 DQ12 DQ12
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DQ11 DQ11 DQ11 DQ11 DQ11 DQ11 DQ11 DQ11 DQ11 DQ11
DQ10 DQ10 DQ10 DQ10 DQ10 DQ10 DQ10 DQ10 DQ10 DQ10
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ZQ ZQ ZQ DQ9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ9 DQ9
CA9 CA9 CA9 CA9 CA9 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8 DQ8
CA8 CA8 CA8 CA8 CA8 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSSCA VSSCA VSSCA VSSCA VSSCA DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t
VDDCA VDDCA VDDCA VDDCA VDDCA DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c
CA7 CA7 CA7 CA7 CA7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CA6 CA6 CA6 CA6 CA6 DM1 DM1 DM1 DM1 DM1 DM1 DM1 DM1 DM1 DM1
CA5 CA5 CA5 CA5 CA5 VSSQ VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VDD1 VDD1 VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
Vref(CA) Vref(CA) Vref(CA) Vref(CA) Vref(CA) VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
VSS VSS VSS VSS VSS VSS VSS VSS VSS
*1
VSS
*1
VSS VSS VSS VSS
*1
VSS
*1
VSS VSS VSS
*1
VSS
VDDCA VDDCA VDDCA VDDCA VDDCA Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ)
CK_c CK_c CK_c CK_c CK_c
CK_t CK_t CK_t CK_t CK_t
VSSCA VSSCA VSSCA VSSCA VSSCA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CKE CKE CKE CKE CKE VDD2 VDD2 VDD2
*1
VDD2 VDD2 VDD2
*1
VDD2 VDD2
*1
CS_N CS_N CS_N CS_N CS_N VDD1 VDD1
*1
VDD1 VDD1
*1
VDD1 VDD1
*1
CA4 CA4 CA4 CA4 CA4 VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
CA3 CA3 CA3 CA3 CA3 VSSQ VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
VSSQ
*1
CA2 CA2 CA2 CA2 CA2 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0 DM0
VDDCA VDDCA VDDCA VDDCA VDDCA VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSSCA VSSCA VSSCA VSSCA VSSCA DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c
CA1 CA1 CA1 CA1 CA1 DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t
CA0 CA0 CA0 CA0 CA0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6 DQ6
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5 DQ5
DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3 DQ3
DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ1
DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 DQ0
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DM2 DM2 DM2 DM2 DM2
VDDQ VDDQ VDDQ VDDQ VDDQ
DQS2_c DQS2_c DQS2_c DQS2_c DQS2_c
DQS2_t DQS2_t DQS2_t DQS2_t DQS2_t
VSSQ VSSQ VSSQ VSSQ VSSQ
DQ23 DQ23 DQ23 DQ23 DQ23
DQ22 DQ22 DQ22 DQ22 DQ22
VDDQ VDDQ VDDQ VDDQ VDDQ
DQ21 DQ21 DQ21 DQ21 DQ21
DQ20 DQ20 DQ20 DQ20 DQ20
VSSQ VSSQ VSSQ VSSQ VSSQ
DQ19 DQ19 DQ19 DQ19 DQ19
DQ18 DQ18 DQ18 DQ18 DQ18
VDDQ VDDQ VDDQ VDDQ VDDQ
DQ17 DQ17 DQ17 DQ17 DQ17
DQ16 DQ16 DQ16 DQ16 DQ16
VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VDDQ VDDQ
*1
VDDQ
*1
VDDQ
*1
VDDQ
*1
VDD2 VDD2 VDD2 VACC VACC VACC VACC VACC VACC
VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
VSS VSS VSS VSS VSS VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS
*1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
JEDEC Standard No. 209-2E
Page 12
2.11 Input/output functional description
2.11.1 Pad Definition and Description
Table 2 — Pad Definition and Description
Name Type Description
CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA
inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR)
inputs, CS_n and CKE, are sampled at the positive Clock edge.
Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is
defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is
defined by the crosspoint of a falling CK_t and a rising CK_c.
CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and
therefore device input buffers and output drivers. Power savings modes are entered and
exited through CKE transitions.
CKE is considered part of the command code. See Command Truth Table on page 148
for command code descriptions.
CKE is sampled at the positive Clock edge.
CS_n Input Chip Select: CS_n is considered part of the command code. See Command Truth Table
on page 148 for command code descriptions.
CS_n is sampled at the positive Clock edge.
CA0 - CA9 Input DDR Command/Address Inputs: Uni-directional command/address bus inputs.
CA is considered part of the command code. See Command Truth Table on page 148 for
command code descriptions.
DQ0-DQ7
(x8)
DQ0 - DQ15
(x16)
DQ0 - DQ31
(x32)
I/O Data Inputs/Output: Bi-directional data bus
DQS0_t,
DQS0_c
(x8)
DQS0_t,
DQS0_c,
DQS1_t,
DQS1_c
(x16)
DQS0_t -
DQS3_t,
DQS0_c -
DQS3_c
(x32)
I/O Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for
read and write data) and differential (DQS_t and DQS_c). It is output with read data and
input with write data. DQS_t is edge-aligned to read data and centered with write data.
For x8, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7.
For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and
DQS1_c to the data on DQ8 - DQ15.
For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and
DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23,
DQS3_t and DQS3_c to the data on DQ24 - DQ31.
DM0
(x8)
DM0-DM1
(x16)
DM0 - DM3
(x32)
Input Input Data Mask: For LPDDR2 devices that do not support the DNV feature, DM is the
input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of
DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or
DQS_c).
DM0 is the input data mask signal for the data on DQ0-7.
For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is
the input data mask signal for the data on DQ24-31.
JEDEC Standard No. 209-2E
Page 13
NOTE 1 Data includes DQ and DM.
DM0/DNV0
(x8)
DM0/DNV0-
DM1/DNV1
(x16)
DM0/DNV0 -
DM3/DNV3
(x32)
I/0 Input Data Mask/Data Not Valid: For LPDDR2 devices that support the DNV feature,
DM/DNV is bidirectional (used for write and read data). It is output with read data, input
with write data. DM/DNV is the input mask signal for write data and is an output signal
validating a read burst.
For data write accesses:
Input data is masked when DM/DNV is sampled HIGH coincident with DQ input data
during a WRITE access.
DM0 is the input data mask signal for the data on DQ0-7.
For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is
the input data mask signal for the data on DQ24-31.
For data read accesses:
See “LPDDR2: Data Not Valid” on page 92 for detailed description of DNV functionality.
DNV0, DNV1, DNV2, and DNV3 are driven coincident with output read data. DNV0,
DNV1, DNV2, and DNV3 are driven with the same value and shall be sampled with
DQS0, DQS1, DQS2, and DQS3 respectively.
The DM/DNV loading shall match the DQ and DQS_t (or DQS_c) loading.
V
DD1
Supply Core Power Supply 1: Core power supply for LPDDR2-N and LPDDR2-SX devices.
V
DD2
Supply Core Power Supply 2: Core power supply for LPDDR2-S2B, LPDDR2-S4 and
LPDDR2-N-B devices.
V
DDCA
Supply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c
input buffers.
V
DDQ
Supply I/O Power Supply: Power supply for Data input/output buffers.
V
ACC
Supply NVM Acceleration Supply: NVM device specific embedded operation acceleration.
V
ACC
enables some NVM device specific functionality. When not used for NVM device
specific functionality, V
ACC
shall be driven to a level of V
DD1
.
V
REF(CA)
Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage
for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers.
V
REF(DQ)
Supply Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.
V
SS
Supply Ground
V
SSCA
Supply Ground for Input Receivers
V
SSQ
Supply I/O Ground
ZQ I/O Reference Pin for Output Drive Strength Calibration
Name Type Description
JEDEC Standard No. 209-2E
Page 14
2.12 LPDDR2 SDRAM Addressing
Table 3 — LPDDR2 SDRAM Addressing
NOTE 1 The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.
NOTE 2 t
REFI
values for all bank refresh is Tc = -25~85 °C, Tc means Operating Case Temperature
NOTE 3 Row and Column Address values on the CA bus that are not used are “don’t care.”
2.13 LPDDR2 NVM Addressing
2.13.1 Three-Phase Addressing
The memory controller delivers an array address to the memory in three phases (See Figure 1 on page 15 and
Figure 2 on page 16). The Command Truth Table on page 148 defines the required assignment of logical address bits
to CA pins. Scrambling of the logical address bits in any order different than those described in the Command truth
table is prohibited.
During a Preactive command, part of a row address (driven on the CA input pins) is stored in a Row Address Buffer
(RAB) selected by BA2-BA0.
During an Activate command, BA2-BA0 select an RAB to retrieve the first part of the row address. Meanwhile, the
remainder of the row address is driven on the CA input pins. These two parts of the row address select one row from
the memory array. Activate also causes internal sensing circuits to transfer that memory content into a Row Data
Buffer (RDB) also selected by BA2-BA0.
An {RAB, RDB} pair selected by BA2-BA0 is referred to as a Row Buffer (RB). BA2-BA0 do not address any
portion of the array and only select an RAB into which address is placed and/or an RDB into which data is placed.
The controller may use any value of BA2-BA0 for any array location.
During a Read or Write command BA2-BA0 selects an RDB, and the column address is driven on the CA input pins
to choose the starting address of the read or write burst.
The Preactive command is optional when the desired RAB already contains the desired partial row address. The
Activate command is optional when the desired RDB already contains the desired memory content.
Upon completion of Device Auto-Initialization, all Row Buffers are in the Idle state, and RABs contain 0x0000 and
all RDBs contain indeterminate values.
Items 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb
Device Type S2/S4 S2/S4 S2/S4 S2/S4 S2 S4 S2 S4 S2/S4 S2/S4
Number of Banks 4 4 4 4 4 8 4 8 8 8
Bank Addresses BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA2 BA0-BA1 BA0-BA2 BA0-BA2 BA0-BA2
t
REFI
(us)
*2
15.6 15.6 7.8 7.8 7.8 7.8 3.9 3.9 3.9 3.9
x8
Row Addresses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13 R0-R13 R0-R14
Column Addresses
*1
C0-C8 C0-C9 C0-C9 C0-C10 C0-C10 C0-C10 C0-C10 C0-C10 C0-C11 C0-C11
x16
Row Addresses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13 R0-R13 R0-R14
Column Addresses
*1
C0-C7 C0-C8 C0-C8 C0-C9 C0-C9 C0-C9 C0-C9 C0-C9 C0-C10 C0-C10
x32
Row Addresses R0-R11 R0-R11 R0-R12 R0-R12 R0-R13 R0-R12 R0-R14 R0-R13 R0-R13 R0-R14
Column Addresses
*1
C0-C6 C0-C7 C0-C7 C0-C8 C0-C8 C0-C8 C0-C8 C0-C8 C0-C9 C0-C9
JEDEC Standard No. 209-2E
Page 15
2.13.1 Three-Phase Addressing (cont’d)
NOTE 1 In the Preactive phase, a[max] is dependent on the density of the NVM device.
NOTE 2 In the Activate phase, the lower order row address bit a[x] is dependent on the size of the Row Data Buffer
(RDB).
NOTE 3 In the Read phase, column address bit C[y] is dependent on the size of the Row Data Buffer (RDB) and the
data bus width.
NOTE 4 An {RAB, RDB} pair selected by BA[2:0] is referred to as a Row Buffer (RB).
NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.
NOTE 6 An {RAB, RDB} pair can be associated with any portion of the memory array.
a[max:20]
Figure 1 — LPDDR2-N: Three-Phase Address Read
NVM

Preactive Phase
C[y:1]
BA[2:0]
Memory Array
RAB #0
RAB #1
RAB #2
RAB #3
RAB #7
RDB #0
RDB #1
RDB #2
RDB #3
RDB #7
Upper Row Address Lower Row Address
Activate Phase
a[19:x]
Output
State
Machine
DQ
Read Phase
BA[2:0]
Row Decoder
S
e
n
s
e

A
m
p
l
i
f
i
e
r
s
BA[2:0]
JEDEC Standard No. 209-2E
Page 16
2.13.1 Three-Phase Addressing (cont’d)
NOTE 1 In the Preactive phase, a[max] is dependent on the density of the NVM device.
NOTE 2 In the Activate phase, the lower order row address bit a[x] is dependent on the size of the Row Data Buffer
(RDB).
NOTE 3 In the Write phase, column address bit C[y] is dependent on the size of the Row Data Buffer (RDB) and
the data bus width.
NOTE 4 An {RAB, RDB} pair selected by BA[2:0] is referred to as a Row Buffer (RB).
NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.
Table 4 — 64 Mb Addressing
Configuration 8 Mb x 8 4 Mb x 16 2 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a22-a20 a22-a20 a22-a20
Lower Row Address (ACTIVE)
*1
a19-A5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 5 — 128 Mb Addressing
Configuration 16 Mb x 8 8 Mb x 16 4 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a23-a20 a23-a20 a23-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
a[max:20]
Figure 2 — LPDDR2-N: Three-Phase Address Write
NVM
Preactive Phase
C[y:1]
BA[2:0]
Memory Array
RAB #0
RAB #1
RAB #2
RAB #3
RAB #7
RDB #0
RDB #1
RDB #2
RDB #3
RDB #7
Upper Row Address Lower Row Address
Activate Phase
a[19:x]
Input
State
Machine
DQ
Write Phase
BA[2:0]
Row Decoder
S
e
n
s
e

A
m
p
l
i
f
i
e
r
s
BA[2:0]
JEDEC Standard No. 209-2E
Page 17
2.13.1 Three-Phase Addressing (cont’d)
Table 6 — 256 Mb addressing
Configuration 32 Mb x 8 16 Mb x 16 8 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a24-a20 a24-a20 a24-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 7 — 512 Mb addressing
Configuration 64 Mb x 8 32 Mb x 16 16 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a25-a20 a25-a20 a25-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 8 — 1 Gb addressing
Configuration 128 Mb x 8 64 Mb x 16 32 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a26-a20 a26-a20 a26-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 9 — 2 Gb addressing
Configuration 256 Mb x 8 128 Mb x 16 64 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a27-a20 a27-a20 a27-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 10 — 4 Gb addressing
Configuration 512 Mb x 8 256 Mb x 16 128 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a28-a20 a28-a20 a28-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
JEDEC Standard No. 209-2E
Page 18
2.13.1 Three-Phase Addressing (cont’d)
The following notes apply to Table 4 through Table 13 (Tables 4-13)
NOTE 1 All tables above show examples using minimum 32 Byte RDB Size, see Table 14 on page 19 for other
RDB sizes.
NOTE 2 The number of Row Buffers can be 4 or 8. A controller may use a smaller number of Row Buffers
provided that the appropriate most significant BA addresses are driven to “0”.
NOTE 3 One Row Buffer consists of a pair of one Row Address Buffer (RAB) and one Row Data Buffer
(RDB), selected by Buffer Address, BA0-BA2 (CA7r-CA9r).
NOTE 4 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.
NOTE 5 Row and Column Address values on the CA bus that are not used are “don’t care.”
Table 11 — 8 Gb addressing
Configuration 1 Gb x 8 512 Mb x 16 256 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a29-a20 a29-a20 a29-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 12 — 16 Gb addressing
Configuration 2 Gb x 8 1 Gb x 16 512 Mb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a30-a20 a30-a20 a30-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
Table 13 — 32 Gb addressing
Configuration 4 Gb x 8 2 Gb x 16 1 Gb x 32
# of Row Buffers
*2,3
4 4 4
Upper Row Address (PREACTIVE) a31-a20 a31-a20 a31-a20
Lower Row Address (ACTIVE)
*1
a19-a5 a19-a5 a19-a5
Column Address (READ/WRITE)
*1,4
a4-a1 (C4-C1) a4-a2 (C3-C1) a4-a3 (C2-C1)
RDB size
*1
32 Bytes 32 Bytes 32 Bytes
JEDEC Standard No. 209-2E
Page 19
2.13.1 Three-Phase Addressing (cont’d)
NOTE 1 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.
NOTE 2 Row and Column Address values on the CA bus that are not used are “don’t care.”
Table 14 — Addressing Dependent on RDB Size
RDB Size Configuration x8 x16 x32
32 Byte
Lower Row Address
a19-a5 a19-a5 a19-a5
Column Address
a4-a1(C4-C1) a4-a2(C3-C1) a4-a3(C2-C1)
64 Byte
Lower Row Address
a19-a6 a19-a6 a19-a6
Column Address
a5-a1(C5-C1) a5-a2(C4-C1) a5-a3(C3-C1)
128 Byte
Lower Row Address
a19-a7 a19-a7 a19-a7
Column Address
a6-a1(C6-C1) a6-a2(C5-C1) a6-a3(C4-C1)
256 Byte
Lower Row Address
a19-a8 a19-a8 a19-a8
Column Address
a7-a1(C7-C1) a7-a2(C6-C1) a7-a3(C5-C1)
512 Byte
Lower Row Address
a19-a9 a19-a9 a19-a9
Column Address
a8-a1(C8-C1) a8-a2(C7-C1) a8-a3(C6-C1)
1 KB
Lower Row Address
a19-a10 a19-a10 a19-a10
Column Address
a9-a1(C9-C1) a9-a2(C8-C1) a9-a3(C7-C1)
2 KB
Lower Row Address
a19-a11 a19-a11 a19-a11
Column Address
a10-a1(C10-C1) a10-a2(C9-C1) a10-a3(C8-C1)
4 KB
Lower Row Address
a19-a12 a19-a12 a19-a12
Column Address
a11-a1(C11-C1) a11-a2(C10-C1) a11-a3(C9-C1)
JEDEC Standard No. 209-2E
Page 20
3 Functional description
LPDDR2-S is a high-speed SDRAM device internally configured as a 4 or 8-Bank memory.
LPDDR2-N is a high-speed Non-Volatile Memory device, internally configured to have 4 or 8 Row Buffers.
These devices contain the following number of bits:
64 Mb has 67,108,864 bits
128 Mb has 134,217,728 bits
256 Mb has 268,435,456 bits
512 Mb has 536,870,912 bits
1 Gb has 1,073,741,824 bits
2 Gb has 2,147,483,648 bits
4 Gb has 4,294,967,296 bits
8 Gb has 8,589,934,592 bits

The following densities apply to LPDDR2-NVM devices only:
16 Gb has 17,179,869,184 bits
32 Gb has 34,359,738,368 bits
All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number of
input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each
command uses one clock cycle, during which command information is transferred on both the positive and negative
edge of the clock.
LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double
data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data bits per
DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S2 effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal SDRAM core and two corresponding n-bit wide, one-half-
clock-cycle data transfers at the I/O pins.
LPDDR2-S4 and LPDDR2-N also use a double data rate architecture on the DQ pins to achieve high speed operation.
The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two
data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 and LPDDR2-N
effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM/NVM core and four
corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
For LPDDR2-SX devices, accesses begin with the registration of an Activate command, which is then followed by a
Read or Write command. The address and BA bits registered coincident with the Activate command are used to select
the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used
to select the Bank and the starting column location for the burst access.
For LPDDR2-N devices, accesses begin with the registration of an Preactive command, followed by an Activate
command, which is then followed by a Read or Write command. The address and BA bits registered coincident with
the Preactive and Activate commands are used to select the row and the Row Buffer to be accessed. The address bits
registered coincident with the Read or Write command are used to select the Row Buffer and the starting column
location for the burst access.
For LPDDR2-NVM devices, operations other than “array reads” are performed by accessing an overlay window that
is mapped over the array space of the memory. The Overlay Window Base Address (OWBA) is programmed using
the Mode Registers. The overlay window is enabled and disabled by using the Mode Register. When the overlay
window is disabled, all array accesses map to the memory array. When the overlay window is enabled, reads and
writes to Overlay Window within the array memory space access the Overlay Window.
Prior to normal operation, the LPDDR2 must be initialized. The following section provides detailed information
covering device initialization, register definition, command description and device operation.
JEDEC Standard No. 209-2E
Page 21
3.1 Simplified LPDDR2 Bus Interface State Diagram
The simplified LPDDR2 bus interface state diagram provides a simplified illustration of allowed state transitions and
the related commands to control them. For a complete definition of the device behavior, the information provided by
the state diagram should be integrated with the truth tables and timing specification.
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
applied restrictions when considering the actual state of all the banks.
For the command definition, see “LPDDR2 Command Definitions and Timing Diagrams” on page 81.
JEDEC Standard No. 209-2E
Page 22
3.1 Simplified LPDDR2 Bus Interface State Diagram (cont’d)
Self
Idle
*3
Reading
Precharging
*2
Writing
ACT
RD
SREF
*2
REF
*2
PD
MRR
PDX
PDX
PD
WR
Automatic Sequence
Command Sequence
RDA
*2 WRA
*2
Refreshing
Refreshing
Power
Down
Active
*4
with
Reading
with
Active
Reading Writing
PR(A) = Precharge
*2
(All)
MRW = Mode Register Write
SREF = Enter Self Refresh
*2
REF = Refresh
*2
PD = Enter Power Down
PDX = Exit Power Down
ACT = Activate
WR(A) = Write (with Autoprecharge
*2
)
RD(A) = Read (with Autoprecharge
*2
)
SREFX
*2
RD
BST
MR
Autoprecharge Autoprecharge
Deep
Power DPDX
*2
Power
Down
On
BST
WR
BST = Burst Terminate
MRR = Mode Register Read
SREFX = Exit Self Refresh
*2
DPD = Enter Deep Power Down
*2
DPDX = Exit Deep Power Down
*2

MRR
MRW
DPD
*2
Power
Applied
MR
Writing
MR
Reading
Resetting
MR
Reading
Reset
Reset = Reset is achieved through MRW command
MRR
RDA
*2
WRA
*2
Reset
Resetting
Preactivating
*1
Active
Down
Power
Idle
PREACT
*1
Idle
PREACT = Preactive
*1
SDRAM only
*2
NVM only
*1
NVM + SDRAM
Figure 3 — LPDDR2: Simplified Bus Interface State Diagram
NOTE 1 These transitions apply for LPDDR2-N devices only.
NOTE 2 These transitions apply for LPDDR2-SX devices only.
PR
*2
, PRA
*2
PREACT
*1
Power
Down
Resetting
PD
PDX
ACT
*1
MRW
*1
Reset
*1
NOTE 3 For LPDDR2-SDRAM in the Idle state, all banks are precharged.
NOTE 4 For LPDDR2-NVM in the Active state, one or more Row Buffers have been activated.
NOTE 5 Use caution with this diagram. It is intented to provide a floorplan of the possible state transitions
and commands to control them, not all details. In particular, situations involving more than one Bank/Row
Buffer are not captured in full detail.
NOTE 6 Resetting duration is variable. Poll DAI status bit to detect state transition to Idle.
NOTE 7 Reset command sets all Row Address Buffers to 0x0000.
PR
*2
, PRA
*2
JEDEC Standard No. 209-2E
Page 23
3.2 Simplified LPDDR2-SX State Diagram
LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related
commands to control them. For a complete definition of the device behavior, the information provided by the state
diagram should be integrated with the truth tables and timing specification.
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
applied restrictions when considering the actual state of all the banks.
For the command definition, see “LPDDR2 Command Definitions and Timing Diagrams” on page 81.
JEDEC Standard No. 209-2E
Page 24
3.2 Simplified LPDDR2-SX State Diagram (cont’d)
Self
Idle
Reading
Precharging
Writing
ACT
RD
SREF
REF
PD
MRR
PDX
PDX
PD
WR
Automatic Sequence
Command Sequence
RDA
WRA
Refreshing
Refreshing
Power
Down
Active
*1
with
Reading
with
Active
Reading Writing
PR(A) = Precharge (All)
MRW = Mode Register Write
SREF = Enter Self Refresh
REF = Refresh
PD = Enter Power Down
PDX = Exit Power Down
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
SREFX
RD
BST
MR
Autoprecharge Autoprecharge
Deep
Power DPDX
Power
Down
On
BST
WR
BST = Burst Terminate
MRR = Mode Register Read
SREFX = Exit Self Refresh
DPD = Enter Deep Power Down
DPDX = Exit Deep Power Down
MRR
MRW
DPD
Power
Applied
MR
Writing
MR
Reading
Resetting
MR
Reading
Reset
Reset = Reset is achieved through MRW command
MRR
RDA WRA
Reset
Resetting
Active
Down
Power
Idle
Idle
Figure 4 — LPDDR2-S: Simplified Bus Interface State Diagram
PR, PRA
Power
Down
Resetting
PD
PDX
NOTE 1 For LPDDR2-SDRAM in the Idle state, all banks are precharged.
PR, PRA
JEDEC Standard No. 209-2E
Page 25
3.3 Simplified LPDDR2-N Simplified Bus State Diagram
LPDDR2-NVM simplified bus interface state diagram provides a simplified illustration of allowed bus interface state
transitions and the related commands to control them. For a more detalied definition of the device bus interface, the
information provided by the state diagram should be integrated with the truth tables and timing specification.
For the command definition see section See “LPDDR2 Command Definitions and Timing Diagrams” on page 81
LPDDR2-NVM has two types of states: stable states, which are entered and exited with a command, and transitory
states, which are entered with a command and exited automatically.
LPDDR2-NVM stable states are: Power-on, Idle, Active, Resetting Power Down, Idle Power Down, and Active
Power Down.
LPDDR2-NVM transitory states are: Resetting, Resetting MR Reading, Idle MR Reading, MR Writing, Active MR
Reading, Reading, Writing and Preactivating.
LPDDR2-NVM state diagram is shown in Figure 5 on page 27, where each state transition, due to a command, is
represented with a numbered arc.
Follows the description of all the allowed commands for any given state. The arc number of each transition is
included in the description in parenthesis.
3.3.1 Power On and Resetting states
(1) After power up, the device goes in the Power On state.
(2) The Reset command is the only command allowed in this state, and when issued, it brings all Row Buffers (RB)
into the Resetting state after t
INIT4
.
(3) Mode Register Read (MRR) command can be issued from the Resetting state. MRR allows retrieving useful
information such as: memory type, memory characteristics, or the Resetting status through the DAI bit. The device
enters in Resetting Mode Register Reading state when MRR command is registered, and goes back automatically to
Resetting state after t
MRR
.
(4) Enter Power Down command brings all Row Buffers into the Resetting Power Down state. For the complete
description of Power Down entry, see “Power-down” on page 138.
(5) Exit Power Down command brings all Row Buffers from the Resetting Power Down state back to the Resetting
state after t
XP
. For the complete description of Power Down exit, see “Power-down” on page 138.
The duration of Resetting, t
INIT5
, is device specific and it is not defined in this document. The memory controller
shall poll DAI bit to determine the completion of the device initialization. Upon completion of device initialization,
all Row Buffers are in the Idle state and all RABs have a default value of 0x0000.
3.3.2 Idle state
From the Idle state, the following commands are allowed: Reset, Mode Register Write, Mode Register Read,
Preactive, Activate and Enter Power Down.

(6) Reset command brings all Row Buffers into the Resetting state after t
INIT4
.
(7) Mode Register Write command brings all Row Buffers to the MR Writing state. All Row Buffers return to the Idle
state after t
MRW
.
(8) Mode Register Read command brings the Row Buffer to the Idle MR Reading state. The Row Buffer goes
automatically back to the Idle state after t
MRR
.
(9) Preactive command brings the Row Buffer to the Preactivating state. The Row Buffer goes automatically back to
the Idle state after t
RP
.
JEDEC Standard No. 209-2E
Page 26
3.3.2 Idle state (cont’d)
(10) Activate command brings the Row Buffer from the Idle state to the Row Activating state, which is not explicitly
shown in the state diagram. The Row Buffer goes automatically from the Row Activating state to the Active state
after t
RCD
.
(11) Enter Power Down command brings the Row Buffer into the Idle Power Down state. For the complete
description of power down entry see “Power-down” on page 138.
(12) Exit Power Down command brings the Row Buffer from the Idle Power Down state back to the Idle state after
t
XP
. For the complete description of power down exit see “Power-down” on page 138.
3.3.3 Active state
From the Active state, the following commands are allowed: Reset, Mode Register Write, Mode Register Read,
Preactive, Activate, Read, Write and Enter Power Down.
(13) Reset command brings all Row Buffers into the Resetting state after t
INIT4
.
(14) Mode Register Write command brings all Row Buffers to the MR Writing state. All Row Buffers return to the
Idle state after t
MRW
.
(15) Mode Register Read command brings the Row Buffer to the Active MR Reading state. The Row Buffer goes
automatically back to the Active state after t
MRR
.
(16) Preactive command brings the Row Buffer to the Preactivating state. The Row Buffer goes automatically to the
Idle state after t
RP
.
(17) Activate command brings the Row Buffer from the Active state to the Row Activating state, which is not
explicitly shown in the state diagram. The Row Buffer goes automatically back to the Active state after t
RCD
.
(18) Read command moves the Row Buffer to the Reading state. The Row Buffer goes automatically back to the Row
Active state after BL/2 clock cycles, or after a Burst Terminate command. See “Burst Read Command” on page 86
for timing restrictions to apply between the Read command and a following Read, Write, Mode Register Write, Mode
Register Read, Preactive, Activate or Enter Power Down commands that might occur. If a new Read command is
issued within BL/2 clock cycles, the Row Buffer remains in the Reading state.
(19) Write command moves the Row Buffer to the Writing state. The Row Buffer goes automatically back to the Row
Active state after BL/2 clock cycles, or after a Burst Terminate command. See “Burst Write Operation” on page 94
for timing restrictions to apply between the Write command and the following Write, Read, Mode Register Write,
Mode Register Read, Preactive, Activate or Enter Power Down commands that might occur. If a new Write command
is issued within BL/2 clock cycles, the Row buffer remains in the Writing state.
(20) Enter Power Down command brings the Row Buffer into the Active Power Down state. For the complete
description of power down entry see “Power-down” on page 138.
(21) Exit Power Down command brings the Row Buffer from the Active Power Down state back to the Row Active
state after t
XP
. For the complete description of power down exit see “Power-down” on page 138.
JEDEC Standard No. 209-2E
Page 27
3.3.3 Active state (cont’d)
Idle
Reading
ACT
RD
PD
MRR
PDX
PDX
PD
WR
Automatic Sequence
Command Sequence
Power
Down
Active
Active
Reading Writing
MRW = Mode Register Write
PD = Enter Power Down
PDX = Exit Power Down
ACT = Activate
WR = Write
RD = Read
RD
BST
MR
Power
On
BST
WR
BST = Burst Terminate
MRR = Mode Register Read
MRR
MRW
Power
Applied
MR
Writing
MR
Reading
Resetting
MR
Reading
Reset
Reset = Reset is achieved through MRW command
MRR
Reset
Resetting
Preactivating
Active
Down
Power
Idle
PREACT
Idle
PREACT = Preactive
Figure 5 — LPDDR2-N: Simplified Bus Interface State Diagram
PREACT
Power
Down
Resetting
PD
PDX
ACT
MRW
Reset
NOTE 1 For LPDDR2-NVM in the Active state, one or more Row Buffers have been activated.
NOTE 2 Use caution with this diagram. It is intented to provide a floorplan of the possible state transitions
and commands to control them, not all details. In particular, situations involving more than one Row
Buffer are not captured in full detail.
NOTE 3 Resetting duration is variable. Poll DAI status bit to detect state transition to Idle.
NOTE 4 Reset command sets all Row Address Buffers to 0x0000.
1
2
3
4
5
6
8
7
12
11
9
10
14
13
17
15
18
19
20
21
16
JEDEC Standard No. 209-2E
Page 28
3.4 Power-up, Initialization, and Power-Off
LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
3.4.1 Power Ramp and Device Initialization
The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these steps are
mandatory and apply to S2, S4 and N devices.
1. Power Ramp
While applying power (after Ta), CKE shall be held at a logic low level (=< 0.2 x VDDCA), all other inputs shall
be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance
state while CKE is held low.
On or before the completion of the power ramp (Tb) CKE must be held low.
DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid
latch-up. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to
avoid latch-up.
The following conditions apply:
Ta is the point where any power supply first reaches 300 mV.
After Ta is reached, VDD1 must be greater than VDD2 - 200 mV.
After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200 mV.
After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200 mV.
After Ta is reached, VREF must always be less than all other supply voltages.
The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV.
The above conditions apply between Ta and power-off (controlled or uncontrolled).
Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference
voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes
high.
For supply and reference voltage operating conditions, see Table 7.1 on page 160, Table 70 on page 160, and
Table 71 on page 160.
Power ramp duration t
INIT0
(Tb - Ta) must be no greater than 20 ms.
NOTE VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply.
2. CKE and clock:
Beginning at Tb, CKE must remain low for at least t
INIT1
= 100 ns, after which it may be asserted high. Clock
must be stable at least t
INIT2
= 5 x tCK prior to the first low to high transition of CKE (Tc). CKE, CS_n and CA
inputs must observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well
as to the subsequent falling and rising edges).

The clock period shall be within the range defined for t
CKb
(18 ns to 100 ns), if any Mode Register Reads are per-
formed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are
met. Furthermore, some AC parameters (e.g. t
DQSCK
) may have relaxed timings (e.g. t
DQSCKb
) before the system
is appropriately configured.

While keeping CKE high, issue NOP commands for at least t
INIT3
= 200 us. (Td).
3. Reset command:
After t
INIT3
is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally
issue a Precharge-All command (for LPDDR2-SX) or Preactive (for LPDDR2-N) prior to the MRW Reset com-
mand. For LPDDR2-N devices, the subsequent MRW Reset command will set each Row Address Buffers (RAB)
to 0x0000 overwriting the value stored by the previous preactive command. Wait for at least t
INIT4
= 1 µs while
keeping CKE asserted and issuing NOP commands.
JEDEC Standard No. 209-2E
Page 29
3.4.1 Power Ramp and Device Initialization (cont’d)
4. Mode Registers Reads and Device Auto-Initialization (DAI) polling:
After t
INIT4
is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed.
Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification (see “Power-
down” on page 138).

The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete
or the memory controller shall wait a minimum of tINIT5 before proceeding.
As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings
before the system is appropriately configured.
After the DAI-bit (MR0, “DAI”) is set to zero “DAI complete“ by the memory device, the device is in idle state
(Tf). The state of the DAI status bit can be determined by an MRR command to MR0.

All SDRAM devices will set the DAI-bit no later than t
INIT5
(10 us) after the Reset command. The memory con-
troller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.

For NVM devices, repetitive polling of the DAI-Bit is required to determine when this bit has internally been set
to zero “DAI complete“ by the memory device. A Value for t
INIT5
value is not defined for NVMs in this document
because it is device dependent. The only way to determine when Device Auto-Initialization is complete is to poll
DAI. To obtain the shortest boot up time and ensure compatibility with any future NVM device it is recommended
to not rely on any predetermined t
INIT5
value.

After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issu-
ing MRR commands (MR0 “Device Information” etc.).
5. ZQ Calibration:
After t
INIT5
(Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). For
LPDDR2 devices which do not support the ZQ Calibration command, this command shall be ignored. This com-
mand is used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature. Optionally,
the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in
which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration
commands. The device is ready for normal operation after tZQINIT.
6. Normal Operation:
After t
ZQINIT
(Tg), MRW commands shall be used to properly configure the memory, for example the output buf-
fer driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the
target frequency and memory configuration.
To support simple boot from the NVM, some Mode Registers are reset to default values during Device Auto-Ini-
tialization. See the Mode Register section of this specification for default values.
The LPDDR2 device will now be in IDLE state and ready for any valid command.
After Tg, the clock frequency may be changed according to the clock frequency change procedure described in
section “Input clock stop and frequency change” on page 146 of this specification.
JEDEC Standard No. 209-2E
Page 30
3.4.1 Power Ramp and Device Initialization (cont’d)
Figure 6 — Power Ramp and Initialization Sequence
3.4.2 Initialization after Reset (without Power ramp):
If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall
begin with step 3 (Td).
Table 15 — Timing Parameters for initialization
Symbol
Value
Unit Comment
min max
t
INIT0
20 ms Maximum Power Ramp Time
t
INIT1
100 ns Minimum CKE low time after completion of power ramp
t
INIT2
5 tCK Minimum stable clock before first CKE high
t
INIT3
200 µs Minimum Idle time after first CKE assertion
t
INIT4
1 µs Minimum Idle time after Reset command
t
INIT5
S: 10 µs
Maximum duration of
Device Auto-Initialization
N: vendor µs
t
ZQINIT
1 µs
ZQ Initial Calibration for LPDDR2-S4 and LPDDR2-N
devices
t
CKb
18 100 ns Clock cycle time during boot
CK_t / CK_c
Supplies
CKE
CA*
DQ
t
ISCKE

t
INIT0
= 20 ms (max)
t
INIT3
= 200 us (min)
t
INIT1
= 100 ns (min)
t
INIT2
= 5 t
CK
(min)
t
INIT4
= 1 us (min)
t
INIT5

* Midlevel on CA bus means: valid NOP
PD
RESET MRR ZQC
Ta Tb Tc Td Te Tf
Valid
t
ZQINIT

Tg
JEDEC Standard No. 209-2E
Page 31
3.4.3 Power-off Sequence
The following sequence shall be used to power off the LPDDR2 device. Unless specified otherwise, these steps are
mandatory and apply to S2, S4 and N devices.
While removing power, CKE shall be held at a logic low level (=< 0.2 x VDDCA), all other inputs shall be between
VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE
is held low.
For LPDDR2-N devices, all embedded operations must be finished or aborted and the device must be in the ready
state (Status Register, bit 7 = “1”) prior to Power-off.
DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid
latch-up. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during power off sequence
to avoid latch-up.
Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition
table.
Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off.
The time between Tx and Tz (t
POFF
) shall be less than 2s.
The following conditions apply:
Between Tx and Tz, VDD1 must be greater than VDD2 - 200 mV.
Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV.
Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV.
Between Tx and Tz, VREF must always be less than all other supply voltages.
The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV.
For supply and reference voltage operating conditions, see Table 7.1 on page 160, Table 70 on page 160, and
Table 71 on page 160.
NOTE VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply.
3.4.4 Uncontrolled Power-Off Sequence
The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition. Unless
specified otherwise, these steps are mandatory and apply to S2, S4 and N devices.
Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition
table. After turning off all power supplies, any power supply current capacity must be zero, except for any static
charge remaining in the system.
Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off.
The time between Tx and Tz (t
POFF
) shall be less than 2s. The relative level between supply voltages are uncontrolled
during this period.
VDD1 and VDD2 shall decrease with a slope lower than 0.5 V/usec between Tx and Tz.
Uncontrolled power off sequence can be applied only up to 400 times in the life of the device.
Table 16 — Timing Parameters Power-Off
Symbol
Value
Unit Comment
min max
t
POFF
- 2 s Maximum Power-Off ramp time
JEDEC Standard No. 209-2E
Page 32
3.5 Mode Register Definition
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM
Table 17 shows the 16 common mode registers for LPDDR2 SDRAM and NVM. Table 18 shows only LPDDR2
SDRAM mode registers and Table 19 shows only LPDDR2 NVM mode registers. Additionally Table 20 shows
RFU mode registers and Reset Command.
Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it
can be read and written.
Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to write
a register.
Table 17 — Mode Register Assignment in LPDDR2 SDRAM/NVM(Common part)
MR#
MA
<7:0>
Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
0 00
H
Device Info. R (RFU)
RZQI
(optional)
DNVI DI DAI go to MR0
1 01
H
Device Feature 1 W nWR (for AP) WC BT BL go to MR1
2 02
H
Device Feature 2 W (RFU) RL & WL go to MR2
3 03
H
I/O Config-1 W (RFU) DS go to MR3
4 04
H
SDRAM Refr. R. R TUF (RFU) Refresh Rate
go to MR4
NVM Temp. Alert R TUF (RFU) NVM Temp. Alert
5 05
H
Basic Config-1 R LPDDR2 Manufacturer ID go to MR5
6 06
H
Basic Config-2 R Revision ID1 go to MR6
7 07
H
Basic Config-3 R Revision ID2 go to MR7
8 08
H
Basic Config-4 R I/O width Density Type go to MR8
9 09
H
Test Mode W Vendor-Specific Test Mode go to MR9
10 0A
H
IO Calibration W Calibration Code go to MR10
11:15 0B
H
~0F
H
(reserved) (RFU) go to MR11
Table 18 — Mode Register Assignment in LPDDR2 SDRAM/NVM (SDRAM part)
MR#
MA
<7:0>
Function access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
16 10
H
PASR_Bank (S4)
W
Bank Mask
go to MR16
PASR_Bank (S2) (RFU) PASR
17 11
H
PASR_Seg W Segment Mask (S4 SDRAM only) go to MR17
18-19 12
H
-13
H
(Reserved) (RFU) go to MR18
JEDEC Standard No. 209-2E
Page 33
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
The following notes apply to tables 17-20:
NOTE 1 RFU bits shall be set to ‘0’ during Mode Register writes.
NOTE 2 RFU bits shall be read as ‘0’ during Mode Register reads.
NOTE 3 All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t,
DQS_c shall be toggled.
NOTE 4 All Mode Registers that are specified as RFU shall not be written.
NOTE 5 See Vendor Device Datasheets for details on Vendor Specific Mode Registers.
NOTE 6 Writes to read-only registers shall have no impact on the functionality of the device.
Table 19 — Mode Register Assignment in LPDDR2 SDRAM/NVM (NVM part)
MR#
MA
<7:0>
Function access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
20 14
H
NVM Geometry R (RFU)
tRCD
De-Rating
RB
Number
RDB size go to MR20
21 15
H
NVM tRCD R tRCD Value (2nd order) tRCD Value (1st order) go to MR21
22-23 16
H
-17
H
(Reserved) (RFU) go to MR22
24 18
H
Overlay Window
Enable
R/W (RFU) OWD OWE go to MR24
25 19
H
OW Base-Addr 1 R/W OW base-addr 31 (a19 ~ a13) 0
go to MR25
26 1A
H
OW Base-Addr 2 R/W OW base-addr 2 (a27 ~ a20)
27 1B
H
OW Base-Addr 3 R/W (RFU)
OW base-addr 3
(a31 ~ a28)
28 1C
H
(Reserved) (RFU) go to MR28
29 1D
H
DNV Long Delay R tDNV Value (2nd order) tDNV Value (1st order) go to MR29
30-31 1E
H
-1F
H
(Reserved) (RFU) go to MR30
Table 20 — Mode Register Assignment in LPDDR2 SDRAM/NVM
(DQ Calibration and Reset Command)
MR#
MA
<7:0>
Function access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
32 20
H
DQ Calibration
Pattern A
R See “DQ Calibration” on page 130 go to MR32
33:39 21
H
~27
H
(Do Not Use) go to MR33
40 28
H
DQ Calibration
Pattern B
R See “DQ Calibration” on page 130 go to MR40
41:47 29
H
~2F
H
(Do Not Use) go to MR41
48:62 30
H
~3E
H
(Reserved) (RFU) go to MR48
63 3F
H
Reset W X go to MR63
64:126 40
H
~7E
H
(Reserved) (RFU) go to MR64
127 7F
H
(Do Not Use) go to MR127
128:190 80
H
~BE
H
(Reserved for
Vendor Use)
(RFU) go to MR128
191 BF
H
(Do Not Use) go to MR191
192:254 C0
H
~FE
H
(Reserved for
Vendor Use)
(RFU) go to MR192
255 FF
H
(Do Not Use) go to MR255
JEDEC Standard No. 209-2E
Page 34
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR0_Device Information (MA<7:0> = 00
H
):
NOTE 1 LPDDR2 SDRAM will not implement DNV functionality.
NOTE 2 If DNV functionality is not implemented, the device shall not drive the DM/DNV signals.
NOTE 3 RZQI, if supported, will be set upon completion of the MRW ZQ Initialization Calibration command.
NOTE 4 If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to
VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the
assembly error is corrected.
NOTE 5 In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR2 device
will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system
may not function as intended.
NOTE 6 In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a
resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ
resistor tolerance meets the specified limits (i.e. 240-ohm +/-1%).
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU)
RZQI
(optional)
DNVI DI DAI
DAI (Device Auto-Initialization Status) Read-only OP0
0
B
: DAI complete
1
B
: DAI still in progress
DI (Device Information) Read-only OP1
0
B
: S2 or S4 SDRAM
1
B
: NVM
DNVI (Data Not Valid Information) Read-only OP2
0
B
: DNV not supported
1
B
: DNV supported
1,2
RZQI (Built in Self Test for RZQ
Information)
Read-only OP4:OP3
00
B
: RZQ self test not
supported
01
B
: ZQ-pin may con-
nect to VDDCA or float
10
B
: ZQ-pin may short
to GND
11
B
: ZQ-pin self test
completed, no error
condition detected (ZQ-
pin may not connect to
VDDCA or float nor
short to GND)
3
JEDEC Standard No. 209-2E
Page 35
MR1_Device Feature 1 (MA<7:0> = 01
H
):
NOTE 1 BL 16, interleaved is not an official combination to be supported.
NOTE 2 Programmed value in nWR register is the number of clock cycles which determines when to start internal
precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK).
NOTE 3 BL16 is not supported by LPDDR2-NVM with Row Data Buffer size equal to 32-Byte and Data Bus
Width equal to 32-bit.
NOTE 4 OP7:OP5 are reserved for LPDDR2-NVM.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
nWR (for AP) WC BT BL
BL Write-only OP<2:0>
010
B
: BL4 (default)
011
B
: BL8
100
B
: BL16
All others: reserved
BT Write-only OP<3>
0
B
: Sequential (default)
1
B
: Interleaved (allowed for SDRAM only)
1
WC Write-only OP<4>
0
B
: Wrap (default)
1
B
: No wrap (allowed for SDRAM BL4 only)
nWR Write-only OP<7:5>
001
B
: nWR=3 (default)
010
B
: nWR=4
011
B
: nWR=5
100
B
: nWR=6
101
B
: nWR=7
110
B
: nWR=8
All others: reserved
2
JEDEC Standard No. 209-2E
Page 36
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
Table 21 — Burst Sequence by BL, BT, and WC
1. C0 input is not present on CA bus. It is implied zero.
2. For BL=4, the burst address represents C1 - C0.
3. For BL=8, the burst address represents C2 - C0.
4. For BL=16, the burst address represents C3 - C0.
5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page bound-
ary. The variable y may start at any address with C0 equal to 0 and may not start at any address in
Table 22 below for the respective density and bus width combinations.
C3 C2 C1 C0 WC BT BL
Burst Cycle Number and Burst Address Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
X X 0
B
0
B
wrap any
4
0 1 2 3
X X 1
B
0
B
2 3 0 1
X X X 0
B
nw any y y+1 y+2 y+3
X 0
B
0
B
0
B
wrap
seq
8
0 1 2 3 4 5 6 7
X 0
B
1
B
0
B
2 3 4 5 6 7 0 1
X 1
B
0
B
0
B
4 5 6 7 0 1 2 3
X 1
B
1
B
0
B
6 7 0 1 2 3 4 5
X 0
B
0
B
0
B
int
0 1 2 3 4 5 6 7
X 0
B
1
B
0
B
2 3 0 1 6 7 4 5
X 1
B
0
B
0
B
4 5 6 7 0 1 2 3
X 1
B
1
B
0
B
6 7 4 5 2 3 0 1
X X X 0
B
nw any illegal (not allowed)
0
B
0
B
0
B
0
B
wrap
seq
16
0 1 2 3 4 5 6 7 8 9 A B C D E F
0
B
0
B
1
B
0
B
2 3 4 5 6 7 8 9 A B C D E F 0 1
0
B
1
B
0
B
0
B
4 5 6 7 8 9 A B C D E F 0 1 2 3
0
B
1
B
1
B
0
B
6 7 8 9 A B C D E F 0 1 2 3 4 5
1
B
0
B
0
B
0
B
8 9 A B C D E F 0 1 2 3 4 5 6 7
1
B
0
B
1
B
0
B
A B C D E F 0 1 2 3 4 5 6 7 8 9
1
B
1
B
0
B
0
B
C D E F 0 1 2 3 4 5 6 7 8 9 A B
1
B
1
B
1
B
0
B
E F 0 1 2 3 4 5 6 7 8 9 A B C D
X X X 0
B
int illegal (not allowed)
X X X 0
B
nw any illegal (not allowed)
JEDEC Standard No. 209-2E
Page 37
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
Table 22 — LPDDR2-SX Non Wrap Restrictions
NOTE 1 Non-wrap BL=4 data-orders shown above are prohibited.
MR2_Device Feature 2 (MA<7:0> = 02
H
):
MR3_I/O Configuration 1 (MA<7:0> = 03
H
):
64Mb 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb
Not across full page boundary
x8 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001 FFE, FFF, 000, 001
x16 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001
x32 7E, 7F, 00, 01 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001
Not across sub page boundary
x8
07E, 07F, 080, 081
0FE, 0FF, 100, 101
17E, 17F, 180, 181
0FE, 0FF, 100, 101
1FE, 1FF, 200, 201
2FE, 2FF, 300, 301
1FE, 1FF, 200, 201
3FE, 3FF, 400, 401
5FE, 5FF, 600, 601
3FE, 3FF, 400, 401
7FE, 7FF, 800, 801
BFE, BFF, C00, C01
x16 7E, 7F, 80, 81 0FE, 0FF, 100, 101 1FE, 1FF, 200, 201 3FE, 3FF, 400, 401
x32 None None None None
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) RL & WL
RL & WL Write-only OP<3:0>
0001
B
: RL = 3 / WL = 1 (default)
0010
B
: RL = 4 / WL = 2
0011
B
: RL = 5 / WL = 2
0100
B
: RL = 6 / WL = 3
0101
B
: RL = 7 / WL = 4
0110
B
: RL = 8 / WL = 4
All others: reserved
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) DS
DS Write-only OP<3:0>
0000
B
: reserved
0001
B
: 34.3-ohm typical
0010
B
: 40-ohm typical (default)
0011
B
: 48-ohm typical
0100
B
: 60-ohm typical
0101
B
: reserved for 68.6-ohm typical
0110
B
: 80-ohm typical
0111
B
: 120-ohm typical (optional)
All others: reserved
JEDEC Standard No. 209-2E
Page 38
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR4_Device Temperature (MA<7:0> = 04
H
)
NOTE 1 A Mode Register Read from MR4 will reset OP7 to ‘0’.
NOTE 2 OP7 is reset to ‘0’ at power-up. OP<2:0> bits are undefined after power-up.
NOTE 3 If OP2 equals ‘1’, the device temperature is greater than 85°C.
NOTE 4 OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4.
NOTE 5 LPDDR2 might not operate properly when OP[2:0] = 000
B
or 111
B.
NOTE 6 For specified operating temperature range and maximum operating temperature refer to Table 72 on
page 161.
NOTE 7 LPDDR2-SX devices shall be de-rated by adding 1.875 ns to the following core timing parameters:
tRCD, tRC, tRAS, tRP, and tRRD. tDQSCK shall be de-rated according to the tDQSCK de-rating in Table 103
on page 197. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged.
NOTE 8 LPDDR2-NVM devices shall be de-rated by adding the value found at location OP5:OP4 in MR20 to
the following core timing parameters: tRCD, tRC, tRAS, and tRRD. tDQSCK shall be de-rated according to the
tDQSCK de-rating in Table 103 on page 197. Prevailing clock frequency spec and related setup and hold timings
remain unchanged.
NOTE 9 See “Temperature Sensor” on page 129 for information on the recommended frequency of reading
MR4.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
TUF (RFU) SDRAM Refresh Rate
TUF (RFU) NVM Temperature Alert
SDRAM
Refresh Rate
Read-only OP<2:0>
000
B
: SDRAM Low temperature operating limit exceeded
001
B
: 4x t
REFI,
4x t
REFIpb,
4x t
REFW
010
B
: 2x t
REFI,
2x t
REFIpb,
2x t
REFW
011
B
: 1x t
REFI,
1x t
REFIpb,
1x t
REFW
(<=85°C)
100
B
: Reserved
101
B
: 0.25x t
REFI
, 0.25x t
REFIpb,
0.25x t
REFW,
do not de-rate SDRAM AC timing
110
B
: 0.25x t
REFI
, 0.25x t
REFIpb,
0.25x t
REFW,
de-rate SDRAM AC timing
111
B
: SDRAM High temperature operating limit exceeded
NVM
Temperature
Alert
Read-only OP<2:0>
000
B
: NVM Low temperature operating limit exceeded
001
B
: Reserved
010
B
: Reserved
011
B
: Temperature Alert not active, do not de-rate NVM AC timing (<=85°C)
100
B
: Temperature Alert not active, de-rate NVM AC timing
101
B
: Temperature Alert active, do not de-rate NVM AC timing
110
B
: Temperature Alert active, de-rate NVM AC timings
111
B
: NVM High temperature operating limit exceeded
Temperature
Update
Flag
(TUF)
Read-only OP<7>
0
B
: OP<2:0> value has not changed since last read of MR4.
1
B
: OP<2:0> value has changed since last read of MR4.
JEDEC Standard No. 209-2E
Page 39
3.5.1Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR5_Basic Configuration 1 (MA<7:0> = 05
H
):
MR6_Basic Configuration 2 (MA<7:0> = 06
H
):
NOTE 1 MR6 is Vendor Specific.
MR7_Basic Configuration 3 (MA<7:0> = 07
H
):
NOTE 1 MR7 is Vendor Specific.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
LPDDR2 Manufacturer ID
LPDDR2 Manufacturer ID Read-only OP<7:0>
0000 0000B : Reserved
0000 0001B : Samsung
0000 0010B : Qimonda
0000 0011B : Elpida
0000 0100B : Etron
0000 0101B : Nanya
0000 0110B : Hynix
0000 0111B : Mosel
0000 1000B : Winbond
0000 1001B : ESMT
0000 1010B : Reserved
0000 1011B : Spansion
0000 1100B : SST
0000 1101B : ZMOS
0000 1110B : Intel
1111 1110B : Numonyx
1111 1111B : Micron
All Others : Reserved
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID1
Revision ID1 Read-only OP<7:0> 00000000
B
: A-version
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID2
Revision ID2 Read-only OP<7:0> 00000000
B
: A-version
JEDEC Standard No. 209-2E
Page 40
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR8_Basic Configuration 4 (MA<7:0> = 08B
H
):
MR9_Test Mode (MA<7:0> = 09
H
):
MR10_Calibration (MA<7:0> = 0A
H
):
NOTE 1 Host processor shall not write MR10 with “Reserved” values
NOTE 2 LPDDR2 devices shall ignore calibration command when a “Reserved” value is written into MR10.
NOTE 3 See AC timing table for the calibration latency.
NOTE 4 If ZQ is connected to V
SSCA
through R
ZQ
, either the ZQ calibration function (see “Mode Register Write ZQ Calibration
Command” on page 135) or default calibration (through the ZQreset command) is supported. If ZQ is connected to V
DDCA
, the
device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not
change after power is applied to the device.
NOTE 5 LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration command.
NOTE 6 Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connec-
tion.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
I/O width Density Type
Type Read-only OP<1:0>
00
B
: S4 SDRAM
01
B
: S2 SDRAM
10
B
: N NVM
11
B
: Reserved
Density Read-only OP<5:2>
0000
B
: 64Mb
0001
B
: 128Mb
0010
B
: 256Mb
0011
B
: 512Mb
0100
B
: 1Gb
0101
B
: 2Gb
0110
B
: 4Gb
0111
B
: 8Gb
1000
B
: 16Gb
1001
B
: 32Gb
all others: reserved
I/O width Read-only OP<7:6>
00
B
: x32
01
B
: x16
10
B
: x8
11
B
: not used
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Vendor-specific Test Mode
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Calibration Code
Calibration
Code
Write-only OP<7:0>
0xFF: Calibration command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ Reset
others: Reserved
JEDEC Standard No. 209-2E
Page 41
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR11:15_(Reserved) (MA<7:0> = 0B
H
-0F
H
):
MR16_PASR_Bank Mask (MA<7:0> = 010
H
): S2 and S4 SDRAM only
S2 SDRAM:
S4 SDRAM:
1. For 4-bank S4 SDRAM, only OP<3:0> are used.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
S2 SDRAM (RFU) PASR
S4 SDRAM Bank Mask (4-bank or 8-bank)
PASR Map Write-only OP<1:0>
00
B
: Full array (default)
01
B
: 1/2 array - BA1=0 for 4-banks, BA2=0 for 8-banks
10
B
: 1/4 array - BA1=BA0=0 for 4-banks, BA2=BA1=0 for
8-banks
11
B
: 1/8 array - Not used for 4-banks, BA2=BA1=BA0=0
for 8-banks
Bank <7:0> Mask Write-only OP<7:0>
0
B
: refresh enable to the bank (=unmasked, default)
1
B
: refresh blocked (=masked)
1
OP Bank Mask 4-Bank S4 SDRAM 8-Bank S4 SDRAM
0 XXXXXXX1 Bank 0 Bank 0
1 XXXXXX1X Bank 1 Bank 1
2 XXXXX1XX Bank 2 Bank 2
3 XXXX1XXX Bank 3 Bank 3
4 XXX1XXXX - Bank 4
5 XX1XXXXX - Bank 5
6 X1XXXXXX - Bank 6
7 1XXXXXXX - Bank 7
JEDEC Standard No. 209-2E
Page 42
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR17_PASR_Segment Mask (MA<7:0> = 011
H
): 1Gb ~ 8Gb S4 SDRAM only
NOTE This table indicates the range of row addresses in each masked segment. X is do not care for a particular
segment
.
MR18-19_Reserved (MA<7:0> = 012
H
- 013
H
):
MR20_NVM Geometry (MA<7:0> = 014
H
): NVM only
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Segment Mask
Segment <7:0>
Mask
Write-only OP<7:0>
0
B
: refresh enable to the segment (=unmasked, default)
1
B
: refresh blocked (=masked)
1Gb 2Gb,4Gb 8Gb
Segment OP Segment Mask R12:10 R13:11 R14:12
0 0 XXXXXXX1
000
B
1 1 XXXXXX1X 001
B
2 2 XXXXX1XX
010
B
3 3 XXXX1XXX 011
B
4 4 XXX1XXXX
100
B
5 5 XX1XXXXX 101
B
6 6 X1XXXXXX
110
B
7 7 1XXXXXXX 111
B
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU)
tRCD
De-Rating
RB
Number
RDB size
RDB Size Read-only OP<2:0>
000
B
: 32B
001
B
: 64B
010
B
: 128B
011
B
: 256B
100
B
: 512B
101
B
: 1024B
110
B
: 2048B
111
B
: 4096B
RB Number Read-only OP<3>
0
B
: 4 Row Buffers
1
B
: 8 Row Buffers
tRCD De-rating
(t
NVMDERATING
)
Read-only OP<5:4>
00
B
: 0 ns
01
B
: 1.875 ns
10
B
: 3.75 ns
11
B
: 7.5 ns
JEDEC Standard No. 209-2E
Page 43
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR21_NVM tRCD (MA<7:0> = 15
H
): NVM only
NOTE 1 t
RCD
value is obtained adding 1st order value to the 2nd order value
MR22:23_(Reserved) (MA<7:0> = 16
H
:17
H
):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
t
RCD
Value (2nd order) t
RCD
Value (1st order)
t
RCD
Value
(1st order = value
ns)
Read-only OP<3:0>
0000
B
: 0ns
0010
B
: 2ns
0100
B
: 4ns
0110
B
: 6ns
1000
B
: 8ns
1010
B
: 10ns
1100
B
: 12ns
1110
B
: 14ns
0001
B
: 1ns
0011
B
: 3ns
0101
B
: 5ns
0111
B
: 7ns
1001
B
: 9ns
1011
B
: 11ns
1101
B
: 13ns
1111
B
: 15ns
t
RCD
Value
(2nd order =
valuex16 ns)
Read-only OP<7:4>
0000
B
: 0ns
0010
B
: 32ns
0100
B
: 64ns
0110
B
: 96ns
1000
B
: 128ns
1010
B
: 160ns
1100
B
: 192ns
1110
B
: 224ns
0001
B
: 16ns
0011
B
: 48ns
0101
B
: 80ns
0111
B
: 112ns
1001
B
: 144ns
1011
B
: 176ns
1101
B
: 208ns
1111
B
: 240ns
JEDEC Standard No. 209-2E
Page 44
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR24_Overlay Window Enable (MA<7:0> = 18
H
): NVM Only
NOTE 1 Overlay Window Disable (OP1) shall be set to disable the Overlay Window (See Section on the NVM
Overlay Window for more details). OP1 is set by an MRW command with OP1 = “1”. When read, OP1 returns as a
reserved value, “0”.
NOTE 2 Overlay Window Enable (OP0) shall be set to enable the Overlay Window (See Section on the NVM
Overlay Window for more details). OP0 is set by an MRW command with OP0 = “1”. When read, OP0 returns the
status of the Overlay Window. When read, OP0 will reflect whether the Overlay Window is enabled (OP0 = “1”) or
disabled (OP0 = “0”).
NOTE 3 All values for MR24 are reset by the device to “0” during Device Auto-Initialization.
NOTE 4 Only one bit is allowed to be set during any single MRW.
MR25:27_OW Base Address 1~3 (MA<7:0> = 19
H
-1B
H
): NVM only
NOTE 1 a12 - a0 are implied to be 0.The Overlay Window is aligned on a 8-Kbyte boundary.
NOTE 2 Mode Registers 25-27 are readable are writeable
NOTE 3 Only the value ‘0’ can be written to RFU bit. When read RFU bit shall output ‘0’.
NOTE 4 Only the value ‘0’ can be written to OP0 in MR25.
NOTE 5 Only the value ‘0’ can be written to unused row address bits outside of the device address space.
NOTE 6 When read, unused row address bits outside of the device address space shall return ‘0’.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
(RFU) OWD OWE
Overlay Window
Disable
(OWD)
OP<1>
Read Reserved
Write
0
B
: Nop
1
B
: Disable Overlay Window
Overlay Window
Enable
(OWE)
OP<0>
Read
0
B
: Overlay Window Disabled (Default)
1
B
: Overlay Window Enabled
Write
0
B
: Nop
1
B
: Enable Overlay Window
MR OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
25 19
H
a19 a18 a17 a16 a15 a14 a13 0
26 1A
H
a27 a26 a25 a24 a23 a22 a21 a20
27 1B
H
(RFU) a31 a30 a29 a28
JEDEC Standard No. 209-2E
Page 45
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR28_(Reserved) (MA<7:0> = 1C
H
):
MR29_NVM tDNV (MA<7:0> = 1D
H
): NVM only
MR30:31_(NVM Reserved) (MA<7:0> = 1E
H
-1F
H
):
MR32_DQ Calibration Pattern A (MA<7:0> = 20
H
):
Reads to MR32 return DQ Calibration Pattern “A”. See “DQ Calibration” on page 130.
MR33:39_(Do Not Use) (MA<7:0> = 21
H
-27
H
):
MR40_DQ Calibration Pattern B (MA<7:0> = 28
H
):
Reads to MR40 return DQ Calibration Pattern “B”. See “DQ Calibration” on page 130.
MR41:47_(Do Not Use) (MA<7:0> = 29
H
-2F
H
):
MR48:62_(Reserved) (MA<7:0> = 30
H
-3E
H
):
MR63_Reset (MA<7:0> = 3F
H
): MRW only
NOTE 1 For additonal information on MRW RESET see “Mode Register Write Command” on page 132.
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
tDNV Value (2nd order) tDNV Value (1st order)
tDNV Value
(1st order =
value ns)
Read-only OP<3:0>
0000
B
: 0us
0010
B
: 2us
0100
B
: 4us
0110
B
: 6us
1000
B
: 8us
1010
B
: 10us
1100
B
: 12us
1110
B
: 14us
0001
B
: 1us
0011
B
: 3us
0101
B
: 5us
0111
B
: 7us
1001
B
: 9us
1011
B
: 11us
1101
B
: 13us
1111
B
: 15us
tDNV Value
(2nd order =
valuex16 us)
Read-only OP<7:4>
0000
B
: 0us
0010
B
: 32us
0100
B
: 64us
0110
B
: 96us
1000
B
: 128us
1010
B
: 160us
1100
B
: 192us
1110
B
: 224us
0001
B
: 16us
0011
B
: 48us
0101
B
: 80us
0111
B
: 112us
1001
B
: 144us
1011
B
: 176us
1101
B
: 208us
1111
B
: 240us
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
X
JEDEC Standard No. 209-2E
Page 46
3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d)
MR64:126_(Reserved) (MA<7:0> = 40
H
-7E
H
):
MR127_(Do Not Use) (MA<7:0> = 7F
H
):
MR128:190_(Reserved for Vendor Use) (MA<7:0> = 80
H
-BE
H
):
MR191_(Do Not Use) (MA<7:0> = BF
H
):
MR192:254_(Reserved for Vendor Use) (MA<7:0> = C0
H
-FE
H
):
MR255_(Do Not Use) (MA<7:0> = FF
H
):
JEDEC Standard No. 209-2E
Page 47
4 LPDDR2-N Software Interface
4.1 Overlay Window
LPDDR2-NVM functions are controlled using memory-mapped registers in an Overlay Window.
System software can locate the Overlay Window within the memory address range of the device by setting Overlay
Window Base Address (OWBA) in Mode Registers 25, 26 and 27.
The Overlay Window can be positioned only at a 8-KByte aligned address within the address map.
The Overlay Window can be enabled by setting the OWE bit of MR24 to ‘1’, and it can be disabled by setting OWD
bit of MR24 to ‘1’. If OWE bit and OWD bit are set to ‘0’ the Overlay Window status does not change. If OWD bit
is set to ‘1’, OWE bit is automatically cleared to ‘0’.
Once the Overlay Window has been enabled, the address region associated with the overlay window is accessed by
the memory controller like any other section of memory in the array. Preactive, Activate, and Read/Write commands
are used to access the Overlay Window.
When the Overlay Window is enabled, read accesses to addresses outside the Overlay Window region will access the
memory array.
Write commands to addresses outside the Overlay Window may not be allowed.
Within the Overlay Window, memory-mapped control registers are located at static offsets from the base address
(OWBA). The Overlay Window region contains: program buffer, device information, registers to control memory
array operation, etc.
While the Overlay Window is enabled, system software can write to (and/or read from) each memory-mapped control
register at the address OWBA+RegisterStaticOffset according to register definitions shown on the Overlay Window:
Control Register Offsets and Definitions Table on page 48. For LPDDR2-NVM devices, Row Data Buffers are
considered to be write through structures and any write issued to an Overlay Window register is completed when the
issuing Write command is completed.
While the Overlay Window is disabled, the memory-mapped registers are not available.
JEDEC Standard No. 209-2E
Page 48
4.1.1 Map of Control Registers (offsets and definitions)
Table 23 describes the Overlay Window register map.
NOTE 1 System Software shall not write to any Reserved register any value other than 0.
NOTE 2 When read, Reserved registers and Write-Only registers will return indeterminate data.
NOTE 3 Number of bytes in this Overlay Window.
NOTE 4 Program-Buffer Offset is the byte-addressing offset of the beginning of the Program-Buffer in this Overlay Window.
NOTE 5 Program-Buffer Size is the number of bytes in the Program-Buffer in this Overlay Window.
NOTE 6 The memory shall reset this register to Default Value after Device Auto-Initialization, and after complettion of prior command
NOTE 7 Command Address = a[31:0] of byte-address. System software shall write “0” to any most-significant bits of a[31:23] not used by the
memory device.
NOTE 8 Multi-Purpose Register is used as DataCount[31:0] in the buffer-program command. DataCount[31:0] = number of contiguous bytes to
Table 23 — Overlay Window: Control Register Offsets and Definitions
Byte-Addressing
Type Register Item
Default Value
(hex)
Notes
Offset
(hex)
# of bytes
(decimal)
0x001 – 0x000 2 R Overlay Window Query String “P” 0x00 - 0x50
0x003 – 0x002 2 R Overlay Window Query String “F” 0x00 - 0x46
0x005 – 0x004 2 R Overlay Window Query String “O” 0x00 - 0x4F
0x007 – 0x006 2 R Overlay Window Query String “W” 0x00 - 0x57
0x009 – 0x008 2 R Overlay Window ID 0x00 - 0x20
0x00B – 0x00A 2 R Overlay Window Revision Vendor-Specific
0x00D – 0x00C 2 R Overlay Window Size Vendor-Specific 3
0x00F – 0x00E 2 Reserved for JEDEC 1,2
0x011 – 0x010 2 R Program-Buffer Offset Vendor-Specific 4
0x013 – 0x012 2 R Program-Buffer Size Vendor-Specific 5
0x01F – 0x014 12 Reserved for JEDEC 1,2
0x021 – 0x020 2 R JEDEC Manufacturer ID Vendor-Specific
0x023 – 0x022 2 R JEDEC Device ID Vendor-Specific
0x03D – 0x024 26 Reserved for JEDEC 1,2
0x03F - 0x03E 2 W Reserved for JEDEC 2,10
0x07F – 0x040 64 Vendor-Specific Reserved for Vendor Use Vendor-Specific
0x081 – 0x080 2 W Command Code 0x00 - 0x00 6
0x083 – 0x082 2 Reserved for JEDEC 1,2
0x087 – 0x084 4 R/W Command Data
0x08B – 0x088 4 W Command Address 7
0x08F – 0x08C 4 Reserved for JEDEC 1,2
0x093 – 0x090 4 W Multi-Purpose Register 8
0x0BF - 0x094 44 Reserved for JEDEC 1,2
0x0C1 - 0x0C0 2 W Command Execute 0x00 - 0x00
0x0C7 - 0x0C2 6 Reserved for JEDEC 1,2
0x0C9 - 0x0C8 2 R/W Suspend 0x00 - 0x00
0x0CB - 0x0CA 2 R/W Abort 0x00 - 0x00
0x0CD - 0x0CC 2 R/W Status Register 0x00 - 0x80
0x0CF - 0x0CE 2 Reserved for JEDEC
0x0DF - 0x0D0 16 Reserved for Vendor Use
0x0FF – 0x0E0 32 - Reserved for Vendor Use
Vendor-Specific Vendor-Specific Vendor-Specific Reserved for Vendor Use
Vendor-Specific Vendor-Specific Vendor-Specific Program-Buffer
JEDEC Standard No. 209-2E
Page 49
be programmed using the Program-Buffer. All products allow, but some products may not require, system software to write to this register.
DataCount, in conjunction with Command Address, shall not cause data to wrap beyond the end of the Program-Buffer.
NOTE 9 Only one of the following registers may be written to with a value other than 0x0000 during any Write burst: Command Execute,
Suspend, Abort, and the Status Register.

NOTE 10 Overlay Window location 0x03E - 0x03F is a Write-Only register that is reserved. When read, this location will return indeterminate
data.
4.1.1.1 Command Code Register
Device command codes (e.g., 0x0020 for Block Erase) are written to this register. Command execution occurs only
after 0x0001 is written to the Command Execute Register.
See “LPDDR2-NVM Operations” on page 54, for a examples of how the Overlay Window Registers are used.
This register is cleared to its default value after command execution is completed.
Table 24 — Command Code Register
4.1.1.2 Command Data Register
Command data might be written to this register. Results of queries might be provided through this register.
Table 25 — Command Data Register
4.1.1.3 Command Address Register
The command address (e.g., the first data address for buffered program operation, the block address for erase
operation) is written to this registers. The address value (a[31:0]) shall be in byte units.
System software shall write “0” to any most-significant bits of a[31:23] not used by the memory device.
Table 26 — Command Address Register
4.1.1.4 Multi-Purpose Register
The Multi-Purpose Register is used in several operations. For example, it shall be loaded with the number of
contiguous bytes to be programmed during a buffered program operation.
It shall be loaded with the last block address during a block lock/unlock/lock-down operation.
Table 27 — Multi-Purpose Register
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x081 – 0x080 2 W Command Code 0x00 - 0x00
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x087 – 0x084 4 R/W Command Data
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x08B – 0x088 4 W Command Address
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x093 – 0x090 4 W Multi-Purpose Register
JEDEC Standard No. 209-2E
Page 50
4.1.1.5 Command Execute Register
Command execution begins when “0x0001” is written to this register. It is allowed to write this register only when the
device is ready (DRB = “1”). The device executes the current command in the Command Code register. Before
writing “0x0001” to the Command Execute register, the user can change the contents of the Command Code register
(and any related parameters) any number of times.
It is allowed only to write “0x0001” to this register - writing any another value is prohibited, and may result in
undefined operation.
Table 28 — Command Execute Register
4.1.1.6 Suspend Register
When “0x0001” is written to this register, an on-going erase or program operation is suspended. Writing to this
register is effective only while the device is busy performing an erase or program operation - writes during other
times are ignored.
It is allowed only to write “0x0001” to this register - writing any other value can result in undefined operation.
The Suspend register returns “0x0001” from the time a Suspend command is written until the device is ready (DRB =
“1”). The Suspend register returns “0x0000” in all other cases. Once the embedded operation has suspended (or
completed), the Suspend register is reset by the device and returns “0x0000” when read.
Table 29 — Suspend Register
The Status Register shall be read to check if the suspend request was successful: SR.6=1 indicates erase suspend was
successful; SR.2=1 indicates program suspend was successful.
Otherwise, if the suspend request was not successful (SR.6=0; SR.2=0), the ongoing program or erase operation may
have completed successfully before the suspend could take effect; system software should test all Status Register
flags to be certain.
The Suspend Register resets to its default value after suspending the program or erase operation. Also, successful
completion of any on-going program or erase operation will clear this register.
Once the device is suspended, the Resume command must be issued in order to continue the program or erase
operation. Refer to section “Program/Erase Suspend” on page 75 for additional details.
Suspend feature is optional. If LPDDR2-NVM does not support suspend feature, Suspend Register can be set only to
‘0x0000’, and when read Suspend Register shall output the value ‘0x0000’.
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x0C1 - 0x0C0 2 W Command Execute 0x00 - 0x00
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x0C9 - 0x0C8 2 R/W Suspend 0x00 - 0x00
JEDEC Standard No. 209-2E
Page 51
4.1.1.7 Abort Register
When “0x0001” is written to this register, an on-going embedded operation is aborted. Writing to this register is
effective only while the device is busy performing an embedded operation - writes during other times are ignored.
It is allowed only to write “0x0001” to this register - writing any other value can result in undefined operation.
Table 30 — Abort Register
The Abort register returns “0x0001” from the time a Abort command is written until the device is ready (DRB = “1”).
The Abort register returns “0x0000” in all other cases. Once the embedded operation has aborted (or completed), the
Abort register is reset by the device and returns “0x0000” when read.
This register resets to its default value by the device after all embedded operations have ceased and the device
becomes ready (SR.7 = “1”). If any embedded operation is aborted and does not complete due to that abort, one or
more error flags will be set in SR (SR.4 and/or SR.5).
Note that the embedded operation may have completed successfully before the abort could take effect.
Refer to section “Abort” on page 78 for additional details.
Abort feature is optional. If LPDDR2-NVM does not support abort feature, Abort Register can be set only to
‘0x0000’, and when read Abort Register shall output the value ‘0x0000’.
4.1.1.8 Status Register
The Status Register (SR) indicates the state (Ready or Busy) of the device, and status of program, erase, and the other
embedded operations.
Table 31 — Status Register
In particular, SR.7 indicates the state of the device: SR.7 = ’1’ indicates the device is Ready; SR.7 = ’0’ indicates the
device is Busy.
The following Status Register bits are related to the results of embedded operations: Control Mode Status Bit (SR.9),
Object Mode Status Bit (SR.8), Erase Status (SR.5), Program Status (SR.4), Voltage Supply Error Status (SR.3), and
Block Lock Status (SR.1). These bits are set by the device. These bits are cumulative and can only be cleared by
writing a ‘1’ to the Status Register bit to be cleared (W12C is an acronym for “write one to clear”). If these bits are
written with a ‘0’, their value will not change.
The following Status Register bits are related to the current state of any in process embedded operation: Device Busy
(SR.7), Erase Suspended (SR.6), and Program Suspended (SR.2). These bits are set and cleared by the device. Only
the value ‘0’ shall be written to this bits, which will be ignored.
Status Register bit SR.1, SR.2, SR.3, SR.4, SR.5, SR.6, SR. 8, and SR.9 are invalid while SR.7 = ‘0’ (DRB = ‘0’).
Once Activated, a Row Data Buffer (RDB) containing the Status Register shall be automatically updated by the
LPDDR2-N device and shall reflect the current state for the Status Register.
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x0CB - 0x0CA 2 R/W Abort 0x00 - 0x00
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x0CD - 0x0CC 2 R/W Status Register 0x00 - 0x80
JEDEC Standard No. 209-2E
Page 52
4.1.1.8 Status Register (cont’d)
Table 32 — Status Register details
NOTE 1 The “W12C” Status Register bits type are set by the device and can be cleared by writing ‘1’ to them (W12C is an acronym for “write one to clear”)
NOTE 2 The “R only” Status Register bits type can be written only with the value ‘0’ when clearing the status bits.
NOTE 3 ESSB (SR.6) and ESB (SR.5) are reserved if a device does not require Erase features
NOTE 4 PSSB (SR.2) is reserved if a device does not support program suspend.
NOTE 5 ESB (SR.5) is set to ‘1’ if an erase operation is aborted by writing “0x0001” to the Abort Register.
NOTE 6 PSB (SR.4) is set to ‘1’ if a program operation is aborted by writing “0x0001” to the Abort Register.
NOTE 7 CMSB (SR.9) and OMSB (SR.8) are used to indicate error conditions for LPDDR2-NVM devices which support programming region modes. They are
reserved in case programming region modes are not supported.
NOTE 8 All Reserved bits are driven to ‘0’ by the device, and shall be written with ‘0’.
NOTE 9 LPDDR2-N devices may implement Vendor Specific features. Refer to Vendor Datasheets for a complete description of the NVM Status Register
Bit Name Type Description
SR.15
:
SR.10
(Reserved) R Only Reserved for future use.
SR.9
CMSB
Control Mode
Status Bit
W12C
[CMSB,OMSB] indicates additional error conditions for LPDDR2-NVM devices which support program-
ming operations based on Programming Region.
[CMSB,OMSB] = 00 -->Programming successful
[CMSB,OMSB] = 01 --> Programming Error: programming attempt to an Object Mode Programming
Region
[CMSB,OMSB] = 10 --> Programming Error: programming attempt to an invalid Programming Region Ele-
ment;
[CMSB,OMSB] = 11 --> Programming Error: programming attempt using illegal command
PSB will also be set along with [CMSB,OMSB] for the above error conditions.
SR.8
OMSB
Object Mode
Status Bit
W12C
SR.7
DRB
Device
Ready Bit
R Only
DRB indicates Erase, Program, or other embedded operation completion in the device.
0 = Embedded controller is Busy
1 = Embedded controller is Ready
bit SR.1, SR.2, SR.3, SR.4, SR.5, SR.6,SR. 8, and SR.9 are invalid while DRB = ‘0’.
SR.6
ESSB
Erase
Suspend
Status Bit
R Only
ESSB indicates whether the device is in Erase Suspend. After issuing a Suspend command, the embed-
ded controller halts and sets to ‘1’ DRB and ESSB.
ESSB remains set until the device receives a Resume command.
0 = Operation in progress/completed
1 = Operation suspended
SR.5
ESB
Erase
Status Bit
W12C
ESB is set to ‘1’ if an attempted Erase failed.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
0 = Erase operation successful
1 = Erase Error
SR.4
PSB
Program
Status Bit
W12C
PSB is set to ‘1’ if an attempted program failed.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
0 = Program operation successful
1 = Program Error
SR.3
VSESB
Voltage
Supply Error
Status Bit
W12C
VSESB indicates whether the VACC level is valid voltage.
0 = VACC valid voltage level
1 = VACC invalid voltage level, operation aborted
SR.2
PSSB
Program
Suspend
Status Bit
R Only
PSSB indicates whether the device is in Program Suspend. After receiving a Suspend command, the
embedded controller halts execution and sets to ‘1’ DSB and PSSB, which remains set until a Resume
command is received.
0 = Operation in progress/completed
1 = Operation suspended
SR.1
BLSB
Block Lock
Status Bit
W12C
BLSB indicates whether Program or Erase was attempted on a locked block. If the block is locked, the
embedded controller sets to ‘1’ BLSB and aborts the operation.
0 = Unlocked
1 = Aborted Write attempt on a locked block
SR.0 (Reserved) R Only
Reserved for future use.
JEDEC Standard No. 209-2E
Page 53
4.1.1.9 Program-Buffer
The Program-Buffer is used during Buffered Program operation to input the data to be written in memory array. The
Program-Buffer shall be filled prior writing “0x0001” to the Command Execute Register.
Refer to Vendor Datasheets for information about Program-Buffer offset and Program-Buffer size.
Table 33 — Program-Buffer
4.2 Data Byte Lane Assignment for Overlay Window Register
Registers included in the Overlay Window might have various size: 1-byte, 2-byte, 4-byte, etc.
Table 34 describes how each byte of an Overlay Window Register is mapped to data byte lane (DQ[7:0], DQ[15:8],
DQ[23:16] and DQ[31:24]) in case of x8, x16 and x32 LPDDR2-NVM.
In particular, examples for 1-byte, 2-byte and 4-byte registers are shown.
To properly access the Overlay Window Register it is necessary to ensure the correct assignment of each data bit.
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
Vendor-Specific Vendor-Specific Vendor-Specific Program-Buffer
Table 34 — Overlay Window Register Byte Lane Assignment
Byte-Addressing
Register
Data Bus Width
Offset
(hex)
# of
bytes
(decimal
)
x8 x16 x32
C1 C0 DQ C1 C0 DQ C1 C0 DQ
0x000 1 OneByte_Reg_A[7:0] 0 0 DQ[7:0]
0 0
DQ[7:0]
0 0
DQ[7:0]
0x001 1 OneByte_Reg_B[7:0] 0 1 DQ[7:0] DQ[15:8] DQ[15:8]
0x002 1 OneByte_Reg_C[7:0] 1 0 DQ[7:0]
0 1
DQ[7:0] DQ[23:16]
0x003 1 OneByte_Reg_D[7:0] 1 1 DQ[7:0] DQ[15:8] DQ[31:24]
0x001 – 0x000 2
TwoBytes_Reg_A[7:0] 0 0 DQ[7:0]
0 0
DQ[7:0]
0 0
DQ[7:0]
TwoBytes_Reg_A[15:8] 0 1 DQ[7:0] DQ[15:8] DQ[15:8]
0x003 – 0x002
2 TwoBytes_Reg_B[7:0] 1 0 DQ[7:0]
0 1
DQ[7:0] DQ[23:16]
TwoBytes_Reg_B[15:8] 1 1 DQ[7:0] DQ[15:8] DQ[31:24]
0x003 – 0x000 4
FourBytes_Reg_A[7:0] 0 0 DQ[7:0]
0 0
DQ[7:0]
0 0
DQ[7:0]
FourBytes_Reg_A[15:8] 0 1 DQ[7:0] DQ[15:8] DQ[15:8]
FourBytes_Reg_A[23:16] 1 0 DQ[7:0]
0 1
DQ[7:0] DQ[23:16]
FourBytes_Reg_A[31:24] 1 1 DQ[7:0] DQ[15:8] DQ[31:24]
JEDEC Standard No. 209-2E
Page 54
4.3 LPDDR2-NVM Operations
LPDDR2-NVM can be produced from a variety of memory array technologies. This section is not intended to
describe full details of LPDDR2-NVM operations.
The scope of this section is to provide a standard for some aspects of LPDDR2-NVM software interface, that might
be in common among most of NVM technologies.
Based on this standard memory vendors will define their own memory specification, adding all necessary details for
the proper use of the device. These details are technology dependant and not easy to predict for emerging or
completely new technologies.
Some possible exceptions to the standard are mentioned. It is recommended to refer to the device specification for the
complete description.
This section includes the following commands: NOP, Single Word Program, Buffered Program, Block Erase, Block
Lock, Block Unlock, Block Lock-Down, Resume, Suspend, Command Execute, and Abort.
Table 35 defines the command code values to be written to the Command Code Register within the Overlay Window
(see Overlay Window register map table).
An embedded controller handles all timings and verifies the correct execution of LPDDR2-NVM operations.
The commands can be initiated when the embedded controller is not busy (DRB = “1”). The Device Ready Bit (DRB)
is read as part of the Status Register.
VACC shall not change during the period starting from at least 1us prior to the initiation of any embedded operation
until that embedded operation is complete.
During the execution of an embedded operation, the device can be placed in Power Down mode by driving CKE low,
see Power Down section for detailed description on how to enter and exit Power Down.
NOTE 1 The Command Code Register default value is 0x0000 (NOP). If the Command Execute Register is set to
‘0x0001’ when Command Code Register is at the default value (0x0000), the device will become busy and then
ready without executing any operation (NOP).
NOTE 2 Single Word Program is optional.
NOTE 3 Single Word Overwrite and Buffered Overwrite are optional and are only supported by some NVM tech-
nologies and some LPDDR2-NVM devices.
Table 35 — Command Codes
Operation Code Command Note
NOP
0x0000 No Operation
1
Program
0x0041 Single Word Program
2
0x0042 Single Word Overwrite
3
0x00E9 Buffered Program
0x00EA Buffered Overwrite
3
Erase
0x0020 Block Erase
Block Lock
0x0061
Block Lock
Block Unlock
0x0062
Block Unlock
Block Lock-Down
0x0063
Block Lock-Down
Resume
0x00D0
Resume
JEDEC Standard No. 209-2E
Page 55
4.4 Nomenclature
Table 36 — Definition of terms
Term Definition
Block A group of bits that erase with one erase command
Main Array A group of blocks used for storing code or data
Partition A group of blocks that share common program and erase circuitry
JEDEC Standard No. 209-2E
Page 56
4.5 Acronyms
Table 37 — Definition of acronyms
Term Definition
MR Mode Register
MRR Mode Register Read
MRW Mode Register Write
OP0,OP1,...,OP7 OP0, OP1, ..., OP7 represent bit 0,1,...,7 of a Mode Register
CFI Common Flash Interface
DU Don’t Use
RFU Reserved for Future Use
SR Status Register
OW Overlay Window
OWBA Overlay Window Base Address
NVM Non Volatile Memory
DDR Double Data Rate
SDR Single Data Rate
JEDEC Standard No. 209-2E
Page 57
4.6 Conventions
Table 38 — Definition of conventions
Term Definition
0x Hexadecimal number prefix
0b Binary number prefix
Byte 8 bits
Word 2 bytes = 16 bits
Kbit 1024 bits
KByte 1024 bytes
Mbit 1,048,576 bits
MByte 1,048,576 bytes
lower case ‘a’ It represents a logical address bit (e.g. a5)
MRj It represents Mode Register number ‘j’ (e.g. MR22)
MRj.OPk It represents bit ‘k’ of Mode Register ‘j’ (e.g. MR22.OP4)
A[m:n] It denotes a group of similarly named signals, such address bus (e.g. FirstAdd[31:0])
Ak It denotes the element ‘k’ of a group of signals, such an address bit (e.g. FirstAdd7)
OWBA+offset It denotes the address value obtained adding ‘offset’ to ‘OWBA’ (e.g. OWBA+0x088)
JEDEC Standard No. 209-2E
Page 58
4.7 Overlay Window Enable and Disable
When the Overlay Window is enabled, it overlaps a portion of the memory array area.
To enable the Overlay Window the value 0x01 shall be written to MR24. To disable the Overlay Window the value
0x02 shall be written to MR24.
The Overlay Window Base Address shall be stored to MR27, MR26 and MR25.
In particular, if OWBA[31:0] is the desired Overlay Window base address, MR27-MR25 shall be set as follows:
MR27[OP7:OP0] = {0,0,0,0,OWBA[31:28]}
MR26[OP7:OP0] = {OWBA[27:20]}
MR25[OP7:OP0] = {OWBA[19:13],0}
OWBA[12:0] value is assumed to be 0x0000, therefore the Overlay Window can be positioned only at a 8-KByte
aligned address.
MR27, MR26 and MR25 shall be written only if the Overlay Window is disabled, OWBA shall be changed only if
the MR24.OP0 is ‘0’ (OWE).
Software may open the Overlay Window, and close it immediately after it has accessed it. Alternatively, it may keep
the Overlay Window open continuously on a fixed location of the memory map.
If the Overlay Window is enabled and the device is busy (DRB = ‘0’), write access to the Overlay Window is not
allowed expect for the Suspend and Abort registers.
If the Overlay Window is enabled and the device is busy (DRB = ‘0’), read access to the Overlay Window is allowed.
Some OW locations may have valid content only with device ready, refer to device datasheet for complete
information.
NOTE OWBA is the byte address of the desired Overlay Window Base Address
Figure 7 — Overlay Window Enable and Disable
Enable the Overlay Window
Set MR24 to 0x01 (OWE=1)
Locate the Overlay Window
Set MR27 to {0,0,0,0,OWBA[31:28]}
Set MR26 to OWBA[27:20]
Set MR25 to {OWBA[19:13],0}
Disable the Overlay Window
Set MR24 to 0x02 (OWD=1)
Overlay Window Enable
Overlay Window Disable
End
End
JEDEC Standard No. 209-2E
Page 59
4.7.1 Block Lock Command
The Block Lock command is used to lock a block, a consecutive range of blocks, or all blocks and prevents program
or erase operations from changing the data within this range. Some LPDDR2-N devices may support locking single
blocks or a range of blocks, while other LPDDR2-N devices may only support locking all blocks.
Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a
locked block will return an error in the Status Register. The status of a locked block can be changed to unlocked using
the Block Unlock command.
All blocks are locked after power-up or reset. In LPDDR2 memory, reset is achieved by writing MR63.
Block Lock operation is performed by the embedded processor. Block Lock operation shall not be interrupted by
reset or abort (if supported), otherwise the result of this operation is unpredictable.
Block Lock status does not change if an ongoing operation other than Block Lock, Block Unlock and Block Lock-
Down is aborted by writing 0x0001 to the Abort Register.
Block Lock operations cannot be suspended.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
• Write 0x0061 to the Command Code Register,
• Write any address within the desired start block to the Command Address Register,
• Write any address within the desired stop block to the Multi-Purpose Register,
• Write 0x0001 to the Command Execute Register.
For LPDDR2-N devices that only support locking all blocks, the addresses in the Command Address Register and
Multi-Purpose Register are not used and are “Do Not Care”.
NVM vendors may implement additional security features not described in the JEDEC spec. Users shall refer to the
device datasheet for complete information.
Some NVM technologies might not have the notion of block, because they do not require and support the erase
operation.
JEDEC Standard No. 209-2E
Page 60
4.7.1 Block Lock Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Block Lock command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being locked. This step is not required for
devices that only support locking all blocks with the Block Lock command.
NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being locked. This step is not required for
devices that only support locking all blocks with the Block Lock command.
NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the address
written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and the Status
Register bits PSB and ESB are set. This error check is not required for devices that only support locking all blocks
with the Block Lock command.
NOTE 7 Some LPDDR2-N devices will lock all blocks with the Block Lock command. Refer to vendor datasheets
for complete information on the Block Lock command.
Figure 8 — Block Lock Command Flowchart
Lock a range of contiguous blocks
Provide Command Code
Write (0x0061) to address (OWBA+0x080)
Provide Command Addresses (First and Last)
Write FirstBlockAddr[31:0] to address (OWBA+0x088)
Write LastBlockAddr[31:0] to address (OWBA+0x090)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
JEDEC Standard No. 209-2E
Page 61
4.7.2 Block Unlock Command
The Block Unlock command is used to unlock a block or a consecutive range of blocks, allowing the block to be
programmed or erased.
The status of a unlocked block can be changed to locked using the Block Lock command. Some LPDDR2-N devices
may only support unlocking a single block or a range of blocks at any given time. For these devices, the blocks not
selected by the Block Unlock command will be changed to locked after the completion of the Block Unlock
command.
All blocks are locked after power-up or reset. In LPDDR2 memory, reset is achieved by writing MR63.
Block Unlock operation is performed by the embedded processor. Block Unlock operation shall not be interrupted by
reset or abort (if supported), otherwise the result of this operation is unpredictable.
Block Lock status does not change if an ongoing operation other than Block Lock, Block Unlock and Block Lock-
Down is aborted by writing 0x0001 to the Abort Register.
Block Unlock operations cannot be suspended.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
• Write 0x0062 to the Command Code Register,
• Write any address within the desired start block to the Command Address Registers,
• Write any address within the desired stop block to the Multi-Purpose Registers,
• Write 0x0001 to the Command Execute Register.
NVM vendors may implement additional security features not described in the JEDEC spec. Users shall refer to the
device datasheet complete information.
Some NVM technologies might not have the notion of block, because they do not require and support the erase
operation.
JEDEC Standard No. 209-2E
Page 62
4.7.2 Block Unlock Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Block Unlock command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being unlocked.
NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being unlocked.
NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the address
written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and the Status
Register bits PSB and ESB are set.
NOTE 7 Some LPDDR2-N devices will unlock only one block or a range of blocks selected by the Block Unlock
command. All other blocks will be locked by these devices. Refer to vendor datasheets for complete information on
the Block Unlock command.
Figure 9 — Block Unlock Flowchart
Unlock a range of contiguous blocks
Provide Command Code
Write (0x0062) to address (OWBA+0x080)
Provide Command Addresses (First and Last)
Write FirstBlockAddr[31:0] to address (OWBA+0x088)
Write LastBlockAddr[31:0] to address (OWBA+0x090)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
JEDEC Standard No. 209-2E
Page 63
4.7.3 Block Lock-Down Command
The Block Lock-Down command is used to lock-down a block or a consecutive range of blocks, and prevent program
or erase operations from changing the data in it.
Locked-Down blocks are fully protected from program or erase operations. Any program or erase operations
attempted on a locked-down block will return an error in the Status Register. The status of a locked-down block is
reset to the default locked state only after removing and applying again the power supply.
All blocks are locked after power-up or reset. In LPDDR2 memory, reset is achieved by writing MR63.
Block Lock-Down operation is performed by the embedded processor. Block Lock-Down operation shall not be
interrupted by reset or abort (if supported), otherwise the result of this operation is unpredictable.
Block Lock status does not change if an ongoing operation other than Block Lock, Block Unlock, and Block Lock-
Down is aborted by writing 0x0001 to the Abort Register.
Block Lock-Down operations cannot be suspended.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
• Write 0x0063 to the Command Code Register,
• Write any address within the desired start block to the Command Address Registers,
• Write any address within the desired stop block to the Multi-Purpose Registers,
• Write 0x0001 to the Command Execute Register.
NVM vendors may implement additional security features not described in the JEDEC document. Users shall refer to
the device datasheet for complete information.
Some NVM technologies might not have the notion of block, because they do not require and support the erase
operation.
JEDEC Standard No. 209-2E
Page 64
4.7.3 Block Lock-Down Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Block Lock-Down command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being locked
NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being locked
NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the
address written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and
the Status Register bits PSB and ESB are set.
Figure 10 — Block Lock-Down Command Flowchart
Lock-Down a range of contiguous blocks
Provide Command Code
Write (0x0063) to address (OWBA+0x080)
Provide Command Addresses (First and Last)
Write FirstBlockAddr[31:0] to address (OWBA+0x088)
Write LastBlockAddr[31:0] to address (OWBA+0x090)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
JEDEC Standard No. 209-2E
Page 65
4.7.4 Block Erase Command
The Block Erase command is used to erase a Block. It sets all the bits within the selected Block to ’1’. All previous
data in the Block is lost. If the Block is locked, the erase operation will abort, the data in the Block will not be
changed and the Device Status Register will output the error.
The erase operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x0020 to the Command Code Register,
Write any address within the desired block to the Command Address Registers,
Write 0x0001 to the Command Execute Register
The erase operation can be suspended.
If a block being erased is locked during an erase suspend, the operation will complete normally when it is resumed.
The erase is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported).
As data integrity cannot be guaranteed when the Block Erase operation is aborted, the Block must be erased again.
Note that some NVM technologies do not need Erase command, therefore some NVM devices will not support it.
Table 39 — Block Erase Error Conditions
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 1 0 0 0 0 0 Erase operation failure
1 0 1 0 0 0 1 0
Erase operation abort. An erase operation was
attempted on a locked block.
1 0 1 0 1 0 0 0
Erase operation abort. VACC not at appropriate level for
Erase operation.
1 0 1 1 0 0 0 0
Erase operation abort. Block address outside the
LPDDR2-NVM address space.
1 1 1 1 0 0 0 0
Erase operation abort. Attempting to erase a block
during Erase Suspend.
1 0 1 1 0 1 0 0
Erase operation abort. Attempting to erase a block
during Program Suspend.
1 1 1 1 0 1 0 0
Erase operation abort. Attempting to erase a block
during Erase Suspend and Program Suspend.
JEDEC Standard No. 209-2E
Page 66
4.7.4 Block Erase Command (cont’d)
Figure 11 shows the Block Erase Flowchart.

NOTE 1 The Overlay Window must be open to issue Block Erase command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 BlockAddr[31:0] is any byte address within the block being erased
NOTE 5 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 11 — Block Erase Flowchart
Erase one block
Provide Command Code
Write (0x0020) to address (OWBA+0x080)
Provide Command Address
Write BlockAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Invalidate RDB
(5)
JEDEC Standard No. 209-2E
Page 67
4.7.5 Single Word Program Command
The Single Word Program command is used to program a single word (2-byte data) to the memory array.
This is a legacy command and it is optional.
The program operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x0041 (or 0x0040) to the Command Code Register,
Write desired location address to the Command Address Register,
Write desired program data to the Command Data Register (Command Data[15:0] only),
Write 0x0001 to the Command Execute Register.
Programming can be performed in one block at a time.
The Status Register DRB bit, indicates the progress of the Program operation. It should be read to check whether the
operation has completed or not.
After completion of the Program operation (DRB= 1), one of the Status Register error bits (4,3 and 1) going High
means that an error was detected: either a failure occurred during programming, VACC is outside the allowed voltage
range or an attempt to program a locked Block was made. See Section Device Status Register for detailed
information.
The program operation can be suspended.
The program is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported).
As data integrity cannot be guaranteed when the program operation is aborted, the data must be reprogrammed.
Some NVM technologies support the Single Word Program command only under particular conditions.
For example, for LPDDR2-NVM device that has the notion of program region, Single Word Program Command is
supported only by program regions configured in the Control Program mode, and with Command Address value
belonging to a particular portion of the program region.
If a Single Word Program command is issued to a Program Region configured in the Object Program mode, the
Program operation is aborted and PSB and OMSB Status Register bits are set.
For details about program region and program method see the application note.

Table 40 — Single Word Program Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Single Word Program operation failure.
1 0 0 1 0 0 1 0
Single Word Program operation abort. An program
operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Single Word Program operation abort.
VACC not at appropriate level for Program operation.
1 0 1 1 0 0 0 0
Single Word Program operation abort. Program address
outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Single Word Program operation abort.
Attempting to program during Program Suspend.
JEDEC Standard No. 209-2E
Page 68
4.7.5 Single Word Program Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Single Word Program command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 ProgrAddr[31:0] is the target byte address of the programming operation, and ProgrAddr[0] shall be ‘0’.
NOTE 5 ProgrData[15:0] is the desired 2-byte data to be programmed.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 12 — Single Word Program Flowchart
Program using Single Word Program
Provide Command Code
Write (0x0041) to address (OWBA+0x080)
Provide Command Addresses
Write ProgrAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
Provide Command Data
Write ProgrData[15:0] to address (OWBA+0x084)
End
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 69
4.7.6 Single Word Overwrite Command
Single Word Overwrite is supported only by some NVM technologies and some LPDDR2-NVM devices.
The Single Word Overwrite command is used to write a single word (2-byte data) to the memory array.
The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’.
With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With
the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’
are not.
The overwrite operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x0042 to the Command Code Register,
Write desired location address to the Command Address Register,
Write desired program data to the Command Data Register (Command Data[15:0] only),
Write 0x0001 to the Command Execute Register.
Overwriting can be performed in one block at a time.
The Status Register DRB bit, indicates the progress of the Overwrite operation. It should be read to check whether the
operation has completed or not.
After completion of the overwrite operation (DRB= 1), one of the Status Register error bits (4, 3 and 1) going High
means that an error was detected: either a failure occurred during overwriting, VACC is outside the allowed voltage
range or an attempt to overwrite a locked Block was made. See “Status Register” on page 51 for detailed
information.
The overwrite operation may be suspended.
The overwrite is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported).
As data integrity cannot be guaranteed when the overwrite operation is aborted, the data must be rewritten.
Table 41 — Single Word Overwrite Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Single Word Overwrite operation failure.
1 0 0 1 0 0 1 0
Single Word Overwrite operation abort. An overwrite
operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Single Word Overwrite operation abort.
Program voltage violation.
1 0 1 1 0 0 0 0
Single Word Overwrite operation abort. Overwrite
address outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Single Word Overwrite operation abort.
Attempting to program during Overwrite Suspend or
Program Suspend.
JEDEC Standard No. 209-2E
Page 70
4.7.6 Single Word Overwrite Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Single Word Overwrite command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 OverwAddr[31:0] is the target byte address of the overwriting operation, and OverwAddr[0] shall be ‘0’.
NOTE 5 OverwData[15:0] is the desired 2-byte data to be overwritten.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79 .
Figure 13 — Single Word Overwrite Flowchart
Overwrite using Single Word Overwrite
Provide Command Code
Write (0x0042) to address (OWBA+0x080)
Provide Command Addresses
Write OverwAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
Provide Command Data
Write OverwData[15:0] to address (OWBA+0x084)
End
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 71
4.7.7 Buffered Program Command
The Buffered Program Command makes use of the device’s Program Buffer to speed up programming.
The Buffered Program command dramatically reduces in-system programming time compared to other non-buffered
program commands.
If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program
Buffer and programmed into the specified N-Byte aligned location in the main array. The region is determined by bit
[31: K] of the Command Address Register value, where N=2
k
.

The first word data of the Program Buffer to be programmed depends on bit [K-1:0] of Command Address value.
The programming operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data
Count value is in units of bytes and written in the Multi-Purpose Registers.
If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (N-
byte), the programming operation ends without programming the memory array and the Status Register will show an
error (0xB0).
The programming operation doesn't wrap within the program buffer and doesn't cross into the next programming
region.
The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence.
The Command Sequence is:
Write the starting address to the Command Address registers,
Write the Data Count value (number of bytes to be programmed) to the Multi-Purpose Registers,
Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space,
Write 0x00E9 to the Command Code Register,
Write 0x0001 to the Command Execute Register.
If the Block being programmed is locked an error will be set in the Status Register and the operation will abort
without affecting the data in the memory array.
The Buffered Program operation can be suspended.
The program is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity
cannot be guaranteed when the program operation is aborted, the memory array content must be considered invalid.
Table 42 — Buffered Program Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Buffered Program operation failure.
1 0 0 1 0 0 1 0
Buffered Program operation abort. An program operation
was attempted on a locked block.
1 0 0 1 1 0 0 0
Buffered Program operation abort.
Invalid VACC voltage.
1 0 1 1 0 0 0 0
Buffered Program operation abort. Program address
outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Buffered Program operation abort.
Attempting to program during Program Suspend.
1 0 1 1 0 0 0 0
Buffered Program operation abort.
Command Address [K-1:0] value plus the Data Count
Register value exceeds the program buffer boundary (it
is greater than N byte).
JEDEC Standard No. 209-2E
Page 72
4.7.7 Buffered Program Command (cont’d)
Figure 14 shows the Buffered Program Flowchart.
NOTE 1 The Overlay Window must be open to issue Buffered Program command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 DataCount[31:0] is amount of byte being programmed
NOTE 5 ProgrAddr[31:0] is the target byte address of the programming operation.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 14 — Buffered Program Flowchart
Program using Program Buffer
Provide Command Code
Write (0x00E9) to address (OWBA+0x080)
Provide Command Address
Write ProgrAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
Fill the Program Buffer
Write program data to the program buffer
Provide Data Count
Write DataCount[31:0] to address (OWBA+0x090)
End
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 73
4.7.8 Buffered Overwrite Command
This is a command supported only by some NVM technologies and LPDDR2-NVM devices.
The Buffered Overwrite Command makes use of the device’s Program Buffer to speed up overwriting data to the
memory array. The Buffered Overwrite command reduces in-system overwriting time compared to other non-
buffered overwrite commands.
The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’.
With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With
the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’
are not.
If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program
Buffer and overwritten into the specified N-Byte aligned location in the main array. The region is determined by bit
[31: K] of the Command Address Register value, where N=2
k
.
The first word data of the Program Buffer to be overwritten depends on bit [K-1:0] of Command Address value. The
overwriting operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data Count
value is in units of bytes and written in the Multi-Purpose Registers.
If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (N-
byte), the overwriting operation ends without overwriting the memory array and the Status Register will show an
error (0xB0).
The overwriting operation doesn't wrap within the program buffer and doesn't cross into the next programming
region.
The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence.
The Command Sequence is:
Write the starting address to the Command Address Registers,
Write the Data Count value (number of bytes to be overwritten) to the Multi-Purpose Registers,
Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space,
Write 0x00EA to the Command Code Register,
Write 0x0001 to the Command Execute Register.
If the Block being overwritten is locked an error will be set in the Status Register and the operation will abort without
affecting the data in the memory array.
The Buffered Overwrite operation can be suspended.
The overwrite is aborted writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity
cannot be guaranteed when the overwrite operation is aborted, the memory array content must be considered invalid.
Table 43 — Buffered Overwrite Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Buffered Overwrite operation failure.
1 0 0 1 0 0 1 0
Buffered Overwrite operation abort. An overwrite
operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Buffered Overwrite operation abort.
Invalid VACC voltage.
1 0 1 1 0 0 0 0
Buffered Overwrite operation abort. Overwrite address
outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Buffered Overwrite operation abort.
Attempting to overwrite during Overwrite Suspend or
Program Suspend.
1 0 1 1 0 0 0 0
Buffered Overwrite operation abort.
Command Address [K-1:0] value plus the Data Count
Register value exceeds the program buffer boundary (it
is greater than N byte).
JEDEC Standard No. 209-2E
Page 74
4.7.8 Buffered Overwrite Command (cont’d)
Figure 15 shows the Buffered Overwrite Flowchart.
NOTE 1 The Overlay Window must be open to issue Buffered Overwrite command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 DataCount[31:0] is amount of byte being overwritten
NOTE 5 OverwAddr[31:0] is the target byte address of the overwriting operation.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79 .
Figure 15 — Buffered Overwrite Flowchart
Overwrite using Program Buffer
Provide Command Code
Write (0x00EA) to address (OWBA+0x080)
Provide Command Address
Write OverwAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
Fill the Program Buffer
Write overwrite data to the program buffer
Provide Data Count
Write DataCount[31:0] to address (OWBA+0x090)
End
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 75
4.7.9 Program/Erase Suspend
The Program/Erase Suspend request pauses a program or block erase operation. The Program/Erase Resume
command is required to restart the suspended operation.
Program or erase operations can be suspended. For the complete list of embedded operations that can be suspended,
refer to the device datasheet.
The Program/Erase Suspend request is issued by writing ‘0x0001’ to ‘1’ the Suspend Register.
Once the Embedded Controller has paused, bits DRB, ESSB and/or PSSB of the Status Register are set to ‘1’.
The following operations shall be allowed during Program/Erase Suspend:
– Program/Erase Resume
– Read Array (data from erase-suspended block or program-suspended locations is not valid)

Additionally, if the suspended operation was a Block Erase then the following commands are also accepted:
– Single Word Program (except in erase-suspended Block)
– Buffered Program (except in erase suspended Block)
– Block Lock
– Block Unlock
For the complete list of supported commands during Program or Erase Suspend refer to the device datasheet.
Commands not supported during Program or Erase Suspend shall be ignored.
During an erase suspend the Block being erased can be protected by issuing the Block Lock. When the
Program/Erase Resume command is issued the operation will complete.
During a program suspend it is not allowed to write the program buffer.
It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program
operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase
Suspend, the erase operation cannot be resumed until the program operation has completed.
During a Program/Erase Suspend, the device can be placed in Power Down mode by driving CKE low, see Power
Down section for detailed description on how to enter and exit Power Down.
Program/Erase is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported).
Note that some NVM technologies do not need Erase command, therefore some NVM devices will not support it.
JEDEC Standard No. 209-2E
Page 76
4.7.9 Program/Erase Suspend (cont’d)
Figure 16 shows the Program/Erase Suspend Request flowchart.
NOTE 1 The Overlay Window must be open to issue the Program/Erase Suspend command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address.
Figure 16 — Program/Erase Suspend Request Flowchart
Suspend
Request Suspension
Set SUS.0=1
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Write (0x0001) to address (OWBA+0x0C8)
JEDEC Standard No. 209-2E
Page 77
4.7.10 Program/Erase Resume Command
The Program/Erase Resume command is used to restart a previously suspended program or erase operation.
For the complete list of embedded operations that can be resumed, refer to the device datasheet.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00D0 to the Command Code Register
Write 0x0001 to the Command Execute Register.

The command doesn’t require to load any value to the Command Address Register within the Overlay Window. It is
allowed to issue the Program/Erase resume command only when the embedded controller is in the Ready state and if
a program or erase operations has been suspended.
A Resume command when no operation is suspended will be ignored.
If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program
operation has completed.
If an Erase and a Program operation are suspended, the Resume command will Resume the Program command.
Note that some NVM technologies do not need Erase command, therefore some NVM devices will not support it.
Figure 17 shows the Program/Erase Resume command flowchart.
NOTE 1 The Overlay Window must be open to issue the Resume command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address.
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
Figure 17 — Program/Erase Resume Command Flowchart
Resume
Provide Command Code
Write (0x00D0) to address (OWBA+0x080)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
JEDEC Standard No. 209-2E
Page 78
4.7.11 Abort
The Abort request ends all embedded operations.
If any embedded operation is aborted and does not complete due to an abort request, the operation will fail and one or
more Status Register bits will be set.
The Abort request is issued by writing ‘0x0001’ to the Abort Register.
The Abort request is ignored if the Abort Register is written when the device is ready (DRB = “1”).
Therefore, if the device is in program or/and erase suspend, the device will remain in the same status.
In particular, if the device is executing a program operation (DRB = “0”) while it is in erase suspend, the
program will be aborted but the device will remain in erase suspend.
Once the embedded controller has completed the abort request, bit DRB of the Status Register is set to ‘1’ and the
Abort Register is set to ‘0x0000’ by the LPDDR2-NVM device.
Abort feature is optional. If LPDDR2-NVM does not support abort feature, Abort Register may be written only with
0x0000, and when read it shall output the value 0x0000.
Table 44 — Abort Error Conditions
Figure 18 shows the Abort Request flowchart.
NOTE 1 The Overlay Window must be open to issue the Abort command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address.
Figure 18 — Abort Request Flowchart
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0
Abort request issued during program operation.
Abort request issued while program suspend.
1 0 1 0 0 0 0 0
Abort request issued during erase operation.
Abort request issued while erase suspend.
1 0 1 1 0 0 0 0
Abort request issued during erase and program
suspend.
Abort request issued during program operation and
erase suspend.
Abort
Abort Request
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Write (0x0001) to address (OWBA+0x0CA)
JEDEC Standard No. 209-2E
Page 79
4.7.12 Row Data Buffer Incoherency
The ACTIVATE command copies a row content from the memory array to the Row Data Buffer selected by the
BA signals. While a row is open in one Row Data Buffer, the host may program, overwrite or erase that particular
row.
Once the program, overwrite or erase operation is completed (DRB = ‘1’), LPDDR2-NVM device will not update
the Row Data Buffer with the new row content, generating an incoherency between Row Data Buffer and memory
array.
The host shall be aware of this incoherency risk, and manage it in hardware or/and software.
JEDEC Standard No. 209-2E
Page 80
4.8 Dual operations and multiple partition architecture
In some LPDDR2-NVM devices, the memory array may be divided into two or more partitions (multiple partition
architecture). Refer to vendor datasheets to determine support for multiple partition architecture.
LPDDR2-NVM devices that support multiple partition architecture provide greater flexibility for software developers
to split the code and data spaces within the memory array. The dual operations feature simplifies the software
management of the device by allowing code to be executed from one partition while another partition is being
programmed or erased.
The dual operations feature means that while programming or erasing in one partition, read operations are possible in
another partition with zero latency (only one partition at a time is allowed to be in program or erase mode).
If a read operation is required in a partition, which is programming or erasing, the program or erase operation can be
suspended.
Also, if the suspended operation is erase then a program command can be issued to another block, so the device can
have one block in erase suspend mode, one programming, and other partitions available for read operations.
For the complete list of dual operations allowed, refer to the device datasheet.
Table 45 — Simultaneous operations allowed in the same partition
NOTE 1 Depending on the Overlay Window status and the target read address, data may come from the memory
array or from the overlay window.
NOTE 2 Programming may occur during erase suspended.
NOTE 3 LPDDR2-NVM will output invalid data if the read operation occurs in the memory area that is being pro-
grammed.
NOTE 4 LPDDR2-NVM will output invalid data if the read operation occurs in the block that is being erased.
NOTE 5 Not allowed in the block that is being erased.
Table 46 — Simultaneous operations allowed in other partitions
NOTE 1 Depending on the Overlay Window status and the target read address, data may come from the memory
array or from the overlay window.
NOTE 2 Programming may occur during erase suspended.
Status of partition
Operations allowed in the same partition
Read
(1) Buffered
Program
Block
Erase
Idle Yes Yes Yes
Programming
(2)
No No No
Erasing No No No
Program suspended
Yes
(3)
No No
Erase suspended Yes
(4)
Yes
(5)
No
Status of partition
Operations allowed in another partition
Read
(1) Buffered
Program
Block
Erase
Idle Yes Yes Yes
Programming
(2)
Yes No No
Erasing Yes No No
Program suspended
Yes No No
Erase suspended Yes Yes No
JEDEC Standard No. 209-2E
Page 81
5 LPDDR2 Command Definitions and Timing Diagrams
5.1 Activate Command
5.1.1 LPDDR2-SX: Activate Command
The SDRAM Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of
the clock. The bank addresses BA0 - BA2 are used to select the desired bank. The row address R0 through R14 is
used to determine which row to activate in the selected bank. The Activate command must be applied before any
Read or Write operation can be executed. The LPDDR2 SDRAM can accept a read or write command at time t
RCD

after the activate command is sent. Once a bank has been activated it must be precharged before another Activate
command can be applied to the same bank. The bank active and precharge times are defined as t
RAS
and t
RP
,
respectively. The minimum time interval between successive Activate commands to the same bank is determined by
the RAS cycle time of the device (t
RC
). The minimum time interval between Activate commands to different banks is
t
RRD
.
Certain restrictions on operation of the 8-bank devices must be observed. There are two rules. One for restricting the
number of sequential Activate commands that can be issued and another for allowing more time for RAS precharge
for a Precharge All command. The rules are as follows:
• 8-bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated (or refreshed, in the
case of REFpb) in a rolling t
FAW
window. Converting to clocks is done by dividing t
FAW
[ns] by t
CK
[ns], and rounding
up to next integer value. As an example of the rolling window, if RU{ (t
FAW
/ t
CK
) } is 10 clocks, and an activate
command is issued in clock N, no more than three further activate commands may be issued at or between clock N+1
and N+9. REFpb also counts as bank-activation for the purposes of t
FAW
.
• 8-bank device Precharge All Allowance : t
RP
for a Precharge All command for an 8-bank device shall equal t
RPab
,
which is greater than t
RPpb
.
CA0-9
CK_t / CK_c
T0 T2 T1 T3 Tn Tn+1 Tn+2 Tn+3
[Cmd]
RAS - RAS delay time = t
RRD
Read Begins
Figure 19 — LPDDR2-SX: Activate command cycle: t
RCD
= 3, t
RP
= 3, t
RRD
= 2
SDRAM
Bank A
Row Addr Row Addr
Bank B
Row Addr Row Addr
Bank A
Col Addr Col Addr
Bank A Bank A
Row Addr Row Addr
Activate Activate Read Precharge Activate Nop Nop Nop
RAS-CAS delay = t
RCD
Bank Precharge time = t
RP
Row Cycle time = t
RC
Bank Active = t
RAS
NOTE 1 A Precharge-All command uses t
RPab
timing, while a Single Bank Precharge command uses
t
RPpb
timing. In this figure, t
RP
is used to denote either an All-bank Precharge or a Single Bank Precharge.
JEDEC Standard No. 209-2E
Page 82
5.1.1 LPDDR2-SX: Activate Command (cont’d)
5.1.2 LPDDR2-N: Activate Command
The NVM Activate command is issued by holding CS_n LOW, CA0 LOW and CA1 HIGH at the rising edge of the
clock. The Row Buffer (RB) addresses BA0 - BA2 are used to select the desired {RAB, RDB} pair. Devices may
have four or eight Row Buffer pairs. Row Buffers do not correspond directly to any portion of the array; the controller
may use any value of BA0 - BA2 for any array location.
Row address a5 through a19 is used in conjunction with the selected RAB contents to determine which row to load
into the destination RDB. It is recommended to open any single row in only one Row Buffer. If a memory controller
issues an Activate command that causes a single row to be open in more than one RDB, then only the last Row Data
Buffer activated for that given row is valid. The Activate command may be issued only after BL/2 clock cycles after
a previous Read command, or after WL+BL/2+1+RU(tWRA/tCK) clock cycles after a previous Write command.
The Activate command must be applied before any Read or Write operation can be executed. The LPDDR2 NVM
can accept a read or write command at time t
RCD
after the activate command is sent. The activate and preactive times
are defined as t
RAS
and t
RP
, respectively. The minimum time interval between successive Activate commands to the
same Row Buffer pair is determined by the RAS cycle time of the device (t
RC
). The minimum time interval between
Activate commands to different Row Buffer pairs is t
RRD
.
Table 47 — Row Address Buffer selection for Preactive by BA inputs
BA2 (CA9r) BA1 (CA8r) BA0 (CA7r)
Selected {RAB, RDB}
(4-RB devices)
Selected {RAB, RDB}
(8-RB devices)
0 0 0 RB 0 RB 0
0 0 1 RB 1 RB 1
0 1 0 RB 2 RB 2
0 1 1 RB 3 RB 3
1 0 0 RB 0 RB 4
1 0 1 RB 1 RB 5
1 1 0 RB 2 RB 6
1 1 1 RB 3 RB 7
CA0-9
CK_t/CK_c
Tn Tm Tn+1 Tm+1 Tx Tx+1 Ty Ty+1 Ty+2
Figure 20 — LPDDR2-SX: t
FAW
timing
NOTE 1: For 8-bank devices only. No more than 4 banks may be activated in a rolling t
FAW
window.
[Cmd]
Nop ACT
Bank A Bank A
Nop Nop Nop
Tz Tz+2 Tz+1
Nop Nop
SDRAM
ACT
Bank B Bank B
ACT
Bank C Bank C
ACT
Bank D Bank D
Nop ACT
Bank E Bank E
t
FAW
t
RRD
t
RRD
t
RRD
JEDEC Standard No. 209-2E
Page 83
5.1.2 LPDDR2-N: Activate Command (cont’d)
5.2 LPDDR2 Command Input Signal Timing Definition
5.2.1 LPDDR2 Command Input Setup and Hold Timing
Nop
CA0-9
CK_t/CK_c
T0 T2 T1 T3 Tx Tx+1 Tx+2 Tx+3 Tx+4
Figure 21 — LPDDR2-N: Activate command cycle: t
RP
= 2, BL = 4
[Cmd]
Bank Preactive time = t
RP
NVM
Row Cycle time = t
RC
Read to Activate = BL/2 RAS - RAS delay time = t
RRD
RAS-CAS delay = t
RCD
RAB A
Preactive Nop Activate
RB A
Row Addr Row Addr
Activate
RB B
Row Addr Row Addr
Read
RDB A
Col Addr Col Addr
Nop Activate
RB A
Row Addr Row Addr
Nop
Row Addr Row Addr
CA0-9
CK_t/CK_c
T0 T2 T1 T3
Figure 22 — LPDDR2: Command Input Setup and Hold Timing
[Cmd]
CA
Nop
Rise
Command Command Nop
t
IS
t
IH
CS_n
t
IS
t
IH
NOTE Setup and hold conditions also apply to the CKE pin. See section related to power down for timing
diagrams related to the CKE pin.
t
IS
t
IH
t
IS
t
IH
V
IL(AC)
V
IL(DC)
V
IH(AC)
V
IH(DC)
CA
Fall
CA
Rise
CA
Fall
CA
Rise
CA
Fall
CA
Rise
CA
Fall
HIGH or LOW (but a defined logic level)
JEDEC Standard No. 209-2E
Page 84
5.2.2 LPDDR2 CKE Input Setup and Hold Timing
CK_t/CK_c
T0 Tx T1 Tx+1
Figure 23 — LPDDR2: Command Input Setup and Hold Timing
CKE
NOTE 1: After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE speci-
fication (LOW pulse width).
NOTE 2: After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE spec-
ification (HIGH pulse width).
V
ILCKE
V
ILCKE
V
IHCKE
HIGH or LOW (but a defined logic level)
t
IHCKE
V
IHCKE
t
IHCKE
t
ISCKE
t
ISCKE
JEDEC Standard No. 209-2E
Page 85
5.3 Read and Write access modes
5.3.1 LPDDR2-SX: Read and Write access modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW,
CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine
whether the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW).
The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a
burst read or write operation on successive clock cycles.
For LPDDR2-S4 devices, a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4
setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by
Writes provided that this occurs on even clock cycles after the Read or Write command and t
CCD
is met. For
LPDDR2-S2 devices, Reads may interrupt Reads and Writes may interrupt Writes, provided that t
CCD
is met. The
minimum CAS to CAS delay is defined by t
CCD
.
5.3.2 LPDDR2-N: Read and Write access modes
After an RB has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW,
CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine
whether the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW).
The LPDDR2 NVM provides a fast column access operation. A single Read or Write Command will initiate a burst
read or write operation on successive clock cycles. The boundary of the burst cycle is restricted to specific segments
of the Row Data Buffer (RDB) size. For example, if the size of the RDB is 64 Bytes and the device has a 16 bit data
bus interface, the page size of 512 bits is divided into 8, 4, or 2 uniquely addressable boundary segments depending
on burst length, 8 for 4 bit burst, 4 for 8 bit burst, and 2 for 16 bit burst respectively. A 4-bit, 8-bit or 16-bit burst
operation will occur entirely within one of the 8, 4 or 2 groups beginning with the column address supplied to the
device during the Read or Write Command (C1-C4).
For LPDDR2-N devices, a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4
setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by
Writes provided that this occurs on even clock cycles after the Read or Write command and t
CCD
is met. The
minimum CAS to CAS delay is defined by t
CCD
.
JEDEC Standard No. 209-2E
Page 86
5.4 Burst Read Command
The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising
edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column
address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read
Command is issued to the rising edge of the clock from which the t
DQSCK
delay is measured. The first valid datum is
available RL * t
CK
+ t
DQSCK
+ t
DQSQ
after the rising edge of the clock where the Read Command is issued. The data
strobe output is driven LOW t
RPRE
before the first rising valid strobe edge. The first bit of the burst is synchronized
with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the
data strobe. The RL is programmed in the mode registers.
Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c.
t
CH
t
CL
CK_c
CK_t
DQ
DQS_c
DQS_t
t
RPST
Q
t
RPRE
t
QH t
QH
t
DQSQmax
Q Q Q
Figure 24 — Data output (read) timing (t
DQSCKmax
)
t
DQSCKmax t
LZ(DQS)
t
HZ(DQ)
DQS_c
RL - 1 RL
t
LZ(DQ)
t
DQSQmax
t
HZ(DQS)
RL + BL/2
NOTE 1 t
DQSCK
may span multiple clock periods.
NOTE 2 An effective Burst Length of 4 is shown.
DQS_t
t
QSH
t
QSL
t
CH
t
CL
CK_c
CK_t
DQ
DQS_c
DQS_t
Q
t
RPRE
t
QH t
QH
t
DQSQmax
Q Q
Figure 25 — Data output (read) timing (t
DQSCKmin
)
t
LZ(DQS)
t
HZ(DQ)
DQS_c
RL - 1 RL
t
LZ(DQ)
t
HZ(DQS)
t
RPST
t
DQSCKmin
t
DQSQmax
Q
RL + BL/2
NOTE 1 An effective Burst Length of 4 is shown.
DQS_t
t
QSH
t
QSL
JEDEC Standard No. 209-2E
Page 87
5.4 Burst Read Command (cont’d)
CA0-9
DQs
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 26 — LPDDR2-SX: Burst read: RL = 5, BL = 4, t
DQSCK
> t
CK
[Cmd]
t
DQSCK
RL = 5
SDRAM
Nop Read
Bank A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
CK_t / CK_c
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 27 — LPDDR2-SX: Burst read: RL = 3, BL = 8, t
DQSCK
< t
CK
[Cmd]
t
DQSCK
SDRAM
Nop Read
Bank A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DQS_t
CA0-9
DQs
CK_t/CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 28 — LPDDR2-N: Burst read: RL = 5, BL = 4, t
DQSCK
> t
CK
[Cmd]
t
DQSCK
RL = 5
NVM
Nop Read
RDB A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
JEDEC Standard No. 209-2E
Page 88
5.4 Burst Read Command (cont’d)
CA0-9
DQs
CK_t/CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 29 — LPDDR2-N: Burst read: RL = 3, BL = 8, t
DQSCK
< t
CK
[Cmd]
t
DQSCK
NVM
Nop Read
RDB A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DQS_t
CA0-9
DQs
CK_t/CK_c
DQS_c
Tn Tn+2 Tn+1 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8
Figure 30 — LPDDR2: t
DQSCKDL
timing
NOTE 1 t
DQSCKDLmax
is defined as the maximum of ABS(t
DQSCKn
- t
DQSCKm
) for any {t
DQSCKn

,t
DQSCKm
} pair within any 32ms rolling window.
[Cmd]
t
DQSCKn
RL = 5
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
Tm Tm+2 Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
t
DQSCKm
RL = 5
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
t
DQSCKDL
= | t
DQSCKn
– t
DQSCKm
|
32ms maximum
CA0-9
DQs
CK_t/CK_c
DQS_c
Tn Tn+2 Tn+1 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8
Figure 31 — LPDDR2: t
DQSCKDM
timing
NOTE 1 t
DQSCKDMmax
is defined as the maximum of ABS(t
DQSCKn
- t
DQSCKm
) for any
{t
DQSCKn
,t
DQSCKm
} pair within any 1.6us rolling window.
[Cmd]
t
DQSCKn
RL = 5
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
Tm Tm+2 Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
t
DQSCKm
RL = 5
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
t
DQSCKDM
= | t
DQSCKn
– t
DQSCKm
|
.1.6us maximum
JEDEC Standard No. 209-2E
Page 89
5.4 Burst Read Command (cont’d)
CA0-9
DQs
CK_t/CK_c
DQS_c
Tn Tn+2 Tn+1 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8
Figure 32 — LPDDR2: t
DQSCKDS
timing
NOTE 1 t
DQSCKDSmax
is defined as the maximum of ABS(t
DQSCKn
- t
DQSCKm
) for any {t
DQSCKn

,t
DQSCKm
} pair for reads within a consecutive burst within any 160ns rolling window.
[Cmd]
t
DQSCKn
RL = 5
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
Tm Tm+2 Tm+1 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8
t
DQSCKm
Nop Read
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
t
DQSCKDS
= | t
DQSCKn
– t
DQSCKm
|
.160ns maximum
RL = 5
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
3
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
2
DOUT A
0
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 33 — LPDDR2-SX: Burst read followed by burst write: RL = 3, WL = 1, BL = 4
[Cmd]
t
DQSCK
RL = 3
BL/2
t
DQSSmin
WL = 1
SDRAM
Nop Read
Bank A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Write
Bank A
Col Addr Col Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DIN A
0
DIN A
1
DIN A
2
DQS_t
JEDEC Standard No. 209-2E
Page 90
5.4 Burst Read Command (cont’d)
The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL)
and the Burst Length (BL). Minimum read to write latency is RL + RU(t
DQSCK
max/t
CK
) + BL/2 + 1 - WL clock
cycles. Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the
truncated read burst should be used as “BL” to calculate the minimum read to write delay.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 34 — LPDDR2-N: Burst read followed by burst write: RL = 3, WL = 1, BL = 4
[Cmd]
t
DQSCK
RL = 3
BL/2
t
DQSSmin
WL = 1
NVM
Nop Read
RDB A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Write
RDB A
Col Addr Col Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DIN A
0
DIN A
1
DIN A
2
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 35 — LPDDR2-SX: Seamless burst read: RL = 3, BL = 4, t
CCD
= 2
[Cmd]
t
CCD
= 2
RL = 3
SDRAM
Nop Read
Bank N
Col Addr A Col Addr A
Nop Nop Nop Nop Nop Nop Read
Bank N
Col Addr B Col Addr B
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DQS_t
JEDEC Standard No. 209-2E
Page 91
5.4 Burst Read Command (cont’d)
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4
operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation.
For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different banks
as long as the banks are activated.
For LPDDR2-NVM, this operation is allowed regardless of whether the accesses read the same or different RDBs as
long as the RDBs are activated.
5.4.1 Reads interrupted by a read
For LPDDR2-S4 and LPDDR2-N devices, burst read can be interrupted by another read on even clock cycles after
the Read command, provided that t
CCD
is met. For LPDDR2-S2 devices, burst reads may be interrupted by other
reads on any subsequent clock, provided that t
CCD
is met.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 36 — LPDDR2-N: Seamless burst read: RL = 3, BL = 4, t
CCD
= 2
[Cmd]
t
CCD
= 2
RL = 3
NVM
Nop Read
RDB N
Col Addr A Col Addr A
Nop Nop Nop Nop Nop Nop Read
RDB N
Col Addr B Col Addr B
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 37 — LPDDR2-SX: Read burst interrupt example: RL = 3, BL = 8, t
CCD
= 2
[Cmd]
NOTE 1 For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.
NOTE 2 For LPDDR2-S4 devices, read burst interrupt may only occur on even clock cycles after the previous
commands, provided that t
CCD
is met.
NOTE 3 For LPDDR2-S2 devices, read burst interrupt may occur on any clock cycle after the intial read
NOTE 4 Reads can only be interrupted by other reads or the BST command.
NOTE 5 Read burst interruption is allowed to any bank inside DRAM.
NOTE 6 Read burst with Auto-Precharge is not allowed to be interrupted.

t
CCD
= 2
SDRAM
command, provided that t
CCD
is met.
Nop Read
Bank N
Col Addr A Col Addr A
Nop Nop Nop Nop Nop Nop Read
Bank N
Col Addr B Col Addr B
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
4
DOUT B
5
read
DQS_t
NOTE 7 The effective burst length of the first read equals two times the number of clock cycles between the
first read and the interrupting read.
JEDEC Standard No. 209-2E
Page 92
5.4.1 Reads interrupted by a read (cont’d)
5.4.2 LPDDR2: Data Not Valid
LPDDR2 devices will implement Data Not Valid (DNV) signal if they set MR0 OP2 bit to “1”, and will not
implement Data Not Valid signal if they set MR0 OP2 bit to “0”. LPDDR2-SX devices will not implement DNV.
DNV signal, when implemented, is outputted from the memory device with DQ data. The DNV signal and the Data
Mask signal (DM) share the same pin. For information on the DM signal usage, see “Write data mask” on page 70.
DNV signals follow the same timings as the DQ signals for read bursts. DNV0, DNV1, DNV2, and DNV3 timings
are referenced to DQS0, DQS1, DQS2, and DQS3 respectively.
LPDDR2 devices that support Data Not Valid shall drive all DNV signal(s) to the same level for each data beat during
read bursts. The DNV signal(s) are valid only the first four beats of a read burst. The beat 0 of the DNV signal shall
be driven LOW if the data in the burst is valid. Beat 0 of the DNV signal shall be driven HIGH if the data in the burst
is invalid. Beat 1 of DNV indicates how the controller may retry the request, (DNV = LOW) for immediate retry or
(DNV = HIGH) for retry after a pre-specified time in micro seconds in Mode Register 29 (MR29) on page 45. Beat 2
for immediate retries indicates whether the immediate retry should be with read command (DNV=LOW) or active
command (DNV=HIGH), and for long retry (DNV=LOW). When DNV signal for beats 0, 1, and 2 are driven high, it
indicates a currently reserved mode. Beat 3 is not used. Table 48 on page 92 displays DNV retry options.
For devices that implement Data Not Valid, DNV shall be driven to zero during the first data beat during MRR
operations.
NOTE 1 Immediate Retry indicates the controller may retry the request immediately with read or active command as specified.
NOTE 2 Retry Long indicates that the controller should wait for the pre-specified time before retrying the Read. An Active must be issued before
the retry Read command. Optionally, a Preactive command may be issued before the Active command. A retry earlier than the pre-specified time
may result in receiving another DNV signal.
NOTE 3 In case of Mode Register Read (MRR) command, DNV shall be driven to zero during the first data beat.
Table 48 — LPDDR2: Data Not Valid
DNV, beat 0 DNV, beat 1 DNV, beat 2 DNV, beat 3 Read Burst Notes
0 X X X Valid 3
1 0 0 X Immediate Retry with Read 1
1 0 1 X Immediate Retry with Activate 1
1 1 0 X Retry Long with Read 2
1 1 1 X Reserved
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 38 — LPDDR2-N: Read burst interrupt example: RL = 3, BL = 8, t
CCD
= 2
[Cmd]
NOTE 1 For LPDDR2-N devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.
NOTE 2 For LPDDR2-N devices, read burst interrupt may only occur on even clock cycles after the previous
read commands, provided that t
CCD
is met.
NOTE 3 Reads can only be interrupted by other reads or the BST command.
NOTE 4 Read burst interruption is allowed to any RDB inside the NVM.
t
CCD
= 2
NVM
Nop Read
RDB N
Col Addr A Col Addr A
Nop Nop Nop Nop Nop Nop Read
RDB N
Col Addr B Col Addr B
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
4
DOUT B
5
NOTE 5 The effective burst length of the first read equals two times the number of clock cycles between the
first read and the interrupting read.
DQS_t
JEDEC Standard No. 209-2E
Page 93
5.4.2 LPDDR2: Data Not Valid (cont’d)
CA0-9
DQs
CK_t/CK_c
RL = 3
DQS_c/
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 39 — LPDDR2: DNV with valid data: RL = 3, BL = 8
[Cmd]
Nop Read
Row/Bank A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DM/DNV
DQS_t
CA0-9
DQs
CK_t/CK_c
RL = 3
DQS_c/
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 40 — LPDDR2: DNV with invalid data, retry with Read: RL = 3, BL = 8
[Cmd]
Nop Read
Row/Bank A
Col Addr Col Addr
Nop Nop Nop Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DM/DNV
DQS_t
JEDEC Standard No. 209-2E
Page 94
5.5 Burst Write Operation
The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising
edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column
address for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write
Command is issued to the rising edge of the clock from which the t
DQSS
delay is measured. The first valid datum
shall be driven WL * t
CK
+ t
DQSS
from the rising edge of the clock from which the Write command is issued. The
data strobe signal (DQS) should be driven LOW t
WPRE
prior to the data input. The data bits of the burst cycle must be
applied to the DQ pins t
DS
prior to the respective edge of the DQS_t, DQS_c and held valid until t
DH
after that edge.
The burst data are sampled on successive edges of the DQS_t, DQS_c until the burst length is completed, which is 4,
8, or 16 bit burst.
For LPDDR2-SDRAM devices, t
WR
must be satisfied before a precharge command to the same bank may be issued
after a burst write operation.
For LPDDR2-N devices, t
WRA
must be satisfied before an Activate command to the same RDB may be issued after a
burst write operation. A Preactive command may be sent at any time after a Write command.
Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c.
t
DS t
DS
t
DH
t
WPRE
t
WPST
t
DQSH
t
DQSL
DQS_c
DQS_t
D
DMin
DQS_c
DQ
DM
t
DH
DMin DMin DMin
D D D
DQS_t
VIL(ac)
VIH(ac)
V
IL
(ac)
VIH(ac)
VIL(dc)
V
IH
(dc)
VIL(dc)
V
IH
(dc)
Figure 41 — Data input (write) timing
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 Tx Tx+1 Ty Ty+1
Figure 42 — LPDDR2-SX: Burst write : WL = 1, BL = 4
[Cmd]
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
DQs
DQS_c
SDRAM
Completion of Burst Write
t
DQSSmin

t
DSS

t
DSS

t
DSH
t
DSH

WL = 1
WL = 1
Bank A
Precharge Nop Activate
Bank A
Row Addr Row Addr
Nop Nop Nop Nop Nop Write
Bank A
Col Addr Col Addr
t
WR
t
WR
t
RP
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
DQS_t
JEDEC Standard No. 209-2E
Page 95
5.5 Burst Write Operation (cont’d)
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 43 — LPDDR2-N: Burst write followed by Preactive: WL = 1, BL = 4
[Cmd]
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
DQs
DQS_c
NVM
Completion of Burst Write
t
DQSSmin

t
DSS

t
DSS

t
DSH
t
DSH

WL = 1
WL = 1
RAB A
Preactive Nop Nop Nop Nop Nop Nop Write
RDB A
Col Addr Col Addr Row Addr
Nop
Row Addr
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
NOTE 1 A Preactive command may be issued on any clock cycle after a Write command and does not affect the ongoing burst.
DQS_t
DQS_t
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 44 — LPDDR2-N: Burst write followed by Activate: WL = 1, BL = 4
[Cmd]
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
DQs
DQS_c
NVM
Completion of Burst Write
t
DQSSmin

t
DSS

t
DSS

t
DSH
t
DSH

t
WRA
WL = 1
WL = 1
Nop Nop Nop Nop Nop Nop Nop Activate
RB A
Row Addr Row Addr
Write
RDB A
Col Addr Col Addr
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
DQS_t
NOTE 1 The minimum number of clock cycles from the burst write command to the Activate command is [WL + 1 + BL/2 +
RU( tWRA/tCK)].
NOTE 2 If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write
burst shall be used as “BL” to calculate the minimum write to Activate delay.
JEDEC Standard No. 209-2E
Page 96
5.5 Burst Write Operation (cont’d)
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 45 — LPDDR2-SX: Burst write followed by burst read: RL=3, WL = 1, BL = 4
[Cmd]
SDRAM
t
WTR
RL = 3
NOTE 1 The minimum number of clock cycles from the burst write command to the burst read command for any bank
is [WL + 1 + BL/2 + RU( t
WTR
/t
CK
)].
NOTE 2 t
WTR
starts at the rising edge of the clock after the last valid input datum.
NOTE 3 If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write
burst should be used as “BL” to calculate the minimum write to read delay.
WL = 1
Nop Nop Nop Nop Nop Nop Nop Write
Bank M
Col Addr A Col Addr A
Read
Bank N
Col Addr B Col Addr B
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 46 — LPDDR2-N: Burst write followed by burst read: RL=3, WL = 1, BL = 4
[Cmd]
NVM
t
WTR
RL = 3
WL = 1
Nop Nop Nop Nop Nop Nop Nop Write
RDB M
Col Addr A Col Addr A
Read
RDB N
Col Addr B Col Addr B
DIN A
0
DIN A
1
DIN A
2
DIN A
3
NOTE 1 The minimum number of clock cycles from the burst write command to the burst read command for any RDB
is [WL + 1 + BL/2 + RU( t
WTR
/t
CK
)].
NOTE 2 t
WTR
starts at the rising edge of the clock after the last valid input datum.
NOTE 3 If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write
burst should be used as “BL” to calculate the minimum write to read delay.
DQS_t
JEDEC Standard No. 209-2E
Page 97
5.5 Burst Write Operation (cont’d)
5.5.1 Writes interrupted by a write
For LPDDR2-S4 and LPDDR2-N devices, burst write can only be interrupted by another write on even clock cycles
after the Write command, provided that t
CCD
(min) is met.
For LPDDR2-S2 devices, burst writes may be interrupted on any subsequent clock, provided that t
CCD
(min) is met.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 47 — LPDDR2-SX: Seamless burst write: WL = 1, BL = 4, t
CCD
= 2
[Cmd]
SDRAM
NOTE 1: The seamless burst write operation is supported by enabling a write command every other clock for
BL = 4 operation, every four clocks for BL = 8 operation, or every eight clocks for BL=16 operation. This
operation is allowed regardless of same or different banks as long as the banks are activated.
t
CCD
= 2
WL = 1
Nop Nop Nop Nop Nop Nop Write
Bank M
Col Addr A Col Addr A
Write
Bank N
Col Addr B Col Addr B
Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN B
0
DIN B
1
DIN B
2
DIN B
3
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 48 — LPDDR2-N: Seamless burst write: WL = 1, BL = 4
[Cmd]
NVM
NOTE 1: The seamless burst write operation is supported by enabling a write command every other clock for
BL = 4 operation, every four clocks for BL = 8 operation, or every eight clocks for BL=16 operation. This
operation is allowed regardless of same or different Row Buffers as long as the Row Buffers are activated.
WL = 1
Nop Nop Nop Nop Nop Nop Write
RDB M
Col Addr A Col Addr A
Write
RDB N
Col Addr B Col Addr B
Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN B
0
DIN B
1
DIN B
2
DIN B
3
DQS_t
JEDEC Standard No. 209-2E
Page 98
5.5.1 Writes interrupted by a write (cont’d)
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 49 — LPDDR2-SX: Write burst interrupt timing: WL = 1, BL = 8, t
CCD
= 2
[Cmd]
NOTE 1 For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16.
NOTE 2 For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous
write commands, provided that t
CCD
(min) is met.
NOTE 3 For LPDDR2-S2 devices, write burst interrupt may occur on any clock after the initial write command,
NOTE 4 Writes can only be interrupted by other writes or the BST command.
NOTE 5 Write burst interruption is allowed to any bank inside DRAM.
NOTE 6 Write burst with Auto-Precharge is not allowed to be interrupted.

t
CCD
= 2
SDRAM
WL = 1
provided that t
CCD
(min) is met.
Nop Nop Nop Nop Nop Nop Write
Bank M
Col Addr A Col Addr A
Write
Bank N
Col Addr B Col Addr B
Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN B
0
DIN B
1
DIN B
2
DIN B
3
DIN B
4
DIN B
5
DIN B
6
DIN B
7
NOTE 7 The effective burst length of the first write equals two times the number of clock cycles between the
first write and the interrupting write.
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 50 — LPDDR2-N: Write burst interrupt timing: WL = 1, BL = 8, t
CCD
= 2
[Cmd]
NOTE 1 For LPDDR2-N devices, write burst interrupt function is only allowed on burst of 8 and burst of 16.
NOTE 2 For LPDDR2-N devices, write burst interrupt may only occur on even clock cycles after the previous
write commands, provided that t
CCD
(min) is met.
NOTE 3 Writes can only be interrupted by other writes or the BST command.
NOTE 4 Write burst interruption is allowed to any RDB inside the NVM.
t
CCD
= 2
NVM
WL = 1

Nop Nop Nop Nop Nop Nop Write
RDB M
Col Addr A Col Addr A
Write
RDB N
Col Addr B Col Addr B
Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN B
0
DIN B
1
DIN B
2
DIN B
3
DIN B
4
DIN B
5
DIN B
6
DIN B
7
NOTE 5 The effective burst length of the first write equals two times the number of clock cycles between the
first write and the interrupting write.
DQS_t
JEDEC Standard No. 209-2E
Page 99
5.6 Burst Terminate
The Burst Terminate (BST) command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and
CA3 LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read or
Write burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles
after a Read or Write command. The effective burst length of a Read or Write command truncated by a BST
command is as follows:
Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command}
Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the
truncated burst should be used as “BL” to calculate the minimum read to write or write to read delay.
The BST command only affects the most recent read or write command. The BST command truncates an ongoing
read burst RL * t
CK
+ t
DQSCK
+ t
DQSQ
after the rising edge of the clock where the Burst Terminate command is
issued. The BST command truncates an ongoing write burst WL * t
CK
+ t
DQSS
after the rising edge of the clock
where the Burst Terminate command is issued.
For LPDDR2-S2 devices, the 2-bit prefetch architecture allows the BST command to be issued in any cycle after a
Write or Read command.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 51 — LPDDR2-S2: Write burst truncated by BST: WL = 1, BL = 16
[Cmd]
S2 SDRAM
NOTE 1 The BST command truncates an ongoing write burst WL * t
CK
+ t
DQSS
after the rising edge of the clock where the
Burst Terminate command is issued.
NOTE 2 Additional BST commands are not allowed after T1 and may not be issued until after the next Read or Write command.
WL = 1
Nop Nop Nop Nop Nop Nop Write
Bank M
Col Addr A Col Addr A
BST Nop
DIN A
0
DIN A
1
WL * t
CK
+ t
DQSS
DQS_t
JEDEC Standard No. 209-2E
Page 100
5.6 Burst Terminate (cont’d)
For LPDDR2-S4 and LPDDR2-N devices, the 4-bit prefetch architecture allows the BST command to be issued on an
even number of clock cycles after a Write or Read command. Therefore, the effective burst length of a Read or Write
command truncated by a BST command is an integer multiple of 4.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 52 — LPDDR2-S2: Read burst truncated by BST: RL = 3, BL = 4
[Cmd]
S2 SDRAM
NOTE 1 The BST command truncates an ongoing read burst RL * t
CK
+ t
DQSCK
+ t
DQSQ
after the rising edge of the clock where
the Burst Terminate command is issued.
NOTE 2 Additional BST commands are not allowed after T1 and may not be issued until after the next Read or Write command.
RL = 3
Nop Nop Nop Nop Nop Nop BST Nop Read
Bank N
Col Addr A Col Addr A
DOUT A
0
DOUT A
1
RL * t
CK
+ t
DQSCK
+ t
DQSQ
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 53 — LPDDR2-S4: Burst Write truncated by BST: WL = 1, BL = 16
[Cmd]
S4 SDRAM
NOTE 1 The BST command truncates an ongoing write burst WL * t
CK
+ t
DQSS
after the rising edge of the clock where the
Burst Terminate command is issued.
NOTE 2 For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Write command.
NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.
WL = 1
BST not allowed
Nop Nop Nop Nop Nop Nop Write
Bank M
Col Addr A Col Addr A
BST Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
4
DIN A
5
DIN A
6
DIN A
7
WL * t
CK
+ t
DQSS
DQS_t
JEDEC Standard No. 209-2E
Page 101
5.6 Burst Terminate (cont’d)
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 54 — LPDDR2-S4: Burst Read truncated by BST: RL=3, BL = 16
[Cmd]
S4 SDRAM
NOTE 1 The BST command truncates an ongoing read burst RL * t
CK
+ t
DQSCK
+ t
DQSQ
after the rising edge of the clock
where the Burst Terminate command is issued.
NOTE 2 For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Read command.
NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write
command.
RL = 3
BST not allowed
Nop Nop Nop Nop Nop Nop BST Nop Read
Bank N
Col Addr A Col Addr A
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
RL * t
CK
+ t
DQSCK
+ t
DQSQ
DQS_t
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 55 — LPDDR2-N: Burst Write truncated by BST: WL = 1, BL = 16
[Cmd]
NVM
NOTE 1 The BST command truncates an ongoing write burst WL * t
CK
+ t
DQSS
after the rising edge of the clock where the
Burst Terminate command is issued.
NOTE 2 For LPDDR2-N devices, BST can only be issued an even number of clock cycles after the Write command.
NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write
command.
WL = 1
BST not allowed
Nop Nop Nop Nop Nop Nop Write
RDB M
Col Addr A Col Addr A
BST Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
4
DIN A
5
DIN A
6
DIN A
7
WL * t
CK
+ t
DQSS
DQS_t
JEDEC Standard No. 209-2E
Page 102
5.6 Burst Terminate (cont’d)
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 56 — LPDDR2-N: Burst Read truncated by BST: RL=3, BL = 16
[Cmd]
NVM
NOTE 1 The BST command truncates an ongoing read burst RL * t
CK
+ t
DQSCK
+ t
DQSQ
after the rising edge of the clock
where the Burst Terminate command is issued.
NOTE 2 For LPDDR2-N devices, BST can only be issued an even number of clock cycles after the Read command.
NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write
command.
RL = 3
BST not allowed
Nop Nop Nop Nop Nop Nop BST Nop Read
Bank N
Col Addr A Col Addr A
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
RL * t
CK
+ t
DQSCK
+ t
DQSQ
DQS_t
JEDEC Standard No. 209-2E
Page 103
5.7 Write Data Mask
One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the
implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given
cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is
internally loaded identically to data bits to insure matched system timing.
See Table 51 on page 115 for Write to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Write to
Precharge timings for LPDDR2-S2.
Data Mask Timing
DQS_c
DQ
DM
t
DS
t
DH
DQS_t
V
IL
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
CK_c
CK_t
[CMD]
Case 2: max tDQSS
tDQSSmax
tDQSSmin
tWR
Data Mask Function, WL = 2, BL = 4 shown, second DQ masked
Figure 57 — LPDDR2-SX: Write data mask
Case 1: min tDQSS
SDRAM
WL = 2
Write
t
DS
t
DH
V
IL
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
0 1 3 2
0 1 3 2
tWTR
DQS_c
DQ
DM
DQS_c
DQ
DM
DQS_t
DQS_t
JEDEC Standard No. 209-2E
Page 104
5.7 Write Data Mask (cont’d)
Data Mask Timing
CK_c
CK_t
[CMD]
DQS_c
DQ
DM
Case 2: max tDQSS
DQS_c
DQ
DM
tDQSSmax
tDQSSmin
tWRA
Data Mask Function, WL = 2, BL = 4 shown, second DQ masked
Figure 58 — LPDDR2-N: Write data mask
Case 1: min tDQSS
NVM
WL = 2
Write
DQS_c
DQ
DM
t
DS
t
DH
DQS_t
V
IL
(ac)
V
IH
(ac)
V
IL
(dc)
V
IH
(dc)
t
DS
t
DH
VIL(ac)
VIH(ac)
VIL(dc)
VIH(dc)
tWTR
DQS_t
DQS_t
JEDEC Standard No. 209-2E
Page 105
5.8 LPDDR2-N: Preactive operation
The Preactive command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at
the rising edge of clock. After issuing a Preactive command, the target Row Buffer will return to the Idle state once
the minimum Preactive latency (t
RP
) is satisfied and any ongoing Read or Write operation is complete. The Preactive
command addresses one Row Address Buffer (RAB). Each RAB is coupled with one specific Row Data Buffer
(RDB) selected by BA0 - BA2. An {RAB, RDB} pair is referred to as a Row Buffer (RB).
The Preactive command is used to load the upper part of a row address into one RAB selected by BA0 - BA2. The
address subset stored in an RAB will later be combined with the lower portion of the row address sent with the
Activate command to load one row of the memory array or Overlay Window content into an RDB. Note that the row
size of the NVM device may differ from the row size for an SDRAM.
Devices may have four or eight RABs. Each RAB is not restricted to any portion of the device address space,
therefore the controller may use any RAB for any partial row address, including storing the same partial row address
value in multiple RABs concurrently. Each RAB is persistent until a MRW Reset command is issued or power loss
occurs, or until a new Preactive command is issued to that RAB. Therefore, Preactive is optional when the desired
RAB already holds the desired partial row-address value.
The Preactive command does not invoke internal sensing. Therefore, after issuing a Preactive command to any RAB
and then satisfying t
RP
, the memory controller shall issue an Activate command to the corresponding RB before
issuing a Read or Write command to the respective RDB.
All RABs shall be reset to 0x0000 by the memory during the initialization procedure.

Table 49 — Row Address Buffer selection for Preactive by BA inputs
BA2 (CA9r) BA1 (CA8r) BA0 (CA7r)
Selected RAB
(4-RB devices)
Selected RAB
(8-RB devices)
0 0 0 RAB 0 RAB 0
0 0 1 RAB 1 RAB 1
0 1 0 RAB 2 RAB 2
0 1 1 RAB 3 RAB 3
1 0 0 RAB 0 RAB 4
1 0 1 RAB 1 RAB 5
1 1 0 RAB 2 RAB 6
1 1 1 RAB 3 RAB 7
JEDEC Standard No. 209-2E
Page 106
5.8.1 LPDDR2-N: Burst Read operation followed by Activate or Preactive
For LPDDR2-N devices, a Read burst may be followed by a Preactive or Activate command to the same Row Buffer
pair. An Activate command to the same Row Buffer pair may not be issued earlier than BL/2 cycles after the Read
command. For an untruncated burst, BL is the complete burst length selected in the Mode Registers. For a truncated
burst, BL is the effective burst length. A Preactive command may be issued at any time following a Read command.
Following the Preactive command, only BST may be issued to the same Row Buffer until t
RP
is met. Following the
Activate command, a subsequent command to the same Row Buffer shall not be issued until t
RCD
is met. Read bursts
are not impacted by Preactive or Activate commands to different Row Buffer pairs.
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 59 — LPDDR2-N: Burst read operation followed by Preactive: RL = 3, BL = 4
[Cmd]
t
RP

NVM
Nop
RAB M
Preactive Nop Activate
RB M
Row Addr Row Addr
Read
RDB M
Col Addr A Col Addr A
Nop Nop
Row Addr
Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
Row Addr
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 60 — LPDDR2-N: Burst read operation followed by Activate: RL = 3, BL = 4
[Cmd]
BL/2
NVM
Nop Nop Activate
RB M
Row Addr
Read
RDB M
Col Addr A Col Addr A
Nop Nop Nop Nop Nop
Row Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
NOTE 1 If a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read
burst shall be used as “BL” to calculate the minimum Read to Activate delay
JEDEC Standard No. 209-2E
Page 107
5.8.2 LPDDR2-N: Burst Write operation followed by Activate or Preactive
A Preactive command may be issued at any time after a Write command. An Activate command to the same RDB
may be issued t
WRA
after the completion of the last burst write cycle. No Activate command to the same RDB should
be issued prior to the t
WRA
delay.
Minimum Write to Activate command spacing to the same Row Buffer equals WL + BL/2 + 1 + RU(t
WRA
/t
CK
) clock
cycles. For an untruncated burst, BL is the value from the Mode Register. For an truncated burst, BL is the effective
burst length.
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 61 — LPDDR2-N: Burst write followed by Preactive: WL = 1, BL = 4
[Cmd]
t
DQSSmin

DQs
DQS_c
NVM
WL = 1
WL = 1
RAB A
Preactive Nop Nop Nop Nop Nop Nop Write
RDB A
Col Addr Col Addr Row Addr
Nop
Row Addr
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
DQS_t
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
Completion of Burst Write
JEDEC Standard No. 209-2E
Page 108
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 62 — LPDDR2-N: Burst write followed by Activate: WL = 1, BL = 4
[Cmd]
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
t
DQSSmin

DQs
DQS_c
NVM
t
WRA
Completion of Burst Write
WL = 1
WL = 1
Nop Nop Nop Nop Nop Nop Nop Activate
RB A
Row Addr Row Addr
Write
RDB A
Col Addr Col Addr
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
DQS_t
NOTE 1 The minimum number of clock cycles from the burst write command to the Activate command is [WL + 1 + BL/2 +
RU( tWRA/tCK)].
NOTE 2 If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write
burst shall be used as “BL” to calculate the minimum write to Activate delay.
JEDEC Standard No. 209-2E
Page 109
5.8.3 LPDDR2-N: Auto Precharge (AP) bit
The AP bit (CA0f) is ignored during READ and WRITE commands.
5.9 LPDDR2-SX: Precharge operation
The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is
initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock.
The Precharge Command can be used to precharge each bank independently or all banks simultaneously. For 4-bank
devices, the AB flag, and the bank address bits, BA0 and BA1, are used to determine which bank(s) to precharge. For
8-bank devices, the AB flag, and the bank address bits, BA0, BA1, and BA2, are used to determine which bank(s) to
precharge. The bank(s) will be available for a subsequent row access t
RPab
after an All-Bank Precharge command is
issued and t
RPpb
after a Single-Bank Precharge command is issued.
In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices,
the Row Precharge time (t
RP
) for an All-Bank Precharge for 8-bank devices (t
RPab
) will be longer than the Row
Precharge time for a Single-Bank Precharge (t
RPpb
). For 4-bank devices, the Row Precharge time (t
RP
) for an All-
Bank Precharge (t
RPab
) is equal to the Row Precharge time for a Single-Bank Precharge (t
RPpb
).
Figure 19 on page 81 shows Activate to Precharge timing.
Table 50 — Bank selection for Precharge by address bits
AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r)
Precharged Bank(s)
4-bank device
Precharged Bank(s)
8-bank device
0 0 0 0 Bank 0 only Bank 0 only
0 0 0 1 Bank 1 only Bank 1 only
0 0 1 0 Bank 2 only Bank 2 only
0 0 1 1 Bank 3 only Bank 3 only
0 1 0 0 Bank 0 only Bank 4 only
0 1 0 1 Bank 1 only Bank 5 only
0 1 1 0 Bank 2 only Bank 6 only
0 1 1 1 Bank 3 only Bank 7 only
1 DON’T CARE DON’T CARE DON’T CARE All Banks All Banks
JEDEC Standard No. 209-2E
Page 110
5.9.1 LPDDR2-SX: Burst Read operation followed by Precharge
For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command.
For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst
length. A new bank active (command) may be issued to the same bank after the Row Precharge time (t
RP
). A
precharge command cannot be issued until after t
RAS
is satisfied.
For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minimum analog time from
the rising clock edge that initiates the last 4-bit prefetch of a Read command. For LPDDR2-S2 devices, the minimum
Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last
2-bit prefetch of a Read command.This time is called t
RTP
(Read to Precharge).
For LPDDR2-S2 devices, t
RTP
begins BL/2 - 1 clock cycles after the Read command. For LPDDR2-S4 devices, t
RTP

begins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a BST command or a Read
command to a different bank, the effective “BL” shall be used to calculate when t
RTP
begins.
See Table 51 on page 115 for Read to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Read to
Precharge timings for LPDDR2-S2.
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 63 — LPDDR2-S2: Burst read followed by Precharge:
RL = 3, BL = 8, t
RTP
(min) <= t
CK
[Cmd]
t
RP

BL/2
t
RTP
SDRAM
Nop
Bank M
Precharge Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 64 — LPDDR2-S4: Burst read followed by Precharge:
RL = 3, BL = 8, RU(t
RTP
(min)/t
CK
) = 2
[Cmd]
t
RP

BL/2
t
RTP
SDRAM
Nop
Bank M
Precharge Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
4
DOUT A
5
DOUT A
6
DOUT A
7
DQS_t
JEDEC Standard No. 209-2E
Page 111
5.9.1 LPDDR2-SX: Burst Read operation followed by Precharge 9cont’d)
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 65 — LPDDR2-S2: Burst read followed by Precharge:
RL = 3, BL = 4, RU(t
RTP
(min)/t
CK
) = 2
[Cmd]
t
RP

BL/2
t
RTP
= 2
SDRAM
Nop
Bank M
Precharge Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 66 — LPDDR2-S4: Burst read followed by Precharge:
RL = 3, BL = 4, RU(t
RTP
(min)/t
CK
) = 3
[Cmd]
t
RP

BL/2
t
RTP
= 3
SDRAM
Nop
Bank M
Precharge Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
JEDEC Standard No. 209-2E
Page 112
5.9.2 LPDDR2-SX: Burst Write followed by Precharge
For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge
command may be issued. This delay is known as the write recovery time (t
WR
) referenced from the completion of the
burst write to the precharge command. No Precharge command to the same bank should be issued prior to the t
WR

delay.
LPDDR2-S2 devices write data to the array in prefetch pairs (prefetch = 2) and LPDDR2-S4 devices write data to the
array in prefetch quadruples (prefetch = 4). The beginning of an internal write operation may only begin after a
prefetch group has been latched completely. Therefore, the write recovery time (t
WR
) starts at different boundaries for
LPDDR2-S2 and LPDDR2-S4 devices.
For LPDDR2-S2 devices, minimum Write to Precharge command spacing to the same bank is WL + RU(BL/2) + 1 +
RU(t
WR
/t
CK
) clock cycles. For LPDDR2-S4 devices, minimum Write to Precharge command spacing to the same
bank is WL + BL/2 + 1 + RU(t
WR
/t
CK
) clock cycles. For an untruncated burst, BL is the value from the Mode
Register. For an truncated burst, BL is the effective burst length.
See Table 51 on page 115 for Write to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Write to
Precharge timings for LPDDR2-S2.
5.9.3 LPDDR2-SX: Auto Precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge
command or the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the
AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment
during the burst read or write cycle.
If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed and
the bank remains active at the completion of the burst.
If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This feature
allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or
Write latency) thus improving system performance for random data access.
t
DQSSmax

CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 Tx Tx+1 Ty Ty+1
Figure 67 — LPDDR2-SX: Burst write followed by precharge: WL = 1, BL = 4
[Cmd]
Case 1: with t
DQSS
(max)
Case 2: with t
DQSS
(min)
DQs
DQS_c
SDRAM
t
WR
t
WR
>= t
RP
t
DQSSmin

WL = 1
WL = 1
Bank A
Precharge Nop Activate
Bank A
Row Addr Row Addr
Nop Nop Nop Nop Nop Write
Bank A
Col Addr Col Addr
Completion of Burst Write
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
DQS_t
JEDEC Standard No. 209-2E
Page 113
5.9.3.1 LPDDR2-SX: Burst Read with Auto-Precharge
If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged.
LPDDR2-S2 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 - 1 + RU(t
RTP
/t
CK
) clock
cycles later than the Read with AP command. Refer to Table 52 on page 116 for equations related to Auto-Precharge
for LPDDR2-S2.
LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 +
RU(t
RTP
/t
CK
) clock cycles later than the Read with AP command, whichever is greater. Refer to Table 51 on page 115
for equations related to Auto-Precharge for LPDDR2-S4.
A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied
simultaneously.
The RAS precharge time (t
RP
) has been satisfied from the clock at which the auto precharge begins.
The RAS cycle time (t
RC
) from the previous bank activation has been satisfied.

CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 68 — LPDDR2-S4: Burst read with Auto-Precharge:
RL = 3, BL = 4, RU(t
RTP
(min)/t
CK
) = 2
[Cmd]
>= t
RPpb

BL/2
t
RTP
SDRAM
Nop Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
CA0-9
DQs
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 69 — LPDDR2-S2: Burst read with Auto-Precharge:
RL = 3, BL = 4, RU(t
RTP
(min)/t
CK
) = 1
[Cmd]
>= t
RPpb

BL/2
t
RTP
SDRAM
Nop Nop Activate
Bank M
Row Addr
Read
Bank M
Col Addr A Col Addr A
Nop Nop Nop Nop
Row Addr
Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DQS_t
JEDEC Standard No. 209-2E
Page 114
5.9.3.2 LPDDR2-SX: Burst write with Auto-Precharge
If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The
LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is t
WR
cycles after the completion of
the burst write.
A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied.
The RAS precharge time (t
RP
) has been satisfied from the clock at which the auto precharge begins.
The RAS cycle time (t
RC
) from the previous bank activation has been satisfied.
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 70 — LPDDR2-SX: Burst write w/Auto Precharge: WL = 1, BL = 4
[Cmd]
SDRAM
t
WR
t
RPpb
WL = 1
Nop Activate
Bank A
Row Addr Row Addr
Nop Nop Nop Nop Nop Write
Bank A
Col Addr Col Addr
Nop
DIN A
0
DIN A
1
DIN A
2
DIN A
3
DQS_t
JEDEC Standard No. 209-2E
Page 115
5.9.3.2 LPDDR2-SX: Burst write with Auto-Precharge (cont’d)
Table 51 — LPDDR-S4: Precharge & Auto Precharge clarification
From
Command
To Command
Minimum Delay between
“From Command” to “To Command”
Unit Notes
Read
Precharge (to same Bank as Read)
BL/2 + max(2, RU(t
RTP
/t
CK
)) - 2 clks 1
Precharge All
BL/2 + max(2, RU(t
RTP
/t
CK
)) - 2 clks 1
BST
(for Reads)
Precharge (to same Bank as Read)
1 clks 1
Precharge All
1 clks 1
Read w/AP
Precharge (to same Bank as Read w/AP)
BL/2 + max(2, RU(t
RTP
/t
CK
)) - 2 clks 1,2
Precharge All
BL/2 + max(2, RU(t
RTP
/t
CK
)) - 2 clks 1
Activate (to same Bank as Read w/AP)
BL/2 + max(2, RU(t
RTP
/t
CK
)) - 2
+ RU(t
RPpb
/t
CK
)
clks 1
Write or Write w/AP (same bank)
Illegal clks 3
Write or Write w/AP (different bank)
RL + BL/2
+ RU(tDQSCKmax/tCK) - WL + 1
clks 3
Read or Read w/AP (same bank)
Illegal clks 3
Read or Read w/AP (different bank)
BL/2 clks 3
Write
Precharge (to same Bank as Write)
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
BST
(for Writes)
Precharge (to same Bank as Write)
WL + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + RU(t
WR
/t
CK
) + 1 clks 1
Write w/AP
Precharge (to same Bank as Write w/AP)
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Activate (to same Bank as Write w/AP)
WL + BL/2 + RU(t
WR
/t
CK
)
+ 1 + RU(t
RPpb
/t
CK
)
clks 1
Write or Write w/AP (same bank)
Illegal clks 3
Write or Write w/AP (different bank)
BL/2 clks 3
Read or Read w/AP (same bank)
Illegal clks 3
Read or Read w/AP (different bank)
WL + BL/2 + RU(t
WTR
/t
CK
) + 1 clks 3
Precharge
Precharge (to same Bank as Precharge)
1 clks 1
Precharge All
1 clks 1
Precharge All
Precharge
1 clks 1
Precharge All
1 clks 1
NOTE 1 For a given bank, the precharge period should be counted from the latest precharge command,
either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after
t
RP
depending on the latest precharge command issued to that bank.
NOTE 2 Any command issued during the minimum delay time as specified in Table 51 is illegal.
NOTE 3 After Read with AP, seamless read operations to different banks are supported. After Write with
AP, seamless write operations to different banks are supported. Read w/AP and Write w/AP may not be
interrupted or truncated.
JEDEC Standard No. 209-2E
Page 116
5.9.3.2 LPDDR2-SX: Burst write with Auto-Precharge (cont’d)
Table 52 — LPDDR-S2: Precharge & Auto Precharge clarification
From Com-
mand
To Command
Minimum Delay between “From
Command” to “To Command”
Unit Notes
Read
Precharge (to same Bank as Read)
BL/2 + RU(t
RTP
/t
CK
) - 1 clks 1
Precharge All
BL/2 + RU(t
RTP
/t
CK
) - 1 clks 1
BST
(for Reads)
Precharge (to same Bank as Read)
1 clks 1
Precharge All
1 clks 1
Read w/AP
Precharge (to same Bank as Read w/AP)
BL/2 + RU(t
RTP
/t
CK
) - 1 clks 1
Precharge All
BL/2 + RU(t
RTP
/t
CK
) - 1 clks 1
Activate (to same Bank as Read w/AP)
BL/2 + RU(t
RTP
/t
CK
) - 1
+ RU(t
RPpb
/t
CK
)
clks 1
Write or Write w/AP (same bank)
Illegal clks 3
Write or Write w/AP (different bank)
RL + BL/2
+ RU(tDQSCKmax/tCK) - WL + 1
clks 3
Read or Read w/AP (same bank)
Illegal clks 3
Read or Read w/AP (different bank)
BL/2 clks 3
Write
Precharge (to same Bank as Write)
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
BST
(for Writes)
Precharge (to same Bank as Write)
WL + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + RU(t
WR
/t
CK
) + 1 clks 1
Write w/AP
Precharge (to same Bank as Write w/AP)
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Precharge All
WL + BL/2 + RU(t
WR
/t
CK
) + 1 clks 1
Activate (to same Bank as Write w/AP)
WL + BL/2 + RU(t
WR
/t
CK
) + 1
+ RU(t
RPpb
/t
CK
)
clks 1
Write or Write w/AP (same bank)
Illegal clks 3
Write or Write w/AP (different bank)
BL/2 clks 3
Read or Read w/AP (same bank)
Illegal clks 3
Read or Read w/AP (different bank)
WL + BL/2 + RU(t
WTR
/t
CK
) + 1 clks 3
Precharge
Precharge (to same Bank as Precharge)
1 clks 1
Precharge All
1 clks 1
Precharge
All
Precharge
1 clks 1
Precharge All
1 clks 1
NOTE 1 For a given bank, the precharge period should be counted from the latest precharge com-
mand, either one bank precharge or precharge all, issued to that bank. The precharge period is sat-
isfied after t
RP
depending on the latest precharge command issued to that bank.
NOTE 2 Any command issued during the minimum delay time as specified in Table 52 is illegal.
NOTE 3 After Read with AP, seamless read operations to different banks are supported. After
Write with AP, seamless write operations to different banks are supported. Read w/AP and Write
w/AP may not be interrupted or truncated.
JEDEC Standard No. 209-2E
Page 117
5.10 LPDDR2-SX: Refresh command
The Refresh command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge
of clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is
initiated by having CA3 HIGH at the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks.
A Per Bank Refresh command, REFpb performs a refresh operation to the bank which is scheduled by the bank
counter in the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-1-
2-3-4-5-6-7-0-1-...”. The bank count is synchronized between the controller and the SDRAM upon issuing a RESET
command or at every exit from self refresh, by resetting bank count to zero. The bank addressing for the Per Bank
Refresh count is the same as established in the single-bank Precharge command (see Table 50 on page 109, “Bank
selection for Precharge by address bits”).
A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the bank being
refreshed by the Per Bank Refresh command.
As shown in Table 53 on page 118, the REFpb command may not be issued to the memory until the following
conditions are met:
a) t
RFCab
has been satisified after the prior REFab command
b) t
RFCpb
has been satisfied after the prior REFpb command
c) t
RP
has been satisified after the prior Precharge command to that given bank
t
RRD
has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a
different bank than affected by the REFpb command).
The target bank is inaccessable during the Per Bank Refresh cycle time (t
RFCpb
), however other banks within the
device are accessable and may be addressed during the Per Bank Refresh cycle. During the REFpb operation, any of
the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write
command.
When the Per Bank refresh cycle has completed, the affected bank will be in the Idle state.
As shown in Table 53 on page 118, after issuing REFpb:
a) t
RFCpb
must be satisified before issuing a REFab command
b) t
RFCpb
must be satisfied before issuing an ACTIVATE command to the same bank
c) t
RRD
must be satisified before issuing an ACTIVATE command to a different bank
d) t
RFCpb
must be satisified before issuing another REFpb command
An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state
when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count
between the controller and the SDRAM to zero.
As shown in Table 53 on page 118, the REFab command may not be issued to the memory until the following
conditions have been met:
a) t
RFCab
has been satisified after the prior REFab command
b) t
RFCpb
has been satisified after the prior REFpb command
c) t
RP
has been satisified after prior Precharge commands
When the All Bank refresh cycle has completed, all banks will be in the Idle state.
As shown in Table 53 on page 118, after issuing REFab:
a) the t
RFCab
latency must be satisfied before issuing an ACTIVATE command
b) the t
RFCab
latency must be satisfied before issuing a REFab or REFpb command.
JEDEC Standard No. 209-2E
Page 118
5.10 LPDDR2-SX: Refresh command (cont’d)
5.10.1 LPDDR2 SDRAM Refresh Requirements
(1) Minimum number of Refresh commands:
The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh
Window (t
REFW
= 32 ms @ MR4[2:0] = “011” or Tcase s 85 °C). See Table 101 on page 195 and Table 102 on
page 195 for actual numbers per density. The resulting average refresh interval (t
REFI
) is given in Table 102 on
page 195 and Table 101 on page 195.
See Mode Register 4 on page 38 for t
REFW
and t
REFI
refresh multipliers at different MR4 settings.
For LPDDR2-SDRAM devices supporting Per-Bank-Refresh, a REFab command may be replaced by a full cycle of
eight REFpb commands.
(2) Burst Refresh limitation:
To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling t
REFBW

(t
REFBW
= 4 x 8 x t
RFCab
). This condition does not apply if REFpb commands are used.
(3) Refresh Requirements and Self-Refresh:
If any time within a refresh window is spent in Self-Refresh Mode, the number of required Refresh commands in this
particular window is reduced to:
R* = R - RU{t
SRF
/ t
REFI
} = R - RU{R * t
SRF
/ t
REFW
}; where RU stands for the round-up function.
Table 53 — Command Scheduling Separations related to Refresh
Symbol minimum delay from to Notes
t
RFCab REFab
REFab
Activate cmd to any bank .
REFpb
t
RFCpb REFpb
REFab
Activate cmd to same bank as REFpb
REFpb
t
RRD
REFpb
Activate cmd to different bank than REFpb
Activate
REFpb affecting an idle bank (different bank than Activate) 1
Activate cmd to different bank than prior Activate
NOTE 1 A bank must be in the Idle state before it is refreshed. Therefore, after Activate,
REFab is not allowed and REFpb is allowed only if it affects a bank which is in the Idle state.
JEDEC Standard No. 209-2E
Page 119
5.10.1 LPDDR2 SDRAM Refresh Requirements (cont’d)
In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices, LPDDR2-SX devices allow
significant flexibiliy in scheduling REFRESH commends, as long as the boundary conditions above are met.
In the most straight forward case a REFRESH command should be scheduled every t
REFI
. In this case Self-Refresh
may be entered at any time.
The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are
required. In the extreme (e.g., LPDDR2-S4 1Gb) the user may choose to issue a refresh burst of 4096 REFRESH
commands with the maximum allowable rate (limited by t
REFBW
) followed by a long time without any REFRESH
commands, until the refresh window is complete, then repeating this sequence. The achieveable time without
REFRESH commands is given by t
REFW
- (R / 8) * t
REFBW
= t
REFW
- R * 4 * t
RFCab
. (e.g., for a LPDDR2-S4 1Gb
device @ Tcase <= 85°C this can be up to 32 ms - 4096 * 4 * 130 ns ~ 30 ms).
While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh interval,
if they are repeated in every subsequent 32 ms window, extreme care must be taken when transitioning from one
pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. Figure 73
on page 121 shows an example of an allowable transition from a burst pattern to a regular, distributed pattern. If this
transition happens directly after the burst refresh phase, all rolling t
REFW
intervalls will have at least the required
number of refreshes. Figure 74 on page 122 shows an example of a non-allowable transition. In this case the regular
refresh pattern starts after the completion of the pause-phase of the burst/pause refresh pattern. For several rolling
t
REFW
intervals the minimmun number of REFRESH commands is not satisfied. The understanding of the pattern
transition is extremly relevant (even if in normal operation only one pattern is employed), as in Self-Refresh-Mode a
regular, distributed refresh pattern has to be assumed, which is reflected in the equation for R* above. Therefore it is
recommended to enter Self-Refresh-Mode ONLY directly after the burst-phase of a burst/pause refresh pattern as
indicated in Figure 75 on page 122 and begin with the burst phase upon exit from Self-Refresh.
CKE
Figure 71 — LPDDR2-SX: Definition of t
SRF
Several examples on how to t
SRF
is calculated:
A: with the time spent in Self-Refresh Mode fully enclosed in the Refresh Window (t
REFW
),
B: at Self-Refresh entry
C: at Self-Refresh exit
D: with several different intervals spent in Self Refresh during one t
REFW
interval
Enter Self-Refresh
Exit Self-Refresh
SDRAM
t
SRF

t
REFW

CKE
t
SRF

t
REFW

Exit Self-Refresh
CKE
t
SRF

t
REFW

CKE
t
SRF2

t
REFW

t
SRF1

Enter Self-Refresh
Enter Self-Refresh
Exit Self-Refresh
Exit Self-Refresh
t
SRF
= t
SRF1
+ t
SRF2

A)
B)
C)
D)
JEDEC Standard No. 209-2E
Page 120
5.10.1 LPDDR2 SDRAM Refresh Requirements (cont’d)
Figure 72 — LPDDR2-SX: Regular, Distributed Refresh Pattern
vs. Repetitive Burst Refresh with Subsequent Refresh Pause
32 ms
t
REFI
t
REFI
t
REFBW
64 ms
t
REFBW
NOTE 1 For a (e.g.) LPDDR2-S4 1 Gb device @ Tcase less than or equal to 85C the distributed refresh pattern would have one
REFRESH command per 7.8 us; the burst refresh pattern would have an average of one refresh command per 0.52 us followed by
~30 ms without any REFRESH command.
4

0
9
6
4

0
9
7
8

1
9
2
8

1
9
3
4
,
0
9
6
1
2

2
8
8
1
2

2
8
9
1
6

3
8
4
8

1
9
2
1
2

2
8
8
96 ms 0 ms
JEDEC Standard No. 209-2E
Page 121
5.10.1 LPDDR2 SDRAM Refresh Requirements (cont’d)
Figure 73 — LPDDR2-SX: Allowable Transition from Repetitive Burst Refresh with Subsequent
Refresh Pause to Regular, Distributed Refresh Pattern
32 ms
t
REFI
t
REFI
t
REFBW
64 ms
t
REFBW
NOTE 1 For a (e.g.) LPDDR2-S4 1 Gb device @ Tcase less than or equal to 85 C the distributed refresh pattern would have one
REFRESH command per 7.8 us; the burst refresh pattern would have an average of one refresh command per 0.52 us followed by
~30 ms without any REFRESH command.
4

0
9
6
4

0
9
7
8

1
9
2
1
6

3
8
4
1
2

2
8
8
96 ms 0 ms
1
0

2
4
0
JEDEC Standard No. 209-2E
Page 122
5.10.1 LPDDR2 SDRAM Refresh Requirements (cont’d)


Figure 74 — LPDDR2-SX: NOT-Allowable Transition from Repetitive Burst Refresh with Subsequent
Refresh Pause to Regular, Distributed Refresh Pattern
32 ms
tREFI tREFI
tREFBW
64 ms
tREFBW
NOTE 1 Only ~2048 REFRESH commands (<R!!) in the indicated tREFW win-
4

0
9
6
4

0
9
7
8

1
9
2
8
.
1
9
3
1
2

2
8
8
96 ms 0 ms
1
0

2
4
0
tREFW = 32 ms

not enough Refresh commands
in this refresh window!!
Figure 75 — LPDDR2-SX: Recommended Self-refresh entry and exit in conjunction with a
Burst/Pause Refresh patterns.
32 ms
tREFBW tREFBW
4

0
9
6
4

0
9
7
8

1
9
2
0 ms
Self-Refresh
JEDEC Standard No. 209-2E
Page 123
5.10.1 LPDDR2 SDRAM Refresh Requirements (cont’d)
CA0-9
CK_t/CK_c
T0 T2 T1 T3 T4 Tx Tx+1 Ty Ty+1
Figure 76 — LPDDR2-SX: All Bank Refresh Operation
[Cmd]
SDRAM
AB
Precharge Nop Nop Nop Nop REFab REFab ANY
>= t
RPab
>= t
RFCab
>= t
RFCab
CA0-9
CK_t/CK_c
T0 Tx T1 Tx+1 Tx+2 Ty Ty+1 Tz Tz+1
Figure 77 — LPDDR2-SX: Per Bank Refresh Operation
[Cmd]
SDRAM
AB
Precharge Nop Nop REFpb REFpb ACT
>= t
RFCpb
>= t
RFCpb
>= t
RPab
Refresh to Bank 0
Refresh to Bank 1
NOTE 1 In the beginning of this example, the REFpb bank is pointing to Bank 0.
NOTE 2 Operations to other banks than the bank being refreshed are allowed during the t
RFCpb
period.
Activate command to Bank 1
Bank 1
Row A Row A
JEDEC Standard No. 209-2E
Page 124
5.11 LPDDR2-SX: Self Refresh operation
The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The
LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is
defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.
CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following
the power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self
Refresh mode.
LPDDR2-SX devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2-
SX devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low
temperatures and higher at high temperatures. See “LPDDR2 IDD Specification Parameters and Operating
Conditions” on page 186 for details.
Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.
For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ
may be turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ
and VrefCA may be at any level within minimum and maximum levels (see “Absolute Maximum DC Ratings” on
page 159). However prior to exiting Self-Refresh, VrefDQ and VrefCA must be within specified limits (see
“Recommended DC Operating Conditions” on page 160). The SDRAM initiates a minimum of one all-bank refresh
command internally within t
CKESR
period once it enters Self Refresh mode. The clock is internally disabled during
Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh
mode is t
CKESR
. The user may change the external clock frequency or halt the external clock one clock after Self
Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh
operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within
specified limits for a minimum of 2 tCK prior to the positive clock edge that registers CKE HIGH. Once Self Refresh
Exit is registered, a delay of at least t
XSR
must be satisfied before a valid command can be issued to the device to
allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period t
XSR
for
proper operation except for self refresh re-entry. NOP commands must be registered on each positive clock edge
during the Self Refresh exit interval t
XSR
.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when
CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh
command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.
JEDEC Standard No. 209-2E
Page 125
5.11 LPDDR2-SX: Self Refresh operation (cont’d)
For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements
outlined in section “LPDDR2 SDRAM Refresh Requirements” on page 118, since no refresh operations are
performed in power-down mode.
5.11.1 LPDDR2-S2: Partial Array Self-Refresh: Bank Masking
LPDDR2-S2 SDRAM keeps the same PASR mapping of LPDDR SDRAM (JESD209). The choice of partial array to
be refreshed in self refresh mode allows to reduce the range into lower numbered banks. MR16 has to be properly
programmed to choose the PASR range (See Mode Register 16 as described on page 41). The PASR range becomes
effective when the device goes into self refresh mode and determines which bank or banks to be refreshed.
Table 54 — Bank Masking in LPDDR2-S2 4-Bank devices (64mb-2Gb)
Table 55 — Bank Masking in LPDDR2-S2 8-Bank devices (4Gb-8Gb)
PASR
Choice
Bank 0 Bank 1 Bank 2 Bank 3
Full Array
1/2 Array No Self-Refresh
1/4 Array No Self-Refresh
PASR
Choice
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Full Array
1/2 Array No Self-Refresh
1/4 Array No Self-Refresh
1/8 Array No Self-Refresh
CKE
[CMD]
2 t
CK
(min)
CS_n
Figure 78 — LPDDR2-SX: Self-Refresh Operation
NOTE 1 Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a
minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency
for the particular speed grade.
NOTE 2 Device must be in the “All banks idle” state prior to entering Self Refresh mode.
NOTE 3 t
XSR
begins at the rising edge of the clock after CKE is driven HIGH.
NOTE 4 A valid command may be issued only after t
XSR
is satisfied. NOPs shall be issued during t
XSR
.
Enter SR NOP Valid
Enter Self-Refresh
t
CKESR(min)
Exit Self-Refresh
Exit SR NOP NOP Valid
t
ISCKE

t
XSR(min)
SDRAM
Input clock frequency may be changed
or stopped during Self-Refresh
t
IHCKE

t
IHCKE

t
ISCKE

CK_c
CK_t
JEDEC Standard No. 209-2E
Page 126
5.11.2 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking
LPDDR2-S4 SDRAM has 4 or 8 banks. For LPDDR2-S4 devices, 64Mb to 512Mb LPDDR2 SDRAM has 4 banks,
while 1Gb and higher density has 8. Each bank of LPDDR2 SDRAM can be independently configured whether a self
refresh operation is taking place. One mode register unit of 8 bits accessible via MRW command is assigned to
program the bank masking status of each bank up to 8 banks. For bank masking bit assignments, see Mode Register
16 as described on page 41.
The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via
MRW, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh
mode. To enable a refresh operation to a bank, a coupled mask bit has to be programmed, “unmasked”. When a bank
mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits, which is
decribed in the following chapter.
5.11.3 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking
Segment masking scheme may be used in lieu of or in combination with bank masking scheme in LPDDR2-S4
SDRAM. The number of segments differ by the density and the setting of each segment mask bit is applied across all
the banks. For segment masking bit assignments, see Mode Register 17 as described on page 41.
For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is
blocked when the mask bit to this segment is programmed, “masked”. Programming of segment mask bits is similar
to the one of bank mask bits. LPDDR2 SDRAM whose density is 64Mb, 128Mb, 256Mb, or 512Mb does not support
segment masking. Only bank masking scheme is available. For 1Gb and larger densities, 8 segments are used as listed
in Mode Register 17 as described on page 41. One mode register unit is used for the programming of segment mask
bits up to 8 bits. One more mode register unit may be reserved for future use. These 2 mode register units are noted as
“not used” for low-density LPDDR2-S4 SDRAM and a programming of mask bits has no effect on the device
operation.
NOTE 1 This table illustrates an example of an 8-bank LPDDR2-S4 device, when a refresh operation to bank 1
and bank 7, as well as segment 2 and segment 7 are masked.
Table 56 — Example of Bank and Segment Masking use in LPDDR2-S4 devices
Segment Mask
(MR17)
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask
(MR16)
0 1 0 0 0 0 0 1
Segment 0 0 M M
Segment 1 0 M M
Segment 2 1 M M M M M M M M
Segment 3 0 M M
Segment 4 0 M M
Segment 5 0 M M
Segment 6 0 M M
Segment 7 1 M M M M M M M M
JEDEC Standard No. 209-2E
Page 127
5.12 Mode Register Read Command
The Mode Register Read command is used to read configuration and status data from mode registers for both NVM
and SDRAM. The Mode Register Read (MRR) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-
CA4r}. The mode register contents are available on the first data beat of DQ0-DQ7, RL * t
CK
+ t
DQSCK
+ t
DQSQ
after
the rising edge of the clock where the Mode Register Read Command is issued. Subsequent data beats contain valid,
but undefined content, except in the case of the DQ Calibration function DQC, where subsequent data beats contain
valid content as described in “DQ Calibration” on page 130. All DQS_t, DQS_c shall be toggled for the duration of
the Mode Register Read burst. The MRR command has a burst length of four. The Mode Register Read operation
(consisting of the MRR command and the corresponding data traffic) shall not be interrupted. The MRR command
period (t
MRR
) is 2 clock cycles. Mode Register Reads to reserved and write-only registers shall return valid, but
undefined content on all data beats and DQS_t, DQS_c shall be toggled.
The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 +
BL/2 + RU( t
WTR
/t
CK
) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be
truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the
effective burst length of the truncated burst should be used as “BL.”
CA0-9
DQ[0-7]
CK_t / CK_c
RL = 3
DQS_t
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 79 — Mode Register Read timing example: RL = 3, t
MRR
= 2
[Cmd]
UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
NOTE 1 Mode Register Read has a burst length of four.
NOTE 2 Mode Register Read operation shall not be interrupted.
NOTE 3 Mode Register data is valid only on DQ[0-7] on the first beat. Subsequent beats contain valid,
but undefined data. DQ[8-max] contain valid, but undefined data for the duration of the MRR burst.
NOTE 4 The Mode Register Command period is t
MRR
. No command (other than Nop) is
allowed during this period.

t
MRR
= 2
DQ[8-max]
t
MRR
= 2
CMD not allowed
MRR
Reg A
MRR
Reg B Reg A Reg B
DOUT A UNDEF UNDEF UNDEF DOUT B UNDEF UNDEF UNDEF
UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
DQS_c
NOTE 5 Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in
the section on DQ Calibration.
NOTE 6 Minimum Mode Register Read to write latency is RL + RU(t
DQSCK
max/t
CK
) + 4/2 + 1 - WL clock
cycles.
NOTE 7 Minimum Mode Register Read to Mode Register Write latency is RL + RU(t
DQSCK
max/t
CK
) + 4/2 + 1
clock cycles.
JEDEC Standard No. 209-2E
Page 128
5.12 Mode Register Read Command (cont’d)
CA0-9
DQ[0-7]
CK_t / CK_c
RL = 3
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 80 — LPDDR2: Read to MRR timing example: RL = 3, t
MRR
= 2
[Cmd]

BL/2
DQ[8-max]
t
MRR
= 2
CMD not allowed
Read
Col Addr A
MRR
Reg B Col Addr A Reg B
BA M
DOUT B UNDEF UNDEF UNDEF
UNDEF UNDEF UNDEF UNDEF
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
NOTE 1: The minimum number of clocks from the burst read command to the Mode Register Read command is
BL/2.
NOTE 2: The Mode Register Read Command period is t
MRR
. No command (other than Nop) is allowed during this
period.
DQS_t
CA0-9
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 81 — LPDDR2: Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4
[Cmd]
NOTE 1 The minimum number of clock cycles from the burst write command to the Mode Register Read
command is [WL + 1 + BL/2 + RU( t
WTR
/t
CK
)].
NOTE 2 The Mode Register Read Command period is t
MRR
. No command (other than Nop) is allowed during
this period.
WL = 1
Write
BA N
Col Addr A Col Addr A
DIN A
0
DIN A
1
DIN A
2
DIN A
3
t
WTR
MRR
Reg B
RL = 3
CMD not allowed
t
MRR
= 2
Reg B
DQS_t
JEDEC Standard No. 209-2E
Page 129
5.12.1 Temperature Sensor
LPDDR2-SX and LPDDR2-N devices feature a temperature sensor whose status can be read from MR4. This sensor
can be used to determine an appropriate refresh rate (SDRAM), determine whether AC timing de-rating is required in
the Extended Temperature Range (SDRAM and NVM), and/or monitor the operating temperature (SDRAM and
NVM). Either the temperature sensor or the device TOPER ( See “Operating Temperature Range” on page 161) may
be used to determine whether operating temperature requirements are being met.
LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or
power-down, the device temperature status bits shall be no older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the TOPER specification (
See “Operating Temperature Range” on page 161) that applies for the Standard or Extended Temperature Ranges. For
example, TCASE may be above 85
o
C when MR4[2:0] equals 011B.
To assure proper operation using the temperature sensor, applications should consider the following factors:
TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of interest
over a range of 2
o
C.
ReadInterval is the time period between MR4 reads from the system.
TempSensorInterval (tTSI) is maximum delay between internal updates of MR4.
SysRespDelay is the maximum time between a read of MR4 and the response by the system.
LPDDR2 devices shall allow for a 2
o
C temperature margin between the point at which the device temperature enters
the Extended Temperature Range and point at which the controller re-configures the system accordingly.
In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and
the maximum response time of the system using the following equation:
For example, if TempGradient is 10
o
C/s and the SysRespDelay is 1 ms:
In this case, ReadInterval shall be no greater than 167 ms.
Table 57 — Temperature Sensor
Parameter Symbol Max/Min Value Unit Notes
System Temperature Gradient TempGradient Max System Dependent
o
C/s
MR4 Read Interval ReadInterval Max System Dependent ms
Temperature Sensor Interval tTSI Max 32 ms
System Response Delay SysRespDelay Max System Dependent ms
Device Temperature Margin TempMargin Max 2
o
C
TempGradient ReadInterval tTSI SysRespDelay + + ( ) × 2C s
10C
s
---------- ReadInterval 32ms 1ms + + ( ) × 2C s
JEDEC Standard No. 209-2E
Page 130
5.12.1 Temperature Sensor (cont’d)
5.12.2 DQ Calibration
LPDDR2-SX and LPDDR2-N devices feature a DQ Calibration function that outputs one of two predefined system
timing calibration patterns. A Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the
specified pattern on DQ[0] for x8 devices, DQ[0] and DQ[8] for x16 devices, and DQ[0], DQ[8], DQ[16], and
DQ[24] for x32 devices. For x8 devices, DQ[7:1] may optionally drive the same information as DQ[0] or may drive
0b during the MRR burst. For x16 devices, DQ[7:1] and DQ[15:9] may optionally drive the same information as
DQ[0] or may drive 0b during the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may
optionally drive the same information as DQ[0] or may drive 0b during the MRR burst.
For LPDDR2-SX devices, MRR DQ Calibration commands may only occur in the Idle state.
Table 58 — Data Calibration Pattern Description
Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3
Pattern “A” (MR32) 1 0 1 0
Pattern “B” (MR40) 0 0 1 1
Figure 82 — Temp Sensor Timing
Temp
2
o
C
tTSI
ReadInterval
< (tTSI + ReadInterval + SysRespDelay)
SysRespDelay
MR4 = 0x03 MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x06
MRR MR4 = 0x03 MRR MR4 = 0x86
MR4
Time
T
e
m
p
G
ra
d
ie
n
t
Trip Level
Temperature
Sensor
Update
Host
MR4 Read
Device
Temp
Margin
JEDEC Standard No. 209-2E
Page 131
5.12.2 DQ Calibration (cont’d)
CA0-9
DQ[0]
CK_t / CK_c
RL = 3
DQS_t
T0 T2 T1 T3 T4 T5 T6 T7 T8
Figure 83 — MR32 and MR40 DQ Calibration timing example: RL = 3, t
MRR
= 2
[Cmd]
UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
NOTE 1 Mode Register Read has a burst length of four.
NOTE 2 Mode Register Read operation shall not be interrupted.
NOTE 3 Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x16
devices, DQ[8] shall drive the same information as DQ[0] during the burst. For x32 devices, DQ[8], DQ[16], and
NOTE 5 The Mode Register Command period is t
MRR
. No command (other than Nop) is allowed during this period
t
MRR
= 2
DQ[7:1]
t
MRR
= 2
CMD not allowed
MRR32
Reg 32
MRR40
Reg 40 Reg 32 Reg 40
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
DQS_c
Optionally driven the same as DQ0 or to 0b
DQ[8] UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
DQ[15:9]
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
DQ[16] UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
DQ[23:17]
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
DQ[24] UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF
DQ[31:25]
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
x16
x32
NOTE 4 For x8 devices, DQ[7:1] may optionally drive the same information as DQ[0] or they may drive 0b
during the burst. For x16 devices, DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0]
or they may drive 0b during the burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may
optionally drive the same information as DQ[0] or they may drive 0b during the burst.
DQ[24] shall drive the same information as DQ[0] during the burst.
Pattern ”A” Pattern ”B”
x8
JEDEC Standard No. 209-2E
Page 132
5.13 Mode Register Write Command
The Mode Register Write command is used to write configuration data to mode registers for both NVM and SDRAM.
The Mode Register Write (MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW,
and CA3 LOW at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data
to be written to the mode register is contained in CA9f-CA2f. The MRW command period is defined by t
MRW
. Mode
Register Writes to read-only registers shall have no impact on the functionality of the device.
5.13.1 LPDDR2-SX: Mode Register Write
For LPDDR2-S devices, the MRW may only be issued when all banks are in the idle precharge state. One method of
ensuring that the banks are in the idle precharge state is to issue a Precharge-All command.
5.13.2 LPDDR2-N: Mode Register Write
For LPDDR2-N devices, the MRW may be issued from the Row Active or Idle states. If the MRW command is
issued from the Row Active state, all row buffer contents are invalidated and the device returns to the Idle state.
The minimum time from the burst read command to the MRW command is defined by the Read Latency (RL) and the
Burst Length (BL). Minimum Read to MRW latency is RL + RU(t
DQSCK
max/t
CK
) + BL/2 clock cycles. The
minimum time from the burst write command to the MRW command is defined by the Write Latency (WL) and the
Burst Length (BL). Minimum Write to MRW latency is WL + 1 + BL/2 + RU(t
WTR
/t
CK
) clock cycles. Note that if a
read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated
burst should be used as “BL.”
CA0-9
CK_t / CK_c
T0 T2 T1 Tx Tx + 1 Tx + 2 Ty Ty + 1 Ty + 2
Figure 84 — Mode Register Write timing example: RL = 3, t
MRW
= 5
[Cmd]
NOTE 1 The Mode Register Write Command period is t
MRW
. No command (other than Nop)
is allowed during this period.
CMD not allowed
t
MRW

t
MRW
MRW
MR Addr MR Data
MRW
MR Addr MR Data
ANY
NOTE 2 At time Ty, the device is in the idle state.
JEDEC Standard No. 209-2E
Page 133
5.13.2 LPDDR2-N: Mode Register Write (cont’d)
CA0-9
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 Tx
Figure 85 — LPDDR2-N: Burst Write Followed by MRW: WL = 1, BL = 4
[Cmd]
NVM
NOTE 1 The minimum number of clock cycles from the burst write command to the Mode Register Write command is [WL
+ 1 + BL/2 + RU( t
WTR
/t
CK
)].
NOTE 2 The Mode Register Write Command period is t
MRW
. No command (other than Nop) is allowed during this period.
WL = 1
Write
RDB M
Col Addr A Col Addr A
DIN A
0
DIN A
1
DIN A
2
DIN A
3
MRW
MR Addr MR Data
t
WTR
t
MRW

DQS_t
CMD not allowed
CA0-9
DQs
CK_t / CK_c
DQS_c
T0 T2 T1 T3 T4 T5 T6 T7 Tx
Figure 86 — LPDDR2-N: Burst Read followed by MRW: RL = 3, BL = 4
[Cmd]
t
DQSCK
RL = 3
BL/2
NVM
Nop Read
RDB A
Col Addr Col Addr
Nop Nop Nop Nop
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
MRW
MR Addr MR Data
NOTE 1 The minimum number of clock cycles from the burst read command to the Mode Register Write command is [RL +
RU( t
DQSCK
/t
CK
) + BL/2].
NOTE 2 The Mode Register Write Command period is t
MRW
. No command (other than Nop) is allowed during this period.
t
MRW
DQS_t
CMD not allowed
JEDEC Standard No. 209-2E
Page 134
5.13.2 LPDDR2-N: Mode Register Write (cont’d)
5.13.3 Mode Register Write Reset (MRW Reset)
Any MRW command issued to MRW63 initiates an MRW Reset. The MRW Reset command brings the device to the
Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence (step 3 in section 3.4.1). The
MRW Reset command may be issued from the Idle state for LPDDR2-SX devices and the Idle or Active states for
LPDDR2-N devices. This command resets all Mode Registers to their default values. In addition, for LPDDR2-N
devices, this command ends all embedded operations and resets all Overlay Window registers to their default values.
No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (t
INIT4
). After
MRW Reset, boot timings must be observed until the device initialization sequence is complete and the device is in
the Idle state. Array data for LPDDR2-SX devices are undefined after the MRW Reset command.
For the timing diagram related to MRW Reset, refer to Figure 6 on page 30.
Table 59 — Truth Table for Mode Register Read (MRR)
and Mode Register Write (MRW)
Current State
Command
Intermediate State
Next State
SDRAM NVM SDRAM NVM
SDRAM NVM
All Banks Idle All RBs idle
MRR
Mode Register Reading
(All Banks Idle)
Mode Register Reading
(All RBs Idle)
All Banks Idle All RBs Idle
MRW
Mode Register Writing
(All Banks Idle)
Mode Register Writing
(All RBs Idle)
All Banks Idle All RBs Idle
MRW (RESET)
Resetting
(Device Auto-Init)
Device Auto-Init
(Resetting)
All Banks Idle All RBs Idle
Bank(s) Active RB(s) Active
MRR
Mode Register Reading
(Bank(s) Active)
Mode Register Reading
(RB(s) Active)
Bank(s) Active RB(s) Active
MRW Not Allowed
Mode Register Writing
(RB(s) Active)
Not Allowed All RBs Idle
MRW (RESET) Not Allowed
Device Auto-Init
(Resetting)
Not Allowed All RBs Idle
JEDEC Standard No. 209-2E
Page 135
5.13.4 Mode Register Write ZQ Calibration Command
The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to
calibrate the LPDDR2 ouput drivers (RON) over process, temperature, and voltage. LPDDR2-S2 devices do not
support ZQ Calibration and the ZQ Calibration command shall be ignored by these devices. LPDDR2-S4 and
LPDDR2-N devices support ZQ Calibration.
There are four ZQ Calibration commands and related timings, tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT
corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long
calibration, and tZQCS is for short calibration. See Mode Register 10 on page 40 for description on the command
codes for the different ZQ Calibration commands.
The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 and LPDDR2-N devices. This
Initialization Calibration achieves a RON accuracy of +/-15%. After initialization, the ZQ Long Calibration may be
used to re-calibrate the system to a RON accuracy of +/-15%. A ZQ Short Calibration may be used periodically to
compensate for temperature and voltage drift in the system.
The ZQReset Command resets the RON calibration to a default accuracy of +/-30% across process, voltage, and
temperature. This command is used to ensure RON accuracy to +/-30% when ZQCS and ZQCL are not used.
One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within
tZQCS for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and
Temperature Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables
and other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by
the following formula:
where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage
sensitivities.
For example, if TSens = 0.75% /
o
C, VSens = 0.20% / mV, Tdriftrate = 1
o
C / sec and
Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:
For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all
banks precharged. For LPDDR2-N devices, a ZQ Calibration command may only be issued when the device is in the
Idle or Active states.
No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL,
tZQCS). The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time
after the ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at
any given time. After calibration is achieved, the LPDDR2 device shall disable the ZQ ball’s current consumption
path to reduce power.
In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or
tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be
connected permanently to VDDCA. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the
device will use the default calibration settings ( See “Output Driver DC Electrical Characteristics without ZQ
Calibration” on page 179)
ZQCorrection
TSens Tdriftrate × ( ) VSens Vdriftrate × ( ) +
-----------------------------------------------------------------------------------------------------------------
1.5
0.75 1 × ( ) 0.20 15 × ( ) +
---------------------------------------------------------- 0.4s =
JEDEC Standard No. 209-2E
Page 136
5.13.4 Mode Register Write ZQ Calibration Command (cont’d)
CA0-9
CK_t / CK_c
T0 T2 T1 T3 T4 T5 Tx Tx + 1 Tx + 2
Figure 87 — ZQ Calibration Initialization timing example
[Cmd]
NOTE 1: The ZQ Calibration Initialization period is t
ZQINIT
. No command (other than Nop)
NOTE 2: CKE must be continuously registered HIGH during the calibration period.
CMD not allowed
t
ZQINIT

MRW
MR Addr MR Data
ANY
NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process.
is allowed during this period.
CA0-9
CK_t / CK_c
T0 T2 T1 T3 T4 T5 Tx Tx + 1 Tx + 2
Figure 88 — ZQ Calibration Short timing example
[Cmd]
NOTE 1: The ZQ Calibration Short period is t
ZQCS
. No command (other than Nop) is allowed during this period.
NOTE 2: CKE must be continuously registered HIGH during the calibration period.
CMD not allowed
t
ZQCS

MRW
MR Addr MR Data
ANY
NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process.
CA0-9
CK_t / CK_c
T0 T2 T1 T3 T4 T5 Tx Tx + 1 Tx + 2
Figure 89 — ZQ Calibration Long timing example
[Cmd]
NOTE 1 The ZQ Calibration Long period is t
ZQCL
. No command (other than Nop) is allowed during this period.
NOTE 2 CKE must be continuously registered HIGH during the calibration period.
CMD not allowed
t
ZQCL

MRW
MR Addr MR Data
ANY
NOTE 3 All devices connected to the DQ bus should be high impedance during the calibration process.
JEDEC Standard No. 209-2E
Page 137
5.13.4 Mode Register Write ZQ Calibration Command (cont’d)
5.13.4.1 ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ Calibration function, a 240 Ohm +/- 1% tolerance external resistor must be connected between the ZQ
pin and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between multiple
LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive loading
on the ZQ pin must be limited ( See “Input/output capacitance” on page 182).
CA0-9
CK_t / CK_c
T0 T2 T1 T3 T4 T5 Tx Tx + 1 Tx + 2
Figure 90 — ZQ Calibration Reset timing example
[Cmd]
NOTE 1 The ZQ Calibration Reset period is t
ZQRESET
. No command (other than Nop) is allowed during this peri
NOTE 2 CKE must be continuously registered HIGH during the calibration period.
CMD not allowed
t
ZQRESET

MRW
MR Addr MR Data
ANY
NOTE 3 All devices connected to the DQ bus should be high impedance during the calibration process.
JEDEC Standard No. 209-2E
Page 138
5.14 Power-down
For LPDDR2 SDRAM, power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the
rising edge of clock. For LPDDR2 NVM, power-down is synchronously entered when CKE is registered LOW at the
rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP command must be driven in
the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or
write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation,
preactive, precharge, autoprecharge, or refresh is in progress, but power-down IDD spec will not be applied until
finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down.
For LPDDR2 SDRAM, if power-down occurs when all banks are idle, this mode is referred to as idle power-down; if
power-down occurs when there is a row active in any bank, this mode is referred to as active power-down.
For LPDDR2 NVM, if power-down occurs when all row buffers are idle, this mode is referred to as idle power-down;
if power-down occurs when any row buffer is in the active state, this mode is referred to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down
mode, CKE must be maintained LOW while all other input signals are “Don’t Care”. CKE LOW must be maintained
until t
CKE
has been satisfied. V
REF
must be maintained at a valid level during power down.
VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to
exiting power down, both VDDQ and VREFDQ must be within their respective min/max operating ranges ( See
“Recommended DC Operating Conditions” on page 160).
For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements
outlined in section “LPDDR2 SDRAM Refresh Requirements” on page 118, as no refresh operations are performed
in power-down mode.
The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction
with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until t
CKE
has been satisfied. A
valid, executable command can be applied with power-down exit latency, t
XP
after CKE goes HIGH. Power-down
exit latency is defined in the timing parameter table of this standard.
CKE
[CMD]
2 t
CK
(min)
CS_n
Figure 91 — LPDDR2-SX: Basic power down entry and exit timing diagram
NOTE 1 Input clock frequency may be changed or the input clock stopped during power-down, provided that
upon exiting power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to
power-down exit and the clock frequency is between the minimum and maximum frequency for the particular
speed grade.
Enter PD NOP Valid
Enter Power-Down mode
t
CKE(min)
Exit Power-Down mode
Exit PD Valid
t
ISCKE

t
XP(min)
t
CKE(min)
SDRAM
Input clock frequency may be changed
or the input clock stopped during Power-Down
t
IHCKE

t
IHCKE

t
ISCKE

Valid NOP
CK_c
CK_t
JEDEC Standard No. 209-2E
Page 139
5.14 Power-down (cont’d)
CKE
[CMD]
2 t
CK
(min)
CS_n
Figure 92 — LPDDR2-N: Basic power down entry and exit timing diagram
NOTE 1 Input clock frequency may be changed or the input clock stopped during power-down, provided that
upon exiting power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to
power-down exit and the clock frequency is between the minimum and maximum frequency for the particular
speed grade.
NOTE 2 CS_n is “do not care” for entry into power-down for NVM.
Enter PD NOP Valid
Enter Power-Down mode
t
CKE(min)
Exit Power-Down mode
Exit PD NOP Valid Valid
t
ISCKE

t
XP(min)
t
CKE(min)
NVM
Input clock frequency may be changed
or the input clock stopped during Power-Down
t
IHCKE

t
IHCKE

t
ISCKE

CK_c
CK_t
CK_t
CKE
CK_c
t
CKE
t
CKE
t
CKE
t
CKE
Figure 93 — Example of CKE intensive environment
CK_t
[CMD]
CK_c
CKE
t
CKE
t
REFI

NOTE 1 The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM
guarantees all AC and DC timing & voltage specifications with temperature and voltage drift
Figure 94 — REF to REF timing with CKE intensive environment for LPDDR2 SDRAM
t
XP
t
CKE
t
XP
t
CKE
t
CKE
REF REF
SDRAM
JEDEC Standard No. 209-2E
Page 140
5.14 Power-down (cont’d)
CK_t
[CMD]
CKE
DQ
DQS_t
[CMD]
CKE
DQ
DQS_t
CK_c
RL
CKE should be kept HIGH until the end of burst operation.
RL
Q Q Q Q
Q Q Q Q Q Q Q Q
CKE should be kept HIGH until the end of burst operation.
RD
Read operation starts with a read command and
T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 T1 T2 Tx+1 Tx+7 Tx+8 Tx+9
T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 T1 T2 Tx+1 Tx+7 Tx+8 Tx+9
DQS_c
DQS_c
t
ISCKE
Figure 95 — Read to power-down entry
RD
NOTE 1 CKE may be registered LOW RL + RU(t
DQSCK(MAX)
/t
CK
) + BL/2 + 1 clock cycles after the clock on
which the Read command is registered.
t
ISCKE
[CMD]
CKE
DQ
DQS_t
[CMD]
CKE
DQ
DQS_t
BL=8
BL/2
with t
RTP
= 7.5 ns
& t
RAS
min satisfied
BL/2
with t
RTP
= 7.5 ns
& t
RAS
min satisfied
CK_t
CK_c
Start internal precharge
RL
BL=4
CKE should be kept HIGH
CKE should be kept HIGH
until the end of burst operation.
RL
T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 T1 T2 Tx+1 Tx+7 Tx+8 Tx+9
until the end of burst operation.
Q Q Q Q Q Q Q Q
Q Q Q Q
T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 T1 T2 Tx+1 Tx+7 Tx+8 Tx+9
DQS_c
DQS_c
t
ISCKE
t
ISCKE
Figure 96 — LPDDR2 SDRAM Read with autoprecharge to power-down entry
RDA PRE
RDA PRE
Start internal precharge
NOTE 1 CKE may be registered LOW RL + RU(t
DQSCK(MAX)
/t
CK
)+ BL/2 + 1 clock cycles after the clock on
which the Read command is registered.
SDRAM
JEDEC Standard No. 209-2E
Page 141
5.14 Power-down (cont’d)
[CMD]
CKE
DQ
DQS_t
[CMD]
CKE
DQ
DQS_t
T0 Tm+1 Tm+3 Tx Tx+1 Tx+2 Tx+3 T1 Tm Tm+2 Tx+4 Tx+5 Tx+6
BL=8
D D D D
D D D D D D D D
t
WR
t
WR
CK_t
CK_c
WL
BL=4
WL
T0 Tm+1 Tm+3 Tm+4 Tm+5 Tx Tx+1 T1 Tm Tm+2 Tx+2 Tx+3 Tx+4
DQS_c
DQS_c
t
ISCKE
t
ISCKE
Figure 97 — Write to power-down entry
WR
WR
NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(t
WR
/t
CK
) clock cycles after the clock on which the
Write command is registered.
SDRAM
[CMD]
CKE
DQ
DQS_c
[CMD]
CKE
DQ
DQS_c
T0 Tm+1 Tm+3 Tx Tx+1 Tx+2 Tx+3 T1 Tm Tm+2 Tx+4 Tx+5 Tx+6
BL=8
D D D D
D D D D D D D D
t
WRA
t
WRA
CK_t
CK_c
WL
BL=4
WL
T0 Tm+1 Tm+3 Tm+4 Tm+5 Tx Tx+1 T1 Tm Tm+2 Tx+2 Tx+3 Tx+4
DQS_t
DQS_t
t
ISCKE
t
ISCKE
Figure 98 — Write to power-down entry
WR
WR
NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(t
WRA
/t
CK
) clock cycles after the clock on which the
Write command is registered.
NVM
JEDEC Standard No. 209-2E
Page 142
5.14 Power-down (cont’d)
[CMD]
CKE
DQ
DQS_t
[CMD]
CKE
DQ
DQS_t
T0 Tm+1 Tm+3 Tx Tx+1 Tx+2 Tx+3 T1 Tm Tm+2 Tx+4 Tx+5 Tx+6
BL=8
t
WR
D D D D
D D D D D D D D
t
WR
CK_t
CK_c
BL=4
WL
WL
T0 Tm+1 Tm+3 Tm+4 Tm+5 Tx Tx+1 T1 Tm Tm+2 Tx+2 Tx+3 Tx+4
CK_t
CK_c
DQS_c
DQS_c
t
ISCKE
t
ISCKE
Figure 99 — LPDDR2-SX: Write with autoprecharge to power-down entry
Start Internal Precharge
WRA PRE
Start Internal Precharge
PRE WRA
SDRAM
NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(t
WR
/t
CK
) + 1 clock cycles after the Write command is
registered.
[CMD]
CKE
T0 T3 T5 T6 T7 T8 T9 T1 T2 T4 T10
CK_t
CK_c
T11
t
ISCKE
Figure 100 — LPDDR2-SX: Refresh command to power-down entry
REF
SDRAM
t
IHCKE
NOTE 1 CKE may go LOW t
IHCKE
after the clock on which the Refresh command is registered.
JEDEC Standard No. 209-2E
Page 143
5.14 Power-down (cont’d)
[CMD]
CKE
T0 T3 T5 T6 T7 T8 T9 T1 T2 T4 T10 T11
t
ISCKE
Figure 101 — Activate command to power-down entry
ACT
CK_t
CK_c
t
IHCKE
NOTE 1 CKE may go LOW t
IHCKE
after the clock on which the Activate command is registered.
T0 T3 T5 T6 T7 T8 T9 T1 T2 T4 T10
[CMD]
CKE
T11
t
ISCKE
Figure 102 — Preactive/Precharge/Precharge-all command to power-down entry
PRE
CK_t
CK_c
t
IHCKE
NOTE 1 CKE may go LOW t
IHCKE
after the clock on which the Preactive/Precharge/Precharge-All command is
registered.
CK_t
[CMD]
CKE
DQ
DQS_t
CK_c
CKE should be kept HIGH until the end of burst operation.
RL
Q Q Q Q
MRR
Mode Register Read operation starts with a MRR command and
T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 T1 T2 Tx+1 Tx+7 Tx+8 Tx+9
DQS_c
t
ISCKE
Figure 103 — Mode Register Read to power-down entry
NOTE 1 CKE may be registered LOW RL + RU(t
DQSCK(MAX)
/t
CK
) + 4/2 + 1 clock cycles after the clock on which
the Mode Register Read command is registered.
JEDEC Standard No. 209-2E
Page 144
5.14 Power-down (cont’d)
T0 T3 T5 T6 T7 T8 T9 T1 T2 T4 T10
[CMD]
CKE
T11
t
ISCKE
Figure 104 — MRW command to power-down entry
MRW
CKE can go to LOW t
MRW
after a Mode Register Write command
CK_t
CK_c
NOTE 1 CKE may be registered LOW t
MRW
after the clock on which the Mode Register Write command is
t
MRW
JEDEC Standard No. 209-2E
Page 145
5.15 LPDDR2-SX: Deep Power-Down
Deep Power-Down is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2
LOW at the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down
command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress.
All banks must be in idle state with no activity on the data bus prior to entering the Deep Power Down mode. During
Deep Power-Down, CKE must be held LOW.
In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal
circuitry may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting
Deep Power-Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (see “Absolute
Maximum DC Ratings” on page 159). However prior to exiting Deep Power-Down, Vref must be within specified
limits ( See “Recommended DC Operating Conditions” on page 160).
The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.
The Deep Power-Down state is exited when CKE is registered HIGH, while meeting t
ISCKE
with a stable clock input.
The SDRAM must be fully re-initialized as described in the Power up initialization Sequence. The SDRAM is ready
for normal operation after the initialization sequence.
CK_c
CKE
[CMD]
t
ISCKE

t
INIT3
= 200 us (min)
2 t
CK
(min)
Tc
CS_n
Figure 105 — LPDDR2-SX: Deep power down entry and exit timing diagram
NOTE 1 Initialization sequence may start at any time after Tc.
NOTE 2 t
INIT3
, and Tc refer to timings in the LPDDR2 initialization sequence. For more detail, see “Power-up,
Initialization, and Power-Off” on page 28.
NOTE 3 Input clock frequency may be changed or the input clock stopped during deep power-down, provided
that upon exiting deep power-down, the clock is stable and within specified limits for a minimum of 2 clock cycles
prior to deep power-down exit and the clock frequency is between the minimum and maximum frequency for the
particular speed grade.
Enter
Nop RESET
t
IHCKE

Enter Deep Power-Down mode
t
DPD
Exit Deep Power-Down mode
DPD
SDRAM
t
ISCKE

Input clock frequency may be changed
or the input clock stopped during Deep Power-Down
Exit PD NOP
CK_t
NOP
t
RP
JEDEC Standard No. 209-2E
Page 146
5.16 Input clock stop and frequency change
LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh Requirements apply during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• Any Activate, Preactive, or Precharge commands have executed to completion prior to changing the frequency;
• The related timing conditions (t
RCD
, t
RP
) have been met prior to changing the frequency;
• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;
• The clock satisfies t
CH(abs)
and t
CL(abs)
for a minimum of 2 clock cycles prior to CKE going HIGH.
After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to
set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock
frequency.
LPDDR2 devices support clock stop during CKE LOW under the following conditions:
• CK_t is held LOW and CK_c is held HIGH during clock stop;
• Refresh Requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate, Preactive, or Precharge commands have executed to completion prior to stopping the clock;
• The related timing conditions (t
RCD
, t
RP
) have been met prior to stopping the clock;
• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;
• The clock satisfies t
CH(abs)
and t
CL(abs)
for a minimum of 2 clock cycles prior to CKE going HIGH.
LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:
• tCK(abs)min is met for each clock cycle;
• Refresh Requirements apply during clock frequency change;
• Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must
have executed to completion, including any associated data bursts prior to changing the frequency;
• The related timing conditions (t
RCD
, t
WR
, t
WRA
, t
RP
, t
MRW
, t
MRR
, etc.) have been met prior to changing the
frequency;
• CS_n shall be held HIGH during clock frequency change;
• During clock frequency change, only REFab or REFpb commands may be executing;
• The LPDDR2 device is ready for normal operation after the clock satisfies t
CH(abs)
and t
CL(abs)
for a minimum of
2tCK + tXP.
After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.
These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.
LPDDR2 devices support clock stop during CKE HIGH under the following conditions:
• CK_t is held LOW and CK_c is held HIGH during clock stop;
• CS_n shall be held HIGH during clock clock stop;
• Refresh Requirements apply during clock stop;
• During clock stop, only REFab or REFpb commands may be executing;
• Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must
have executed to completion, including any associated data bursts prior to stopping the clock;
• The related timing conditions (t
RCD
, t
WR
, t
WRA
, t
RP
, t
MRW
, t
MRR
, etc.) have been met prior to stopping the clock;
• The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies t
CH(abs)
and t
CL(abs)
for a minimum of 2tCK + tXP.
JEDEC Standard No. 209-2E
Page 147
5.17 No Operation command
The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted
command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP
command may be issued at clock cycle N. A NOP command has two possible encodings:
1. CS_n HIGH at the clock rising edge N.
2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.
The No Operation command will not terminate a previous operation that is still executing, such as a burst read or
write cycle.
5.18 Truth tables
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the
LPDDR2 device must be powered down and then restarted through the specified initialization sequence before
normal operation can continue.
JEDEC Standard No. 209-2E
Page 148
5.18.1 Command Truth Table
Table 60 — Command Truth Table
SDR Command Pins DDR CA pins (10)
SDRAM
Command
NVM
Command
CKE
CS_N CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
CK_t
EDGE
CK_t(n-1) CK_t(n)
MRW MRW H H
L L L L L MA0 MA1 MA2 MA3 MA4 MA5
X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
MRR MRR H H
L L L L H MA0 MA1 MA2 MA3 MA4 MA5
X MA6 MA7 X
Refresh
(per bank)
11
- H H
L L L H L X
X X
Refresh
(all bank)
- H H
L L L H H X
X X
Enter
Self Refresh
Enter
Power Down
H
L
L L L H X
X X X
Activate
(bank)
Activate
(row buffer)
H H
L L H R8/a15 R9/a16 R10/a17 R11/a18 R12/a19 BA0 BA1 BA2
X R0/a5 R1/a6 R2/a7 R3/a8 R4/a9 R5/a10 R6/a11 R7/a12 R13/a13 R14/a14
Write
(bank)
Write
(RDB)
H H
L H L L RFU RFU C1 C2 BA0 BA1 BA2
X AP
3,4
C3 C4 C5 C6 C7 C8 C9 C10 C11
Read
(bank)
Read
(RDB)
H H
L H L H RFU RFU C1 C2 BA0 BA1 BA2
X AP
3,4
C3 C4 C5 C6 C7 C8 C9 C10 C11
Precharge
(pre bank,
all bank)
Preactive
(RAB)
H H
L H H L H AB/a30 X/a31 X/a32 BA0 BA1 BA2
X X/a20 X/a21 X/a22 X/a23 X/a24 X/a25 X/a26 X/a27 X/a28 X/a29
BST BST H H
L H H L L X
X X
Enter
Deep Power Down
Enter
Power Down
H
L
L H H L X
X X X
NOP NOP H H
L H H H X
X X
Maintain
PD, SREF, DPD
(NOP)
Maintain
Power Down
(NOP)
L L
L H H H X
X X
NOP NOP H H
H X
X X
Maintain
PD, SREF, DPD
(NOP)
Maintain
Power Down
(NOP)
L L
H X
X X
Enter
Power Down
Enter
Power Down
H
L
H X
X X X
Exit
PD, SREF, DPD
Exit
Power Down
L
H
H X
X X X
JEDEC Standard No. 209-2E
Page 149
5.18.1 Command Truth Table (cont’d)
Notes to Table 60
NOTE 1 All LPDDR2 commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising
edge of the clock.
NOTE 2 For LPDDR2 SDRAM, Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be oper-
ated upon. For LPDDR2 NVM, BA0, BA1, BA2 determine a row buffer.
NOTE 3 AP is significant only to SDRAM. AP is do-not-care for NVM.
NOTE 4 AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the
bank associated with the READ or WRITE command.
NOTE 5 “X” means “H or L (but a defined logic level)”
NOTE 6 Self refresh exit and Deep Power Down exit are asynchronous.
NOTE 7 VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation.
NOTE 8 CAxr refers to command/address bit “x” on the rising edge of clock.
NOTE 9 CAxf refers to command/address bit “x” on the falling edge of clock.
NOTE 10 CS_n and CKE are sampled at the rising edge of clock.
NOTE 11 Per Bank Refresh is only allowed in devices with 8 banks.
NOTE 12 The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.
NOTE 13 AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank
Address is do-not-care.
JEDEC Standard No. 209-2E
Page 150
5.19 LPDDR2-SDRAM Truth Tables
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
applied restrictions when considering the actual state of all the Banks.
NOTE 1 “CKE
n
” is the logic state of CKE at clock rising edge n; “CKE
n-1
” was the state of CKE at the previous clock edge.
NOTE 2 “CS_n” is the logic state of CS_n at the clock rising edge n;
NOTE 3 “Current state” is the state of the LPDDR2 device immediately prior to clock edge n.
NOTE 4 “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.
NOTE 5 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
NOTE 6 Power Down exit time (t
XP
) should elapse before a command other than NOP is issued.
NOTE 7 Self-Refresh exit time (t
XSR
) should elapse before a command other than NOP is issued.
NOTE 8 The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Func-
tional Description.
NOTE 9 The clock must toggle at least twice during the t
XP
period.
NOTE 10 The clock must toggle at least twice during the t
XSR
time.
NOTE 11 'X’ means ‘Don’t care’.
NOTE 12 Upon exiting Resetting Power Down, the device will return to the Idle state if tINIT5 has expired.
Table 61 — LPDDR2-SX: CKE Table
Device Current State
*3
CKE
n-1
*1
CKE
n
*1
CS_n
*2
Command n
*4
Operation n
*4
Device Next State Notes
Active
Power Down
L L X X Maintain Active Power Down Active Power Down
L H H NOP Exit Active Power Down Active 6, 9
Idle Power Down
L L X X Maintain Idle Power Down Idle Power Down
L H H NOP Exit Idle Power Down Idle 6, 9
Resetting
Power Down
L L X X
Maintain
Resetting Power Down
Resetting
Power Down
L H H NOP Exit Resetting Power Down
Idle or
Resetting
6, 9, 12
Deep Power Down
L L X X
Maintain
Deep Power Down
Deep Power Down
L H H NOP Exit Deep Power Down Power On 8
Self Refresh
L L X X Maintain Self Refresh Self Refresh
L H H NOP Exit Self Refresh Idle 7, 10
Bank(s) Active H L H NOP
Enter
Active Power Down
Active Power Down
All Banks Idle
H L H NOP
Enter
Idle Power Down
Idle Power Down
H L L
Enter
Self-Refresh
Enter
Self Refresh
Self Refresh
H L L Deep Power Down
Enter
Deep Power Down
Deep Power Down
Resetting H L H NOP
Enter
Resetting Power Down
Resetting Power Down
H H Refer to the Command Truth Table
JEDEC Standard No. 209-2E
Page 151
5.19 LPDDR2-SDRAM Truth Tables (cont’d)
NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH, and after t
XSR
or t
XP
has been met if the previous state was
Power Down.
NOTE 2 All states and sequences not shown are illegal or reserved.
NOTE 3 Current State Definitions:
Idle: The bank or banks have been precharged, and tRP has been met.
Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accessesare in
progress.
Reading: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Writing: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
NOTE 4 The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable com-
mands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks
are determined by its current state and Table 2, and according to Table 3.

Precharging: starts with the registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank will be in
the idle state.

Row Activating: starts with registration of an Activate command and ends when tRCD is met. Once tRCD is met, the bank will be
in the ‘Active’ state.

Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when tRP has
been met. Once tRP has been met, the bank will be in the idle state.

Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank will be in the idle state.
Table 62 — Current State Bank n - Command to Bank n
Current State Command Operation Next State NOTES
Any NOP Continue previous operation Current State
Idle
ACTIVATE Select and activate row Active
Refresh (Per Bank) Begin to refresh Refreshing (Per Bank) 6
Refresh (All Bank) Begin to refresh Refreshing(All Bank) 7
MRW Load value to Mode Register MR Writing 7
MRR Read value from Mode Register
Idle
MR Reading
Reset Begin Device Auto-Initialization Resetting 7, 8
Precharge Deactivate row in bank or banks Precharging 9, 15
Row
Active
Read Select column, and start read burst Reading
Write Select column, and start write burst Writing
MRR Read value from Mode Register
Active
MR Reading
Precharge Deactivate row in bank or banks Precharging 9
Reading
Read Select column, and start new read burst Reading 10, 11
Write Select column, and start write burst Writing 10, 11, 12
BST Read burst terminate Active 13
Writing
Write Select column, and start new write burst Writing 10, 11
Read Select column, and start read burst Reading 10, 11, 14
BST Write burst terminate Active 13
Power On Reset Begin Device Auto-Initialization Resetting 7, 9
Resetting MRR Read value from Mode Register Resetting MR Reading
JEDEC Standard No. 209-2E
Page 152
5.19 LPDDR2-SDRAM Truth Tables (cont’d)
Notes (cont’d) to Table 62
NOTE 5 The following states must not be interrupted by any executable command; NOP commands must be applied to each pos-
itive clock edge during these states.

Refreshing (Per Bank): starts with registration of an Refresh (Per Bank) command and ends when tRFCpb is met. Once tRFCpb is
met, the bank will be in an ‘idle’ state.

Refreshing (All Bank): starts with registration of an Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is
met, the device will be in an ‘all banks idle’ state.

Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,
the bank will be in the Idle state.

Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been
met, the bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been
met, the bank will be in the Active state.

MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the
bank will be in the Idle state.

Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. Once tRP is met, the bank will
be in the idle state.
NOTE 6 Bank-specific; requires that the bank is idle and no bursts are in progress.
NOTE 7 Not bank-specific; requires that all banks are idle and no bursts are in progress.
NOTE 8 Not bank-specific reset command is achieved through Mode Register Write command.
NOTE 9 This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre-
charging.
NOTE 10 A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is
enabled.
NOTE 11 The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.
NOTE 12 A Write command may be applied after the completion of the Read burst; otherwise, a BST must be used to end the
Read prior to asserting a Write command.
NOTE 13 Not bank-specific. Burst Terminate (BST) command affects the most recent read/write burst started by the most recent
Read/Write command, regardless of bank.
NOTE 14 A Read command may be applied after the completion of the Write burst; otherwise, a BST must be used to end the
Write prior to asserting a Read command.
NOTE 15 If a Precharge command is issued to a bank in the Idle state, tRP shall still apply.
JEDEC Standard No. 209-2E
Page 153
5.19 LPDDR2-SDRAM Truth Tables (cont’d)
Table 63 — Current State Bank n - Command to Bank m
NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH, and after t
XSR
or t
XP
has been met if the previous state was
Self Refresh or Power Down.
NOTE 2 All states and sequences not shown are illegal or reserved.
NOTE 3 Current State Definitions:

Idle: the bank has been precharged, and tRP has been met.

Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.

Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
NOTE 4 Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle.
NOTE 5 A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current
state only.
Current State of
Bank n
Command for
Bank m
Operation
Next State for
Bank m
NOTES
Any NOP Continue previous operation Current State of Bank m
Idle Any Any command allowed to Bank m - 18
Row Activating,
Active, or
Precharging
Activate Select and activate row in Bank m Active 7
Read Select column, and start read burst from Bank m Reading 8
Write Select column, and start write burst to Bank m Writing 8
Precharge Deactivate row in bank or banks Precharging 9
MRR Read value from Mode Register
Idle MR Reading or
Active MR Reading
10, 11, 13
BST
Read or Write burst terminate an ongoing
Read/Write from/to Bank m
Active 18
Reading
(Autoprecharge
disabled)
Read Select column, and start read burst from Bank m Reading 8
Write Select column, and start write burst to Bank m Writing 8, 14
Activate Select and activate row in Bank m Active
Precharge Deactivate row in bank or banks Precharging 9
Writing
(Autoprecharge
disabled)
Read Select column, and start read burst from Bank m Reading 8, 16
Write Select column, and start write burst to Bank m Writing 8
Activate Select and activate row in Bank m Active
Precharge Deactivate row in bank or banks Precharging 9
Reading with
Autoprecharge
Read Select column, and start read burst from Bank m Reading 8, 15
Write Select column, and start write burst to Bank m Writing 8, 14, 15
Activate Select and activate row in Bank m Active
Precharge Deactivate row in bank or banks Precharging 9
Writing with
Autoprecharge
Read Select column, and start read burst from Bank m Reading 8, 15, 16
Write Select column, and start write burst to Bank m Writing 8, 15
Activate Select and activate row in Bank m Active
Precharge Deactivate row in bank or banks Precharging 9
Power On Reset Begin Device Auto-Initialization Resetting 12, 17
Resetting MRR Read value from Mode Register Resetting MR Reading
JEDEC Standard No. 209-2E
Page 154
5.19 LPDDR2-SDRAM Truth Tables (cont’d)
Notes (cont’d) to Table 63
NOTE 6 The following states must not be interrupted by any executable command; NOP commands must be applied during each
clock cycle while in these states:

Idle MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met, the
bank will be in the Idle state.

Resetting MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been
met, the bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met,
the bank will be in the Active state.

MR Writing: starts with the registration of a MRW command and ends when t
MRW
has been met. Once t
MRW
has been met, the
bank will be in the Idle state.
NOTE 7 t
RRD
must be met between Activate command to Bank n and a subsequent Activate command to Bank m.
NOTE 8 Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and
Writes with Auto Precharge disabled.
NOTE 9 This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre-
charging.
NOTE 10 MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and
ends when t
RCD
is met.)
NOTE 11 MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends
when t
RP
is met.
NOTE 12 Not bank-specific; requires that all banks are idle and no bursts are in progress.
NOTE 13 The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The
reader shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and
Precharging, the next state may be Active and Precharge dependent upon t
RCD
and t
RP
respectively.
NOTE 14 A Write command may be applied after the completion of the Read burst, otherwise a BST must be issued to end the
Read prior to asserting a Write command.
NOTE 15 Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to
other banks provided that the timing restrictions in Table 51 on page 115 and Table 52 on page 116 are followed.
NOTE 16 A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the
Write prior to asserting a Read command.
NOTE 17 Reset command is achieved through Mode Register Write command.
NOTE 18 BST is allowed only if a Read or Write burst is ongoing.
JEDEC Standard No. 209-2E
Page 155
5.20 LPDDR2-N: Truth Tables
The truth tables provide complementary information to the state diagram, they clarify the device behavior and the
applied restrictions when considering the actual state of all the Row Buffers.
Table 64 on page 155 describes Power Down transitions for a LPDDR2-NVM. If the Enter Power Down command is
issued when all Row Buffers are Idle the device goes into the Idle Power Down state. However, if the Enter Power
Down command is issued when one or more Row Buffers are Active, the device goes into the Active Power Down
state. CKE shall be held low to maintain the Power Down state. When CKE is driven high with CS_n high the device
exits the Power Down State. For additional details on entering and exiting power down, please refer to section
“Power-down” on page 138.
NOTE 1 “CKE
n
” is the logic state of CKE at clock rising edge n; “CKE
n-1
” was the state of CKE at the previous clock rising edge.
NOTE 2 “CS_n” is the logic state of CS_n at clock rising edge n;
NOTE 3 “Row Buffer Current State” is the state of a particular Row Buffer immediately prior to clock cycle n.
NOTE 4 “Device Current State” is the state of LPDDR2-NVM immediately prior to clock cycle n.
NOTE 5 “Command n” is the command registered at clock cycle n, and “Operation n” is the result of “Command n”.
NOTE 6 All states and sequences not shown are illegal or reserved, unless explicitly described elsewhere in this standard.
NOTE 7 Power Down exit time (t
XP
) should elapse before a command other than NOP is issued.
NOTE 8 The clock must toggle at least twice during the t
XP
period.
NOTE 9 Clock frequency may be reduced, and/or the clock may be stopped, during ‘Idle Power Down’, ‘Resetting Power Down’, or
‘Active Power Down’ states.
NOTE 10 Power Down may not be entered while Read, Write, Mode Register Read, Mode Register Write, or Preactive operations are in
progress. A Power Down command shall be followed by a NOP command.
NOTE 11 RB
j
and RB
k
refer to different Row Buffer pairs, (j) and (k).
Table 64 — LPDDR2-N: CKE Table
Row Buffer
Current State
*3
Device
Current State
*4
CKE
n-1
*1
CKE
n
*1
CS_n
*2
Command n
*5
Operation n
*5
Row Buffer
Next State
Device
Next State
Notes
All Resetting Resetting H L X
ENTER
POWER
DOWN
Enter in
Resetting
Power Down
Resetting
Power Down
Resetting
Power
Down
10
All Idle Idle H L X
ENTER
POWER
DOWN
Enter in Idle
Power Down
Idle
Power Down
Idle
Power
Down
10
RB
j
Active
Not
Power
Down
H L X
ENTER
POWER
DOWN
Enter in Active
Power Down
Active
Power Down
Active
Power
Down
10,11
RB
k
Idle
Idle
Power Down
All
Resetting
Power Down
Resetting
Power Down
L L X X
Maintain
Resetting
Power Down
Resetting
Power Down
Resetting
Power
Down
9
All
Idle
Power Down
Idle
Power Down
L L X X
Maintain Idle
Power Down
Idle
Power Down
Idle
Power
Down
9
RB
j
Active
Power Down
Active
Power
Down
L L X X
Maintain Active
Power Down
Active
Power Down
Active
Power
Down
9,11
RB
k
Idle
Power Down
Idle
Power Down
All
Resetting
Power Down
Resetting
Power Down
L H H
EXIT
POWER
DOWN
Exit Resetting
Power Down
Resetting Resetting 7,8
All
Idle
Power Down
Idle
Power Down
L H H
EXIT
POWER
DOWN
Exit Idle
Power Down
Idle Idle 7,8
RB
j
Active
Power Down
Active
Power
Down
L H H
EXIT
POWER
DOWN
Exit Active
Power Down
Active
Not
Power
Down
7,8,11
RB
k
Idle
Power Down
Idle
JEDEC Standard No. 209-2E
Page 156
5.20 LPDDR2-N: Truth Tables (cont’d)
Table 65 on page 156 shows the transition from the current state to the next state of a given Row Buffer due to
command issued on the same Row Buffer.
Only allowed commands are shown, all other commands are illegal or reserved for the given Row Buffer state.
For the state definition refer to section LPDDR2-NVM state diagram.

NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH, and after t
XP
has been met if the previous state was Power
Down.
NOTE 2 The following states must not be interrupted by a command issued to the same Row Buffer. NOP commands or allow-
able commands to other Row Buffer should be issued on any clock cycle occurring during these states.
Preactivating: starts with the registration of a Preactive command and ends when t
RP
is met. The Row Buffer will return to the Idle
state once t
RP
is satisfied and any ongoing Read or Write operation is complete.
Row Activating: starts with registration of an Activate command and ends when t
RCD
is met. Once t
RCD
is met, the Row Buffer
will be in the Row Active state.
NOTE 3 The following states must not be interrupted by any executable command; NOP commands must be applied to each
clock cycle during these states.
Idle MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met, the
Row Buffer will be in the Idle state.
Resetting MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been
met, the Row Buffer will be in the Resetting state.
Active MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met,
the Row Buffer will be in the Active state.
MR Writing: starts with the registration of a MRW command and ends when t
MRW
has been met. Once t
MRW
has been met, the
Row Buffer will be in the Idle state.
NOTE 4 BURST TERMINATE command affects the read/write burst started by the most recent READ/WRITE command.
NOTE 5 Reset command is achieved through MODE REG. WRITE command. Reset command sets all Row Address Buffers to
0x0000.
NOTE 6 t
RC
must be met between Activate command to Row Buffer n and subsequent Activate command to Row Buffer n.
Table 65 — Current State Row Buffer n - Command to Row Buffer n
Current
State
Command Operation Next State Notes
Any NOP Continue previous operation Current State
Idle
PREACTIVE Load RAB Preactivating
ACTIVATE Select RAB & RDB, and activate RDB Active
MRW Load value to Mode Register MR Writing
MRR Read value from Mode Register
Idle
MR Reading
Reset Begin Device Auto-Initialization Resetting 6
Active
PREACTIVE Load RAB Preactivating
ACTIVATE Select RAB & RDB, and activate RDB Active 7
READ Select RDB & column, and start read burst Reading
WRITE Select RDB & column, and start write burst Writing
MRW Load value to Mode Register MR Writing
MRR Read value from Mode Register
Active
MR Reading
Reset Begin Device Auto-Initialization Resetting 6
Reading
READ Select RDB & column, and start new read burst Reading
BST Read burst terminate Active 4
Writing
BST Write burst terminate Active 4
WRITE Select RDB & column, and start new write burst Writing
Power On Reset Begin Device Auto-Initialization Resetting 6
Resetting MRR Read value from Mode Register
Resetting
MR Reading
JEDEC Standard No. 209-2E
Page 157
5.20 LPDDR2-N: Truth Tables (cont’d)
Given the state of a Row Buffer (n), Table 66 on page 157 shows allowed commands to another Row Buffer (m), and
the corresponding next state. Only allowed commands are shown, all other commands are illegal or reserved for the
given Row Buffer state, unless explicitly described elsewhere in this standard.
For the state definition refer to section LPDDR2-NVM state diagram.
Table 66 — Current State Row Buffer n - Command to Row Buffer m
NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH, and after t
XP
has been met if the previous state was Power
Down.
NOTE 2 The following states must not be interrupted by any executable command; NOP commands must be applied during each
clock cycle while in these states:

Idle MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met, the
Row Buffer will be in the Idle state.
Resetting MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been
met, the Row Buffer will be in the Resetting state.
Active MR Reading: starts with the registration of a MRR command and ends when t
MRR
has been met. Once t
MRR
has been met,
the Row Buffer will be in the Active state.
MR Writing: starts with the registration of a MRW command and ends when t
MRW
has been met. Once t
MRW
has been met, all
Row Buffers will be in the Idle state.
NOTE 3 BURST TERMINATE command affects the read/write burst started by the most recent READ/WRITE command.
NOTE 4 Reset command is achieved through MODE REGISTER WRITE command. Reset command sets all Row Address Buf-
fers to 0x0000.
NOTE 5 t
RRD
must be met between Activate command to Row Buffer n and a subsequent Activate command to Row Buffer m.
NOTE 6 MRR is allowed during the Row Activating state and MRW is prohibited during the Row Activating state. (Row Acti-
vating starts with registration of an Activate command and ends when t
RCD
is met.)
NOTE 7 MRR is allowed during the Preactivating state and MRW is prohibited during the Preactivating state. (Preactivating
starts with registration of an Preactivate command and ends when tRP is met.)
NOTE 8 The next state for Row Buffer m depends on the current state of Row Buffer m (Idle, Row Activating, or Active). Note
that the state may be in transition when a MRR is issued. Therefore, if Row Buffer m is in the Row Activating state, the next state
may be Active dependent upon tRCD.
NOTE 9 BST is allowed only if a Read or Write burst is ongoing.
Current State of
Row Buffer n
Command for
Row Buffer m
Operation
Next State for
Row Buffer m
Notes
Any NOP Continue previous operation
Current State of Row Buf-
fer m
Idle Any Any command allowed to Row Buffer m - 9
Row Activating,
Active, or
Preactivating
ACTIVATE Select RABm & RDBm, and activate row in RDB m Active 5
READ Select RDBm & column, and start read burst from RDBm Reading
BST
Read or Write burst terminate an ongoing Read/Write
from/to Row Buffer m
Active 3, 9
WRITE Select RDBm & column, and start write burst to RDBm Writing
PREACTIVE Load RABm Preactivating
MRW Load value to Mode Register MR Writing 6, 7
MRR Read value from Mode Register
Idle MR Reading or
Active MR Reading
6, 7, 8
Reset Begin Device Auto-Initialization Resetting 4
Reading
READ Select RDBm & column, and start read burst from RDBm Reading
ACTIVATE Select RABm & RDBm, and activate row in RDB m Active
PREACTIVE Load RABm Preactivating
Writing
WRITE Select RDBm & column, and start write burst to RDBm Writing
ACTIVATE Select RABm & RDBm, and activate row in RDB m Active
PREACTIVE Load RABm Preactivating
Power On Reset Begin Device Auto-Initialization Resetting 4
Resetting MRR Read value from Mode Register Resetting MR Reading
JEDEC Standard No. 209-2E
Page 158
5.21 Data Mask Truth Table
Table 67 on page 158 provides the data mask truth table.
NOTE 1 Used to mask write data, provided coincident with the corresponding data.
Table 67 — DM truth table
Name (Functional) DM DQs Note
Write enable
L Valid 1
Write inhibit
H X 1
JEDEC Standard No. 209-2E
Page 159
6 Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 68 — Absolute Maximum DC Ratings
NOTE 1 Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability
NOTE 2 See “Power-Ramp” section in “Power-up, Initialization, and Power-Off” on page 28 for relationships
between power supplies.
NOTE 3 VREFDQ 0.6 x VDDQ; however, VREFDQ may be VDDQ provided that VREFDQ 300mV.
NOTE 4 VREFCA 0.6 x VDDCA; however, VREFCA may be VDDCA provided that VREFCA
300mV.
NOTE 5 Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device.
For the measurement conditions, please refer to JESD51-2 standard.
NOTE 6 Refer to vendor datasheet for VACC absolute maximum value.
Parameter Symbol Min Max Units Notes
VDD1 supply voltage relative to VSS VDD1 -0.4 2.3 V 2
VDD2 supply voltage relative to VSS
VDD2
(1.35V)
-0.4 1.8 V 2
VDD2
(1.2V)
-0.4 1.6 V 2
VDDCA supply voltage relative to VSSCA VDDCA -0.4 1.6 V 2,4
VDDQ supply voltage relative to VSSQ VDDQ -0.4 1.6 V 2,3
VACC supply voltage relative to VSS
VACC
(9 V)
-0.4 11.5 V
6
VACC
(VAP)
-0.4 7 V
Voltage on any ball relative to VSS VIN, VOUT -0.4 1.6 V
Storage Temperature T
STG
-55 125 °C 5
X s
>
X s
X s
>
X s
JEDEC Standard No. 209-2E
Page 160
7 AC & DC Operating Conditions
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the
LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before
normal operation can continue.
7.1 Recommended DC Operating Conditions
Table 69 — Recommended LPDDR2-S2 DC Operating Conditions
NOTE 1 When VDD2 is used, VDD1 uses significantly less current than VDD2
N/A(Not available)
Table 70 — Recommended LPDDR2-S4 DC Operating Conditions
NOTE 1 VDD1 uses significantly less power than VDD2
Table 71 — Recommended LPDDR2-N DC Operating Conditions
NOTE 1 When VACC is in the lockout voltage range, program and erase functions are disabled and will not be
executed. The lockout voltage range provides hardware program and erase protection for the LPDDR2-NVM
array.
NOTE 2 The maximum time for the device to be in the Acceleration Power range for VACC is 80 hours.
NOTE 3 Refer to vendor datasheet for VACC acceleration power supply value and VAP value. VAP shall not
be less than 3.3 V.
Symbol
LPDDR2-S2A LPDDR2-S2B
DRAM Unit
Min Typ Max Min Typ Max
VDD1 1.70 1.80 1.95 1.70 1.80 1.95 Core Power1 V
VDD2 N/A N/A N/A 1.14 1.20 1.3 Core Power2 V
VDDCA 1.14 1.20 1.3 1.14 1.20 1.3 Input Buffer Power V
VDDQ 1.14 1.20 1.3 1.14 1.20 1.3 I/O Buffer Power V
Symbol
LPDDR2-S4A LPDDR2-S4B
DRAM Unit
Min Typ Max Min Typ Max
VDD1 1.70 1.80 1.95 1.70 1.80 1.95 Core Power1 V
VDD2 1.28 1.35 1.42 1.14 1.20 1.3 Core Power2 V
VDDCA 1.14 1.20 1.3 1.14 1.20 1.3 Input Buffer Power V
VDDQ 1.14 1.20 1.3 1.14 1.20 1.3 I/O Buffer Power V
Symbol
Voltage LPDDR2-N-A LPDDR2-N-B
NVMem Unit
Min Typ Max Min Typ Max
VDD1 1.7 1.8 1.95 1.7 1.8 1.95 Core Power V
VDD2 N/A N/A N/A 1.14 1.2 1.3 Core Power 2 V
VDDCA 1.14 1.2 1.3 1.14 1.2 1.3 Input Buffer Power V
VDDQ 1.14 1.2 1.3 1.14 1.2 1.3 I/O Buffer Power V
VACC
(3)
-0.4 0.0 0.4 -0.4 0.0 0.4 Lockout Voltage V
1.7 1.8 1.95 1.7 1.8 1.95 Normal Operation V
8.5 9 9.5 8.5 9 9.5
Acceleration Power V
VAP-0.4 V VAP VAP+0.4 V VAP-0.4 V VAP VAP+0.4 V
JEDEC Standard No. 209-2E
Page 161
7.2 Input Leakage Current
Table 72 — Input Leakage Current
NOTE 1 The minimum limit requirement is for testing purposes. The leakage current on V
REFCA
and V
REFDQ
pins
should be minimal.
NOTE 2 Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage
specification.
7.3 Operating Temperature Range
Table 73 — Operating Temperature Range
NOTE 1 Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For
the measurement conditions, please refer to JESD51-2 standard.
NOTE 2 Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended
Temperature Range between 85
o
C and 105
o
C case temperature. For LPDDR2 devices, some derating is neccessary
to operate in this range. See MR4 on page 40.
NOTE 3 Either the device case temperature rating or the temperature sensor ( See “Temperature Sensor” on
page 129) may be used to set an appropriate refresh rate (SDRAM), determine the need for AC timing de-rating
(SDRAM and NVM) and/or monitor the operating temperature (SDRAM and NVM). When using the temperature
sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or
Extended Temperature Ranges. For example, TCASE may be above 85
o
C when the temperature sensor indicates a
temperature of less than 85
o
C.
Parameter/Condition Symbol Min Max Unit Notes
Input Leakage current
For CA, CKE, CS_n, CK_t, CK_c
Any input 0V VIN VDDCA
(All other pins not under test = 0V)
I
L
-2 2 uA 2
V
REF
supply leakage current
V
REFDQ
= VDDQ/2 or V
REFCA
= VDDCA/2
(All other pins not under test = 0V)
I
VREF
-1 1 uA 1
Parameter/Condition Symbol Min Max Unit
Standard
T
OPER
-25 85
o
C
Extended 85 105
o
C
X s X s
JEDEC Standard No. 209-2E
Page 162
8 AC and DC Input Measurement Levels
8.1 AC and DC Logic Input Levels for Single-Ended Signals
8.1.1 AC and DC Input Levels for Single-Ended CA and CS_n Signals
8.1.2 AC and DC Input Levels for CKE
Table 75 — Single-Ended AC and DC Input Levels for CKE
8.1.3 AC and DC Input Levels for Single-Ended Data Signals
Table 74 — Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
Min Max Min Max
V
IHCA
(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2
V
ILCA
(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2
V
IHCA
(DC) DC input logic high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V 1
V
ILCA
(DC) DC input logic low VSSCA Vref - 0.130 VSSCA Vref - 0.200 V 1
V
RefCA
(DC) Reference Voltage for CA and
CS_n inputs
0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3, 4
NOTE 1 For CA and CS_n input only pins. Vref = VrefCA(DC).
NOTE 2 See “Overshoot and Undershoot Specifications” on page 174
NOTE 3 The ac peak noise on V
RefCA
may not allow V
RefCA
to deviate from V
RefCA(DC)
by more than +/-1%
VDDCA (for reference: approx. +/- 12 mV).
NOTE 4 For reference: approx. VDDCA/2 +/- 12 mV.
Symbol Parameter Min Max Unit Notes
V
IHCKE
CKE Input High Level 0.8 * VDDCA Note 1 V 1
V
ILCKE
CKE Input Low Level Note 1 0.2 * VDDCA V 1
Note 1 See “Overshoot and Undershoot Specifications” on page 174
Table 76 — Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
Min Max Min Max
V
IHDQ
(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2, 5
V
ILDQ
(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2, 5
V
IHDQ
(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200 VDDQ V 1
V
ILDQ
(DC) DC input logic low VSSQ Vref - 0.130 VSSQ Vref - 0.200 V 1
V
RefDQ(DC)
Reference Voltage for
DQ, DM inputs
0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ 0.51 * VDDQ V 3, 4
NOTE 1 For DQ input only pins. Vref = VrefDQ(DC).
NOTE 2 See “Overshoot and Undershoot Specifications” on page 174
NOTE 3 The ac peak noise on V
RefDQ
may not allow V
RefDQ
to deviate from V
RefDQ(DC)
by more than +/-1%
VDDQ (for reference: approx. +/- 12 mV).
NOTE 4 For reference: approx. VDDQ/2 +/- 12 mV.
JEDEC Standard No. 209-2E
Page 163
8.2 Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages V
RefCA
and V
RefDQ
are illustrated in
Figure 106. It shows a valid reference voltage V
Ref
(t) as a function of time. (V
Ref
stands for V
RefCA
and V
RefDQ

likewise). VDD stands for VDDCA for V
RefCA
and VDDQ for V
RefDQ
. V
Ref
(DC) is the linear average of V
Ref
(t)
over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA
also over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 74.
Furthermore V
Ref
(t) may temporarily deviate from V
Ref(DC)
by no more than +/- 1% VDD. Vref(t) cannot track noise
on VDDQ or VDDCA if this would send Vref outside these specifications.
:
The voltage levels for setup and hold time measurements V
IH(AC)
, V
IH(DC)
, V
IL(AC)
and V
IL(DC)
are dependent on
V
Ref
.
“V
Ref
“ shall be understood as V
Ref(DC)
, as defined in Figure 106.
This clarifies that dc-variations of V
Ref
affect the absolute voltage a signal has to reach to achieve a valid high or low
level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate
timing deratings with V
REF
outside these specified levels so long as V
REF
is maintained between 0.44 x V
DDQ
(or
V
DDCA
) and 0.56 x V
DDQ
(or V
DDCA
) and so long as the controller achieves the required single-ended AC and DC
input levels from instantaneous V
REF
(see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs Table
on page 162 and Single-Ended AC and DC Input Levels for DQ and DM on page 171.) Therefore, system timing and
voltage budgets need to account for V
REF
deviations outside of this range.
This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage
associated with V
Ref
ac-noise. Timing and voltage effects due to ac-noise on V
Ref
up to the specified limit (+/-1% of
VDD) are included in LPDDR2 timings and their associated deratings.
VDD
VSS
VDD/2
V
Ref(DC)
V
Ref
ac-noise
voltage
time
V
Ref(DC)max
V
Ref(DC)min
V
Ref
(t)
Figure 106 — Illustration of V
Ref(DC)
tolerance and V
Ref
ac-noise limits
JEDEC Standard No. 209-2E
Page 164
8.3 Input Signal
Figure 107 — LPDDR2-466 to LPDDR2-1066 Input Signal
VIH(AC)
VIH(DC)
0.820V
0.730V
0.624V
0.612V
0.600V
0.588V
0.576V
0.470V
0.380V
VIL(DC)
VIL(AC)
0.820V
0.730V
0.624V
0.612V
0.600V
0.588V
0.576V
0.470V
0.380V
Minimum VIL and VIH Levels
1.200V
0.000V
-0.350V
VIL and VIH Levels With Ringback
1.550V VDD + 0.35V
VDD
VIH(AC)
VIH(DC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
VIL(DC)
VIL(AC)
VSS
VSS - 0.35V
NOTE 1 Numbers reflect nominal values.
NOTE 2 For CA0-9, CK_t, CK_c,and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c,
VDD stands for VDDQ.
NOTE 3 For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c,
VSS stands for VSSQ.
JEDEC Standard No. 209-2E
Page 165
8.3 Input Signal (cont’d)
Figure 108 — LPDDR2-200 to LPDDR2-400 Input Signal
VIH(AC)
VIH(DC)
0.900V
0.800V
0.624V
0.612V
0.600V
0.588V
0.576V
0.400V
0.300V
VIL(DC)
VIL(AC)
0.900V
0.800V
0.624V
0.612V
0.600V
0.588V
0.576V
0.400V
0.300V
Minimum VIL and VIH Levels
1.200V
0.000V
-0.350V
VIL and VIH Levels With Ringback
1.550V VDD + 0.35V
VDD
VIH(AC)
VIH(DC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
VIL(DC)
VIL(AC)
VSS
VSS - 0.35V
NOTE 1 Numbers reflect nominal values
NOTE 2 For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and
DQS_c, VDD stands for VDDQ.
NOTE 3 For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c,
VSS stands for VSSQ.
JEDEC Standard No. 209-2E
Page 166
8.4 AC and DC Logic Input Levels for Differential Signals
8.4.1 Differential signal definition
8.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c)
Table 77 — Differential AC and DC Input Levels
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
Min Max Min Max
V
IHdiff(dc)
Differential input high 2 x (VIH(dc) - Vref) note 3 2 x (VIH(dc) - Vref) note 3 V 1
V
ILdiff(dc)
Differential input low Note 3 2 x (VIL(dc) - Vref) Note 3 2 x (VIL(dc) - Vref) V 1
V
IHdiff(ac)
Differential input high ac 2 x (VIH(ac) - Vref) Note 3 2 x (VIH(ac) - Vref) Note 3 V 2
V
ILdiff(ac)
Differential input low ac note 3 2 x (VIL(ac) - Vref) note 3 2 x (VIL(ac) - Vref) V 2
NOTE 1 Used to define a differential signal slew-rate. For CK_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for
DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group,
then the reduced level applies also here.
NOTE 2 For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and
VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
NOTE 3 These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be
within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot
and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 174.
NOTE 4 For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).
Figure 109 — Definition of differential ac-swing and “time above ac-level” t
DVAC
V
IHDIFF(AC)
MIN
V
IHDIFF(DC)
MIN
V
ILDIFF(DC)
MAX
V
ILDIFF(AC)
MAX
0.0
CK_t - CK_c
DQS_t - DQS_c
half cycle
t
DVAC
t
DVAC
differential
time
voltage
JEDEC Standard No. 209-2E
Page 167
8.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c)
(cont’d)
Table 78 — Allowed time before ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c
Slew Rate [V/ns]
tDVAC [ps]
@ |VIH/Ldiff(ac)| = 440mV
tDVAC [ps]
@ |VIH/Ldiff(ac)| = 600mV
min min
> 4.0 175 75
4.0 170 57
3.0 167 50
2.0 163 38
1.8 162 34
1.6 161 29
1.4 159 22
1.2 155 13
1.0 150 0
< 1.0 150 0
JEDEC Standard No. 209-2E
Page 168
8.4.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain
requirements for single-ended signals.
CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle.
DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid
transition.
Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.
Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential
signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_c and VDDCA/2 for CK_t, CK_c; this is
nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
The signal ended requirements for CK_t, CK_c, DQS_t, and DQS_c are found in tables 74 and 76, respectively.
Table 79 — Single-ended levels for CK_t, DQS_t, CK_c, DQS_c
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit Notes
Min Max Min Max
VSEH(AC) Single-ended high-level for strobes (VDDQ / 2) + 0.220 note 3 (VDDQ / 2) + 0.300 note 3 V 1, 2
Single-ended high-level for CK_t, CK_c (VDDCA / 2) + 0.220 note 3 (VDDCA / 2) + 0.300 note 3 V 1, 2
VSEL(AC) Single-ended low-level for strobes note 3 (VDDDQ / 2) - 0.220 note 3 (VDDQ / 2) - 0.300 V 1, 2
Single-ended low-level for CK_t, CK_c note 3 (VDDCA / 2) - 0.220 note 3 (VDDCA / 2) - 0.300 V 1, 2
NOTE 1 For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use
VIH/VIL(ac) of DQs.
NOTE 2 VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
NOTE 3 These values are not defined, ho\wever the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t,
DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Refer to “Overshoot and Undershoot Specifications” on page 174
VSSCA or VSSQ
VDDCA or VDDQ
VSEL(ac)max
VSEH(ac)min
VSEH(ac)
VSEL(ac)
time
VDDCA/2 or VDDQ/2
Figure 110 — Single-ended requirement for differential signals.
DQS_t, or DQS_c
CK_t, CK_c
JEDEC Standard No. 209-2E
Page 169
8.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross
point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements in Table 79.
The differential input cross point voltage V
IX
is measured from the actual cross point of true and complement signals
to the midlevel between of VDD and VSS.
NOTE 1 The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and
VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input sig-
nals must cross.
NOTE 2 For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).
Table 80 — Cross point voltage for differential input signals (CK, DQS)
Symbol Parameter
LPDDR2-1066 to LPDDR2-200
Unit Notes
Min Max
V
IXCA
Differential Input Cross Point Voltage rel-
ative to VDDCA/2 for CK_t, CK_c
- 120 120 mV 1,2
V
IXDQ
Differential Input Cross Point Voltage rel-
ative to VDDQ/2 for DQS_t, DQS_c
- 120 120 mV 1,2
VDDCA or VDDQ
VSSCA or VSSQ
VDDCA/2 or VDDQ/2
V
IX
V
IX
V
IX
CK_c, DQS_c
CK_t, DQS_t
Figure 111 — Vix Definition
JEDEC Standard No. 209-2E
Page 170
8.6 Slew Rate Definitions for Single-Ended Input Signals
See “CA and CS_n Setup, Hold and Derating” on page 206 for single-ended slew rate definitions for address and
command signals.
See “Data Setup, Hold and Slew Rate Derating” on page 212 for single-ended slew rate definitions for data signals.
8.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in
Table 81 and Figure 112.
Table 81 — Differential Input Slew Rate Definition
Description
Measured
Defined by
from to
Differential input slew rate for rising edge
(CK_t - CK_c and DQS_t - DQS_c).
V
ILdiffmax
V
IHdiffmin
[V
IHdiffmin -
V
ILdiffmax
] / DeltaTRdiff
Differential input slew rate for falling edge
(CK_t - CK_c and DQS_t - DQS_c).
V
IHdiffmin
V
ILdiffmax
[V
IHdiffmin -
V
ILdiffmax
] / DeltaTFdiff
NOTE 1 The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds.
Figure 112 — Differential Input Slew Rate Definition for DQS_t, DQS_c and CK_t, CK_c
Delta TRdiff
V
IHdiffmin
V
ILdiffmax
D
i
f
f
e
r
e
n
t
i
a
l

I
n
p
u
t

V
o
l
t
a
g
e

(
i
.
e
.

D
Q
S
_
t

-

D
Q
S
_
c
;

C
K
_
t

-

C
K
_
c
)
0
Delta TFdiff
JEDEC Standard No. 209-2E
Page 171
9 AC and DC Output Measurement Levels
9.1 Single Ended AC and DC Output Levels
Table 82 shows the output levels used for measurements of single ended signals.
Table 82 — Single-ended AC and DC Output Levels
NOTE 1 IOH = -0.1mA.
NOTE 2 IOL = 0.1mA.
9.2 Differential AC and DC Output Levels
Table 83 shows the output levels used for measurements of differential signals (DQS_t, DQS_c).
Table 83 — Differential AC and DC Output Levels
NOTE 1 IOH = -0.1mA.
NOTE 2 IOL = 0.1mA
Symbol Parameter
LPDDR2-1066
to LPDDR2-200
Unit Notes
V
OH(DC)
DC output high measurement level (for IV curve linearity) 0.9 x V
DDQ
V 1
V
OL(DC)
DC output low measurement level (for IV curve linearity) 0.1 x V
DDQ
V 2
V
OH(AC)
AC output high measurement level (for output slew rate ) V
REFDQ
+ 0.12 V
V
OL(AC)
AC output low measurement level (for output slew rate ) V
REFDQ
- 0.12 V
I
OZ
Output Leakage current (DQ, DM, DQS_t, DQS_c)
(DQ, DQS_t, DQS_c are disabled; 0V VOUT VDDQ
Min -5 uA
Max 5 uA
MM
PUPD
Delta RON between pull-up and pull-down for DQ/DM
Min -15 %
Max 15 %
Symbol Parameter
LPDDR2-1066
to LPDDR2-200
Unit Notes
V
OHdiff(AC)
AC differential output high measurement level (for output SR) + 0.20 x V
DDQ
V
V
OLdiff(AC)
AC differential output low measurement level (for output SR) - 0.20 x V
DDQ
V
X s X s
JEDEC Standard No. 209-2E
Page 172
9.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between V
OL(AC)
and V
OH(AC)
for single ended signals as shown in Table 84 and Figure 113.
Table 84 — Single-ended Output Slew Rate Definition
Table 85 — Output Slew Rate (single-ended)
Description
Measured
Defined by
from to
Single-ended output slew rate for rising edge V
OL(AC)
V
OH(AC)
[V
OH(AC) -
V
OL(AC)
] / DeltaTRse
Single-ended output slew rate for falling edge V
OH(AC)
V
OL(AC)
[V
OH(AC) -
V
OL(AC)
] / DeltaTFse
NOTE 1 Output slew rate is verified by design and characterization, and may not be subject to production test.
Parameter Symbol
LPDDR2-1066 to LPDDR2-200
Units
Min Max
Single-ended Output Slew Rate (RON = 40O +/- 30%)
SRQse
1.5 3.5 V/ns
Single-ended Output Slew Rate (RON = 60O +/- 30%)
SRQse
1.0 2.5 V/ns
Output slew-rate matching Ratio (Pull-up to Pull-down) 0.7 1.4
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
NOTE 1 Measured with output reference load.
NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the
entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and
pull-down drivers due to process variation.
NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and
VOH(AC).
NOTE 4 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving
logic-high and 1/2 of DQ signals per data byte driving logic-low.
Figure 113 — Single Ended Output Slew Rate Definition
Delta TRse
V
OH(AC)
V
OL(AC)
S
i
n
g
l
e

E
n
d
e
d

O
u
t
p
u
t

V
o
l
t
a
g
e

(
i
.
e
.

D
Q
)

V
REF
Delta TFse
JEDEC Standard No. 209-2E
Page 173
9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 86 and Figure 114.
Table 86 — Differential Output Slew Rate Definition
Table 87 — Differential Output Slew Rate
Description
Measured
Defined by
from to
Differential output slew rate for rising edge V
OLdiff(AC)
V
OHdiff(AC)
[V
OHdiff(AC) -
V
OLdiff(AC)
] / DeltaTRdiff
Differential output slew rate for falling edge V
OHdiff(AC)
V
OLdiff(AC)
[V
OHdiff(AC) -
V
OLdiff(AC)
] / DeltaTFdiff
NOTE 1 Output slew rate is verified by design and characterization, and may not be subject to production test.
Parameter Symbol
LPDDR2-1066 to LPDDR2-200
Units
Min Max
Differential Output Slew Rate (RON = 40O +/- 30%)
SRQdiff
3.0 7.0 V/ns
Differential Output Slew Rate (RON = 60O +/- 30%)
SRQdiff
2.0 5.0 V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
NOTE 1 Measured with output reference load.
NOTE 2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and
VOH(AC).
NOTE 3 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving
logic-high and 1/2 of DQ signals per data byte driving logic-low.
Figure 114 — Differential Output Slew Rate Definition
V
OHdiff(AC)
V
OLdiff(AC)
D
i
f
f
e
r
e
n
t
i
a
l

O
u
t
p
u
t

V
o
l
t
a
g
e

(
i
.
e
.

D
Q
S
_
t

-

D
Q
S
_
c
)

0
Delta TFdiff
Delta TRdiff
JEDEC Standard No. 209-2E
Page 174
9.5 Overshoot and Undershoot Specifications
Table 88 — AC Overshoot/Undershoot Specification
Parameter
1066 933 800 667 533 466 400 333 266 200
Units
Maximum peak amplitude
allowed for overshoot area.
(See Figure 115)
Max 0.35 V
Maximum peak amplitude
allowed for undershoot area.
(See Figure 115)
Max 0.35 V
Maximum area above VDD.
(See Figure 115)
Max 0.15 0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 V-ns
Maximum area below VSS.
(See Figure 115)
Max 0.15 0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 V-ns
(CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM/DNV)
NOTE 1 For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c, VDD stands for
VDDQ.
NOTE 2 For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c, VSS stands for
VSSQ.
NOTE 3 Values are referenced from actual VDDQ, VDDCA, VSSQ, and VSSCA levels.
Overshoot Area
Maximum Amplitude
VDD
Undershoot Area
Maximum Amplitude
VSS
Volts
(V)
Time (ns)
Figure 115 — Overshoot and Undershoot Definition
NOTE 1 For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c, VDD stands for
VDDQ.
NOTE 2 For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c, VSS stands for
VSSQ.
JEDEC Standard No. 209-2E
Page 175
9.6 Output buffer characteristics
9.6.1 HSUL_12 Driver Output Timing Reference Load
These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or
a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation
tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test
conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Output
VREF
LPDDR2
0.5 x VDDQ
SDRAM/NVM
Cload = 5pF
NOTE 1 All output timing parameter values (like t
DQSCK
, t
DQSQ
, t
QHS,
t
HZ
, t
RPRE
etc.) are reported
with respect to this reference load. This reference load is also used to report slew rate.
RTT = 50 O
VTT = 0.5 x VDDQ
Figure 116 — HSUL_12 Driver Output Reference Load for Timing and Slew Rate
JEDEC Standard No. 209-2E
Page 176
9.7 RON
PU
and RON
PD
Resistor Definition
RONPU
VDDQ Vout – ( )
ABS Iout ( )
----------------------------------------- =
NOTE 1: This is under the condition that RON
PD
is turned off
RONPD
Vout
ABS Iout ( )
-------------------------- =
NOTE 1: This is under the condition that RON
PU
is turned off
Figure 117 — Output Driver: Definition of Voltages and Currents
VDDQ
VSSQ
DQ
RON
PU
RON
PD
To
other
circuitry
like
RCV,
...
Chip in Drive Mode
Output Driver
V
Out
I
Out
I
PU
I
PD
JEDEC Standard No. 209-2E
Page 177
9.7.1 RON
PU
and RON
PD
Characteristics with ZQ Calibration
Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240O.
NOTE 1 Across entire operating temperature range, after calibration.
NOTE 2 RZQ = 240O.
NOTE 3 The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the
tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature
sensitivity.
NOTE 4 Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ.
NOTE 5 Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure RON
PU
and
RON
PD
, both at 0.5 x VDDQ:
For example, with MMPUPD(max) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
Table 89 — Output Driver DC Electrical Characteristics with ZQ Calibration
RON
NOM
Resistor Vout
Min Nom Max Unit Notes
34.3O
RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4
RON34PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4
40.0O
RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4
RON40PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4
48.0O
RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4
RON48PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4
60.0O
RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4
RON60PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4
80.0O
RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4
RON80PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4
120.0O
(optional)
RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4
RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4
Mismatch between
pull-up and pull-down
MM
PUPD
-15.00 +15.00 % 1,2,3,4,5
MMPUPD
RONPU RONPD –
RONNOM
------------------------------------------------ 100 × =
JEDEC Standard No. 209-2E
Page 178
9.7.2 Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables shown
below.
NOTE 1 (@ calibration), (@ calibration)
NOTE 2 dRONdT and dRONdV are not subject to production test but are verified by design and
characterization.
Table 90 — Output Driver Sensitivity Definition
Resistor
Vout Min Max Unit Notes
RONPD
0.5 x VDDQ % 1,2
RONPU
Table 91 — Output Driver Temperature and Voltage Sensitivity
Symbol
Parameter MIn Max Unit Notes
dRONdT RON Temperature Sensitivity 0.00 0.75 % / C
dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV
85 dRONdT T A × ( ) – dRONdV V A × ( ) – 115 dRONdT T A × ( ) dRONdV V A × ( ) + +
T A T T – = V A V V – =
JEDEC Standard No. 209-2E
Page 179
9.7.3 RON
PU
and RON
PD
Characteristics without ZQ Calibration
Output driver impedance RON is defined by design and characterization as default setting.
NOTE 1 Across entire operating temperature range, without calibration.
Table 92 — Output Driver DC Electrical Characteristics without ZQ Calibration
RON
NOM
Resistor Vout
Min Nom Max Unit Notes
34.3O
RON34PD 0.5 x VDDQ 24 34.3 44.6 O 1
RON34PU 0.5 x VDDQ 24 34.3 44.6 O 1
40.0O
RON40PD 0.5 x VDDQ 28 40 52 O 1
RON40PU 0.5 x VDDQ 28 40 52 O 1
48.0O
RON48PD 0.5 x VDDQ 33.6 48 62.4 O 1
RON48PU 0.5 x VDDQ 33.6 48 62.4 O 1
60.0O
RON60PD 0.5 x VDDQ 42 60 78 O 1
RON60PU 0.5 x VDDQ 42 60 78 O 1
80.0O
RON80PD 0.5 x VDDQ 56 80 104 O 1
RON80PU 0.5 x VDDQ 56 80 104 O 1
120.0O
(optional)
RON120PD 0.5 x VDDQ 84 120 156 O 1
RON120PU 0.5 x VDDQ 84 120 156 O 1
JEDEC Standard No. 209-2E
Page 180
9.7.4 RZQ I-V Curve
Table 93 — RZQ I-V Curve
Voltage[V]
RON = 240O (RZQ)
Pull-Down
Pull-Up
Current [mA] / RON [Ohms]
Current [mA] / RON [Ohms]
default value
after ZQReset
with
Calibration
default value
after
ZQReset
with
Calibration
Min Max Min Max Min Max Min Max
[mA] [mA] [mA] [mA] [mA] [mA] [mA] [mA]
0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26
0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53
0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78
0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04
0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29
0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53
0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79
0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03
0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26
0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49
0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72
0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94
0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15
0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36
0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55
0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74
0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91
0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05
0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23
1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33
1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44
1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52
1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59
1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65
JEDEC Standard No. 209-2E
Page 181
9.7.4 RZQ I-V Curve (cont’d)
Figure 118 — RON = 240 Ohms
IV Curve after ZQReset
m
A
Voltage
PDIn-Fab Min
PDIn-Fab Max
PUIn-Fab Min
PUIn-Fab Max
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-6
-4
-2
0
2
4
6
Figure 119 — RON = 240 Ohms
IV Curve after calibration
m
A
Voltage
PDCal Min
PDCal Max
PUCal Min
PUCal Max
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
-6
-4
-2
0
2
4
6
JEDEC Standard No. 209-2E
Page 182
10 Input/Output Capacitance
10.1 Input/Output Capacitance
(TOPER; V
DDQ
= 1.14-1.3V; V
DDCA
= 1.14-1.3V; V
DD1
= 1.7-1.95V, LPDDR2-S4A V
DD2
= 1.28-1.42V,
LPDDR2-S2B, LPDDR2-N-B V
DD2
= 1.14-1.3V)
Table 94 — Input/output capacitance
Parameter Symbol
LPDDR2 1066-466 LPDDR2 400-200
Units Notes
Input capacitance,
CK_t and CK_c
CCK
Min 1.0 pF 1,2
Max 2.0 pF 1,2
Input capacitance delta,
CK_t and CK_c
CDCK
Min 0 pF 1,2,3
Max 0.20 0.25 pF 1,2,3
Input capacitance,
all other input-only pins
CI
Min 1.0 pF 1,2,4
Max 2.0 pF 1,2,4
Input capacitance delta,
all other input-only pins
CDI
Min -0.40 -0.50 pF 1,2,5
Max 0.40 0.50 pF 1,2,5
Input/output capacitance,
DQ, DM, DQS_t, DQS_c
CIO
Min 1.25 pF 1,2,6,7
Max 2.5 pF 1,2,6,7
Input/output capacitance delta,
DQS_t, DQS_c
CDDQS
Min 0 pF 1,2,7,8
Max 0.25 0.30 pF 1,2,7,8
Input/output capacitance delta,
DQ, DM
CDIO
Min -0.5 -0.6 pF 1,2,7,9
Max 0.5 0.6 pF 1,2,7,9
Input/output capacitance ZQ Pin CZQ
Min 0 pF 1,2
Max 2.5 pF 1,2
Package Input capacitance,
CK_t and CK_c
CPKGCK
Min pF 2,10
Max pF 2,10
Package Input capacitance delta,
CK_t and CK_c
CDPKGCK
Min pF 2,10,11
Max pF 2,10,11
Package Input capacitance,
all other input-only pins
CPKGI
Min pF 2,10,12
Max pF 2,10,12
Package Input capacitance delta,
all other input-only pins
CDPKGI
Min pF 2,10,13
Max pF 2,10,13
Package Input/output capacitance,
DQ, DM, DQS_t, DQS_c
CPKGIO
Min pF 2,10,5
Max pF 2,10,5
Package Input/output capacitance delta,
DQS_t, DQS_c
CDPKGDQS
Min pF 2,10,14
Max pF 2,10,14
Package Input/output capacitance delta,
DQ, DM
CDPKGIO
Min pF 2,10,15
Max pF 2,10,15
Package Input/output capacitance,
ZQ Pin
CDPKZQ
Min pF 2,10
Max pF 2,10,16
JEDEC Standard No. 209-2E
Page 183
10.1 Input/Output Capacitance (cont’d)
Notes to Table 94
NOTE 1 This parameter applies to die device only (does not include package capacitance).
NOTE 2 This parameter is not subject to production test. It is verified by design and characterization. The
capacitance is measured according to JEP147 (Procedure for measuring input capacitance using a vector network
analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ applied and all other pins floating.
NOTE 3 Absolute value of CCK_t - CCK_c.
NOTE 4 CI applies to CS_n, CKE, CA0-CA9.
NOTE 5 CDI = CI - 0.5 * (CCK_t + CCK_c)
NOTE 6 DM loading matches DQ and DQS.
NOTE 7 MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 Ohm typical)
NOTE 8 Absolute value of CDQS_t and CDQS_c.
NOTE 9 CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte-lane.
NOTE 10 This parameter applies to package only (does not include die capacitance). This value is vendor spe-
cific.
NOTE 11 Absolute value of CPKGCK_t and CPKGCK_c.
NOTE 12 CPKGI applies to CS_n, CKE, CA9-CA0.
NOTE 13 CDPKGI = CPKGI - 0.5 * (CPKGDQS_t + CPKGDQS_c).
NOTE 14 Absolute value of CPKGDQS_t and CPKGDQS_c.
NOTE 15 CDPKGIO = CPKGIO - 0.5 * (CPKGDQS_t + CPKGDQS_c) in byte lane.
NOTE 16 Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other
LPDDR2 devices: 5 pF.
JEDEC Standard No. 209-2E
Page 184
11 IDD Specification Parameters and Test Conditions
11.1 IDD Measurement Conditions
The following definitions are used within the IDD measurement tables:
LOW: VIN VIL(DC) MAX
HIGH: VIN VIH(DC) MIN
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See Table 95 and Table 96.
NOTE 1 CS_n must always be driven HIGH.
NOTE 2 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
NOTE 3 The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD val-
ues that require SWITCHING on the CA bus.
Table 95 — Definition of Switching for CA Input Signals
Switching for CA
CK_t
(RISING) /
CK_c
(FALLING)
CK_t
(FALLING) /
CK_c
(RISING)
CK_t
(RISING) /
CK_c
(FALLING)
CK_t
(FALLING) /
CK_c
(RISING)
CK_t
(RISING) /
CK_c
(FALLING)
CK_t
(FALLING) /
CK_c
(RISING)
CK_t
(RISING) /
CK_c
(FALLING)
CK_t
(FALLING) /
CK_c
(RISING)
Cycle N N+1 N+2 N+3
CS_n HIGH HIGH HIGH HIGH
CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
X s
Y >
JEDEC Standard No. 209-2E
Page 185
11.1 IDD Measurement Conditions (cont’d)
NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
NOTE 2 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R.
NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
NOTE 2 Data masking (DM) must always be driven LOW.
NOTE 3 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W.
Table 96 — Definition of Switching for IDD4R
Clock
CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ
Rising HIGH LOW N Read_Rising HLH LHLHLHL L
Falling HIGH LOW N Read_Falling LLL LLLLLLL L
Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H
Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L
Rising HIGH LOW N + 2 Read_Rising HLH HLHLLHL H
Falling HIGH LOW N + 2 Read_Falling LLL HHHHHHH H
Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H
Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L
Table 97 — Definition of Switching for IDD4W
Clock
CKE CS_n
Clock Cycle
Number
Command
CA0-
CA2
CA3-CA9
All
DQ
Rising HIGH LOW N Write_Rising HLL LHLHLHL L
Falling HIGH LOW N Write_Falling LLL LLLLLLL L
Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H
Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L
Rising HIGH LOW N + 2 Write_Rising HLL HLHLLHL H
Falling HIGH LOW N + 2 Write_Falling LLL HHHHHHH H
Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H
Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L
JEDEC Standard No. 209-2E
Page 186
11.2 IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire standard range, with the
exception of IDD6ET which is for the entire extended temperature range.
Table 98 — LPDDR2 IDD Specification Parameters and Operating Conditions
Parameter/Condition Symbol
Power
Supply
Units Notes
Operating one bank active-precharge current (SDRAM):
Operating one RB active current (NVM):
t
CK
= t
CK(avg)min
; t
RC
= t
RCmin
;
CKE is HIGH;
CS_n is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD0
1
VDD1 mA 4
IDD0
2
VDD2 mA 4
IDD0
IN
VDDCA
VDDQ
mA 4,5
Idle power-down standby current:
t
CK
= t
CK(avg)min
;
CKE is LOW;
CS_n is HIGH;
All banks/RBs idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2P
1
VDD1 mA 4
IDD2P
2
VDD2 mA 4
IDD2P
IN
VDDCA
VDDQ
mA 4,5
Idle power-down standby current with clock stop:
CK_t =LOW, CK_c =HIGH;
CKE is LOW;
CS_n is HIGH;
All banks/RBs idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2PS
1
VDD1 mA 4
IDD2PS
2
VDD2 mA 4
IDD2PS
IN
VDDCA
VDDQ
mA 4,5
Idle non power-down standby current:
t
CK
= t
CK(avg)min
;
CKE is HIGH;
CS_n is HIGH;
All banks/RBs idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD2N
1
VDD1 mA 4
IDD2N
2
VDD2 mA 4
IDD2N
IN
VDDCA
VDDQ
mA 4,5
Idle non power-down standby current with clock stop:
CK_t =LOW, CK_c =HIGH;
CKE is HIGH;
CS_n is HIGH;
All banks/RBs idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD2NS
1
VDD1 mA 4
IDD2NS
2
VDD2 mA 4
IDD2NS
IN
VDDCA
VDDQ
mA 4,5
Active power-down standby current:
t
CK
= t
CK(avg)min
;
CKE is LOW;
CS_n is HIGH;
One bank/RB active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3P
1
VDD1 mA 4
IDD3P
2
VDD2 mA 4
IDD3P
IN
VDDCA
VDDQ
mA 4,5
Active power-down standby current with clock stop:
CK_t=LOW, CK_c=HIGH;
CKE is LOW;
CS_n is HIGH;
One bank/RB active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3PS
1
VDD1 mA 4
IDD3PS
2
VDD2 mA 4
IDD3PS
IN
VDDCA
VDDQ
mA 4,5
JEDEC Standard No. 209-2E
Page 187
Active non power-down standby current:
t
CK
= t
CK(avg)min
;
CKE is HIGH;
CS_n is HIGH;
One bank/RB active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
IDD3N
1
VDD1 mA 4
IDD3N
2
VDD2 mA 4
IDD3N
IN
VDDCA
VDDQ
mA 4,5
Active non power-down standby current with clock
stop:
CK_t=LOW, CK_c=HIGH;
CKE is HIGH;
CS_n is HIGH;
One bank/RB active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
IDD3NS
1
VDD1 mA 4
IDD3NS
2
VDD2 mA 4
IDD3NS
IN
VDDCA
VDDQ
mA 4,5
Operating burst read current:
t
CK
= t
CK(avg)min
;
CS_n is HIGH between valid commands;
One bank/RB active;
BL = 4; RL = RLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer
IDD4R
1
VDD1 mA 4
IDD4R
2
VDD2 mA 4
IDD4R
IN
VDDCA mA 4
IDD4R
Q
VDDQ mA 4,8
Operating burst write current:
t
CK
= t
CK(avg)min
;
CS_n is HIGH between valid commands;
One bank/RB active;
BL = 4; WL = WLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer
IDD4W
1
VDD1 mA 4
IDD4W
2
VDD2 mA 4
IDD4W
IN
VDDCA
VDDQ
mA 4,5
All Bank Refresh Burst current:
t
CK
= t
CK(avg)min
;
CKE is HIGH between valid commands;
t
RC
= t
RFCabmin
;
Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5
1
VDD1 mA 1,4
IDD5
2
VDD2 mA 1,4
IDD5
IN
VDDCA
VDDQ
mA 1,4,5
All Bank Refresh Average current:
t
CK
= t
CK(avg)min
;
CKE is HIGH between valid commands;
t
RC
= t
REFI
;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5AB
1
VDD1 mA 1,4
IDD5AB
2
VDD2 mA 1,4
IDD5AB
IN
VDDCA
VDDQ
mA 1,4,5
Per Bank Refresh Average current:
t
CK
= t
CK(avg)min
;
CKE is HIGH between valid commands;
t
RC
= t
REFI
/8;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDD5PB
1
VDD1 mA 1,2,4
IDD5PB
2
VDD2 mA 1,2,4
IDD5PB
IN
VDDCA
VDDQ
mA 1,2,4,5
Self refresh current (Standard Temperature Range):
CK_t=LOW, CK_c=HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
Maximum 1x Self-Refresh Rate;
IDD6
1
VDD1 mA 1,3,4,11,12
IDD6
2
VDD2 mA 1,3,4,11,12
IDD6
IN
VDDCA
VDDQ
mA 1,3,4,5,11,
12
Parameter/Condition Symbol
Power
Supply
Units Notes
JEDEC Standard No. 209-2E
Page 188
NOTE 1 Refresh currents and Deep Power Down currents are not relevant for NVM devices.
NOTE 2 Per Bank Refresh only applicable for LPDDR2-S4 devices of 1Gb or higher densities and LPDDR2-S2 devices of
4Gb and higher densities.
NOTE 3 This is the general definition that applies to full array Self Refresh. Refer to IDD6 Partial Array Self-Refresh Cur-
rent on page 188 for details of Partial Array Self Refresh IDD6 specification.
NOTE 4 IDD values published are the maximum of the distribution of the arithmetic mean.
NOTE 5 Measured currents are the summation of VDDQ and VDDCA.
NOTE 6 Some LPDDR2-N devices do not support the erase function.
NOTE 7 To calculate total current consumption, the currents of all active operations must be considered.
NOTE 8 Guaranteed by design with output load of 5pF and RON = 40Ohm.
NOTE 9 Currents related to VDD2 do not apply to LPDDR2-N-A and LPDDR2-S2A devices.
NOTE 10 IDD current specifications are tested after the device is properly initialized.
NOTE 11 In addition, supplier data sheets may include additional Self Refresh IDD values for temperature subranges
within the Standard or Extended Temperature Ranges.
NOTE 12 1x Self-Refresh Rate is the rate at which the LPDDR2-SX device is refreshed internally during Self-Refresh
before going into the Extended Temperature range.
NOTE 13 IDD6ET is a typical value, is sampled only and is not tested.
NOTE 1 LPDDR2-S2 SDRAM uses the same PASR scheme & IDD6 current value categorization as LPDDR (JESD209).
NOTE 2 LPDDR2-S4 SDRAM uses the same IDD6 current value categorization as LPDDR2-S2 SDRAM. Some
LPDDR2-S4 SDRAM densities support both bank-masking & segment-masking. The IDD6 currents are measured using
bank-masking only.
NOTE 3 IDD values published are the maximum of the distribution of the arithmetic mean.
Self refresh current (Extended Temperature Range):
CK_t=LOW, CK_c=HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
IDD6ET
1
VDD1 mA 1,3,11,13
IDD6ET
2
VDD2 mA 1,3,11,13
IDD6ET
IN
VDDCA
VDDQ
mA 1,3,5,11,13
Deep Power-Down current:
CK_t=LOW, CK_c=HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
IDD8
1
VDD1 uA 1,4
IDD8
2
VDD2 uA 1,4
IDD8
IN
VDDCA
VDDQ
uA 1,4,5
LPDDR2-N Program current:
CK_t =LOW, CK_c =HIGH;
CKE is LOW;
RBs active or idle;
CS_n is HIGH;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDDN
P1
VDD1 mA 4,7
IDDN
P2
VDD2 mA 4,7
LPDDR2-N Erase current:
CK_t =LOW, CK_c =HIGH;
CKE is LOW;
RBs active or idle;
CS_n is HIGH;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
IDDN
E1
VDD1 mA 4,6,7
IDDN
E2
VDD2 mA 4,6,7
Table 99 — IDD6 Partial Array Self-Refresh Current
Parameter
LPDDR2-S2 LPDDR2-S4
Unit
64Mb-2Gb 4Gb-8Gb 64Mb-512Mb 1Gb-8Gb
IDD6 Partial Array
Self-Refresh Current
Full Array - - - - uA
1/2 Array - - - - uA
1/4 Array - - - - uA
1/8 Array NA - NA - uA
Parameter/Condition Symbol
Power
Supply
Units Notes
JEDEC Standard No. 209-2E
Page 189
12 Electrical Characteristics and AC Timing
12.1 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may
result in malfunction of the LPDDR2 device.
12.1.1 Definition for t
CK
(avg) and nCK
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock
period is calculated from rising edge to rising edge.
Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’
represents one clock cycle of the input clock, counting the actual clock edges.
tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are
met.
12.1.2 Definition for t
CK
(abs)
t
CK
(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge.
t
CK
(abs) is not subject to production test.
12.1.3 Definition for t
CH
(avg) and t
CL
(avg)
t
CH
(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.
t
CL
(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
12.1.4 Definition for t
JIT
(per)
t
JIT
(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg).
t
JIT
(per) = Min/max of {tCK
i
- tCK(avg) where i = 1 to 200}.
t
JIT
(per),act is the actual clock jitter for a given system.
t
JIT
(per),allowed is the specified allowed clock period jitter.
t
JIT
(per) is not subject to production test.
tCK avg ( ) tCK
j
j 1 =
N
¿
\ .
|
|
| |
N =
where N 200 =
tCH avg ( ) tCH
j
j 1 =
N
¿
\ .
|
|
| |
N tCK avg ( ) × ( ) =
where N 200 =
tCL avg ( ) tCL
j
j 1 =
N
¿
\ .
|
|
| |
N tCK avg ( ) × ( ) =
where N 200 =
JEDEC Standard No. 209-2E
Page 190
12.1.5 Definition for t
JIT
(cc)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
t
JIT
(cc) = Max of |{tCK
i +1
- tCK
i
}|.
t
JIT
(cc) defines the cycle to cycle jitter.
t
JIT
(cc) is not subject to production test.
12.1.6 Definition for t
ERR
(nper)
t
ERR
(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg).
t
ERR
(nper),act is the actual clock jitter over n cycles for a given system.
t
ERR
(nper),allowed is the specified allowed clock period jitter over n cycles.
t
ERR
(nper) is not subject to production test.
t
ERR
(nper),min can be calculated by the formula shown below:
t
ERR
(nper),max can be calculated by the formula shown below:
Using these equations, t
ERR
(nper) tables can be generated for each t
JIT
(per),act value.
tERR nper ( ) tCK
j
j i =
i n 1 – +
¿
\ .
|
|
| |
n tCK avg ( ) × – =
tERR nper ( ) min , 1 0.68LN n ( ) + ( ) tJIT per ( ) × min , =
tERR nper ( ) max , 1 0.68LN n ( ) + ( ) tJIT per ( ) × max , =
JEDEC Standard No. 209-2E
Page 191
12.1.7 Definition for duty cycle jitter t
JIT
(duty)
t
JIT
(duty) is defined with absolute and average specification of tCH / tCL.
12.1.8 Definition for tCK(abs), tCH(abs) and tCL(abs)
These parameters are specified per their average values, however it is understood that the following relationship
between the average timing and the absolute instantaneous timing holds at all times.
NOTE 1 tCK(avg),min is expressed is ps for this table.
NOTE 2 tJIT(duty),min is a negative value.
Table 100 — Definition for tCK(abs), tCH(abs), and tCL(abs)
Parameter Symbol Min Unit
Absolute Clock Period t
CK
(abs) tCK(avg),min + tJIT(per),min
ps
Absolute Clock HIGH Pulse Width t
CH
(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)
Absolute Clock LOW Pulse Width t
CL
(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)
tJIT duty ( ) min , MIN tCH abs ( ) min tCH avg ( ) min , – , ( ) tCL abs ( ) min tCL avg ( ) min , – , ( ) , ( ) tCK avg ( ) × =
H abs ( ) max tCH avg ( ) max , – , ) tCL abs ( ) max tCL avg ( ) max , – , ( ) , ) tCK avg ( ) ×
JEDEC Standard No. 209-2E
Page 192
12.2 Period Clock Jitter
LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section
describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found in
Table 103 on page 197 and how to determine cycle time de-rating and clock cycle de-rating.
12.2.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR,
tRC, tRAS, tRRD, tFAW )
Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when
measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the
LPDDR2 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}.
When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need
to be increased based on the values for each core timing parameter.
12.2.1.1 Cycle time de-rating for core timing parameters
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and
actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error
(tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the
equation results in a positive value for a core timing parameter (tCORE).
A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time
derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter.
12.2.1.2 Clock Cycle de-rating for core timing parameters
For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified
with amount of period jitter (tJIT(per)).
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and
actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error
(tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the
equation results in a positive value for a core timing parameter (tCORE).
A clock cycle de-rating analysis should be conducted for each core timing parameter.
12.2.2 Clock jitter effects on Command/Address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb,
tIHb, tISCKEb, tIHCKEb)
These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its
respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied
(i.e., tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address.
Regardless of clock jitter values, these values shall be met.
CycleTimeDerating MAX
tPARAM tERR tnPARAM ( ) act tERR tnPARAM ( ) allowed , – , +
tnPARAM
----------------------------------------------------------------------------------------------------------------------------------------------------------------- tCK avg ( ) –
\ .
| |
0 ,
¹ )
´ `
¦ ¹
=
ClockCycleDerating RU
tPARAM tERR tnPARAM ( ) act tERR tnPARAM ( ) allowed , – , +
tCK avg ( )
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
¹ )
´ `
¦ ¹
tnPARAM – =
JEDEC Standard No. 209-2E
Page 193
12.2.3 Clock jitter effects on Read timing parameters
12.2.3.1 tRPRE
When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter
(tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings
are relative to the input clock.
For example,
if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 ps, tJIT(per),act,min = -172 ps and
tJIT(per),act,max = + 193 ps, then
tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628
tCK(avg)
12.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0–31)
transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock
jitter applied (i.e. tJIT(per).
12.2.3.3 tQSH, tQSL
These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min.
tQSH(abs)min = tCH(abs)min – 0.05
tQSL(abs)min = tCL(abs)min – 0.05
These parameters determine absolute Data-Valid window at the LPDDR2 device pin.
Absolute min data-valid window @ LPDDR2 device pin =
min {(tQSH(abs)min * tCK(avg)min – tDQSQmax – tQHSmax) , (tQSL(abs)min * tCK(avg)min – tDQSQmax –
tQHSmax)}
This minimum data-valid window shall be met at the target frequency regardless of clock jitter.
12.2.3.4 tRPST
tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by
tCL(abs)min.
tRPST(abs)min = tCL(abs)min – 0.05 = tQSL(abs)min
tRPRE min derated , ( ) 0.9
tJIT per ( ) act max , , tJIT per ( ) allowed max , , –
tCK avg ( )
------------------------------------------------------------------------------------------------------------------
\ .
| |
– =
JEDEC Standard No. 209-2E
Page 194
12.2.4 Clock jitter effects on Write timing parameters
12.2.4.1 tDS, tDH
These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 –31) transition edge to its respective
data strobe signal (DQSn_t, DQSn_c : n=0,1,2,3) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values shall be met.
12.2.4.2 tDSS, tDSH
These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal
(CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the
setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter
values, these values shall be met.
12.2.4.3 tDQSS
This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal
(CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the
actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed.
For example,
if the measured jitter into a LPDDR2-800 device has tCK(avg)= 2500 ps, tJIT(per),act,min= -172 ps and
tJIT(per),act,max= + 193 ps, then
tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 =
.7788 tCK(avg)
and
tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 =
1.2128 tCK(avg)
tDQSS min derated , ( ) 0.75
tJIT per ( ) act min , , tJIT per ( ) allowed min , , –
tCK avg ( )
---------------------------------------------------------------------------------------------------------------- – =
tDQSS max derated , ( ) 1.25
tJIT per ( ) act max , , tJIT per ( ) allowed max , , –
tCK avg ( )
------------------------------------------------------------------------------------------------------------------ – =
JEDEC Standard No. 209-2E
Page 195
12.3 LPDDR2-SX Refresh Requirements by Device Density
Table 101 — LPDDR2-S2 Refresh Requirement Parameters (per density)
Parameter Symbol 64 Mb 128 Mb 256 Mb 512 Mb 1 Gb 2 Gb 4 Gb 8 Gb Unit
Number of Banks
4 8
Refresh Window
Tcase 85°C
t
REFW
32 ms
Refresh Window
85°C < Tcase 105°C
t
REFW
8 ms
Required number of
REFRESH commands (min)
R 2,048 2,048 4,096 4,096 4096 8,192 8,192 8,192
average time
between REFRESH
commands
(for reference only)
Tcase 85°C
REFab t
REFI
15.6 15.6 7.8 7.8 7.8 3.9 3.9
3.9 us
REFpb t
REFIpb
(REFpb not allowed below 4Gb)
0.4875 0.4875 us
Refresh Cycle time t
RFCab
90 90 90 90 130 130 130
210 ns
Per Bank Refresh Cycle time t
RFCpb
NA 60
90 ns
Burst Refresh Window
= 4 x 8 x t
RFCab
t
REFBW
2.88 2.88 2.88 2.88 4.16 4.16 4.16 6.72 us
Table 102 — LPDDR2-S4 Refresh Requirement Parameters (per density)
Parameter Symbol 64 Mb 128 Mb 256 Mb 512 Mb 1 Gb 2 Gb 4 Gb 8 Gb Unit
Number of Banks
4
8
Refresh Window
Tcase 85°C
t
REFW
32 ms
Refresh Window
85°C < Tcase 105°C
t
REFW
8 ms
Required number of
REFRESH commands (min)
R 2,048 2,048 4,096 4,096 4,096 8,192 8,192 8,192
average time
between REFRESH
commands
(for reference only)
Tcase 85°C
REFab t
REFI
15.6 15.6 7.8 7.8 7.8 3.9 3.9
3.9 us
REFpb t
REFIpb
(REFpb
not allowed below 1 Gb.)
0.975 0.4875
0.4875 0.4875 us
Refresh Cycle time t
RFCab
90 90 90 90 130 130 130
210 ns
Per Bank Refresh Cycle time t
RFCpb
NA 60 60 60
90 ns
Burst Refresh Window
= 4 x 8 x t
RFCab
t
REFBW
2.88 2.88 2.88 2.88 4.16 4.16 4.16 6.72 us
X s
X s
X s
X s
X s
X s
JEDEC Standard No. 209-2E
Page 196
J
E
D
E
C

S
t
a
n
d
a
r
d

N
o
.

2
0
9
-
2
E
P
a
g
e

1
9
7
12.4 AC Timings
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
Max. Frequency
*4
~ 533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Average Clock Period t
CK
(avg)
min 1.875 2.15 2.5 3 3.75 4.3 5 6 7.5 10
ns
max 100
Average high pulse width t
CH
(avg)
min 0.45
t
CK
(avg)
max 0.55
Average low pulse width t
CL
(avg)
min 0.45
t
CK
(avg)
max 0.55
Absolute Clock Period t
CK
(abs) min t
CK
(avg)min + t
JIT
(per),min ps
Absolute clock HIGH pulse width
(with allowed jitter)
t
CH
(abs),
allowed
min 0.43 t
CK
(avg)
max 0.57 t
CK
(avg)
Absolute clock LOW pulse width
(with allowed jitter)
t
CL
(abs),
allowed
min 0.43 t
CK
(avg)
max 0.57 t
CK
(avg)
Clock Period Jitter (with allowed jitter)
t
JIT
(per),
allowed
min -90 -95 -100 -110 -120 -130 -140 -150 -180 -250
ps
max 90 95 100 110 120 130 140 150 180 250
Maximum Clock Jitter between two consecutive clock
cycles (with allowed jitter)
t
JIT
(cc),
allowed
max 180 190 200 220 240 260 280 300 360 500 ps
Duty cycle Jitter (with allowed jitter)
t
JIT
(duty),
allowed
min min((t
CH
(abs),min - t
CH
(avg),min), (t
CL
(abs),min - t
CL
(avg),min)) * t
CK
(avg) ps
max max((t
CH
(abs),max - t
CH
(avg),max), (t
CL
(abs),max - t
CL
(avg),max)) * t
CK
(avg) ps
Cumulative error across 2 cycles
t
ERR
(2per),
allowed
min -132 -140 -147 -162 -177 -191 -206 -221 -265 -368
ps
max 132 140 147 162 177 191 206 221 265 368
Cumulative error across 3 cycles
t
ERR
(3per),
allowed
min -157 -166 -175 -192 -210 -227 -245 -262 -314 -437
ps
max 157 166 175 192 210 227 245 262 314 437
Cumulative error across 4 cycles
t
ERR
(4per),
allowed
min -175 -185 -194 -214 -233 -253 -272 -291 -350 -486
ps
max 175 185 194 214 233 253 272 291 350 486
Cumulative error across 5 cycles
t
ERR
(5per),
allowed
min -188 -199 -209 -230 -251 -272 -293 -314 -377 -524
ps
max 188 199 209 230 251 272 293 314 377 524
Cumulative error across 6 cycles
t
ERR
(6per),
allowed
min -200 -211 -222 -244 -266 -288 -311 -333 -399 -555
ps
max 200 211 222 244 266 288 311 333 399 555
Cumulative error across 7 cycles
t
ERR
(7per),
allowed
min -209 -221 -232 -256 -279 -302 -325 -348 -418 -581
ps
max 209 221 232 256 279 302 325 348 418 581
J
E
D
E
C

S
t
a
n
d
a
r
d

N
o
.

2
0
9
-
2
E
P
a
g
e

1
9
8
Cumulative error across 8 cycles
t
ERR
(8per),
allowed
min -217 -229 -241 -266 -290 -314 -338 -362 -435 -604
ps
max 217 229 241 266 290 314 338 362 435 604
Cumulative error across 9 cycles
t
ERR
(9per),
allowed
min -224 -237 -249 -274 -299 -324 -349 -374 -449 -624
ps
max 224 237 249 274 299 324 349 374 449 624
Cumulative error across 10 cycles
t
ERR
(10per),
allowed
min -231 -244 -257 -282 -308 -334 -359 -385 -462 -641
ps
max 231 244 257 282 308 334 359 385 462 641
Cumulative error across 11 cycles
t
ERR
(11per),
allowed
min -237 -250 -263 -289 -316 -342 -368 -395 -474 -658
ps
max 237 250 263 289 316 342 368 395 474 658
Cumulative error across 12 cycles
t
ERR
(12per),
allowed
min -242 -256 -269 -296 -323 -350 -377 -403 -484 -672
ps
max 242 256 269 296 323 350 377 403 484 672
Cumulative error across n = 13, 14 . . . 49, 50
cycles
t
ERR
(nper),
allowed
min t
ERR
(nper),allowed,min = (1 + 0.68ln(n)) * t
JIT
(per),allowed,min
ps
max t
ERR
(nper),allowed,max = (1 + 0.68ln(n)) * t
JIT
(per),allowed,max
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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N
o
.

2
0
9
-
2
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P
a
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1
9
9
ZQ Calibration Parameters
Initialization Calibration Time t
ZQINIT
min 1 us
Long Calibration Time t
ZQCL
min 6 360 ns
Short Calibration Time t
ZQCS
min 6 90 ns
Calibration Reset Time t
ZQRESET
min 3 50 ns
Read Parameters
*14
DQS output access time from CK_t/CK_c t
DQSCK
min 2500
ps
max 5500
DQSCK Delta Short
*18
t
DQSCKDS
max 330 380 450 540 670 770 900 1080 1350 1800 ps
DQSCK Delta Medium
*19
t
DQSCKDM
max 680 780 900 1050 1350 1550 1800 1900 2000 2100 ps
DQSCK Delta Long
*20
t
DQSCKDL
max 920 1050 1200 1400 1800 2100 2400 - - - ps
DQS - DQ skew t
DQSQ
max 200 220 240 280 340 370 400 500 600 700 ps
Data hold skew factor t
QHS
max 230 260 280 340 400 450 480 600 750 1000 ps
DQS Output High Pulse Width t
QSH
min t
CH
(abs) - 0.05 t
CK
(avg)
DQS Output Low Pulse Width t
QSL
min t
CL
(abs) - 0.05 t
CK
(avg)
Data Half Period t
QHP
min min(t
QSH
, t
QSL
) t
CK
(avg)
DQ / DQS output hold time from DQS t
QH
min t
QHP
- t
QHS
ps
Read preamble
*15,*16
t
RPRE
min 0.9 t
CK
(avg)
Read postamble
*15,*17
t
RPST
min t
CL
(abs) - 0.05 t
CK
(avg)
DQS low-Z from clock
*15
t
LZ(DQS)
min t
DQSCK(MIN)
- 300 ps
DQ low-Z from clock
*15
t
LZ(DQ)
min t
DQSCK(MIN)
- (1.4 * t
QHS(MAX)
) ps
DQS high-Z from clock
*15
t
HZ(DQS)
max t
DQSCK(MAX)
- 100 ps
DQ high-Z from clock
*15
t
HZ(DQ)
max t
DQSCK(MAX)
+ (1.4 * t
DQSQ(MAX)
) ps
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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o
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2
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-
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2
0
0
Write Parameters
*14
DQ and DM input hold time (Vref based) t
DH
min 210 235 270 350 430 450 480 600 750 1000 ps
DQ and DM input setup time (Vref based) t
DS
min 210 235 270 350 430 450 480 600 750 1000 ps
DQ and DM input pulse width t
DIPW
min 0.35 t
CK
(avg)
Write command to 1st DQS latching transition t
DQSS
min 0.75
t
CK
(avg)
max 1.25
DQS input high-level width t
DQSH
min 0.4 t
CK
(avg)
DQS input low-level width t
DQSL
min 0.4 t
CK
(avg)
DQS falling edge to CK setup time t
DSS
min 0.2 t
CK
(avg)
DQS falling edge hold time from CK t
DSH
min 0.2 t
CK
(avg)
Write postamble t
WPST
min 0.4 t
CK
(avg)
Write preamble t
WPRE
min 0.35 t
CK
(avg)
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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o
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2
0
9
-
2
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a
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e

2
0
1
CKE Input Parameters
CKE min. pulse width (high and low pulse width) t
CKE
min 3 3 t
CK
(avg)
CKE input setup time t
ISCKE
*2 min 0.25 t
CK
(avg)
CKE input hold time t
IHCKE
*3 min 0.25 t
CK
(avg)
Command Address Input Parameters
*14
Address and control input setup time (Vref based) t
IS
*
1
min 220 250 290 370 460 520 600 740 900 1150 ps
Address and control input hold time (Vref based) t
IH
*
1
min 220 250 290 370 460 520 600 740 900 1150 ps
Address and control input pulse width t
IPW
min 0.40 t
CK
(avg)
Boot Parameters (10 MHz - 55 MHz)
*8,10,11
Clock Cycle Time t
CKb
max
-
100
ns
min 18
CKE Input Setup Time t
ISCKEb
min - 2.5 ns
CKE Input Hold Time t
IHCKEb
min - 2.5 ns
Address & Control Input Setup Time t
ISb
min - 1150 ps
Address & Control Input Hold Time t
IHb
min - 1150 ps
DQS Output Data Access Time
from CK_t/CK_c
t
DQSCKb
min
-
2.0
ns
max 10.0
Data Strobe Edge to
Ouput Data Edge t
DQSQb
- 1.2
t
DQSQb
max - 1.2 ns
Data Hold Skew Factor t
QHSb
max - 1.2 ns
Mode Register Parameters
MODE REGISTER Write command period t
MRW
min 5 5 t
CK
(avg)
Mode Register Read command period t
MRR
min 2 2 t
CK
(avg)
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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o
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-
2
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2
0
2
LPDDR2 SDRAM Core Parameters
*12
Read Latency RL min 3 8 7 6 5 4 3 3 t
CK
(avg)
Write Latency WL min 1 4 4 3 2 2 1 1 t
CK
(avg)
ACTIVE to ACTIVE command period t
RC
min
t
RAS
+ t
RPab
(with all-bank Precharge)
t
RAS
+ t
RPpb
(with per-bank Precharge)
ns
CKE min. pulse width during Self-Refresh
(low pulse width during Self-Refresh)
t
CKESR
min 3 15 15 ns
Self refresh exit to next valid command delay t
XSR
min 2 t
RFCab
+ 10 ns
Exit power down to next valid command delay t
XP
min 2 7.5 7.5 ns
LPDDR2-S4 CAS to CAS delay t
CCD
min 2 2 2 t
CK
(avg)
LPDDR2-S2 CAS to CAS delay t
CCD
min 1 1 1 t
CK
(avg)
Internal Read to Precharge command delay t
RTP
min 2 7.5 7.5 ns
RAS to CAS Delay t
RCD
Fast 3 15 15 ns
Typ 3 18 18 ns
Slow 3 24 24 ns
Row Precharge Time
(single bank)
t
RPpb
Fast 3 15 15 ns
Typ 3 18 18 ns
Slow 3 24 24 ns
Row Precharge Time
(all banks)
t
RPab
4-bank
Fast 3 15 15 ns
Typ 3 18 18 ns
Slow 3 24 24 ns
Row Precharge Time
(all banks)
t
RPab
8-bank
Fast 3 18 18 ns
Typ 3 21 21 ns
Slow 3 27 27 ns
Row Active Time t
RAS
min 3 42 42 ns
max - 70 70 us
Write Recovery Time t
WR
min 3 15 15 ns
Internal Write to Read
Command Delay
t
WTR
min 2 7.5 10 ns
Active bank A to Active bank B t
RRD
min 2 10 10 ns
Four Bank Activate Window t
FAW
min 8 50 50 60 ns
Minimum Deep Power Down Time t
DPD
min 500 500 us
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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o
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2
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-
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2
0
3
LPDDR2 NVM Core Parameters
*12
Read Latency RL min 3 8 7 6 5 4 3 t
CK
(avg)
Write Latency WL min 1 4 3 2 1 t
CK
(avg)
Activate to Read/Write command period (min) t
RCDMIN
min
15 ns
max
255 ns
Activate to Read/Write command period t
RCD
*6, *21
min 5
t
RCDMIN
ns
Activate to Activate command period
(different Row Buffer)
t
RRD
*7, *21
min 5 t
RCDMIN
ns
Activate to Activate command period
(same Row Buffer)
t
RC
*21
min 5
t
RCDMIN
ns
CAS to CAS delay t
CCD
min 2 2 t
CK
(avg)
Write recovery time before Activate t
WRA min
3 15 ns
Internal write to read command delay t
WTR min
2 7.5 10 ns
Preactive to Activate command period t
RP min
3 3 t
CK
(avg)
Activate to Preactive command period t
RAS
*21
min
5 t
RCDMIN
ns
Exit power down to next valid command delay t
XP
min 2 10 ns
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
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2
0
4
NOTE 1 Input set-up/hold time for signal(CA0 ~ 9, CS_n)
NOTE 2 CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing.
NOTE 3 CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level .
NOTE 4 Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities.
NOTE 5 The speed bins 466, 266, and 200 are for NVM only.
NOTE 6 For NVM, t
RCDMIN
defines the minimum tRCD value. Vendors may choose a minimum tRCD value within the range of t
RCDMIN
.
NOTE 7 For NVM, vendors may choose a value for tRRD that is less than or equal to the tRCD value.
NOTE 8 To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in the Table 103 on page 197 . Boot parameter symbols have the letter b appended, e.g. tCK during boot is
t
CKb
.
NOTE 9 Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities.
NOTE 10 The SDRAM/NVM will set some Mode register default values upon receiving a RESET (MRW) command as specified in “Mode Register Definition” on page 32.
NOTE 11 The output skew parameters are measured with Ron default settings into the reference load.
NOTE 12 The min tCK column applies only when tCK is greater than 6ns for LPDDR2-SX devices and 10ns for LPDDR2-N devices. In this case, both min tCK values and analog timings (ns) shall be satisfied.
NOTE 13 All AC timings assume an input slew rate of 1V/ns.
NOTE 14 Read, Write, and Input Setup and Hold values are referenced to Vref.
NOTE 15 For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters
are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Figure 120 shows a method to calculate the point
when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
LPDDR2 Temperature De-Rating
t
DQSCK
De-Rating
t
DQSCK
(Derated)
max 5620 6000 ps
Core Timings Temperature De-Rating
for SDRAM
t
RCD
(Derated)
min t
RCD
+ 1.875 ns
t
RC
(Derated)
min t
RC
+ 1.875 ns
t
RAS
(Derated)
min t
RAS
+ 1.875 ns
t
RP
(Derated)
min t
RP
+ 1.875 ns
t
RRD
(Derated)
min t
RRD
+ 1.875 ns
Core Timings Temperature De-Rating
for NVM
*22
t
RCD
(Derated)
min t
RCD
+ t
NVMDERATING
ns
t
RC
(Derated)
min t
RC
+ t
NVMDERATING
ns
t
RAS
(Derated)
min t
RAS
+ t
NVMDERATING
ns
t
RRD
(Derated)
min t
RRD
+ t
NVMDERATING
ns
Table 103 — LPDDR2 AC Timing Table
*9
Parameter Symbol min max min t
CK
LPDDR2
Unit
1066 933 800 667 533
466
*5
400 333
266
*5
200
*5
JEDEC Standard No. 209-2E
Page 205
12.4 AC Timings (cont’d)
The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing
parameters tRPRE and tRPST are determined from the differential signal DQS_t-DQS_c.
NOTE 16 Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge.
NOTE 17 Measured from the from start driving the last falling strobe edge to the stop driving DQS_t - DQS_c.
NOTE 18 tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane)
within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design.
Temperature drift in the system is < 10C/s. Values do not include clock jitter.
NOTE 19 tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane)
within a 1.6us rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is <
10C/s. Values do not include clock jitter.
NOTE 20 tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane)
within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is <
10C/s. Values do not include clock jitter.
NOTE 21 Min tCK of 5 clocks is valid when the Overlay Window is disabled. Refer to vendor datasheets for min tCK when
the Overlay Window is enabled.
NOTE 22 For LPDDR2-NVM De-rating, the de-rating value found in MR20 OP5:OP4 (t
NVMDERATING
) shall be used to
de-rate the following parameters: tRCD, tRRD, tRAS, and tRC.
Figure 120 — HSUL_12 Driver Output Reference Load for Timing and Slew Rate
tHZ(DQS), tHZ(DQ)
stop driving point = 2 x T1 - T2
VOL + 2x X mV
T1 T2
VOL + X mV
VOH - X mV
VOH - 2x X mV
tLZ(DQS), tLZ(DQ)
begin driving point = 2 x T1 - T2
VOL
VTT - Y mV
VOH
T2 T1
VTT - 2x Y mV
VTT + 2x Y mV
VTT + Y mV
VTT VTT
Y
2x Y
actual waveform
X
2x X
JEDEC Standard No. 209-2E
Page 206
12.5 CA and CS_n Setup, Hold and Derating
For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the
data sheet tIS(base) and tIH(base) value (see Table 104) to the AtIS and AtIH derating value (see Table 105 and
Table 106) respectively. Example: tIS (total setup time) = tIS(base) + AtIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
REF(dc)
and
the first crossing of V
IH(ac)
min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of V
REF(dc)
and the first crossing of Vil(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘V
REF(dc)
to ac region’, use nominal slew rate for derating value (see Figure
Figure 121). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V
REF(dc)
to ac
region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 123).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and
the first crossing of V
REF(dc)
. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of Vih(dc)min and the first crossing of V
REF(dc)
. If the actual signal is always later than the nominal slew
rate line between shaded ‘dc to V
REF(dc)
region’, use nominal slew rate for derating value (see Figure 122). If the
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V
REF(dc)
region’, the slew rate
of a tangent line to the actual signal from the dc level to V
REF(dc)
level is used for derating value (see Figure 124).
For a valid transition the input signal has to remain above/below V
IH/IL(ac)
for some time t
VAC
(see Table 107).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
V
IH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach V
IH/IL(ac)
.
For slew rates in between the values listed in Table 105, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 104 — CA and CS_n Setup and Hold Base-Values for 1V/ns
NOTE 1 ac/dc referenced for 1V/ns CA and CS_n slew rate and 2V/ns differential CK_t-CK_c slew rate.
unit [ps]
LPDDR2
reference
1066 933 800 667 533 466
tIS(base) 0 30 70 150 240 300 V
IH/L(ac) = VREF(dc) +/-220mV
tIH(base) 90 120 160 240 330 390 V
IH/L(dc) = VREF(dc) +/-130mV
unit [ps]
LPDDR2
reference
400 333 266 200
tIS(base) 300 440 600 850 V
IH/L(ac) = VREF(dc) +/-300mV
tIH(base) 400 540 700 950 V
IH/L(dc) = VREF(dc) +/-200mV
JEDEC Standard No. 209-2E
Page 207
12.5 CA and CS_n Setup, Hold and Derating (cont’d)
Table 105 — Derating values LPDDR2 tIS/tIH - ac/dc based AC220
NOTE 1 Cell contents shaded in red are defined as ‘not supported’.
Table 106 — Derating values LPDDR2 tIS/tIH - ac/dc based - AC300
NOTE 1 Cell contents shaded in red are defined as ‘not supported’.
Table 107 — Required time t
VAC
above VIH(ac) {below VIL(ac)} for valid transition
AtIS, AtIH derating in [ps] AC/DC based
AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV
DC100 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV
CK_t,CK_c Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH
CA,
CS_n
Slew
rate
V/ns
2.0 110 65 110 65 110 65
1.5 74 43 73 43 73 43 89 59
1.0 0 0 0 0 0 0 16 16 32 32
0.9 -3 -5 -3 -5 13 11 29 27 45 43
0.8 -8 -13 8 3 24 19 40 35 56 55
0.7 2 -6 18 10 34 26 50 46 66 78
0.6 10 -3 26 13 42 33 58 65
0.5 4 -4 20 16 36 48
0.4 -7 2 17 34
AtIS, AtIH derating in [ps] AC/DC based
AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV
DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV
CK_t,CK_c Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH AtIS AtIH
CA,
CS_n
Slew
rate
V/ns
2.0 150 100 150 100 150 100
1.5 100 67 100 67 100 67 116 83
1.0 0 0 0 0 0 0 16 16 32 32
0.9 -4 -8 -4 -8 12 8 28 24 44 40
0.8 -12 -20 4 -4 20 12 36 28 52 48
0.7 -3 -18 13 -2 29 14 45 34 61 66
0.6 2 -21 18 -5 34 15 50 47
0.5 -12 -32 4 -12 20 20
0.4 -35 -40 -11 -8
Slew Rate [V/ns] t
VAC
@ 300mV [ps] t
VAC
@ 220mV [ps]
min max min max
> 2.0 75 - 175 -
2.0 57 - 170 -
1.5 50 - 167 -
1.0 38 - 163 -
0.9 34 - 162 -
0.8 29 - 161 -
0.7 22 - 159 -
0.6 13 - 155 -
0.5 0 - 150 -
< 0.5 0 - 150 -
JEDEC Standard No. 209-2E
Page 208
12.5 CA and CS_n Setup, Hold and Derating (cont’d)
V
SSCA
Setup Slew Rate Setup Slew Rate
Rising Signal
Falling Signal
ATF ATR
V
REF(dc)
- V
IL(ac)
max
ATF
=
V
IH(ac)
min - V
REF(dc)
ATR
=
V
DDCA
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
nominal
nominal
slew rate
VREF to ac
region
VREF to ac
region
tVAC
tVAC
slew rate
tIH
tIS
CK_t
CK_c
tIH tIS
Figure 121 — Illustration of nominal slew rate and t
VAC
for setup time t
IS

for CA and CS_n with respect to clock.
JEDEC Standard No. 209-2E
Page 209
12.5 CA and CS_n Setup, Hold and Derating (cont’d)
V
SSCA
Hold Slew Rate
Hold Slew Rate
Falling Signal
Rising Signal
ATR ATF
V
REF(dc)
- V
IL(dc)
max
ATR
=
V
IH(dc)
min - V
REF(dc)
ATF
=
V
DDCA
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
nominal
slew rate
nominal
slew rate
dc to V
REF
region
dc to V
REF
region
tIH tIS
CK_t
CK_c
tIH tIS
Figure 122 — Illustration of nominal slew rate for hold time t
IH

for CA and CS_n with respect to clock
JEDEC Standard No. 209-2E
Page 210
12.5 CA and CS_n Setup, Hold and Derating (cont’d)
V
SSCA
tIH
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
ATF
ATR
tangent line[V
REF(dc)
- V
IL(ac)
max]
ATF
=
tangent line[V
IH(ac)
min - V
REF(dc)
]
ATR
=
V
DDCA
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
tIS
tangent
tangent
V
REF
to ac
region
V
REF
to ac
region
line
line
nominal
line
nominal
line
tVAC
tVAC
CK_t
CK_c
tIH tIS
Figure 123 — Illustration of tangent line for setup time t
IS

for CA and CS_n with respect to clock
JEDEC Standard No. 209-2E
Page 211
12.5 CA and CS_n Setup, Hold and Derating (cont’d)
V
SSCA
Hold Slew Rate
ATF
ATR
tangent line [ V
IH(dc)
min - V
REF(dc)
]
ATF
=
V
DDCA
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
tangent
tangent
dc to V
REF
region
dc to V
REF
region
line
line
nominal
line
nominal
line

Falling Signal
Hold Slew Rate
tangent line [ V
REF(dc)
- V
IL(dc)
max ]
ATR
=

Rising Signal
tIH tIS
CK_t
CK_c
tIH tIS
Figure 124 — Illustration of tangent line for for hold time t
IH

for CA and CS_n with respect to clock
JEDEC Standard No. 209-2E
Page 212
12.6 Data Setup, Hold and Slew Rate Derating
For all input signals (DQ, DM) the total tDS (setup time) and tDH (hold time) required is calculated by adding the
data sheet tDS(base) and tDH(base) value (see Table 108) to the AtDS and AtDH (see Table 109 and Table 110)
derating value respectively. Example: tDS (total setup time) = tDS(base) + AtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
REF(dc)
and
the first crossing of V
IH(ac)
min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of V
REF(dc)
and the first crossing of V
IL(ac)
max (see Figure 125). If the actual signal is always earlier
than the nominal slew rate line between shaded ‘V
REF(dc)
to ac region’, use nominal slew rate for derating value. If
the actual signal is later than the nominal slew rate line anywhere between shaded ‘V
REF(dc)
to ac region’, the slew
rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 127).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
IL(dc)
max
and the first crossing of V
REF(dc)
. Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of V
IH(dc)
min and the first crossing of V
REF(dc)
(see Figure 126). If the actual signal is
always later than the nominal slew rate line between shaded ‘dc level to V
REF(dc)
region’, use nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V
REF(dc)

region’, the slew rate of a tangent line to the actual signal from the dc level to V
REF(dc)
level is used for derating value
(see Figure 128).
For a valid transition the input signal has to remain above/below V
IH/IL(ac)
for some time t
VAC
(see Table 111).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
V
IH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach V
IH/IL(ac)
.
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 108 — Data Setup and Hold Base-Values
NOTE 1 ac/dc referenced for 1V/ns DQ, DM slew rate and 2V/ns differential DQS_t-DQS_c slew rate.
[ps]
LPDDR2
reference
1066 933 800 667 533 466
tDS(base) -10 15 50 130 210 230 V
IH/L(ac) = VREF(dc) +/- 220mV
tDH(base) 80 105 140 220 300 320 V
IH/L(dc) = VREF(dc) +/- 130mV
unit [ps]
LPDDR2
reference
400 333 266 200
tDS(base) 180 300 450 700 V
IH/L(ac) = VREF(dc) +/-300mV
tDH(base) 280 400 550 800 V
IH/L(dc) = VREF(dc) +/-200mV
JEDEC Standard No. 209-2E
Page 213
12.6 Data Setup, Hold and Slew Rate Derating (cont’d)
Table 109 — Derating values LPDDR2 tDS/tDH - ac/dc based AC220
NOTE 1 Cell contents shaded in red are defined as ‘not supported’.
Table 110 — Derating values LPDDR2 tDS/tDH - ac/dc based AC300
NOTE 1 Cell contents shaded in red are defined as ‘not supported’.
Table 111 — Required time t
VAC
above VIH(ac) {below VIL(ac)} for valid transition
AtDS, ADH derating in [ps] AC/DC based
AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV
DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV
DQS_t, DQS_c Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH
DQ,DM
Slew rate
V/ns
2.0 110 65 110 65 110 65 - - - - - - - - - -
1.5 74 43 73 43 73 43 89 59 - - - - - - - -
1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -
0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - -
0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - -
0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78
0.6 - - - - - - - - 10 -3 26 13 42 33 58 65
0.5 - - - - - - - - - - 4 -4 20 16 36 48
0.4 - - - - - - - - - - - - -7 2 17 34
AtDS, ADH derating in [ps] AC/DC based
AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV
DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV
DQS_t, DQS_c Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH
DQ,DM
Slew rate
V/ns
2.0 150 100 150 100 150 100 - - - - - - - - - -
1.5 100 67 100 67 100 67 116 83 - - - - - - - -
1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -
0.9 - - -4 -8 -4 -8 12 8 28 24 44 40 - - - -
0.8 - - - - -12 -20 4 -4 20 12 36 28 52 48 - -
0.7 - - - - - - -3 -18 13 -2 29 14 45 34 61 66
0.6 - - - - - - - - 2 -21 18 -5 34 15 50 47
0.5 - - - - - - - - - - -12 -32 4 -12 20 20
0.4 - - - - - - - - - - - - -35 -40 -11 -8
Slew Rate [V/ns] t
VAC
@ 300mV [ps] t
VAC
@ 220mV [ps]
min max min max
> 2.0 75 - 175 -
2.0 57 - 170 -
1.5 50 - 167 -
1.0 38 - 163 -
0.9 34 - 162 -
0.8 29 - 161 -
0.7 22 - 159 -
0.6 13 - 155 -
0.5 0 - 150 -
< 0.5 0 - 150 -
JEDEC Standard No. 209-2E
Page 214
12.6 Data Setup, Hold and Slew Rate Derating (cont’d)
V
SSQ
Setup Slew Rate Setup Slew Rate
Rising Signal
Falling Signal
ATF ATR
V
REF(dc)
- V
IL(ac)
max
ATF
=
V
IH(ac)
min - V
REF(dc)
ATR
=
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
nominal
nominal
slew rate
VREF to ac
region
VREF to ac
region
tVAC
tVAC
slew rate
tDH tDS
DQS_t
DQS_c
tDH tDS
Figure 125 — Illustration of nominal slew rate and t
VAC
for setup time t
DS

for DQ with respect to strobe
JEDEC Standard No. 209-2E
Page 215
12.6 Data Setup, Hold and Slew Rate Derating (cont’d)
V
SSQ
Hold Slew Rate
Hold Slew Rate
Falling Signal
Rising Signal
ATR ATF
V
REF(dc)
- V
IL(dc)
max
ATR
=
V
IH(dc)
min - V
REF(dc)
ATF
=
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
nominal
slew rate
nominal
slew rate
dc to V
REF
region
dc to V
REF
region
tDH tDS
DQS_t
DQS_c
tDH tDS
Figure 126 — Illustration of nominal slew rate for hold time t
DH

for DQ with respect to strobe
JEDEC Standard No. 209-2E
Page 216
12.6 Data Setup, Hold and Slew Rate Derating (cont’d)
V
SSQ
tDH
Setup Slew Rate
Setup Slew Rate
Rising Signal
Falling Signal
ATF
ATR
tangent line[V
REF(dc)
- V
IL(ac)
max]
ATF
=
tangent line[V
IH(ac)
min - V
REF(dc)
]
ATR
=
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
tDS
tangent
tangent
V
REF
to ac
region
V
REF
to ac
region
line
line
nominal
line
nominal
line
tVAC
tVAC
DQS_t
DQS_c
tDH tDS
Figure 127 — Illustration of tangent line for setup time t
DS

for DQ with respect to strobe
JEDEC Standard No. 209-2E
Page 217
12.6 Data Setup, Hold and Slew Rate Derating (cont’d)
V
SSQ
Hold Slew Rate
ATF
ATR
tangent line [ V
IH(dc)
min - V
REF(dc)
]
ATF
=
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
tangent
tangent
dc to V
REF
region
dc to V
REF
region
line
line
nominal
line
nominal
line

Falling Signal
Hold Slew Rate
tangent line [ V
REF(dc)
- V
IL(dc)
max ]
ATR
=

Rising Signal
tDH tDS
DQS_t
DQS_c
tDH tDS
Figure 128 — Illustration of tangent line for for hold time t
DH

for DQ with respect to strobe
JEDEC Standard No. 209-2E
Page 218
Annex A LPDDR2-NVM Software Application Notes
A.1 Scope
LPDDR2-NVM can be produced from a variety of memory array technologies.
The variety of technologies causes variation in software that manages the non-volatile arrays.
This application note shows a program method for a particular NV memory technology as an example of possible
implementation.
A.2 Programming operations based on Programming Region
A.2.1 Introduction
This section describes a particular program method that might be implemented in some LPDDR2-NVM devices. The
scope of this section is only to provide an example, other technology or product may implement a different program
method.
Users should refer to the vendor memory datasheet for complete information.
Some LPDDR2-NVM devices may implement innovative features specially developed to improve the storage
flexibility and efficiency of memory arrays.
A.2.2 Programming Modes
Typically, the memory array of an NVM is divided into multiple blocks. Each block can be divided in uniform
programming regions.
Each programming region in a block can be configured for one of two programming modes: Control Mode or Object
Mode. The programming mode is automatically set based on the data pattern when a region is first programmed. The
selection of either Control Mode or Object Mode is done according to the specific needs of the system with
consideration given to two types of information:
• Control Mode: Flash File System (FFS) or Header information, including frequently changing code or data. Control
Mode allows for multiple programs within a programming region between block erases.
• Object Mode: Large, infrequently changing code or data, such as objects or payloads. Object Mode allows only a
single program operation within each programming region between block erases.
By implementing the appropriate programming mode, software can efficiently organize how information is stored in
the flash memory array.
Control Mode programming regions and Object Mode programming regions can be intermingled within the same
erase block. However, the programming mode of any region within a block can be changed only after erasing the
entire block.
A.2.3 Programming Regions
The following table shows the amount of Programming Regions within each block for various block sizes and 512-
Byte and 1-KByte Programming region size.
Refer to the device datasheet to discover the actual size of the Programming Region.
Erase operations have a Block granularity, whereas program operations have a Programming Region granularity.
The user can configure each Programming Region to be programmed either in the Control mode or in the Object
mode.
A given Block can contain Programming Regions configured in the Control mode and others configured in the Object
mode.
Table 112 — Number of Programming Regions
Block Size
Programming Region Size
512Byte 1KByte
64KByte 128 64
128KByte 256 128
256KByte 512 256
JEDEC Standard No. 209-2E
Page 219
A.2.3 Programming Regions (cont’d)
Special care should be taken when selecting the programming mode for the Programming Regions because once the
Programming Regions are configured their program mode cannot be changed until the entire Block is erased.
Each Programming Region is split into elements, and the element size can be either 8 Bytes or 16 Bytes. There are
even elements and odd elements as defined in Table 113, where a3 and a4 are byte address bits.
Figure 129 — Programming Regions and elements
A.2.4 Program Modes
There are two program modes, which allow the memory to store different types of data.
A.2.4.1 Control Mode
The Control mode is best suited to the storage of small, dynamic information. Typically such data is contained within
one Programming Region and it will be frequently updated and/or new data will be added to it.
Programming Regions are configured in the Control mode by programming data only to the even elements. The odd
elements must remain erased, that is they should not contain any zeros (Figure 129, “Programming Regions and
elements” on page 219 ).
In a Programming Region of 1-KByte (512Byte) configured in the Control mode, only 512 Byte (256Byte) of data
can be stored, in particular only even elements are writable while odd elements are reserved.
Some LPDDR2-NVM devices will allow to program each byte of the even elements only once. Some others will not
have this restriction, therefore each byte might be programmed subsequently several times without erasing the Block.
When the Programming Regions are configured in the Control mode, any program command can be used: the Single
Word (if supported) or the Buffered Program command.
Once a Programming Region has been configured in the Control mode, if a zero is written to an odd element, the
program operation is terminated without programming the array and an error is generated.
The Status Register bits MR22.OP4 (PSB) and MR23.OP1 (CMSB) are set to ‘1’. (Refer to Status Register
description and to Table 114, “Relationships Between Program Commands and Programming modes” on page 222
for details).
Table 113 — Even and Odd elements
Element 8-Byte 16-Byte
Even Element a3 = 0 a4 = 0
Odd Element a3 = 1 a4 = 1
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
Programming Region 0
Programming Region 1
Block
Programming Region 2
Programming Region N
even element odd element
a3 = 0 a3 = 1 8-Byte element
a4 = 0 a4 = 1 16-Byte element
JEDEC Standard No. 209-2E
Page 220
A.2.4.1 Control Mode (cont’d)
The program mode of a Programming Region configured in the Control mode can only be changed by first erasing
the Block that contains the Programming Region.
NOTE 1 Only the even elements of a Programming Region configured Control Mode are writable.
NOTE 2 Reserved elements return “0xFF” when read.
Figure 130 — Programming Regions Configured in Control Mode
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
Programming Region 0
Programming Region 1
Block
Programming Region 2
Programming Region N
even element odd element
a3 = 0 a3 = 1 8-Byte element
a4 = 0 a4 = 1 16-Byte element
Reserved
Writable
element
element
0x000
Reserved
Byte
Writable
Byte
0x008
0x020 0x028
0x010 0x018
0x1F0 0x1F8
...
0x000 0x010
0x040 0x050
0x020 0x030
0x2E0 0x2F0
...
8-Byte element
512-Byte Programming Region
16-Byte element
1-KByte Programming Region
Reserved Writable
element element
Reserved Writable
element element
JEDEC Standard No. 209-2E
Page 221
A.2.4.2 Object Mode
The Object mode is best suited to the storage of large, static information. In a Programming Region of 1-KByte (512-
Byte) configured in the Object mode, 1-KByte (512-Byte) of data can be stored.
When a Programming Region is configured in the Object mode, it cannot be reprogrammed nor have new data added
without first erasing the entire Block that contains the Programming Region.
Programming Regions are configured in the Object mode simply by programming at least one bit in one of the odd
elements.
If the programmed data is smaller than 1-KByte (512Byte), the unused space remains in the erased state (all the bytes
set to 0xFF), but can no longer be used to program data. See Figure 129, “Programming Regions and elements” on
page 219.
Only the Buffered Program command can be used to establish an Object mode region.
NOTE: All elements of a Programming Region configured Object Mode are writable.
Figure 131 — Programming Regions Configured in Object Mode
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
even element odd element
Programming Region 0
Programming Region 1
Block
Programming Region 2
Programming Region N
even element odd element
a3 = 0 a3 = 1 8-Byte element
a4 = 0 a4 = 1 16-Byte element
Reserved
Writable
element
element
0x000
Reserved
Byte
Writable
Byte
0x008
0x020 0x028
0x010 0x018
0x1F0 0x1F8
...
0x000 0x010
0x040 0x050
0x020 0x030
0x2E0 0x2F0
...
8-Byte element
512-Byte Programming Region
16-Byte element
1-KByte Programming Region
Writable
element
Writable
element
Writable
element
Writable
element
JEDEC Standard No. 209-2E
Page 222
A.2.4.3 Programming Region Configuration
Based on the current programming region status, the following table shows the next programming region status after
a programming operations.
NOTE 1 At least one bit is programmed in an even element
NOTE 2 At least one bit is programmed in an odd element
NOTE 3 If supported
NOTE 4 Program aborted, Status Register error bits MR22.OP4 (PSB), MR23.OP0 (OMSB) and MR23.OP1
(CMSB) are set
NOTE 5 Program aborted, Status Register error bits MR22.OP4 (PSB) MR23.OP1 (CMSB) are set
NOTE 6 Program aborted, subsequent program not allowed, Status Register error bits MR22.OP4 (PSB)
MR23.OP0 (OMSB) are set
Figure 132 shows an example of Programming Region configuration. The Programming Region size is 512Byte, the
element size is 8Byte, and the Block sizes are 64KByte, 128KByte and 256KByte.
Independently of the Block size, the Programming Region configuration is periodic: the first 124 Programming
Regions (62KByte) are configured in Object Mode Region, and the following 4 Programming Regions (2KByte) are
configured in Control Mode.
Table 114 — Relationships Between Program Commands and Programming modes
Programming
Region Status
Next Programming Region Status
Element Buffered Program Single Word Program
(3)
Erased
Even
(1)
Control mode
Object mode
Control mode
Odd
(2)
Object mode Not allowed
(4)
Control
Program mode
Even
(1)
Control mode Control mode
Odd
(2)
Not allowed
(5)
Not allowed
(4)
Object
Program mode
Even
(1)
Not allowed
(6)
Not allowed
(6)
Not allowed
(6)
Odd
(2)
Not allowed
(6)
Not allowed
(4)
JEDEC Standard No. 209-2E
Page 223
A.2.4.3 Programming Region Configuration (cont’d)
Figure 132 — Control Mode and Program Mode Example
Reserved
Writable
element
element
64-KByte Block
128-KByte Block
256-KByte Block
62-KB Object Mode
2-KB Control Mode
0x00000000
0x0001FFFF
0x0002FFFF
0x0003FFFF
0x0000FFFF
0x00010000
0x00020000
0x00030000
62-KB Object Mode
2-KB Control Mode
62-KB Object Mode
2-KB Control Mode
62-KB Object Mode
2-KB Control Mode
JEDEC Standard No. 209-2E
Page 224
Annex B LPDDR2-NVM Boot Procedure
B.1 Booting From an LPDDR2-NVM Device
Figure 133 illustrates an example LPDDR2 memory subsystem that includes both NVM and SDRAM memories.
Chip Select (CSx) and Clock Enable (CKEx) are assigned on a per chip basis, the data bus and the remainder of the
command bus are common to both devices. Because LPDDR2 devices (both DRAM and NVM) assign specific
functions to the different byte lanes of the data bus and even to specific bits within the bytes, byte and bit swapping
shall be avoided. The ZQ input requires connection to a precision 240 ohm resistor that is used to calibrate each
device’s output drive strength. The ZQ inputs can use a common 240 ohm resistor or have captive resistors, in this
example we use a common resistor.
Figure 133 — LPDDR2 based system using both LPDDR2-SDRAM and LPDDR2-NVM
Chipsets implementing an LPDDR2 interface will need to perform a “pre-boot” process prior to accessing the
LPDDR2-NVM device. The pre-boot process will perform the LPDDR2-NVM device initialization (as described in
Section 3.5.1 - Power Ramp and Device Initialization in the LPDDR2-NVM spec) and configure both the LPDDR2
controller and the external LPDDR2-NVM device properly prior to starting code execution from external memory.
The pre-boot process may be performed by executing a code residing in an embedded ROM or it might be
implemented using hardware in the memory controller.
CPU
Embedded
ROM
Embedded
SRAM
LPDDR2
Controller
ZQ ZQ
LPDDR2-NVM LPDDR2-SDRAM
DQ, DQS_t, DQS_c, DM
CA,CK
CS_0
CKE_0
CS_1
CKE_1
Chipset
JEDEC Standard No. 209-2E
Page 225
B.1 Booting From an LPDDR2-NVM Device (cont’d)
The pre-boot process is composed by the following steps:
1. Memory Controller Preliminary Configuration
- Configure the memory controller with initial latency settings compatible with the possible LPDDR2-NVM
devices that may reside on the LPDDR2 bus
2. Initialization Sequence
- Apply clock (frequency between 10MHz and 55MHz)
- Drive CKE High
- Issue the Reset command and wait until the DAI bit in MR0 transitions to 0. It is recommended that this delay
(tINIT5) be accomplished by polling the DAI bit in MR0.
- Issue a ZQ Initialization Command
3. Search for an LPDDR2-NVM memory
- Starting from CS0, check the first LPDDR2-NVM device in the bus by
reading MR0
4. Memory Controller and LPDDR2-NVM configuration
- Read MR8 to retrieve the memory type, bus width, density and configure the memory controller accordingly
- Read MR20 to retrieve Row Data Buffer Size and number of Row Data Buffers, then configure the memory con-
troller accordingly
- Optionally, set the proper Burst Length value in MR1 of the LPDDR2-NVM
- Optionally, adjust tRCD memory controller setting according to MR21 and the
actual tCKb value.
5. Start to read the boot code from the external LPDDR2-NVM device.
Once the pre-boot process has completed and code execution is passed to the external LPDDR2-NVM memory
device the final portion of the memory bus configuration process occurs. During this stage the boot process will
optimize timings and finally increase the clock rate to the target value.
6. Specify how frequently the output impedance should be calibrated
7. Set the appropriate output drive strength
8. Adjust the configuration settings in the controller and memories for higher clock rates
9. Bump up the bus operating frequency
10. Perform data training
JEDEC Standard No. 209-2E
Page 226
B.1.1 Power Ramp and Initialization
During power-on the LPDDR2 power supplies are expected to ramp up to the nominal operating voltages within
20ms. At this point CKE should be driven low and the CK_t/CK_c clock signals should begin to toggle. During this
early part of the boot process the host chipset is expected to clock the LPDDR2 bus at a frequency between 10MHz
and 55MHz. After 100ns and at least five clocks, CKE is driven high to begin internal initialization of the LPDDR2
device. The device is ready to receive the RESET command 200us after CKE is driven high.
Figure 134 — Power-Up and Initialization (see the LPDDR2-NVM spec for details)
Once the RESET command has been issued the boot process must wait for 1us before continuing. After the 1us
tINIT4 time has elapsed the boot process will poll the Device AutoInitialization (DAI) bit in the Device Information
Register (MR0). The DAI bit will transition from high to low when the reset operation has completed.
The LPDDR2 devices after RESET assume the following default configuration:
BL=4;
BT= Sequential, Wrap;
RL=3, WL=1;
DS=40Ohm.
It is recommended that the memory controller default configuration should match with the LPDDR2 devices (at least
RL, otherwise it would not be possible to read the Mode Registers).
CK_t / CK_c
Supplies
CKE
CA*
DQ
t
ISCKE

t
INIT0
= 20 ms (max)
t
INIT3
= 200 us (min)
t
INIT1
= 100 ns (min)
t
INIT2
= 5 t
CK
(min)
t
INIT4
= 1 us (min)
t
INIT5

* Midlevel on CA bus means: valid NOP
PD
RESET MRR ZQC
Ta Tb Tc Td Te Tf
Valid
t
ZQINIT

Tg
JEDEC Standard No. 209-2E
Page 227
B.1.2 ZQ Initialization
Once reset has completed, the ZQ Initialization command (FFh) is written to the Calibration Mode Register (MR10).
During ZQ initialization the on-die output impedance is compared with a 240 ohm precision resistor that is connected
between ground and the device’s ZQ input. Multiple LPDDR2 devices can share the precision resistor as long as only
one of the devices performs calibration at any particular time. Upon completion of the ZQ Initialization the device’s
output impedance will be within 15% of the nominal value.
At the lower operating frequencies used during the boot process the default drive strength value of 40 ohms is
adequate. Adjustment of the drive strength will occur later in the boot process when the clock rate is bumped up prior
to normal operation.
B.1.3 Determine the LPDDR2 bus width, memory type, RDB size and density
The boot process then reads the Basic Configuration 4 Mode Register (MR8) from the LPDDR2 device on CS0 to
determine the data bus width, memory type and also the device density. When the memory is an NVM, MR20 is read
to determine the RDB size. The controller is then configured to operate with the appropriate bus width (x8, x16 or
x32). The density value read back from MR8 is used to configure the address space assigned to CS0. The data bus
width and the RDB size is relevant system information and is used to ensure proper memory addressing and is
mandatory to configure the memory controller accordingly. The embedded ROM can be programmed, or the HW
could be used, to step through the remaining LPDDR2 chip selects and configure the host controller according to the
information available in the respective mode registers.
B.1.4 Align controller and memory latency settings (RL, WL, tRCD)
Prior to performing standard read and write operations the host controller and target memory must align their
Read/Write latencies. The default values for LPDDR2-NVM devices is a three clock read latency and a one clock
write latency. These default values are suitable for normal operation for the specified boot frequency (10MHz to
55MHz). If necessary, the memory controller latencies should be adjusted to match those of the LPDDR2-NVM
device.
The remaining latency issue needing attention is aligning the host controller with the LPDDR2- NVM tRCD
latencies. The value held in the read only tRCD Mode Register (MR21) specifies the minimum tRCD value for the
LPDDR2-NVM device. The embedded boot code should configure the LPDDR2 controller latency values to
accommodate the tRCD value indicated in MR21.
B.1.5 Determining whether to boot from the LPDDR2 Bus
After the initial latencies have been specified the boot process will determine whether a bootable non-volatile device
resides on the LPDDR2 bus. If there is a bootable NVM device on the LPDDR2 bus it will likely reside on the first
chip select (CS0). If the device is nonvolatile, program operation will be redirected to the LPDDR2-NVM device on
CS0. If the device is volatile (SDRAM), the embedded ROM will continue to search for alternate boot memories.
B.1.6 Continued Boot Out Of the LPDDR2-NVM Device
Once the boot process has passed to the LPDDR2-NVM device, system level characteristics are considered. For the
most part this portion of the boot process is used to maximize data throughput by adjusting the output drive strength,
clock rate and the data capture point during read operations.
B.1.7 Output Drive Strength
Given various system level considerations, adjustment of the output drive strength away from the default 40 ohm
setting may be required. This step is required to optimize driver output impedance to accommodate issues like bus
loading (# of devices), PoP/MCP package type, trace length on the PCB and sourcing capabilities of the output driver
power supplies.
The I/O Configuration Mode Register (MR3) is used to configure the LPDDR2-NVM output drive strength.
Available configuration settings include 34.3, 40 (default), 48, 60 and 80 ohm values (120 ohm value is optional).
JEDEC Standard No. 209-2E
Page 228
B.1.8 Setting the Output Impedance Calibration Interval
During normal operation both operating voltage and temperature drift can cause the output drive strength to change
away from the value selected during the boot process. These changes are dealt with by periodically calibrating the
output impedance against the 240 ohm precision resistor connected to the ZQ input. Periodic calibration is performed
to assure that the selected output impedance remains within the nominal +/-15% spec.
LPDDR2 controllers include a periodic timer that will indicate the length of time between calibration cycles. Once
the timer interval has expired the controller will automatically issue a Short Calibration command that will move the
output impedance by up to 1.5% toward the ideal setting. The calibration interval is calculated by considering the
maximum voltage and temperature drift rates. Given a maximum temperature drift rate of 1.0°C/s and a maximum
voltage drift rate of 15mV/s the Short Calibration operation should be performed at least every 400ms. The equation
below is the strategy suggested by JEDEC to determine how frequently output impedance should be calibrated.
ZQS_Interval = (ZQS_Correction/((T_Sensitivity*T_DriftRate)+(V_Sensitivity*VDriftRate))
= 1.5%/(((0.75%/°C)*(1.0°C/s))+((0.2%/mV)*(15mV/s)))
= 400ms
If a single 240 ohm ZQ resistor is common to all LPDDR2 devices the ZQS Calibration operation must be performed
serially on a per device basis. If each LPDDR2 device has its own ZQ resistor the ZQS Calibration operation must
still be performed on a per device basis. See the LPDDR2-NVM spec for further guidance on how to determine the
required length of time between ZQS calibration.
B.1.9 Increasing the Clock Rate
At this point in the boot process, preparation to increase the clock rate can begin. This process has three steps. The
first step is to alter the memory controller settings to accommodate the latency characteristics of the memory devices
on the LPDDR2 bus. The second step is to increase the clock frequency to the target rate. The third and final step is to
perform data training to maximize read timing margin.
While the first step (adjusting latency settings) can be executed from code located in the LPDDR2-NVM device, the
second (increasing clock rate) and third (data training) steps should not be performed using code executing from a
device residing on the LPDDR2 bus. The code used to increase the clock rate and to perform data training should be
executed out of embedded memory located in the chipset. The required code could reside in either the embedded
ROM or it could be copied temporarily into the chipset’s embedded SRAM for execution. Once these three steps have
been performed, program operation will be redirected to the LPDDR2-NVM device with the LPDDR2 bus running at
the target frequency.
Configuration of additional devices residing on the LPDDR2 bus can be performed either before or after the clock
rate is increased. If additional devices are configured before the clock rate is increased, extensions to the code that
manages the LPDDR2-NVM device can be developed. If additional LPDDR2 devices are to be brought on line after
the clock rate is increased, the configuration code for the additional devices could be executed out of the LPDDR2-
NVM device.
B.1.10 Controller Latency Settings for Higher Clock Rates
The first step toward increasing the clock rate is adjusting the controller settings to account for the memory device’s
operational characteristics. The key characteristics include the time required between the Active and Read/Write
commands (tRCD) and also the Read/Write Latencies (RL, WL).
The tRCD value can be read from the tRCD Mode Register (MR21). The number of clocks required to meet the
tRCD spec given a target operating frequency is then calculated and loaded into the memory controller. This process
is repeated for each device sharing the LPDDR2 bus.
Appropriate Read Latency and Write Latency values are then chosen given device characteristics and the target
operating frequency. Once determined, the RL/WL values are loaded into the Device Feature 2 Mode Register
(MR2). The memory controller is also configured to align with the appropriate RL/WL values for each of the devices
on the LPDDR2 bus.
JEDEC Standard No. 209-2E
Page 229
B.1.11 Increasing the Clock Rate
After the latency values have been changed in both the LPDDR2 devices and in the controller the clock rate can be
increased to the target operating frequency. Figure 135 describes the timings relevant to changing the clock
frequency. In this example, the clock rate is changed while the device is in the Power-Down state. The clock may also
be changed when CKE is HIGH. See the LPDDR2 specification for details.
The device must be stable at the new clock frequency for at least two clock cycles before exiting the Power-Down
state (two clocks (min), CKE returns high). Once CKE returns high the LPDDR2-NVM device will require 10ns to
exit Power-Down (tXP) before accepting the first valid command.
Figure 135 — Clock Rate Change Timings
B.1.12 Data Training
The final step in the boot process is to optimize the controller’s read timings. In particular, this step is used to skew
the data capture point with respect to the DQS_t, DQS_c signal generated by the target memory device during a read
operation. This offset will be different for each device residing on the memory bus, requiring that an offset be
associated with each chip select.
In most implementations the host software will request that the controller perform data training. The controller will
then find the optimal read capture point without intervention from the host. Once the controller has completed data
training, code execution will be redirected back to the LPDDR2-NVM device at the new clock rate.
B.1.13 Summary
This application note has described how a system can boot from an LPDDR2-NVM device that shares the LPDDR2
bus with an LPDDR2-SDRAM device. Only a few extensions to the chipset’s embedded ROM, or dedicated HW, are
required to facilitate booting from the LPDDR2 bus. Once code execution has passed from the embedded ROM, or
dedicated HW, to the LPDDR2-NVM device the remaining boot code takes into account system level characteristics.
CK_t
CKE
CMD
2 clocks (min) 2 clocks (min)
tXP = 10ns
Valid
Command
JEDEC Standard No. 209-2E
Page 230
Annex C LPDDR2-N: Replay Protected Memory Block (RPMB)
C.1 Acronyms
Table 115 — Definition of acronyms
C.2 Introduction
The RPMB feature for LPDDR2-NVM described in this section is optional.
A signed access to one or more Replay Protected Memory Block is provided. This function provides means for the
system to store data to the specific memory area in an authenticated and replay protected manner. This is provided by
first programming authentication key information to the LPDDR2-NVM memory (shared secret), then configuring
one or more RPMB resources.
As the system can not be authenticated yet in this phase, the authentication key programming has to take place in a
secure environment like in an OEM production. Further on the authentication key is utilized to sign the read and write
accesses made to the replay protected memory area with a Message Authentication Code (MAC). Usage write count
register provides additional protection against replay of messages where messages could be recorded and played back
later by an attacker.
C.3 Map of Control Registers (offsets and definitions)
Table 116 describes the Overlay Window register map.
Term Definition
RPMB Replay Protected Memory Block
MAC Message Authentication Code
NVM Non Volatile Memory
OTP One Time Programmable
Table 116 — Overlay Window: Control Register Offsets and Definitions (Part 1 of 2)
Byte-Addressing
Type Register Item
Default Value
(hex)
Notes
Offset
(hex)
# of bytes
(decimal)
0x001 – 0x000 2 R Overlay Window Query String “P” 0x00 - 0x50
0x003 – 0x002 2 R Overlay Window Query String “F” 0x00 - 0x46
0x005 – 0x004 2 R Overlay Window Query String “O” 0x00 - 0x4F
0x007 – 0x006 2 R Overlay Window Query String “W” 0x00 - 0x57
0x009 – 0x008 2 R Overlay Window ID 0x00 - 0x20
0x00B – 0x00A 2 R Overlay Window Revision Vendor-Specific
0x00D – 0x00C 2 R Overlay Window Size Vendor-Specific
0x00F – 0x00E 2 Reserved for JEDEC
0x011 – 0x010 2 R Program-Buffer Offset Vendor-Specific
0x013 – 0x012 2 R Program-Buffer Size Vendor-Specific
0x01F – 0x014 12 Reserved for JEDEC
0x021 – 0x020 2 R JEDEC Manufacturer ID Vendor-Specific
0x023 – 0x022 2 R JEDEC Device ID Vendor-Specific
0x03D – 0x024 26 Reserved for JEDEC
0x03F - 0x03E 2 W Reserved for JEDEC
0x07F – 0x040 64 Vendor-Specific Reserved for Vendor Use Vendor-Specific
JEDEC Standard No. 209-2E
Page 231
NOTE 1 After the successful completion of an authenticated Erase, Program or Overwrite operation the Write
Counter value is automatically incremented by the device and OW Write Counter register is updated with the new
value. The OW Write Counter register can be read only after the execution of an Authenticated Program, Overwrite,
Erase, Write Counter Digest command when the device returns ready (DRB=’1’).
NOTE 2 The MAC, Command Response and Command Result registers can be read only when the device is ready.
0x081 – 0x080 2 W Command Code 0x00 - 0x00
0x083 – 0x082 2 Reserved for JEDEC
0x087 – 0x084 4 R/W Command Data
0x08B – 0x088 4 W Command Address
0x08F – 0x08C 4 Reserved for JEDEC
0x093 – 0x090 4 W Multi-Purpose Register
0xBF - 0x094 44 - Reserved for JEDEC
0x0C1 - 0x0C0 2 W Command Execute 0x00 - 0x00
0x0C7 - 0x0C2 6 - Reserved for JEDEC
0x0C9 - 0x0C8 2 R/W Suspend 0x00 - 0x00
0x0CB - 0x0CA 2 R/W Abort 0x00 - 0x00
0x0CD - 0x0CC 2 R/W Status Register 0x00 - 0x80
0x0CF - 0x0CE 2 R Command Result 0x00 - 0x00 2
0x0DF - 0x0D0 16 Reserved for Vendor Use
0x0FF - 0x0E0 32 - Reserved for Vendor Use
0x10F – 0x100 16 R/W Nonce
0x113 – 0x110 4 R/W Write Counter 1
0x115 – 0x114 2 R Command Response 0x0000 2
0x11F – 0x116 10 - Reserved for JEDEC
0x133 – 0x120 20 R/W MAC Register 2
0x13F – 0x134 12 - Reserved for JEDEC use
Vendor-Specific Vendor-Specific Vendor-Specific Reserved for Vendor Use
Vendor-Specific Vendor-Specific Vendor-Specific Program-Buffer
Table 116 — Overlay Window: Control Register Offsets and Definitions (Part 2 of 2)
Byte-Addressing
Type Register Item
Default Value
(hex)
Notes
Offset
(hex)
# of bytes
(decimal)
JEDEC Standard No. 209-2E
Page 232
C.3.1 Command Result Register
The Command Result Register provides information about the status of the internal Write Counter (valid, expired)
and successfulness of an authenticated operation.
The Command Result Register is valid when the device is ready (DRB = ‘1’).
Note that the Command Result Register may be used by other embedded operations, therefore its content may change
if one of these operations is executed.
Table 117 — Command Result data structure
The table is listing the defined results and possible reasons for failures.
NOTE 1 This value can occur in two cases: either after a successful digest command executed with expired
counter (0x0FFF FFFF), or after a successful authenticated write initiated with a counter value of 0x0FFF FFFE.
NOTE 2 The MAC Register content is not valid when one of these values occurs.
NOTE 3 This value is the only valid Result value until the Authentication Key has been enabled (after which it
can never occur again)
NOTE 4 This value is the only valid Result value if the Authentication Key is enabled but no RPMB resource
is enabled.
NOTE 5 If a non authenticated command is issued on an RPMB range the operation fails, the Status Register
error bits 4 and 5 are set.
NOTE 6 This value can only occur when Write Security Register command is issued.
Bit Name Description
OR[7]
WCS
Write Counter Status
WCS indicates whether the internal Write Counter has reached the maximum
value
0 = write counter is valid
1 = write counter is expired.
OR[6:0]
ROR
RPMB Operation Result
ROR indicates the successfulness of the access made to the Replay Protected
Memory Block
Table 118 — Command Result
Valid
Write
Counter
Expired
Write
Counter
Description
0x00
0x80
(1)
Operation OK
0x01
0x81 General failure
0x02
- Authentication failure (MAC comparison not matching, MAC calculation failure)
0x03
- Counter failure (counters not matching in comparison, counter incrementing failure)
0x04
(2)
0x84
(2)
Address failure (address out of range)
0x05 0x85
Write failure (data/counter/result write failure)
Invalid RPMB Start Address, RPMB End Address values.
0x06
0x86 Read failure (data/counter/result read failure)
0x07
(3,2)
- Authentication Key not enabled yet
0x08
(4,2)
- No RPMB resource enabled yet
0x09
(2)
-
Authenticated command issued during program, overwrite or erase suspend
0x0A
(2)
-
Non Authenticated command issued on an RPMB range
(5)
0x0B
(6,2)
- Authenticated Key, RPMB ID, RPMB Start Address, RPMB End Address Register locked down
JEDEC Standard No. 209-2E
Page 233
C.3.2 Nonce Register
The host shall write 16-Byte Nonce value into this register for the execution of Memory Data Digest and Write
Counter Digest commands. Nonce Register is readable for software debug.
The value of this register is undefined after power up or reset.
This register can be written or read only when the device is ready (DRB =’1’).
C.3.3 OW Write Counter Register
The OW Write Counter Register is a 32-bit Register and shall be written with the expected counter value for the
execution of several authenticated commands.
The value of this register is undefined after power up or reset.
The OW Write Counter Register can be read to retrieve the internal Write Counter value only after the execution of an
Authenticated Erase/Program/Overwrite, Write Counter Digest, when the device returns ready (DRB=’1’).
The internal Write Counter is a nonvolatile register which stores the total amount of successful authenticated
program, overwrite, erase operations executed by the device.
See C.4.1, Write Counter, for details about internal Write Counter.
Table 119 — Nonce Register
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x10F – 0x100 16 R/W Nonce
Table 120 — Write Counter Register
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x113 – 0x110 4 R/W Write Counter
JEDEC Standard No. 209-2E
Page 234
C.3.4 Command Response Register
The Command Response Register can be read only after the execution of an authenticated command and when the
device returns ready (DRB=’1’).
Table 122 defines the value stored in the Command Response Register after the completion of each authenticated
command. This register can be read only when the device is ready (DRB =’1’), and it is updated even when the
operation is aborted or fails.
C.3.5 MAC Register
The MAC Register is a 20-Byte register and shall be written with the expected MAC value for the execution of
several authenticated commands.
This OW register can be read to retrieve the MAC value after the execution of an authenticated command, when the
device returns ready (DRB=’1’).
The MAC register is updated only if the Authentication Key is enabled.
Note that MAC Register content is not valid if there is an attempt to issue an authenticated command during suspend,
or a non authenticated command on an RPMB range, or in case of address failure.
The value of this register is undefined after power up or reset and it is updated with the execution of an authenticated
command.
Table 121 — Command Response Register
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x115 – 0x114 2 R Command Response 0x0000
Table 122 — Response
Command Value
Write Security Register
0x00A3
Read Security Register
0x00AE
Write Counter Digest
0x00A4
Authenticated Single Word Program
0x00A1
Authenticated Single Word Overwrite
0x00A2
Authenticated Buffered Program
0x00A9
Authenticated Buffered Overwrite
0x00AA
Authenticated Block Erase
0x00A0
Memory Data Digest
0x00A6
Table 123 — MAC Register
Byte-Addressing
Type Register Item
Default Value
(hex)
Offset
(hex)
# of bytes
(decimal)
0x133 – 0x120 20 R/W MAC Register
JEDEC Standard No. 209-2E
Page 235
C.4 Write Counter, Authentication Key and RPMB Resource
C.4.1 Write Counter
The Write Counter is an internal 32-bit nonvolatile register used to count the total amount of successful authenticated
program, overwrite, or erase operations executed by the device.
Its initial value after LPDDR2-NVM production is 0x0000 0000. The maximum counter value is 0x0FFF FFFF.
The Write Counter value will be incremented by one automatically by the LPDDR2-NVM Replay Protected Memory
Block engine only if the authenticated program, overwrite, or erase operation is executed successfully (no error flag is
set in the Status Register).
The value can not be reset. After the counter has reached its maximum value (0x0FFF FFFF), it will not be
incremented anymore (overflow prevention), the bit [7] in Command Result Register will be permanently set and the
operation being executed will fail.
C.4.2 Authentication Key
Programmable authentication key register. This register can be programmed or overwritten until the Authentication
Lock-Down bit in the Authentication Configuration Register has been set. This register can not be read. The key is
used by the LPDDR2-NVM Replay Protected Memory Block engine to authenticate the accesses when MAC is
calculated. The Authentication Key is 256-bit and it is written using the Write Security Register command (see
“Write Security Register Command” on page 240).
C.4.3 Authentication Key Configuration Register
The Authentication Key Configuration Register includes the Authentication Enable bit and the Authentication Lock-
Down bit and it is written using the Write Security Register command (see “Write Security Register Command” on
page 240).
The Authentication Enable bit (bit 0 of Authentication Key Configuration Register) shall be written to ‘1’ to enable
the Authentication Key.
If the Authentication Enable bit is not yet programmed to ‘1’, the execution of an authenticated command is not
allowed. If the host attempts to execute an authenticated command, the operation will fail and the message 0x07
(Authentication Enable bit not yet programmed) is returned in Result Command Register.
Authentication Lock-Down bit (bit 1of Authentication Key Configuration Register) shall be written to ‘1’ to
permanently lock the Authentication Key and Authentication Enable bit. When the Authentication Lock-Down bit is
written to ‘1’ the Authentication Key and the Authentication Enable bit can not be modified.
The Authentication Lock-Down bit is OTP.
LPDDR2-NVM device is delivered with Authentication Enable bit and Authentication Lock-Down bit equal to ‘0’
(default value).
Authentication Enable bit and Authentication Lock-Down shall be programmed after the Authentication Key.
Table 124 — Authentication Key Configuration Register Definition
Bit Name Description Default
0
AE
Authentication
Enable bit
0 = Authenticated Operation disabled
1 = Authenticated Operation enabled
‘0’
1
AL
Lock-Down bit
0 = Authentication Key writable
1 = Authentication Key permanently locked
‘0’
from 2 to 15 Reserved - ‘0’
JEDEC Standard No. 209-2E
Page 236
C.4.4 RPMB ID, RPMB Start Address, RPMB End Address
LPDDR2-NVM device supports one or more RPMB resources, the number of supported RPMB resources is vendor
specific. Each RPMB resource is indentified by a 16-bit RPMB ID. If the device supports a single RPMB resource,
the RPMB ID shall be equal to 0x00.
RPMB Start Address and RPMB End Address registers define the RPMB range identified by an RPMB ID.
RPMB Start Address and RPMB End Address shall be less than the device density. RPMB Start Address and RPMB
End Address can be set with 16KByte granularity. Therefore RPMB Start Address bits from 0 to 13 are implied to be
‘0’ and shall be program to ‘0’, and RPMB End Address bits from 0 to 13 are implied to be ‘1’ and shall be
programmed to ‘1’. The RPMB range is determined by RPMB Start Address[Max:14] and RPMB End
Address[Max:14].
In particular, if the device technology requires the Erase command, the RPMB Start/End Address may be equal to the
Block size.
RPMB Start Address and RPMB End Address values shall be written using a single Write Security Register
command. The RPMB End Address value shall be greater than the RPMB Start Address. The device checks if this
requirement is met during Write Security Register command execution.
C.4.5 RPMB Configuration Register
The RPMB Configuration Register includes the RPMB Enable bit and the RPMB Lock-Down bit.
RPMB Enable bit (bit 0 of RPMB Configuration Register) shall be written to ‘1’ to enable the relevant RPMB
resource. If RPMB Enable bit is ‘0’, it is not necessary to use Authenticated Commands to change the RPMB content.
RPMB Start Address and RPMB End Address shall be programmed before the RPMB Enable bit.
RPMB Lock-Down bit (bit 1 of RPMB Configuration Register) shall be written to ‘1’ to permanently lock the
relevant RPMB Start Address, RPMB End Address and RPMB Enable bit. When the RPMB Lock-Down bit is
written to ‘1’ the relevant RPMB Start Address, RPMB End Address and RPMB Enable bit can not be modified.
The RPMB Lock-Down bit is OTP.
LPDDR2-NVM device is delivered with RPMB Lock-Down and RPMB Enable bit equal to ‘0’ (default value) for
each RPMB resource.
Table 125 — RPMB Resource
# of bytes Description
2 RPMB ID
4 RPMB Start Address
4 RPMB End Address
Table 126 — RPMB Configuration Register Definition
Bit Name Description Default
0
RPMBE
RPMB Enable bit
0 = RPMB resource disabled
1 = RPMB resource enabled
‘0’
1
RPMBL
Lock-Down bit
0 = RPMB resource writable
1 = RPMB resource permanently locked
‘0’
from 2 to 15 Reserved - ‘0’
JEDEC Standard No. 209-2E
Page 237
C.5 Message Authentication Code Calculation
The message authentication code (MAC) is calculated using HMAC SHA-1 as defined in [HMAC-SHA]. The
HMAC SHA-1 calculation takes as input a key and a message. The resulting signature (MAC) is 160 bits (20 Bytes).
The key used for the MAC calculation is always the 256 bit Authentication Key stored in the LPDDR2-NVM.
The message used as input to the MAC calculation is the concatenation of some OW registers value, the write
counter, buffer program content for embedded operation using the buffer program, memory content for memory data
digest.
When issuing an Authenticated Erase Command, an Authenticated Single Word/Buffered Program command or an
Authenticated Single Word/Buffered Overwrite command, the host shall calculate the signature as described in
Table 127, and store it in the Overlay Window MAC register.
After the completion of an Authenticated Erase Command, an Authenticated Single Word/Buffered Program
command or an Authenticated Single Word/Buffered Overwrite command, the LPDDR2-NVM device updates the
MAC register as described in Table 128.
After the completion of a Memory Data Digest command or a Write Counter Digest command, the LPDDR2-NVM
device provides the signature calculated as described in Table 128 in the MAC register.
Table 127 — MAC calculation bytes order for command authentication
Field
Authenti-
cated
Erase
Command
Authenti-
cated
Single
Word
Program
(1)

Authenti-
cated
Single
Word
Overwrite
(1)

Authenti-
cated
Buffered
Program
Authenti-
cated
Buffered
Overwrite
(1)

Memory
Data
Digest
Write
Counter
Digest
First CmdCode CmdCode CmdCode CmdCode CmdCode
- -
Second Counter
(4)
Counter
(4)
Counter
(4)
Counter
(4)
Counter
(4)
- -
Third
4 bytes
= 0x00
Data Data MPReg MPReg - -
Fourth Address Address Address Address Address
- -
Fifth
- - - 2 bytes
= 0x00
2 bytes
= 0x00
- -
Sixth - - - PB[D-1:0]
(3)
PB[D-1:0]
(3)
- -
Table 128 — MAC calculation bytes order for Result, Data, Write Counter authentication
Field
Authenti-
cated
Erase
Command
Authenti-
cated
Single
Word
Program
(1)

Authenti-
cated
Single
Word
Overwrite
(1)

Authenti-
cated
Buffered
Program
Authenti-
cated
Buffered
Overwrite
(1)

Memory
Data
Digest
Write
Counter
Digest
First Response Response Response Response Response
Response
Response
Second Counter
(4,6)
Counter
(4,6)
Counter
(4,6)
Counter
(4,6)
Counter
(4,6) 4 bytes
= 0x00
Counter
(4,6)
Third
4 bytes
= 0x00
4 bytes
= 0x00
4 bytes
= 0x00
4 bytes
= 0x00
4 bytes
= 0x00
MPReg
4 bytes
= 0x00
Fourth Address Address Address Address Address Address
4 bytes
= 0x00
Fifth Result Result Result Result Result Result Result
Sixth - - - - - Nonce Nonce
Seventh - - - - -
N bytes
(5)
=
Digested
Data
-
JEDEC Standard No. 209-2E
Page 238
The following notes apply to both Table 127 and Table 128.
NOTE 1 Authenticated Single Word command, Authenticated Single Word Overwrite command and Authenti-
cated Buffered Overwrite command are optional and supported only by some NVM technologies
NOTE 2 Counter = Write Counter[3:0], CmdCode = Command Code[1:0], Data = Command Data[3:0],
MPReg = Multi-Purpose Register[3:0], Address = Command Address[3:0], PB[D-1:0] = Program Buffer[D-1:0]
where D is the top location of the program buffer, Nonce = Nonce[15:0], Result = Command Result[1:0],
Response = Command Response[1:0].
NOTE 3 D is the Program Buffer size. If the amount of bytes being programmed is less then the Program Buf-
fer size, not relevant Program buffer bytes shall be considered 0x00 during MAC calculation, the host shall fill
the entire Program Buffer, “0x00” value shall be written to not relevant Program buffer bytes.
NOTE 4 Four most significant bits of the Write Counter are ‘0’.
NOTE 5 N is the amount of bytes on which the MAC is calculated during Memory Data Digest command.
NOTE 6 The incremented counter value shall be used if Authenticated Erase/Program/Overwrite is completed
successfully.
Example: Assume that the write counter is 0x01234567 and the Program Buffer Size is 32 Bytes. The host wants to
program the pattern 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7 at starting address 0x00000010. The host
set the Overlay window register with the following values: Command Code = 0x00A9, Multi-Purpose Register =
0x00000008, Command Address = 0x00000010, and it loads the pattern into the Program buffer starting at the offset:
Program-Buffer Offset + 0x0010 within the OW.
The HMAC SHA-1 shall be calculated over the following message:
Reference: [HMAC-SHA] H. Krawczyk, M. Bellare, R. Canetti. "HMAC: Keyed-Hashing for Message
Authentication", RFC 2104, February1997.
Com. Code Write Counter Multi-Purpose Register Command Address 2 bytes 0x00
0x00, 0xA9, 0x01, 0x23, 0x45, 0x67, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
Program Buffer[0] ...Program Buffer[15]
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
Program Buffer[16] ...Program Buffer[31]
0xA0, 0xA1, 0xA2, 0xA3, 0xA4 0xA5, 0xA6 0xA7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
JEDEC Standard No. 209-2E
Page 239
C.6 LPDDR2-NVM RPMB commands
This section defines the set of commands for the execution of authenticated operations.
The commands for authenticated operations are: Write Security Register, Authenticated Single Word Program,
Authenticated Single Word Overwrite, Authenticated Buffered Program, Authenticated Buffered Overwrite,
Authenticated Block Erase, Write Counter Digest, Memory Data Digest, Command Result Digest.
Write Security Register command can be used to store the authentication key and configure the RPMB resource.
Write Counter value can be authenticated using the Write Counter Digest command.
Erase, program, or overwrite commands issued in an RPMB range are executed only if the command is successfully
authenticated (MAC provided by the host matches the MAC calculated by the device), and if the write counter value
provided by the host is equal to the write counter values stored in the device.
Table 129 summarizes the command code values for the authenticated commands. The command code shall be
written into the Command Code Register within the Overlay Window (see Overlay Window register map table) to
select the desired operation to be executed.
An embedded controller handles all timings and verifies the correct execution of LPDDR2-NVM operations.
The commands can be initiated when the embedded controller is not busy (DRB = ‘1’). The Device Ready Bit (DRB)
is read as part of the Status Register.
VACC shall not change during the period starting from at least 1us prior to the initiation of any embedded operation
until that embedded operation is complete.
During the execution of an embedded operation, the device can be placed in Power Down mode by driving CKE low,
see Power Down section for detailed description on how to enter and exit Power Down.
Table 129 — LPDDR2 RPMB Commands
Command Code
Write Security Register
0x00A3
Read Security Register
0x00AE
Write Counter Digest
0x00A4
Authenticated Single Word Program
(2)

0x00A1
Authenticated Single Word Overwrite
(3)

0x00A2
Authenticated Buffered Program
0x00A9
Authenticated Buffered Overwrite
(3)
0x00AA
Authenticated Block Erase
0x00A0
Memory Data Digest
0x00A6
NOTE 1 The Command Code Register default value is 0x0000 (NOP). If the Command Execute
Register is set to ‘0x0001’ when Command Code Register is at the default value (0x0000), the
device will become busy and then ready without executing any operation (NOP).
NOTE 2 Authenticated Single Word Program is optional.
NOTE 3 Authenticated Single Word Overwrite and Authenticated Buffered Overwrite are
optional and are only supported by some NVM technologies and some LPDDR2-NVM devices.
JEDEC Standard No. 209-2E
Page 240
C.6.1 Write Security Register Command
Write Security Register command allows to program the Authentication Key, the Authentication Key Configuration,
and to define the RPMB resources. As the system can not be authenticated yet in this phase the authentication key
programming have to take place in a secure environment like in an OEM production.
There are two types of data that can be configured: Authentication Key resource and RPMB resources. Type is
provided using the Command Data [15:0].
Each RPMB resource is identified by an ID. RPMB ID is provided using Command Data [31:16]. The number of
available RPMB resources is vendor specific.
Table 130 shows the value to be loaded into the Command Data Register according to the type of data to be written.
The desired data to be written into the Security Registers shall be stored in the Program Buffer.
The offset of the first Security Register to be written shall be stored in Command Address Register as defined on
Table 131. The Multi-Purpose Register shall contain the number of bytes to be programmed.
The program operation is performed by the embedded controller.
This command can not be issued during suspend.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write the offset of the first Security Register to the Command Address register,
Write Register Type and ID to the Command Data Register,
Write the Data Count value (number of bytes to be programmed) to the Multi-Purpose Register,
Write data into the Program Buffer.
Write 0x00A3 to the Command Code Register,
Write 0x0001 to the Command Execute Register.
Table 130 — Data Type Definition
Table 131 — Security Register Mapping for Write Security Register Command
The Status Register DRB bit, indicates the progress of the Program operation. It should be read to check whether the
operation has completed or not.
After completion of the Program operation (DRB= 1), one of the Status Register error bits (5, 4, 3 and 1) going High
means that an error was detected: either a failure occurred during programming, VACC is outside the allowed voltage
range. See Section Device Status Register for detailed information.
Providing not allowed values for Command Data Register, Command Address Register, and Multi-Purpose Register
can result in undefined operation.
The program operation can not be suspended or aborted.
Authenticated Operations are enabled when Authentication Enable bit in the Authentication Key Configuration
Register is ‘1’.
Command Data Register Field
Data Type
Authentication Key RPMB
Command Data [31:16] ID 0x0000 (default) RPMB ID
Command Data [15:0] Type 0x0000 0x0001
Data Type
Command
Addr. Reg.
Value
Program Buffer Range # of bytes Program Buffer Value
Authentication
Key/Configuration
0x0000 Progr. Buffer[0x01F - 0x000] 32 Authent. Key[0x1F:0x00]
0x0020 Progr. Buffer[0x021 - 0x020] 2 Authent. Key Config. [1:0]
RPMB
0x0000 Progr. Buffer[0x003 - 0x000] 4 RPMB Start Address [3:0]
0x0004 Progr. Buffer[0x007 - 0x004] 4 RPMB End Address [3:0]
0x0008 Progr. Buffer[0x009 - 0x008] 2 RPMB Configuration [1:0]
JEDEC Standard No. 209-2E
Page 241
C.6.1 Write Security Register Command (cont’d)
The Authentication Key can be programmed only when Authentication Lock-Down bit is ‘0’. If there is an attempt to
program the Authentication Key or Authentication Key Configuration when the Authentication Lock-Down bit is ‘1’,
the operation will fail and the Command Result Register is set 0x0B.
RPMB Start Address and RPMB End Address values shall be written with a single Write Security Register command.
RPMB Start Address and RPMB End Address can be programmed only when the relevant RPMB Lock-Down bit is
‘0’. If there is an attempt to program these registers when the RPMB Lock-Down bit is ‘1’, the operation will fail and
the Command Result Register is set 0x0B. Since RPMB Lock-Down bits are OTP, the RPMB resource will no longer
be available after the relevant Lock-Down bit has been set.
The paragraph “RPMB ID, RPMB Start Address, RPMB End Address” on page 236 defines the constraints for
RPMB Start Address value and RPMB End Address value.
The RPMB End Address value shall not be lower than the RPMB Start Address value. The device check if this
requirement is met before programming them. If RPMB End Address value is lower than the RPMB Start Address
value, the programming will fail and the Command Result Register is set 0x05.
Table 132 — Write Security Register Error Conditions
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Write Security Data operation failure.
1 0 0 1 0 0 1 0
Write Security Data operation abort.
a) Attempt to program Authentication Key or
Authentication Key Configuration with Authentication
Lock-Down bit equal to ‘1’
b) Attempt to program RPMB Enable/Start/End address
with RPMB Lock-Down bit equal to ‘1’
1 0 1 1 0 0 0 0
Write Security Data operation abort.
a) Program address outside the allowed address space
b) Invalid RPMB ID
c) Attempt to program invalid RPMB Start/End address
content.
1 0 0 1 1 0 0 0
Write Security Data operation abort.
VACC not at appropriate level for Program operation.
1 1 1 1 0 0 0 0
Write Security Data operation abort.
Attempting to execute the command during Erase
Suspend.
1 0 1 1 0 1 0 0
Write Security Data operation abort.
Attempting to execute the command during Program
Suspend.
1 1 1 1 0 1 0 0
Write Security Data operation abort.
Attempting to execute the command during Erase and
Program Suspend.
JEDEC Standard No. 209-2E
Page 242
C.6.1 Write Security Register Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Write Security Register command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address.
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 DataCount[31:0] is amount of byte being programmed.
NOTE 5 SecRegOffset[31:0] is the target byte offset of the programming operation, SecRegType is the type of
data and SecRegID is the ID of the data to be written (see Table 130, Data Type Definition on page 240 and
Table 131, Security Register Mapping for Write Security Register Command on page 240).
Figure 136 — Write Security Register Flowchart
Write Security Register
Provide Command Code
Write (0x00A3) to address (OWBA+0x080)
Provide Command Address
Write SecRegOffset[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Fill the Program Buffer
Write register value to the program buffer
Provide Data Count
Write DataCount[31:0] to address (OWBA+0x090)
Provide Command Data (Type and ID)
Write SecRegType[15:0] to address (OWBA+0x084)
Write SecRegID[15:0] to address (OWBA+0x086)
JEDEC Standard No. 209-2E
Page 243
C.6.2 Read Security Register Command
RPMB Registers and Authentication Key Configuration Register can be read with the Read Security Register
command (code 0x00AE). The Read Security Register command copies the content of the desired register into the
Command Result. Multiple Read Security Register commands can be used to retrieve the value of registers wider
than Command Result.
There are two types of data that can be read: Authentication Key resource and RPMB resources. Type is provided
using the Command Data [15:0].
Each RPMB resource is identified by an ID. The ID of the resource to be read is provided using Command Data
[31:16].
Table 130 on page 240 shows the values to be loaded into the Command Data Register according to the type of data
to be read.
Table 131 on page 240 shows the offset value that shall be loaded into the Command Address Register to select the
desired portion of the Security Register. Please note that if an attempt is made to read the Authentication Key
Register, the device will return undefined data.
Read Security Register operation is performed by the embedded controller.
This command can not be issued during suspend.
This command cannot be aborted or suspended.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write the desired register offset to the Command Address Register,
Write Register Type and ID to the Command Data Register,
Write 0x00AE to the Command Code Register,
Write 0x0001 to the Command Execute Register,
Read the Security Register data from the Command Result Register, if there are no errors in the Status Regster.
Status Register SR4 (PSB) and SR5 (ESB) bits are set to ‘1’ to indicate that the Read Security Register operation has
failed.
Table 133 — Security Register Mapping for Read Security Register Command
Table 134 — Read Security Register Error Conditions
Data Type
Command
Addr. Reg.
Value
Security Register Mapping
Authentication Key/Configuration 0x0020 Authent. Key Config. [1:0]
RPMB
0x0000 RPMB Start Address [1:0]
0x0002 RPMB Start Address [3:2]
0x0004 RPMB End Address [1:0]
0x0006 RPMB End Address [3:2]
0x0008 RPMB Configuration [1:0]
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 1 1 0 1 0 0
Read Security Register operation failure.
Attempting to execute the command during Program
Suspend
1 1 1 1 0 0 0 0
Read Security Register operation failure.
Attempting to execute the command during Erase
Suspend
1 1 1 1 0 1 0 0
Read Security Register operation failure.
Attempting to execute the command during Erase
Suspend and Program Suspend
JEDEC Standard No. 209-2E
Page 244
C.6.2 Read Security Register Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Read Security Register command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address.
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 SecRegOffset[31:0] is the target byte offset of the Security Register, SecRegType is the type of data
and SecRegID is the ID of the data to be read (see Table 130, Data Type Definition on page 240 and Table 133,
Security Register Mapping for Read Security Register Command on page 243).
.
Figure 137 — Read Security Register Flowchart
.
Read Security Register
Provide Command Code
Write (0x00AE) to address (OWBA+0x080)
Provide Command Data (Type and ID)
Write SecRegType[15:0] to address (OWBA+0x084)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Write SecRegID[15:0] to address (OWBA+0x086)
Read Security Register Data
Read desired register data from the address (OWBA+0x0CE)
Provide Command Address
Write SecRegOffset[31:0] to address (OWBA+0x088)
JEDEC Standard No. 209-2E
Page 245
C.6.3 Write Counter Digest Command
Write Counter Digest command provides the digestment of write counter value (the MAC).
The host shall provide a 16-Byte Nonce, which will be used in the MAC calculation.
Note that the OW Write Counter register is updated during the execution of the authenticated program, overwrite
erase command or Write Counter Digest command; and it shall be read only when the device is ready.
The Write Counter Digest command can not be issued during suspend.
The Write Counter Digest operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00A4 to the Command Code Register,
Write the nonce into the Nonce Register,
Write 0x0001 to the Command Execute Register.
The Status Register DRB bit, indicates the progress of the Write Counter Digest operation. It should be read to check
whether the operation has completed or not.
After completion of the Write Counter Digest operation (DRB= 1), the device updates the following Overlay Window
registers: the Write Counter, the Command Result, the Command Response and the MAC.
See “Message Authentication Code Calculation” on page 237 for details about MAC calculation.
The Nonce value received in the request is available in the Nonce Register.
The Write Counter Digest operation can not be suspended but it can be aborted.
The successfulness of the Write Counter Digest can be checked reading the Command Result Register (when DRB =
’1’).
If Write Counter Digest command is issued during suspend then returned result is 0x09 (Command issued during
suspend), the Status Register error bits 4 and 5 are set, and MAC Register content is no longer valid.
If reading of the counter value fails then returned result is 0x06 (Read failure).
If the Write Counter Digest command is aborted or if some other error occurs then result is 0x01 (General failure).
If counter has expired also bit 7 is set to 1 in returned result (Result values 0x80, 0x86 and 0x81).
Note that the MAC Register content is no longer valid if the Write Counter Digest command has been aborted.
Table 135 — Write Counter Digest Error Conditions
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 1 1 0 1 0 0
Write Counter Digest operation failure.
Attempting to execute the command during Program
Suspend
1 1 1 1 0 0 0 0
Write Counter Digest operation failure.
Attempting to execute the command during Erase
Suspend
1 1 1 1 0 1 0 0
Write Counter Digest operation failure.
Attempting to execute the command during Erase
Suspend and Program Suspend
JEDEC Standard No. 209-2E
Page 246
C.6.3 Write Counter Digest Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Write Counter Digest command
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 Command Result shall be read when the device is ready (DRB==’1’).
NOTE 5 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 138 — Write Counter Digest Flowchart
C.6.4 Memory Data Digest Command
The Memory Data Digest command provides the digestment of data stored in an RPMB range of the memory (the
MAC).
The host shall provide: 16-Byte Nonce, the start address of the data region in the Command Address Register, and the
amount of bytes of the data region in the Multi-Purpose Register.
Start address shall be 32-Byte aligned and the amount of bytes of the data region shall be a multiple of 32 Bytes and
equal or lower than 1 KByte. Providing not allowed values can result in undefined operation.
The device will read the data region and use it for the MAC calculation.
Write Counter Digest
Provide Command Code
Write (0x00A4) to address (OWBA+0x080)
Provide Nonce
Write the Nonce to address (OWBA+0x100)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Read MAC and Write Counter
Read MAC from the address (OWBA+0x120)
Read Command Result
Read Command Result from the address (OWBA+0x0CE)
Read Write Counter from the address (OWBA+0x110)
Invalidate RDB
(5)
JEDEC Standard No. 209-2E
Page 247
Data from the RPMB range can be read issuing PREACTIVE, ACTIVATE and READ commands, and it is not
mandatory to execute the Memory Data Digest command to read RPMB range.
The Memory Data Digest command is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00A8 to the Command Code Register,
Write the nonce into the Nonce Register,
Write the desired address into the Command Address register,
Write the desired amount of bytes into the Multi-Purpose register,
Write 0x0001 to the Command Execute Register.
The Status Register DRB bit, indicates the progress of the authentication operation. It should be read to check
whether the operation has completed or not.
After completion of the Memory Data Digest operation (DRB = ‘1’), the device updates the following Overlay
Window registers: the Command Result, the Command Response, and the MAC.
See “Message Authentication Code Calculation” on page 237 for details about MAC calculation.
The Nonce value received in the request is available in the Nonce Register.
The Memory Data Digest operation can be suspended and it can be aborted.
PSSB (SR.2) bit of the Status Register is set to ‘1’ during Memory Data Digest suspended.
The successfulness of the Memory Data Digest can be checked reading the Command Result Register (when DRB =
’1’).
If Memory Data Digest command is issued during suspend then returned result is 0x09 (Command issued during
suspend), the Status Register error bits 4 and 5 are set, and MAC Register content is no longer valid.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure), no Status
Register error bits are set, and MAC Register content is no longer valid. If the MAC calculation fails Command
Result Register is set to 0x02 (Authentication failure), otherwise it is set to 0x00 (Operation OK). If Memory Data
Digest is aborted or if some other error occurs during the read procedure then returned result is 0x01 (General
failure).
If the counter has expired, bit 7 is also set to 1 in returned result (Result values 0x80, 0x84 and 0x82).
Note that the MAC Register content is no longer valid if the Memory Data Digest command has been aborted.
Table 136 — Memory Data Digest Error Conditions
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 1 1 0 1 0 0
Memory Data Digest operation failure.
Attempting to execute the command during Program
Suspend
1 1 1 1 0 0 0 0
Memory Data Digest operation failure.
Attempting to execute the command during Erase
Suspend
1 1 1 1 0 1 0 0
Memory Data Digest operation failure.
Attempting to execute the command during Erase
Suspend and Program Suspend
JEDEC Standard No. 209-2E
Page 248
C.6.4 Memory Data Digest Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Memory Data Digest command
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 Command Result can be read when the device is ready (DRB==’1’).
NOTE 5 ReadAddr[31:0] is the target byte address of the data region to be digested, and it shall be 32-Byte
aligned.
NOTE 6 DataLength[31:0] is amount of bytes the data region to be digested, and it shall be a multiple of 32.
NOTE 7 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 139 — Memory Data Digest Flowchart
Memory Data Digest
Provide Command Code
Write (0x00A6) to address (OWBA+0x080)
Provide Nonce
Write the Nonce to address (OWBA+0x100)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Provide Command Address
Write ReadAddr[31:0] to address (OWBA+0x088)
Read data, MAC
Read the desired data from the memory array and the MAC
Provide Data Length
Write DataLength[31:0] to address (OWBA+0x090)
Read Command Result
Read Command Result from the address (OWBA+0x0CE)
Invalidate RDB
(7)
JEDEC Standard No. 209-2E
Page 249
C.6.5 Authenticated Block Erase Command
The Authenticated Block Erase command is used to erase a Block included in an RPMB range. It sets all the bits
within the selected Block to ’1’. All previous data in the Block is lost. If the Block is locked, the erase operation will
abort, the data in the Block will not be changed and the Device Status Register will output the error.
The erase operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00A0 to the Command Code Register,
Write any address within the desired block to the Command Address Registers,
Write the expected write counter value into OW Write Counter Register
Write the MAC to MAC register
Write 0x0001 to the Command Execute Register
The Authenticated Block Erase command can be suspended but it can not be aborted.
Note that some NVM technologies do not need Erase command, therefore some NVM devices will not support it.
The Status Register DRB bit indicates the progress of the Authenticated Block Erase operation. It should be read to
check whether the operation has completed or not.
The successfulness of the Authenticated Block Erase command should be checked by reading the Status Register and
the Command Result Register (when DRB = ’1’).
If the Authenticated Block Erase command is issued during suspend, the operation fails, the Status Register error bits
4 and 5 are set, the Command Result register is set to 0x09 (Command issued during suspend), and MAC Register
content is no longer valid.
If the Block being erased is locked an error will be set in the Status Register and the operation will abort without
affecting the data in the memory array.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure), no Status
Register error bits are set, and MAC Register content is no longer valid.
Then the device checks whether the write counter has expired. If the write counter is expired the LPDDR2-NVM
device sets the Command Result Register to 0x85 (write failure, write counter expired), and no Status Register error
bit is set.
If the write counter is not expired, the LPDDR2-NVM starts MAC calculation as described in Table 127, MAC
calculation bytes order for command authentication on page 237. Note that the OW Write Counter Register and not
the internal Write Counter Register shall be used for this calculation.
LPDDR2-NVM device compares the calculated MAC with the MAC value received in the MAC Register.
If the two MAC’s are different the Command Result Register is set to 0x02 (authentication failure). The
Authenticated Block Erase command is not executed.
If the MAC in the request and the calculated MAC are equal then the LPDDR2-NVM device compares the write
counter in the request present in the OW Write Counter Register with the write counter stored in the device. If the two
counters are different then the device sets the Command Result Register to 0x03 (counter failure). The embedded
operation is not executed.
If the MAC and write counter comparisons are successful the command request is considered to be authenticated, and
the erase operation is executed.
If the embedded command is successfully completed the write counter is incremented by 1.
If the erase command fails, the Status Register error bit 5 is set and the returned Command Result Register is 0x05
(write failure).
If some other error occurs during the embedded command procedure then returned result is 0x01 (General failure).
After completion of the Authenticated Block Erase operation (DRB= 1), the device updates the following Overlay
Window registers: the Command Result, the Write Counter, the Command Response and the MAC.
During the busy state, the device updates automatically the OW MAC Register as described in Table 128, MAC
calculation bytes order for Result, Data, Write Counter authentication on page 237.
JEDEC Standard No. 209-2E
Page 250
C.6.5 Authenticated Block Erase Command (cont’d)
The reset command interrupts an ongoing erase operation. As data integrity cannot be guaranteed when the erase
operation is aborted, the memory array content must be considered invalid.
Table 137 — Authenticated Block Erase Error Conditions
7 6 5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 1 0 0 0 0 0 Erase operation failure
1 0 1 0 0 0 1 0
Erase operation abort.
An erase operation was attempted on a locked block.
1 0 1 0 1 0 0 0
Erase operation abort.
VACC not at appropriate level for Erase operation.
1 0 1 1 0 0 0 0
Erase operation abort. Block address outside the
LPDDR2-NVM address space.
1 1 1 1 0 0 0 0
Erase operation abort.
Attempting to erase a block during Erase Suspend.
1 0 1 1 0 1 0 0
Erase operation abort.
Attempting to erase a block during Program Suspend.
1 1 1 1 0 1 0 0
Erase operation abort.
Attempting to erase a block during Erase Suspend and
Program Suspend.
JEDEC Standard No. 209-2E
Page 251
C.6.5 Authenticated Block Erase Command (cont’d)
Figure 140 shows the Authenticated Block Erase Flowchart.

NOTE 1 The Overlay Window must be open to issue Authenticated Block Erase command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 BlockAddr[31:0] is any byte address within the block being erased
NOTE 5 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 140 — Authenticated Block Erase Flowchart
Authenticated Block Erase
Provide Command Code
Write (0x00A0) to address (OWBA+0x080)
Provide Command Addresses
Write BlockAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Provide the Write Counter
Write the expected write counter value to (OWBA+0x110)
Provide the MAC
Write the MAC to address (OWBA+0x120)
Invalidate RDB
(5)
JEDEC Standard No. 209-2E
Page 252
C.6.6 Authenticated Single Word Program Command
The Authenticated Single Word Program command is used to program a single word (2-byte data) into an RPMB
range.
This command is optional.
The program operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00A1 to the Command Code Register,
Write desired location address to the Command Address Register,
Write desired program data to the Command Data Register (Command Data[15:0] only),
Write the expected write counter value into OW Write Counter Register
Write the MAC to MAC register
Write 0x0001 to the Command Execute Register.
Programming can be performed in one block at a time.
The Status Register DRB bit indicates the progress of the Program operation. It should be read to check whether the
operation has completed or not.
After completion of the Program operation (DRB= 1), one of the Status Register error bits (4,3 and 1) going High
means that an error was detected: either a failure occurred during programming, VACC is outside the allowed voltage
range or an attempt to program a locked Block was made. See Section Device Status Register for detailed
information.
The authenticated program operation can be suspended but it can not be aborted.
The successfulness of the Authenticated Single Word Program command should be checked by reading the Status
Register and the Command Result Register (when DRB = ’1’).
If the Authenticated Single Word Program command is issued during suspend, the operation fails, the Status Register
error bits 4 and 5 are set, the Command Result register is set to 0x09 (Command issued during suspend), and MAC
Register content is no longer valid.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure), no Status
Register error bits are set, and MAC Register content is no longer valid.
The device checks whether the write counter has expired. If the write counter is expired the LPDDR2-NVM device
sets the Command Result Register to 0x85 (write failure, write counter expired), and no Status Register error bit is
set.
If the write counter is not expired, the LPDDR2-NVM starts MAC calculation as described in Table 127, MAC
calculation bytes order for command authentication on page 237. Note that the OW Write Counter Register and not
the internal Write Counter Register shall be used for this calculation.
LPDDR2-NVM device compares the calculated MAC with the MAC value received in the MAC Register.
If the two MAC’s are different the Command Result Register is set to 0x02 (authentication failure). The
Authenticated Single Word Program command is not executed.
If the MAC in the request and the calculated MAC are equal then the LPDDR2-NVM device compares the write
counter in the request present in the OW Write Counter Register with the write counter stored in the device. If the two
counters are different then the device sets the Command Result Register to 0x03 (counter failure). The embedded
operation is not executed.
If the MAC and write counter comparisons are successful the command request is considered to be authenticated, and
the program operation is executed.
If the embedded command is successfully completed the write counter is incremented by 1.
If the program command fails, the Status Register error bit 4 is set and the returned Command Result Register is 0x05
(write failure).
If some other error occurs during the embedded command procedure then returned result is 0x01 (General failure).
After completion of the Authenticated Single Word Program operation (DRB= 1), the device updates the following
Overlay Window registers: the Command Result, the Write Counter, the Command Response and the MAC.
During the busy state, the device updates automatically the OW MAC Register as described in Table 128, MAC
calculation bytes order for Result, Data, Write Counter authentication on page 237.
JEDEC Standard No. 209-2E
Page 253
C.6.6 Authenticated Single Word Program Command (cont’d)
The reset command interrupts an ongoing program operation. As data integrity cannot be guaranteed when the
program operation is aborted, the memory array content must be considered invalid.
Some NVM technologies support the Authenticated Single Word Program command only under particular
conditions.
For example, for LPDDR2-NVM device that has the notion of program region, Authenticated Single Word Program
Command is supported only by program regions configured in the Control Program mode, and with Command
Address value belonging to a particular portion of the program region.
If an Authenticated Single Word Program command is issued to a Program Region configured in the Object Program
mode, the Program operation is aborted and PSB and OMSB Status Register bits are set.
For details about program region and program method see the application note.

Table 138 — Authenticated Single Word Program Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Authenticated Single Word Program operation failure.
1 0 0 1 0 0 1 0
Authenticated Single Word Program operation abort.
A program operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Authenticated Single Word Program operation abort.
VACC not at appropriate level for Program operation.
1 0 1 1 0 0 0 0
Authenticated Single Word Program operation abort.
Program address outside the LPDDR2-NVM address
space
1 0 1 1 0 1 0 0
Authenticated Single Word Program operation abort.
Attempting to program during Suspend.
JEDEC Standard No. 209-2E
Page 254
C.6.6 Authenticated Single Word Program Command (cont’d)
NOTE 1 The Overlay Window must be open to issue Authenticated Single Word Program command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 ProgrAddr[31:0] is the target byte address of the programming operation, and ProgrAddr[0] shall be ‘0’.
NOTE 5 ProgrData[15:0] is the desired 2-byte data to be programmed.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 141 — Authenticated Single Word Program Flowchart
Program using Authenticated Single Word Program
Provide Command Code
Write (0x00A1) to address (OWBA+0x080)
Provide Command Addresses
Write ProgrAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Provide Command Data
Write ProgrData[15:0] to address (OWBA+0x084)
Provide the Write Counter
Write the expected write counter value to (OWBA+0x110)
Provide the MAC
Write the MAC to address (OWBA+0x120)
Invalidate RDB
JEDEC Standard No. 209-2E
Page 255
C.6.7 Authenticated Single Word Overwrite Command
Authenticated Single Word Overwrite is supported only by some NVM technologies and some LPDDR2-NVM
devices.
The Authenticated Single Word Overwrite command is used to write a single word (2-byte data) into an RPMB range.
The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’.
With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With
the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’
are not.
The overwrite operation is performed by the embedded controller.
The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence.
The Command Sequence is:
Write 0x00A2 to the Command Code Register,
Write desired location address to the Command Address Register,
Write desired program data to the Command Data Register (Command Data[15:0] only),
Write the expected write counter value into OW Write Counter Register
Write the MAC to MAC register
Write 0x0001 to the Command Execute Register.
Overwriting can be performed in one block at a time.
The Status Register DRB bit, indicates the progress of the Overwrite operation. It should be read to check whether the
operation has completed or not.
After completion of the overwrite operation (DRB= 1), one of the Status Register error bits (4, 3 and 1) going High
means that an error was detected: either a failure occurred during overwriting, VACC is outside the allowed voltage
range or an attempt to overwrite a locked Block was made. See “Status Register” on page 51 for detailed
information.
The overwrite operation can be suspended but it can not be aborted.
The successfulness of the Authenticated Single Word Overwrite command should be checked by reading the Status
Register and the Command Result Register (when DRB = ’1’).
If the Authenticated Single Word Overwrite command is issued during suspend, the operation fails, the Status
Register error bits 4 and 5 are set, the Command Result register is set to 0x09 (Command issued during suspend), and
MAC Register content is no longer valid.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure), no Status
Register error bits are set, and MAC Register content is no longer valid.
The device checks whether the write counter has expired. If the write counter is expired the LPDDR2-NVM device
sets the Command Result Register to 0x85 (write failure, write counter expired), and no Status Register error bit is
set.
If the write counter is not expired, the LPDDR2-NVM performs MAC calculation as described in Table 127, MAC
calculation bytes order for command authentication on page 237. Note that the OW Write Counter Register and not
the internal Write Counter Register shall be used for this calculation.
LPDDR2-NVM device compares the calculated MAC with the MAC value received in the MAC Register.
If the two MAC’s are different the Command Result Register is set to 0x02 (authentication failure). The
Authenticated Single Word Overwrite command is not executed.
If the MAC in the request and the calculated MAC are equal then the LPDDR2-NVM device compares the write
counter in the request present in the OW Write Counter Register with the write counter stored in the device. If the two
counters are different then the device sets the Command Result Register to 0x03 (counter failure). The embedded
operation is not executed.
If the MAC and write counter comparisons are successful the command request is considered to be authenticated, and
the overwrite operation is executed.
C.6.7 Authenticated Single Word Overwrite Command (cont’d)
JEDEC Standard No. 209-2E
Page 256
If the embedded command is successfully completed the write counter is incremented by 1.
If the overwrite command fails, the Status Register error bit 4 is set and the returned Command Result Register is
0x05 (write failure).
If some other error occurs during the embedded command procedure then returned result is 0x01 (General failure).
After completion of the Authenticated Single Word Overwrite operation (DRB= 1), the device updates the following
Overlay Window registers: the Command Result, the Write Counter, the Command Response and the MAC.
During the busy state, the device updates automatically the OW MAC Register as described in Table 128, MAC
calculation bytes order for Result, Data, Write Counter authentication on page 237.
The reset command interrupts an ongoing program operation. As data integrity cannot be guaranteed when the
overwrite operation is aborted, the memory array content must be considered invalid.
.
Table 139 — Authenticated Single Word Overwrite Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Single Word Overwrite operation failure.
1 0 0 1 0 0 1 0
Single Word Overwrite operation abort. An overwrite
operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Single Word Overwrite operation abort.
Program voltage violation.
1 0 1 1 0 0 0 0
Single Word Overwrite operation abort. Overwrite
address outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Single Word Overwrite operation abort.
Attempting to program during Overwrite suspend or
Program Suspend.
JEDEC Standard No. 209-2E
Page 257
C.6.7 Authenticated Single Word Overwrite Command (cont’d)
NOTE 1 The Overlay Window must be open to issue the Authenticated Single Word Overwrite command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 OverwAddr[31:0] is the target byte address of the overwriting operation, and OverwAddr[0] shall be ‘0’.
NOTE 5 OverwData[15:0] is the desired 2-byte data to be overwritten.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 142 — Authenticated Single Word Overwrite Flowchart
Overwrite using Authenticated Single Word Overwrite
Provide Command Code
Write (0x00A2) to address (OWBA+0x080)
Provide Command Addresses
Write OverwAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Provide Command Data
Write OverwData[15:0] to address (OWBA+0x084)
Provide the Write Counter
Write the expected write counter value to (OWBA+0x110)
Provide the MAC
Write the MAC to address (OWBA+0x120)
Invalidate RDB
JEDEC Standard No. 209-2E
Page 258
C.6.8 Authenticated Buffered Program Command
The Authenticated Buffered Program Command makes use of the device’s Program Buffer to speed up programming.
The Authenticated Buffered Program command dramatically reduces in-system programming time compared to other
non-buffered program commands.
If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program
Buffer and programmed into the specified N-Byte aligned location in the main array. The region is determined by bit
[31: K] of the Command Address Register value, where N=2
k
.

The first word data of the Program Buffer to be programmed depends on bit [K-1:0] of Command Address value.
The programming operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data
Count value is in units of bytes and written in the Multi-Purpose Registers.
Note that the host shall fill the entire Program Buffer even if the amount of bytes being programmed is less than the
Program Buffer size; “0x00” value shall be written to not relevant Program buffer bytes.
If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (N-
byte), the programming operation ends without programming the memory array and the Status Register will show an
error (0xB0).
The programming operation doesn't wrap within the program buffer and doesn't cross into the next programming
region.
The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence.
The Command Sequence is:
Write the starting address to the Command Address register,
Write the Data Count value (number of bytes to be programmed) to the Multi-Purpose Register,
Write the expected write counter value into OW Write Counter Register
Write the MAC to MAC register
Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space,
Write 0x00A9 to the Command Code Register,
Write 0x0001 to the Command Execute Register.
The Authenticated Buffered Program command can be suspended but it can not be aborted.
The Status Register DRB bit, indicates the progress of the Authenticated Buffered Program operation. It should be
read to check whether the operation has completed or not.
The successfulness of the Authenticated Buffered Program command should be check by reading the Status Register
and the Command Result Register (when DRB = ’1’).
If Authentication Buffered Program command is issued during suspend, the operation fails, the Status Register error
bits 4 and 5 are set, and the Command Result register is set to 0x09 (Command issued during suspend), and MAC
Register content is no longer valid.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure) and no Status
Register error bits are set, and MAC Register content is no longer valid.
If the Block being programmed is locked an error will be set in the Status Register and the operation will abort
without affecting the data in the memory array.
Then the device checks whether the write counter has expired. If the write counter is expired the LPDDR2-NVM
device sets the Command Result Register to 0x85 (write failure, write counter expired), and no Status Register error
bit is set.
If the write counter was not expired, the LPDDR2-NVM starts the MAC calculation as described in Table 127, MAC
calculation bytes order for command authentication on page 237. Note that the OW Write Counter Register and not
the internal Write Counter Register shall be used for this calculation.
LPDDR2-NVM device compares the calculated MAC with the MAC value received in the MAC Register.
If the two MAC’s are different the Command Result Register is set to 0x02 (authentication failure). The Buffered
Program command is not executed.
If the MAC in the request and the calculated MAC are equal then the LPDDR2-NVM device compares the write
counter in the request present in the OW Write Counter Register with the write counter stored in the device. If the two
counters are different then device sets the Command Result Register to 0x03 (counter failure). The embedded
operation is not executed.
JEDEC Standard No. 209-2E
Page 259
C.6.8 Authenticated Buffered Program Command (cont’d)
If the MAC and write counter comparisons are successful the command request is considered to be authenticated, and
the program operation is executed.
If the embedded command is successfully completed the write counter is incremented by 1.
If the buffered program command fails, the Status Register error bit 4 is set and the returned Command Result
Register is 0x05 (write failure).
If some other error occurs during the embedded command procedure then returned result is 0x01 (General failure).
After completion of the Authenticated Buffered Program operation (DRB= 1), the device updates the following
Overlay Window registers: the Command Result, the Write Counter, the Command Response and the MAC.
During the busy state, the device updates automatically the MAC OW Register as described in Table 128 MAC
calculation bytes order for Result, Data, Write Counter authentication on page 237.
The reset command interrupts an ongoing program operation. As data integrity cannot be guaranteed when the
program operation is aborted, the memory array content must be considered invalid.
Table 140 — Buffered Program Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Buffered Program operation failure.
1 0 0 1 0 0 1 0
Buffered Program operation abort. An program operation
was attempted on a locked block.
1 0 0 1 1 0 0 0
Buffered Program operation abort.
Invalid VACC voltage.
1 0 1 1 0 0 0 0
Buffered Program operation abort. Program address
outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Buffered Program operation abort.
Attempting to program during Program Suspend.
1 0 1 1 0 0 0 0
Buffered Program operation abort.
Command Address [K-1:0] value plus the Data Count
Register value exceeds the program buffer boundary (it is
greater than N byte).
JEDEC Standard No. 209-2E
Page 260
C.6.8 Authenticated Buffered Program Command (cont’d)
Figure 143 shows the Authenticated Buffered Program Flowchart.
NOTE 1 The Overlay Window must be open to issue Buffered Program command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 DataCount[31:0] is amount of byte being programmed
NOTE 5 ProgrAddr[31:0] is the target byte address of the programming operation.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 143 — Authenticated Buffered Program Flowchart
Provide Command Code
Write (0x00A9) to address (OWBA+0x080)
Provide Command Address
Write ProgrAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Fill the Program Buffer
Write program data to the program buffer
Provide Data Count
Write DataCount[31:0] to address (OWBA+0x090)
Provide the Write Counter
Write the expected write counter value to (OWBA+0x110)
Provide the MAC
Write the MAC to address (OWBA+0x120)
Authenticated Program using Program Buffer
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 261
C.6.9 Authenticated Buffered Overwrite Command
This is a command supported only by some NVM technologies and LPDDR2-NVM devices.
The Authenticated Buffered Overwrite Command makes use of the device’s Program Buffer to speed up overwriting
data to the memory array. The Authenticated Buffered Overwrite command reduces in-system overwriting time
compared to other non-buffered overwrite commands.
The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’.
With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With
the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’
are not.
If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program
Buffer and overwritten into the specified N-Byte aligned location in the main array. The region is determined by bit
[31: K] of the Command Address Register value, where N=2
k
.
The first word data of the Program Buffer to be overwritten depends on bit [K-1:0] of Command Address value. The
overwriting operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data Count
value is in units of bytes and written in the Multi-Purpose Registers.
Note that the host shall fill the entire Program Buffer even if the amount of bytes being programmed is less than the
Program Buffer size; “0x00” value shall be written to not relevant Program buffer bytes.
If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (N-
byte), the overwriting operation ends without overwriting the memory array and the Status Register will show an
error (0xB0).
The overwriting operation doesn't wrap within the program buffer and doesn't cross into the next programming
region.
The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence.
The Command Sequence is:
Write the starting address to the Command Address Registers,
Write the Data Count value (number of bytes to be overwritten) to the Multi-Purpose Registers,
Write the expected write counter value into OW Write Counter Register
Write the MAC to MAC register
Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space,
Write 0x00AA to the Command Code Register,
Write 0x0001 to the Command Execute Register.
If the Block being overwritten is locked an error will be set in the Status Register and the operation will abort without
affecting the data in the memory array.
The Authenticated Buffered Overwrite command can be suspended but it can not be aborted.
The Status Register DRB bit, indicates the progress of the Authenticated Overwrite operation. It should be read to
check whether the operation has completed or not.
The successfulness of the Authenticated Buffered Overwrite command should be checked by reading the Status
Register and the Command Result Register (when DRB = ’1’).
If the Authenticated Buffered Overwrite command is issued during suspend, the operation fails, the Status Register
error bits 4 and 5 are set, the Command Result register is set to 0x09 (Command issued during suspend), and MAC
Register content is no longer valid.
If the address is outside RPMB range then Command Result Register is set to 0x04 (Address failure), no Status
Register error bits are set, and MAC Register content is no longer valid.
If the Block being programmed is locked an error will be set in the Status Register and the operation will abort
without affecting the data in the memory array.
Then the device checks whether the write counter has expired. If the write counter is expired the LPDDR2-NVM
device sets the Command Result Register to 0x85 (write failure, write counter expired), and no Status Register error
bit is set.
If the write counter is not expired, the LPDDR2-NVM starts MAC calculation as described in Table 127, MAC
calculation bytes order for command authentication on page 237. Note that the OW Write Counter Register and not
the internal Write Counter Register shall be used for this calculation.
LPDDR2-NVM device compares the calculated MAC with the MAC value received in the MAC Register.
JEDEC Standard No. 209-2E
Page 262
C.6.9 Authenticated Buffered Overwrite Command (cont’d)
If the two MAC’s are different the Command Result Register is set to 0x02 (authentication failure). The
Authenticated Buffered Overwrite command is not executed.
If the MAC in the request and the calculated MAC are equal then the LPDDR2-NVM device compares the write
counter in the request present in the OW Write Counter Register with the write counter stored in the device. If the two
counters are different then the device sets the Command Result Register to 0x03 (counter failure). The embedded
operation is not executed.
If the MAC and write counter comparisons are successful the command request is considered to be authenticated, and
the overwrite operation is executed.
If the embedded command is successfully completed the write counter is incremented by 1.
If the buffered overwrite command fails, the Status Register error bit 4 is set and the returned Command Result
Register is 0x05 (write failure).
If some other error occurs during the embedded command procedure then returned result is 0x01 (General failure).
After completion of the Authenticated Buffered Overwrite operation (DRB= 1), the device updates the following
Overlay Window registers: the Command Result, the Write Counter, the Command Response and the MAC.
During the busy state, the device updates automatically the OW MAC Register as described in Table 128, MAC
calculation bytes order for Result, Data, Write Counter authentication on page 237.
The reset command interrupts an ongoing overwrite operation. As data integrity cannot be guaranteed when the
program operation is aborted, the memory array content must be considered invalid.
Table 141 — Authenticated Buffered Overwrite Error Conditions
NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.
7 6
(1)
5 4 3 2 1 0 Description
DRB ESSB ESB PSB VSESB PSSB BLSB -
1 0 0 1 0 0 0 0 Buffered Overwrite operation failure.
1 0 0 1 0 0 1 0
Buffered Overwrite operation abort. An overwrite
operation was attempted on a locked block.
1 0 0 1 1 0 0 0
Buffered Overwrite operation abort.
Invalid VACC voltage.
1 0 1 1 0 0 0 0
Buffered Overwrite operation abort. Overwrite address
outside the LPDDR2-NVM address space
1 0 1 1 0 1 0 0
Buffered Overwrite operation abort.
Attempting to overwrite during Overwrite Suspend or
Program Suspend.
1 0 1 1 0 0 0 0
Buffered Overwrite operation abort.
Command Address [K-1:0] value plus the Data Count
Register value exceeds the program buffer boundary (it
is greater than N byte).
JEDEC Standard No. 209-2E
Page 263
C.6.9 Authenticated Buffered Overwrite Command (cont’d)
Figure 144 shows the Authenticated Buffered Overwrite Flowchart.
NOTE 1 The Overlay Window must be open to issue Authenticated Buffered Overwrite command.
NOTE 2 OWBA is the byte address of the Overlay Window Base Address
NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.
NOTE 4 DataCount[31:0] is amount of byte being overwritten
NOTE 5 OverwAddr[31:0] is the target byte address of the overwriting operation.
NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and
RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.
Figure 144 — Authenticated Buffered Overwrite Flowchart
Overwrite using Authenticated Program Buffer
Provide Command Code
Write (0x00AA) to address (OWBA+0x080)
Provide Command Address
Write OverwAddr[31:0] to address (OWBA+0x088)
Execute (Begin)
Write (0x0001) to address (OWBA+0x0C0)
Poll Device Ready bit
Repeat:
1) Read (OWBA+0x0CC) (Status Register)
2) Test only bit 7 (DRB)
Until DRB == 1 (Ready)
End
Fill the Program Buffer
Write overwrite data to the program buffer
Provide Data Count
Write DataCount[31:0] to address (OWBA+0x090)
Provide the MAC
Write the MAC to address (OWBA+0x120)
Provide the Write Counter
Write the expected write counter value to (OWBA+0x110)
Invalidate RDB
(6)
JEDEC Standard No. 209-2E
Page 264
C.7 Dual operations with Authenticated Command
Please note: this section is meant to replace section Dual operations and multiple partition architecture on page 80
in the LPDDR2 Jedec standard spec.
In some LPDDR2-NVM devices, the memory array may be divided into two or more partitions (multiple partition
architecture). Refer to vendor datasheets to determine support for multiple partition architecture.
LPDDR2-NVM devices that support multiple partition architecture provide greater flexibility for software developers
to split the code and data spaces within the memory array. The dual operations feature simplifies the software
management of the device by allowing code to be executed from one partition while another partition is being
programmed or erased.
The dual operations feature means that while programming or erasing in one partition, read operations are possible in
another partition with zero latency (only one partition at a time is allowed to be in program or erase mode).
If a read operation is required in a partition, which is programming or erasing, the program or erase operation can be
suspended.
Also, if the suspended operation is erase then a program command can be issued to another block, so the device can
have one block in erase suspend mode, one programming, and other partitions available for read operations.
For the complete list of dual operations allowed, refer to the device datasheet.
Table 142 — Simultaneous operations allowed in the same partition
NOTE 1 Depending on the Overlay Window status and the target read address, data may come from the mem-
ory array or from the overlay window.
NOTE 2 Non-Authenticated Program operations include: Single Word Program, Single Word Overwrite, Buff-
ered Program, Buffered Overwrite.
NOTE 3 Authenticated Operations include: Authenticated Single Word Program, Authenticated Single Word
Overwrite, Authenticated Buffered Program, Authenticated Buffered Overwrite, Authenticated Block Erase,
Memory Data Digest, Write Security Register, Read Security Register, Write Counter Digest.
NOTE 4 Programming is defined by the execution of one of the following operations: Single Word Program,
Single Word Overwrite, Buffered Program, Buffered Overwrite, Authenticated Single Word Program, Authenti-
cated Single Word Overwrite, Authenticated Buffered Program, Authenticated Buffered Overwrite.
NOTE 5 Programming may occur during erase suspended.
NOTE 6 Erasing states is defined by the execution of one of the following operations: Block Erase, Authenti-
cated Block Erase.
NOTE 7 LPDDR2-NVM will output invalid data if the read operation occurs in the memory area that is being
programmed.
NOTE 8 LPDDR2-NVM will output invalid data if the read operation occurs in the block that is being erased.
NOTE 9 Not allowed in the block that is being erased.
Device Status
Operations allowed in the same partition
Read
(1)
Non-Authenticated
Program
(2)
Non-Authenticated
Block Erase
Authenticated
Operations
(3)
Idle Yes Yes Yes Yes
Programming
(4,5)
No No No No
Erasing
(6)
No No No No
Program suspended Yes
(7)
No No No
Erase suspended Yes
(8)
Yes
(9)
No No
Authenticated operation suspended
(3)
Yes
(7)
No No No
Memory Data Digest No No No No
JEDEC Standard No. 209-2E
Page 265
C.7 Dual operations with Authenticated Command (cont’d)
Table 143 — Simultaneous operations allowed in other partitions
NOTE 1 Depending on the Overlay Window status and the target read address, data may come from the mem-
ory array or from the overlay window.
NOTE 2 Programming may occur during erase suspended.
NOTE 3 The following authenticated operations can be suspended: Authenticated Single Word Program,
Authenticated Single Word Overwrite, Authenticated Buffered Program, Authenticated Buffered Overwrite,
Authenticated Block Erase, Memory Data Digest.
Device Status
Operations allowed in another partition
Read
(1)
Non-Authenticated
Program
Non-Authenticated
Block Erase
Authenticated
Operations
Idle Yes Yes Yes Yes
Programming
(2)
Yes No No No
Erasing Yes No No No
Program suspended Yes No No No
Erase suspended Yes Yes No No
Authenticated operation
suspended
(3)
Yes No No No
Memory Data Digest Vendor Specific No No No
JEDEC Standard No. 209-2E
Page 266
Annex D (informative) Differences between Document Revisions
D.1 Initial Release JESD209-2
LPDDR2 Specification Released as JESD209-2.
D.2 JESD209-2 Updated to JESD209-2A
Table 144 — Changes from JESD209-2 to JESD209-2A
Changes Sections Effected Description of Changes
Added RZQI to
Mode Register 0
“Power Ramp and Device Initialization” on page 28
“Mode Register Assignment in LPDDR2
SDRAM/NVM(Common part)” on page 32
MR0, page 34
MR10, page 40
Added Optional RZQI
information to Mode Register 0
to determine the connection of ZQ-pin
Clarified Row Data
Buffer Write policy
“Overlay Window” on page 47
Row Data Buffers are considered to
be Write through structures. All writes
to the Overlay Window is completed
when the issuing Write Command is
completed.
Clarified BST during
tRP for LPDDR2-
NVM
“LPDDR2-N: Burst Read operation followed by
Activate or Preactive” on page 106
Clarification that a BST command is
allowed during the tRP period for
LPDDR2-NVM.
Clarified device
temperature
monitoring during
power down
“Temperature Sensor” on page 129
The LPDDR2 device shall monitor the
device temperature and update MR4
during idle and active power down,
and in self-refresh states according to
tTSI.
Clarified tMRW in
timing diagrams
“LPDDR2-N: Burst Write Followed by MRW: WL = 1,
BL = 4” on page 133
“LPDDR2-N: Burst Read followed by MRW: RL = 3,
BL = 4” on page 133
Replaced T8 in both timing diagrams
with Tx to clarify that tMRW lasts for
greater than 3 cycles.
Replaced precharge
power down with
idle power down in
text
“Power-down” on page 138
The precharge power down state in
LPDDR2 was renamed to idle power
down. This change is semantic.
Removed CKE from
notes below Input
Signal Figure
“LPDDR2-200 to LPDDR2-400 Input Signal” on page
165
“LPDDR2-466 to LPDDR2-1066 Input Signal” on
page 164
CKE is a LVCMOS input signal and
does not belong in this input signal
diagram.
Changed switching
definition for IDD4R
and IDD4W
“Definition of Switching for IDD4R” on page 185
“Definition of Switching for IDD4W” on page 185
Changed the definition of the CA3-
CA9 inputs during the N+1 and N+2
cycles in order to maintain accesses
to the same banks/RBs during the
Read/Write burst measurement
Added IDD3NS and
IDD2NS to IDD
specifications
parameters
“LPDDR2 IDD Specification Parameters and
Operating Conditions” on page 186
Added IDD2NS and IDD3NS to the
IDD specification table in order to
have IDD measurement conditions for
the non-power down clock stop mode.
Fixed error in
LPDDR2-N
program/erase
currents
“LPDDR2 IDD Specification Parameters and
Operating Conditions” on page 186
Removed CKE is HIGH from the
LPDDR2-N program/erase currents.
CKE is LOW is the current condition.
tJIT(duty) definition
updated
“Definition for duty cycle jitter tJIT(duty)” on page 191
“LPDDR2 AC Timing Table*9” on page 197
Updated Clock Duty Cycle Jitter
definition and added table entry.
JEDEC Standard No. 209-2E
Page 267
Removed tCK, tCH,
tCL, and tHP table
entries
“LPDDR2 AC Timing Table*9” on page 197
tCK, tCL, tCH, and tHP definitions are
redundant to the tCK(avg), tCL(avg),
and tCH(avg) definitions.
Clarify Deep Power-
Down Entry
“LPDDR2-SX: Deep Power-Down” on page 145
Entry into Deep Power-Down is only
from the idle state.
Added Package
diagrams
“Package ballout & addressing” on page 2
Added PoP, MCP, and Discrete
packages for LPDDR2
Changed tTSI
timing variable
“Temperature Sensor” on page 129 Changed tTSI from 16ms to 32ms.
Changed Overlay
Window Location
0x03E - 0x03F
Overlay Window: Control Register Offsets and
Definitions on page 48
Changed these locations from
Reserved to Write-Only Reserved
Fixed typo in Self-
Refresh diagram
notes
“LPDDR2-SX: Definition of tSRF” on page 119
Fixed typo for the refresh window
symbol. Changed tREF to tREFW.
Fixed Typo in Bank-
Masking section for
LPDDR2-S4
“LPDDR2-S4: Partial Array Self-Refresh: Bank
Masking” on page 126
Fixed typo in the wording on the Bank
Masking section for PASR for
LPDDR2-S4.
Added clarification
for Overlay Window
in LPDDR2-NVM
Flow Charts
“Overlay Window Enable and Disable” on page 58
Added the following sentence to notes
for the flowcharts for LPDDR2-NVM:
“Enabling the Overlay Window is not
mandatory if the Overlay Window is
already open. “
Added clarification
for MRR to MRW
and MRR to Write
timing
Figure 79 on page 127
MRR to MRW and MRR to Write
timing clarified.
Table 144 — Changes from JESD209-2 to JESD209-2A
Changes Sections Effected Description of Changes
JEDEC Standard No. 209-2E
Page 268
D.3 JESD209-2A Updated to JESD209-2B

Table 145 — Changes from JESD209-2A to JESD209-2B
Changes Sections Effected Description of Changes
Fixed power down
diagrams to show
appropriate timing
from CKE going
LOW to CK “don’t
care” and exiting PD
“LPDDR2-SX: Self-Refresh Operation” on page 125
“LPDDR2-SX: Basic power down entry and exit
timing diagram” on page 138
“LPDDR2-N: Basic power down entry and exit timing
diagram” on page 139
“LPDDR2-SX: Deep power down entry and exit
timing diagram” on page 145
Clock may be stopped only when
CK_t is LOW. Figure previously
implied that clock may be stopped
when CK_t was HIGH. Two valid
clocks must be issued prior to exiting
Power Down states.
Timing diagram had
incorrect axis labels
“Differential Output Slew Rate Definition” on page
173
Fixed axis labels. VOH(AC) ->
VOHdiff(AC), VREF -> 0, VOL(AC) ->
VOLdiff(AC)
Fixed typo in notes
“162-ball x16/x32 LPDDR2 and SDR-Flash package
ballout” on page 8
Incorrect row numbers in note 1 for
package ballout. Fixed to indicate 20
rows instead of 17.
Clarified pad
sequence
“LPDDR2 Pad Sequence” on page 11
Added note to clarify pad sequence.
CA and DQ pads are on opposite
sides of the die.
Clarified Read to
Precharge with
truncated burst
“LPDDR2-SX: Burst Read operation followed by
Precharge” on page 110
Added text clarifying that the effective
BL shall be used when calculating
Read to Precharge.
Added Section on
Row Data Buffer
Incoherency
“Row Data Buffer Incoherency” on page 79
Added text to explain a situation with
Row Data Buffer Incoherency when
the device is programmed
Removed “Enable
Overlay Window”
and “Disable
Overlay Window”
from NVM
flowcharts
“Block Lock Command Flowchart” on page 60,
“Block Unlock Flowchart” on page 62, “Block Lock-
Down Command Flowchart” on page 64, “Block
Erase Flowchart” on page 66, “Single Word Program
Flowchart” on page 68, “Single Word Overwrite
Flowchart” on page 70, “Buffered Program Flowchart”
on page 72, “Buffered Overwrite Flowchart” on page
74, “Program/Erase Resume Command Flowchart”
on page 77
Removed “Enable Overlay Window”
and “Disable Overlay Window” and
related note from NVM flow charts.
This was done to simplify the flow
charts and to avoid confusion about
when to open and close the overlay
window.
Clarified MRR and
MRW in NVM Truth
Table
“Current State Row Buffer n - Command to Row
Buffer m” on page 157
MRR is allowed for Preactivating
state, while MRW is not. Also
corrected note numbers in table.
Clarified that BL in
Read to Activate for
NVM.
“LPDDR2-N: Burst Read operation followed by
Activate or Preactive” on page 106
BL is the effective BL for Read to
Activate calculation for NVM.
Clarified “effective
BL” in timing
diagrams for Read
to Activate and
Write to Activate for
NVM
“LPDDR2-N: Burst write followed by Activate: WL = 1,
BL = 4” on page 95, “LPDDR2-N: Burst read
operation followed by Activate: RL = 3, BL = 4” on
page 106, “LPDDR2-N: Burst write followed by
Activate: WL = 1, BL = 4” on page 108
Added notes to timing diagrams
clarifying that the BL used in the
calculations should be the effective
BL when a read or write burst is
truncated.
Fixed error in
formula for NVM
Write to Activate
“LPDDR2-N: Activate Command” on page 82
Corrected formula for Write to
Activate timing. The previous
equation was missing a “+1”.
Values for tJIT(cc)
were swapped for
400 and 1066
values
“LPDDR2 AC Timing Table*9” on page 197
Values for tJIT(cc) for 400 and 1066
were incorrect and now are corrected.
Added notes for
NVM flow charts
“Program/Erase Suspend Request Flowchart” on
page 76, “Abort Request Flowchart” on page 78
Added notes for two NVM flowcharts
that were missing the OW notes.
Fixed typos in
Package Ballouts
“LPDDR2 12x12 PoP 1-channel x32 package ballout
using MO-273” on page 3, “79-ball x16 LPDDR2
0.5mm pitch package ballout (Discrete/MCP)” on
page 6
Changed INT#, WP# to INT, WP# in
12x12 PoP 1-channel ballout and
fixed DQ15 typo in 79-ball x16 MCP.
JEDEC Standard No. 209-2E
Page 269
D.4 JESD209-2B Updated to JESD209-2C

Table 146 — Changes from JESD209-2B to JESD209-2C
Changes Sections Effected Description of Changes
Added min tCK
values for tZQCS and
tZQCL. Changed
max to min for tZQ
values.
“LPDDR2 AC Timing Table*9” on page 197
Specified minimum tCK values for
tZQCS and tZQCL to 6 tCK. Editorial
change of tZQ values from maximum to
minimum.
tPOFF value
changed.
“Timing Parameters Power-Off” on page 31
“Power-off Sequence” on page 31
“Uncontrolled Power-Off Sequence” on page 31
Changed tPOFF value from maximum
20ms to maximum 2s.
Added clarifying
notes for MR0, RZQI.
“Mode Register Assignment and Definition in
LPDDR2 SDRAM and NVM” on page 32
RZQI codes clarified in MR0.
Updated
VOHDIFF(AC) and
VOLDIFF(AC) to
match single ended
values
“Differential AC and DC Output Levels” on page 171
VOHDIFF(AC) updated from
+.25*VDDQ to +.2*VDDQ to align with
VOH(AC)
VOLDIFF(AC) updated from
+.25*VDDQ to -.2*VDDQ to align with
VOL(AC)
Updated Notes for
Status Register.
“Status Register details” on page 52
Removed conflicting note for the use of
the Abort command.
Updated Note 12 in
AC Timing Table
“LPDDR2 AC Timing Table*9” on page 197
Clarified that both analog (ns) and min
tCK values shall be used when the min
tCK column applies.
Corrected typos in
162-ball and 180-ball
MCP ballmaps
“162-ball x16/x32 LPDDR2 and SDR-Flash package
ballout” on page 8
“180-ball x16/x32 LPDDR2, SDR-Flash, and e-MMC
package ballout” on page 9
The 162-ball MCP ball B3 changed to
DQS instead of DQ5 and ball B4
changed to DAT7 instead of DAT2.
The 180-ball MCP ball B3 changed to
DQS instead of DQ5.
Added section for
RPMB for LPDDR2-
NVM devices
“LPDDR2-N: Replay Protected Memory Block (RPMB)”
on page 230
Replay Protected Memory Block is an
optional feature for LPDDR2-NVM
devices.
CS_N and CKE clari-
fication in Command
Truth Table
“Command Truth Table” on page 148
CS_N is registered on the rising edge of
clock and is don’t care for the falling
edge of clock. CKE timing clarified.
When CKE changes, from HIGH to
LOW or LOW to HIGH, it is don’t care on
the falling edge of clock.
Added CKE timing
clarification.
“LPDDR2 CKE Input Setup and Hold Timing” on page 84
CKE input timing diagram clarifies CKE
input timing usage.
Suspend register
clarification
“Suspend Register” on page 50
Replaced “allowed” with “effective”.
Writes to this register are only effective
when embedded operation is in prog-
ress.
Abort register clarifi-
cation
“Abort Register” on page 51
Replaced “allowed” with “effective”.
Writes to this register are only effective
when embedded operation is in prog-
ress. Also, noted that the embedded
operation may have completed suc-
cessfully before the abort could have
taken effect.
IDD specification
note clarification
“LPDDR2 IDD Specification Parameters and Operating
Conditions” on page 186
Added clarification for Note 8 that out-
load load is 5pF.
JEDEC Standard No. 209-2E
Page 270
D.5 JESD209-2C Updated to JESD209-2D

Table 147 — Changes from JESD209-2C to JESD209-2D
Changes Sections Effected Description of Changes
Fixed notation for
active low signals
“LPDDR2 12x12 PoP 1-channel x32 package ballout
using MO-273” on page 3
Changed “#” with “_n”
Added 121-Ball
MCP Ballout
“121-ball x16 LPDDR2, SDR Flash-NVM, and e-MMC
package ballout” on page 10
Added 121-ball LPDDR2 x16 / Flash
Ballout
Removed RTT
waveform
“Power Ramp and Device Initialization” on page 28
“Power Ramp and Initialization” on page 226
Removed RTT waveform from
Figure 6 on page 30
Clarified MR4
OP<2:0> bits value
after power-up
“Mode Register Assignment and Definition in
LPDDR2 SDRAM and NVM” on page 32
Added the text in red ink to NOTE 2
".... OP<2:0> bits are undefined after
power-up" see MR4 on page 38
Fixed ESSB and
PSSB value in error
condition table
“Block Erase Command” on page 65
Fixed ESSB and PSSB Status
Register bits value in case of Erase
command issued during suspend.
Fixed PSSB value
in error condition
tables
“Single Word Program Command” on page 67
“Single Word Overwrite Command” on page 69
“Buffered Program Command” on page 71
“Buffered Overwrite Command” on page 73
Fixed PSSB Status Register bit value
in case of command issued during
program suspend.
Added a note about ESSB value.
Added RDB invali-
dation step in
LPDDR2-NVM
flowcharts
“Block Erase Command” on page 65
“Single Word Program Command” on page 67
“Single Word Overwrite Command” on page 69
“Buffered Program Command” on page 71
“Buffered Overwrite Command” on page 73
Added a new step in the flowcharts
and a note.
Clarified clock
requirement for self
refresh exit
“LPDDR2-SX: Self Refresh operation” on page 124
Improved the text as follows.
“First, the clock shall be stable and
within specified limits for a minimum
of 2 tCK clock cycles prior to the
positive clock edge that registers CKE
going back HIGH.”
Fixed tCK(MIN) and
tCK(MAX)
“Input clock stop and frequency change” on page 146
Substituted tCK(MIN) with
tCK(abs)min
Removed tCK(MAX)
Fixed VILdiff(dc)
and VILdiff(ac) max
values
“Differential signal definition” on page 166
Changed the sign to VILdiff(dc) and
VILdiff(ac) max values, and completed
note 1.
Fixed tCKmin “IDD Specifications” on page 186
Substituted all "tCKmin" with
"tCK(avg)min" in the LPDDR2 IDD
Specification Parameters and Operating
Conditions Table on page 186
Clarified
temperature range
for IDD values
“IDD Specifications” on page 186
Clarified temperature range for IDD
values. Delete reference to note 4
from IDD6ET.
Removed some OW
registers for RPMB
“Overlay Window: Control Register Offsets and
Definitions” on page 230
Removed the following OW registers:
Authentication Configuration Reg,
RPMB ID Regs, RPMB Start Address
Regs, RPMB Start Address Regs.
Updated note 1.
Removed some
Command Result
values
“Command Result” on page 232
Removed the following values
because they never occur: 0x82,
0x83, 0x8A, 0x8B. Added note 1, note
2 and note 6. Modified note 4. Made
some minor editorial changes.
JEDEC Standard No. 209-2E
Page 271
Added description
for some OW Regs.
“Nonce Register” on page 233,
“MAC Register” on page 234
Added description for Nonce Register
and MAC Register
Clarified Write
Counter Reg.
description
“OW Write Counter Register” on page 233
Clarified the purpose of Write Counter
Register and its value after power up
or reset. Made few editorial changes.
Clarified Authenti-
cation Key Configu-
ration Register
description
“Authentication Key Configuration Register” on page
235
Clarified the register value when the
device is delivered.
Made few editorial changes.
Clarified RPMB ID,
RPMB Start
Address, RPMB
End Address
“RPMB ID, RPMB Start Address, RPMB End
Address” on page 236
Made some editorial changes to
improve the description.
Added RPMB
Configuration
Register
“RPMB Configuration Register” on page 236
Added RPMB Configuration Register
which includes enable bit and lock-
down bit.
Clarified MAC
calculation bytes
order
“Message Authentication Code Calculation” on page
237
The MAC calculation bytes order table
has been split in two tables.
Changed note 6. Removed column for
Command Result Digest.
Added Read
Security Registers
command
“LPDDR2 RPMB Commands” on page 239 Added command code.
Removed
Command Result
Digest Command
“LPDDR2-NVM RPMB commands” on page 239
“Dual operations with Authenticated Command” on
page 264
Command Result Digest command
has been removed.
Changed Security
Register program
method
“Write Security Register Command” on page 240
Defined a new method for
programming Security Registers.
Added several new
Authenticated
commands
“LPDDR2-NVM RPMB commands” on page 239
“Read Security Register Command” on page 243,
“Authenticated Block Erase Command” on page 249,
“Authenticated Single Word Program Command” on
page 252, “Authenticated Single Word Overwrite
Command” on page 255, “Authenticated Buffered
Overwrite Command” on page 261
The following commands have been
added: Read Security Register,
Authenticated Block Erase,
Authenticated Single Word Program,
Authenticated Single Word Overwrite,
Authenticated Buffered Overwrite.
Changed Status
Register error
conditions
“Write Counter Digest Command” on page 245
Added error conditions table. Added
RDB invalidation step in flowchart.
Made some editorial changes.
Changed Status
Register error
conditions
“Memory Data Digest Command” on page 246
Added error conditions table. Added
RDB invalidation step in flowchart.
Made some editorial changes.
Fixed PSSB value
in error condition
table
“Authenticated Buffered Program Command” on
page 258
Fixed PSSB Status Register bit value
in case of command issued during
program suspend. Added a note
about ESSB value.
Added address failure error condition
for Command Result Register. Added
RDB invalidation step in flowchart.
Table 147 — Changes from JESD209-2C to JESD209-2D
Changes Sections Effected Description of Changes
JEDEC Standard No. 209-2E
Page 272
D.6 JESD209-2D Updated to JESD209-2E
Table 148 — Changes from JESD209-2D to JESD209-2E
Changes Sections Effected Description of Changes
Added VACC = VAP
acceleration power supply
value
“Absolute Maximum DC Ratings” on
page 158 “Recommended DC Operating
Conditions” on page 159
Added VACC absolute maximum value =
7V in Table 68 on page 158, and note 6.
Added VACC = VAP in Table 71 on page
159, and note 3.
Fixed tERR(8per) value for
DDR667
“AC Timings” on page 195
tERR(8per) value for DDR667 has been
changed from 256 ps to 266 ps.
Clarified Command Result
Reg. definition “Command Result Register” on page 229
Clarified that bit 7 of Command Result
Register provides information about the
internal Write Counter
Removed the text about the
internal Write Counter
“OW Write Counter Register” on page 231
The description of the internal Write
Counter has been moved to a dedicated
paragraph. Changed the paragraph
heading to “OW Write Counter”
Added the “Write Counter”
paragraph
“Write Counter, Authentication Key and
RPMB Resource” on page 233 “Write
Counter” on page 233
Most of the text was previously included
Write Counter paragraph in the section
“Map of Control Registers”.
Clarified write counter
update
“Write Counter Digest Command” on
page 243
Clarified that the sentence about Write
Counter Update refers to the OW Write
Counter and not the internal Write Counter
Fixed command code value
for Memory Data Digest
command
“Memory Data Digest Command” on
page 245
Fixed a typo in the descritption of the
command sequence: according to Table
129 on page 237, the command code
value is 0x00A6 and not 0x00A8.
Clarified which Write
Counter shall be used during
“Authenticated Block Erase Command”
on page 247 “Authenticated Single Word
Program Command” on page 250
“Authenticated Single Word Overwrite
Command” on page 253
Added a sentence to clarify that the OW
Write Counter shall be used in the MAC
calculation for command authen-
MAC calculation “Authenticated Buffered Program
Command” on page 256 “Authenticated
Buffered Overwrite Command” on page
259
tication.
Clarified Write Counter
values used during
“Authenticated Block Erase Command”
on page 247 “Authenticated Single Word
Program Command” on page 250
“Authenticated Single Word Overwrite
Command” on page 253
Clarified that during the write counter
comparison, the device shall compare OW
Write Counter Register content
comparison “Authenticated Buffered Program
Command” on page 256 “Authenticated
Buffered Overwrite Command” on page
259
with the internal Write Counter value.
Added 14x14 ballout New 2.3 on page 4 From JCB-10-90
Rev. 9/02



Standard Improvement Form JEDEC JESD209-2E

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JEDEC Standard No. 209-2E

Contents

1 Scope ..................................................................................................................................1 2 Package ballout & addressing .........................................................................................2 2.1 LPDDR2 12x12 PoP 2-channel 2x32 package ballout .................................................. 2 2.2 LPDDR2 12x12 PoP 1-channel x32 package ballout using MO-273............................. 3 2.3 LPDDR2 14x14 PoP Dual x32 Channel ballout using MO-273 .................................... 4 2.4 LPDDR2 10x10 PoP 1-channel x32 package ballout ..................................................... 5 2.5 79-ball x16 LPDDR2 0.5mm pitch package ballout (Discrete/MCP) ........................... 6 2.6 2.5 134-ball x16/x32 LPDDR2 package ballout (Discrete/MCP) ................................. 7 2.7 162-ball x16/x32 LPDDR2 and SDR-Flash package ballout ........................................ 8 2.8 180-ball x16/x32 LPDDR2, SDR-Flash, and e-MMC package ballout ........................ 9 2.9 121-ball x16 LPDDR2, SDR Flash-NVM, and e-MMC package ballout ..................... 10 2.10 LPDDR2 Pad Sequence ............................................................................................... 11 2.11 Input/output functional description .............................................................................. 12 2.11.1 Pad Definition and Description ................................................................................. 12 2.12 LPDDR2 SDRAM Addressing .................................................................................... 14 2.13 LPDDR2 NVM Addressing ......................................................................................... 14 2.13.1 Three-Phase Addressing ........................................................................................... 14 3 Functional description .................................................................................................... 20 3.1 Simplified LPDDR2 Bus Interface State Diagram .........................................................21 3.2 Simplified LPDDR2-SX State Diagram .........................................................................23 3.3 Simplified LPDDR2-N Simplified Bus State Diagram ..................................................25 3.3.1 Power On and Resetting states .................................................................................... 25 3.3.2 Idle state ...................................................................................................................... 25 3.3.3 Active state .................................................................................................................. 26 3.4 Power-up, Initialization, and Power-Off .........................................................................28 3.4.1 Power Ramp and Device Initialization ....................................................................... 28 3.4.2 Initialization after Reset (without Power ramp): ......................................................... 30 3.4.3 Power-off Sequence .................................................................................................... 31 3.4.4.Uncontrolled Power-Off Sequence ............................................................................. 31 3.5 Mode Register Definition ................................................................................................32 3.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM ............ 32 4 LPDDR2-N Software Interface ...................................................................................... 47 4.1 Overlay Window ............................................................................................................ 47 4.1.1 Map of Control Registers (offsets and definitions) ..................................................... 48 4.1.1.1 Command Code Register .......................................................................................... 49 4.1.1.2 Command Data Register .......................................................................................... 49 4.1.1.3 Command Address Register ..................................................................................... 49 4.1.1.4 Multi-Purpose Register ............................................................................................ 49 4.1.1.5 Command Execute Register ..................................................................................... 50 4.1.1.6 Suspend Register ...................................................................................................... 50 4.1.1.7 Abort Register .......................................................................................................... 51 4.1.1.8 Status Register ......................................................................................................... 51
-i-

.......................................2 LPDDR2-N: Activate Command ................................... 78 4...2 Data Byte Lane Assignment for Overlay Window Register .........................................9...... 92 5......................... 55 4............7...........................................................................7...............7................................3 Read and Write access modes ...........................2 LPDDR2-N: Burst Write operation followed by Activate or Preactive .............10 Program/Erase Resume Command ....1 LPDDR2-SX: Read and Write access modes ......... 85 5......... 81 5.... 109 5...........4 Burst Read Command ......... 109 5.........................................................9 Program-Buffer .. 84 5....................................4.........................................6 Burst Terminate ....................................................................12 Row Data Buffer Incoherency ................. 105 5.....................................................................7....................................... 58 4.......................................................................3 LPDDR2-N: Auto Precharge (AP) bit ........2 LPDDR2 CKE Input Setup and Hold Timing ...... 81 5......1 LPDDR2-SX: Burst Read operation followed by Precharge ...............4 Nomenclature ......................................................... 75 4.................2 LPDDR2: Data Not Valid ......................................................................................11 Abort ..................................................8......7............1............................. 107 5........................1 LPDDR2 Command Input Setup and Hold Timing .............................................. 59 4.................... 69 4.................. 99 5.6 Conventions .......................................................................................................................6 Single Word Overwrite Command .............. 81 5.................... 61 4.........................................1 LPDDR2-SX: Activate Command .2..................................... 94 5............1 Block Lock Command ..............................................................7....................... 56 4............................................................................................................................. 83 5..................................7........................................................ 110 5.. 209-2E Contents (cont’d) 4................................................ 63 4...........5..................................................................................................2 LPDDR2-SX: Burst Write followed by Precharge .........2 LPDDR2-N: Read and Write access modes .......3.................................. 7Buffered Program Command .......................................................1.......................... 91 5............ 71 4.............................................................. 106 5.8 LPDDR2-N: Preactive operation .3 LPDDR2-NVM Operations .......... 97 5........................... 77 4.........................................................................................................7 Write Data Mask ...............2 LPDDR2 Command Input Signal Timing Definition .........................2 Block Unlock Command ............................... 79 4.... 53 4.................................................1 Writes interrupted by a write .........................................................................5 Single Word Program Command ....................................7.................................................................. 80 5 LPDDR2 Command Definitions and Timing Diagrams .............7.......................................................5 Burst Write Operation ..............8 Dual operations and multiple partition architecture . 83 5......... 103 5. 65 4...............8.................................................5 Acronyms .................. 57 4....................................7.................1 Reads interrupted by a read .............9 LPDDR2-SX: Precharge operation ...............8............3 Block Lock-Down Command .......................................8 Buffered Overwrite Command ..... 67 4......................................3.....4 Block Erase Command .. 54 4...........................2...................................................... 53 4.7..............................................................1 Activate Command .....................................................................................................7 Overlay Window Enable and Disable ....................................1 LPDDR2-N: Burst Read operation followed by Activate or Preactive ............................ 85 5...................... 85 5...................7............................ 73 4.........................................9 Program/Erase Suspend ..............1..1...........JEDEC Standard No............................... 82 5......................... 112 -ii- .......................................................................................4....9. 86 5..........................................................................................................................

...... 164 8...............................................................................................................3................. 161 8 AC and DC Input Measurement Levels .............................. 138 5........... 159 6..................1 Differential signal definition .........................................1...................................3 Operating Temperature Range ................10 LPDDR2-SX: Refresh command .................................................2 DQ Calibration ..........13 Mode Register Write Command .................. 162 8.................................... 155 5................................................................................................ 132 5............ 147 5... Tolerance..........18....... 162 8.............11 LPDDR2-SX: Self Refresh operation .............. 126 5......15 LPDDR2-SX: Deep Power-Down .............................................. 159 7 AC & DC Operating Conditions .................. 134 5.............................. 137 5............................................................. 112 5.....................................4.......... 124 5..........................................21 Data Mask Truth Table ....1 Absolute Maximum DC Ratings ............2 AC and DC Input Levels for CKE ........................................................................... 117 5........................................................3 AC and DC Input Levels for Single-Ended Data Signals ................................................................................................................................................................................................ 127 5.........10..............................................16 Input clock stop and frequency change ..................... 130 5.......3 LPDDR2-SX: Auto Precharge operation ..20 LPDDR2-N: Truth Tables .................................................... 160 7........................ 113 5........1.. 166 8.... and Capacitive Loading .................................................................................11.. 163 8............................................4 AC and DC Logic Input Levels for Differential Signals .............2 LPDDR2-SX: Burst write with Auto-Precharge .....................................................3 Input Signal ..... 166 -iii- .........2 Input Leakage Current ................................................................1 LPDDR2-SX: Burst Read with Auto-Precharge ...............13.............................................4.....................19 LPDDR2-SDRAM Truth Tables ...........................................................................................................9....3....................................................................................................................................................................1.................................... 158 6 Absolute Maximum Ratings ............................................................................................................................. 162 8........17 No Operation command ..1 AC and DC Input Levels for Single-Ended CA and CS_n Signals . 209-2E Contents 5.....1 LPDDR2 SDRAM Refresh Requirements ................................... 148 5...................................3 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking ................... 162 8.................. 135 5......................................................................1 LPDDR2-SX: Mode Register Write .......................................... 145 5........................................13..................................................18 Truth tables ............................................ 125 5............................12...............13.................... 132 5.......................................................4 Mode Register Write ZQ Calibration Command ........................9................................12.................................. 161 7..... 160 7..................2 Vref Tolerances ..............12 Mode Register Read Command .....................................1 Command Truth Table ...... 118 5..............JEDEC Standard No.....................................................2 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking .........................14 Power-down ......... 162 8..... 146 5......... 147 5..........11.............................1 LPDDR2-S2: Partial Array Self-Refresh: Bank Masking ..............1 AC and DC Logic Input Levels for Single-Ended Signals ........1 Recommended DC Operating Conditions ......3 Mode Register Write Reset (MRW Reset) ....13..2 LPDDR2-N: Mode Register Write .......1 ZQ External Resistor Value.1 Temperature Sensor ..............11...................9..............................................................................................13........................ 132 5... 114 5... 126 5..................................... 150 5.................................... 129 5.....................

. 209-2E Contents (cont’d) 8...1 tRPRE ...........1.................. 170 8....... 171 9....................................... 171 9.................................. 190 12.......................... 178 9.. 191 12............... 192 12..................2.................................................... 189 12... tHZ(DQ)................................ 193 -iv- .....................1...............................5 Differential Input Cross Point Voltage .......................... 189 12. 193 12...................2 Period Clock Jitter ..................... 192 12......... 174 9............5 Overshoot and Undershoot Specifications .................................1........7..6.................................................2 Definition for tCK(abs) .................1............................................1.................2 Output Driver Temperature and Voltage Sensitivity ..........7........................... 182 11 IDD Specification Parameters and Test Conditions ............... 171 9............. 186 12 Electrical Characteristics and AC Timing .. 168 8...............................................................4 Definition for tJIT(per) .............................................. tDQSCK....... 189 12...............1 RONPU and RONPD Characteristics with ZQ Calibration ................................1..............1..............................................4................................................................... 190 12.................................2 Clock Cycle de-rating for core timing parameters .......................... 169 8........ 184 11..................................... 182 10..........................................................................................1 Clock period jitter effects on core timing parameters ...............................3 Single Ended Output Slew Rate ...2........................................CK_c) and strobe .....................................1 Clock Specification ............................................ tCH(abs) and tCL(abs) .4.............................................................................................................................2...............................................................1........... 170 9 AC and DC Output Measurement Levels ......... 176 9..........................................1 Input/Output Capacitance .................................... 184 11........................................2 Differential AC and DC Output Levels ....................7 Slew Rate Definitions for Differential Input Signals ........................3 Single-ended requirements for differential signals ........................2............................................. 192 12...........1 Single Ended AC and DC Output Levels .................2 Clock jitter effects on Command/Address timing parameters ..........................4 RZQ I-V Curve ................................................ 179 9..................... 189 12.....7.........1 Cycle time de-rating for core timing parameters .................................................................................6 Definition for tERR(nper) .................... 166 8...5 Definition for tJIT(cc) ...... 189 12....................1................ 172 9................................................................................ tLZ(DQS)................................. 192 12...3 Clock jitter effects on Read timing parameters .........................................................................1 HSUL_12 Driver Output Timing Reference Load .................................... 193 12........................ 175 9........................7 RONPU and RONPD Resistor Definition ..... 189 12....................2 IDD Specifications ...................................................................... 177 9...1 Definition for tCK(avg) and nCK ...............4 Differential Output Slew Rate .........7 Definition for duty cycle jitter tJIT(duty) ..................6 Slew Rate Definitions for Single-Ended Input Signals ........1.................................... 191 12........7..................... 173 9.......2........................3...................2 Differential swing requirements for clock (CK_t ...................................................... 180 10 Input/Output Capacitance .........3 Definition for tCH(avg) and tCL(avg) .......................1 IDD Measurement Conditions .............................................. 192 12............................................8 Definition for tCK(abs)................2....3.............. tHZ(DQS) ...................................2 tLZ(DQ)........................6 Output buffer characteristics ..........................................3 RONPU and RONPD Characteristics without ZQ Calibration .........JEDEC Standard No.... 175 9........................................................................2.

............................. Hold and Derating ................ 193 12...................................................1 Acronyms ........................ 230 C.......4 AC Timings .3 Programming Regions ............. 212 Annex A LPDDR2-NVM Software Application Notes ........................ 227 B.... 232 C.....1........... 228 B.............1 Command Result Register ............................. 219 A........................................................................................................................................ 229 Annex C LPDDR2-N: Replay Protected Memory Block (RPMB) ...................2.....................................4 Program Modes ....... tRCD) .............................................................................1.............................................................. 209-2E Contents 12.................................................................. 230 C...............1 Power Ramp and Initialization .......................................1...........................5 Determining whether to boot from the LPDDR2 Bus ...............2.................................9 Increasing the Clock Rate .............2.......1 tDS................1............................... 228 B....... 226 B............................4..................2........................................................ 218 A... 197 12.................7 Output Drive Strength ... 228 B............ 227 B................................................ WL...........13 Summary ............................4 tRPST .......................................................................................................... tDH ....................3 Determine the LPDDR2 bus width.......................1.......2 ZQ Initialization ...1.................6 Continued Boot Out Of the LPDDR2-NVM Device ................................... 224 B.......................................................... 227 B...................... 227 B..............1.............4.....................3 Programming Region Configuration .......................................................4...................................................JEDEC Standard No... 224 B........8 Setting the Output Impedance Calibration Interval ................................................................ 218 A......................................2 Introduction ...2................. 231 C............4 Clock jitter effects on Write timing parameters ....... 229 B............................. 230 C.....3 LPDDR2-SX Refresh Requirements by Device Density ............ 227 B.................................2...........................................................................................................3 tQSH.......... 218 A......10 Controller Latency Settings for Higher Clock Rates .......... 222 Annex B LPDDR2-NVM Boot Procedure ..............................................................3...........2 Nonce Register .......................................................................................................................................2 Programming operations based on Programming Region ...... tQSL .............................1 Control Mode .......................................... 221 A...............2...........3 Map of Control Registers (offsets and definitions) ..2 Object Mode ..................2......... 206 12.......................................................... 193 12............... Hold and Slew Rate Derating ..............................................................12 Data Training ........... memory type...........1........................................... 233 -v- ..... 230 C.............1.........................................................................4.3 Write Counter Register ............................4.................................................................... tDSH .....2 tDSS....................................4........3...................................1................2............................... 218 A.....................................................................................................................3......................................................5 CA and CS_n Setup......2.....................................2...................3 tDQSS .......... 194 12............3............................1 Introduction .............................................. 218 A...........4 Align controller and memory latency settings (RL...1 Booting From an LPDDR2-NVM Device ................3. 194 12...............................................................................................2 Programming Modes ............................................ 194 12............................. 194 12..... 195 12.....................1................... 227 B....................................................... 229 B....................... RDB size and density ...............................................................2...........1 Scope ..1.........2..................................11 Increasing the Clock Rate ......................... 219 A............ 218 A.......................................6 Data Setup...............1............

........................6.................................................. 266 D.......................................... 235 C..............................5 MAC Register ................................................4 Authentication Key and RPMB Resource .. 270 D....... 234 C................................................................................................... 235 C.............................................4.... 269 D............... 258 C........................3 Updated Specification to JESD209-2B ..........................................7 Authenticated Single Word Overwrite Command .............5 Message Authentication Code Calculation .............................6.................4 Memory Data Digest Command .........................9 Authenticated Buffered Overwrite Command ..........................4 RPMB Configuration Register ... 239 C...3 RPMB ID......................................4.. 268 D.............3.6 Updated Specification to JESD209-2E ................................................... 252 C.........2 Authentication Key Configuration Register ............................. 234 C......... RPMB Start Address.........................4............................................4.......... 272 -vi- .............. 209-2E Contents (cont’d) C.................5 Updated Specification to JESD209-2D ....2 Updated Specification to JESD209-2A ................2 Read Security Register ............... 266 D................... 235 C.................7 Dual operations with Authenticated Command ...............................4 Command Response Register.......... 261 C.....................................5 Authenticated Block Erase Command ........... 266 D..............................3................................. 235 C.........6 Authenticated Single Word Program Command ............1 Write Security Register Command .....6......6........................................................................................... 237 C... 240 C........................................ 255 C..6............................................................................................................................................ 249 C........................................................ 247 C............. 245 C........................................................................1 Authentication Key ................. RPMB End Address ............... 236 C......6.... 243 C.....................4 Updated Specification to JESD209-2C .......................6................................................3 Write Counter Digest Command ..............................8 Authenticated Buffered Program Command .......1 Initial Release JESD209-2 ................................6........6.........................................................6 LPDDR2-NVM RPMB commands ...................................................JEDEC Standard No......................................................................................................... 264 Annex D (informative) Differences between Document Revisions ......................

and JCB-10-91. and LPDDR-NVM (N07-NV1A). 209-2E Page 1 LOW POWER DOUBLE DATA RATE 2 (LPDDR2) (From JEDEC Board ballots JCB-10-54.) 1 Scope This document defines the LPDDR2 specification. DDR3 (JESD79-3). and x32 for NVM devices. The accumulation of these ballots were then incorporated to prepare the LPDDR2 specification. JCB-10-90. and LPDDR2-N-B. LPDDR (JESD209). . packages. including features. LPDDR2-S4A. x16. This specification was created using aspects of the following specifications: DDR2 (JESD79-2). formulated under the cognizance of the JC-42.JEDEC Standard No. and ball/signal assignments. functionalities.6 Subcommittee on Low Power Memory. This specification covers the following technologies: LPDDR2-S2A. LPDDR2-N-A. The purpose of this specification is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8. LPDDR2-S4B. Each aspect of the specification were considered and approved by committee ballot(s). LPDDR2-S2B. AC and DC characteristics. x16. and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8.

A1 in Top Left Corner See JESD21-C. 209-2E Page 2 2 2. 0.2 . 29 rows NOTE 2 NOTE 3 NOTE 4 216 Ball Count Top View.12.4mm pitch.1 1 A B C Package ballout & addressing LPDDR2 12x12 PoP 2-channel 2x32 package ballout 2 VSSa/b VACC DQ16_b VDDQ_b DQ19_b DQ20_b VDDQ_b DQ23_b VDDQ_b Channel b Channel a Power Ground Do Not Use ZQ Clock 3 VDD2_a/b DQ31_a 4 DQ30_a VDDQ_a 5 DQ29_a DQ28_a 6 VSSQ_a DQ27_a 7 DQ26_a VDDQ_a 8 DQ25_a DQ24_a 9 VSSQ_a VDDQ_a 10 DQS3_c_a DQS3_t_a 11 VSSQ_a DM3_a 12 DQ14_a DQ15_a 13 DQ13_a VDDQ_a 14 VSS_a VSSQ_a 15 VDD1_a Vref(DQ)_a 16 VDD2_a VDD2_a 17 DQ11_a DQ12_a 18 DQ10_a VDDQ_a 19 DQ9_a DQ8_a 20 DQS1_t_a DQS1_c_a 21 DM_1_a VSSQ_a 22 VDDQ_a DM_0_a 23 DQS0_t_a DQS0_c_a 24 DQ7_a VSSQ_a 25 DQ6_a VDDQ_a 26 DQ4_a DQ5_a 27 DQ3_a DQ2_a 28 VSS_a/b VACC VDD1_a DQ1_a VSSQ_a DM2_a 29 DNU VSSQ_a VDD2_a/b VDDQ_a DQ0_a VDDQ_a DNU VSSQ_b/ VSS VDD1_a/b DQ17_b DQ18_b VSSQ_b DQ21_b DQ22_b VSSQ_b D E F G H J DQS2_t_a DQS2_c_a VSSQ_a VDDQ_a DQ20_a DQ19_a VDDQ_a DQ16_a VDD2_b VSS_b VDDCA_b Vref(CA)_b VSSCA_b CA4_b CSB0_b VSSCA_b CK_t_b VDDCA_b CA7_b CA8_b VSSCA_b VDD2_a/b VDD2_a/b DQ12_b DQ13_b VDDQ_b VSSQ_b DQ14_b DQ15_b VDDQ_b DM3_b VSSQ_b DQS3_t_b DQS3_c_b VDDQ_b DQ24_b DQ26_b DQ25_b DQ27_b VSSQ_b VDDQ_b DQ28_b DQ30_b DQ29_b VSSQ_b DQ31_b VDD2_a VDD1_a Vref(CA)_a VSS_a CA9_a ZQ_a VSSCA_a CA8_a CA7_a VDDCA_a CA6_a CA5_a CK_c_a CK_t_a VDDCA_a VSSCA_a CKE0_a CKE1_a CSB0_a CSB1_a CA3_a CA4_a CA2_a VDDCA_a CA1_a CA0_a VDD1_a/b VSS_a/b DQ23_a DQ22_a DQ21_a VSSQ_a DQ18_a DQ17_a VDD1_b CA0_b CA1_b CA2_b CA3_b CSB1_b CKE1_b CKE0_b CK_c_b CA5_b CA6_b VDDCA_b CA9_b ZQ_b VSSCA_a DNU K DQS2_c_b DQS2_t_b L M N P R T U V W Y DM2_b DQ1_b DQ2_b VSS_b VDD1_b VDD2_b VDDQ_b DQ4_b DQ6_b VDDQ_b DQ0_b VSSQ_b VDD1_b VSS_b Vref(DQ)_b VDD2_b DQ3_b VSSQ_b DQ5_b DQ7_b AA DQS0_t_b DQS0_c_b AB AC DM0_b VDDQ_b VSSQ_b DM1_b AD DQS1_c_b DQS1_t_b AE AF AG AH AJ DQ8_b DQ9_b DQ10_b VSSQ_b DNU VSSQ_b VDDQ_b DQ11_b VDD1_a/b VSS_a/b NOTE 1 12x12 mm.JEDEC Standard No. Section 3.

2.5mm pitch. 209-2E Page 3 VDDCA VSSmm VDDmm VACC VSSQ DQS2_c VDD1 NOTE 1 12x12 mm. A1 in Top Left Corner See JESD21-C.WP_n P R T U V W Y A A A B A C ZQ VSS CA9 CA7 VSSCA CA5 CK_c VSS DNU DNU DQS0_c VSSQ VDDQ DQS0_t DQ6 DQ5 VDDQ DQ2 DQ1 VDDQ CS0_n CS1_n VDD1 CKE0 CKE1 VSS CA1 CA0 VSSCA CA2 CA3 CA4 VDD2 VSS DQ16 VSSQ VDDQ DQ17 DQ18 DQ19 DQ20 VSSQ VDDQ DQ21 DQ22 DQS2_t VDDQ DQ23 DM2 VDD2 VSS DNU DNU DQ7 VSSQ DQ4 DQ3 VSSQ DQ0 DNU DNU JEDEC Standard No. RST_n. Section 3.4) AVD_n INT NC NC RST_n / DPD must be conDPD figured active high ADV_n WP_n N INT. ADV_n.2 . 0.12. CLKm DAT6m m DAT4m DAT2m DAT0m VDD1 ADQ3 VSSm ADQ2 ADQ1 VSSm DAT7m m DAT5m DAT3m m ADQ0 DAT1m VSS VSSQ DQS3_c VDD1 DM3 DQ24 DQS3_t VDDQ D E Flash Memory (eMMC/MuxOneNand/NAND/AADMuxNOR) ADD/CTRL LPDDR2 DQ LPDDR2 CA Power Ground Do Not Use ZQ Clock Ball LocaA3 A4 K1 K2 L1 L2 N1 Mux One- eMMC Raw NAND ADDMux WAIT CLK WE_n OE_n Comment DQ12 DQ11 VDDQ DQ8 F VCCQmm VSSmm VDDImm G H J K L M ADQ14 ADQ15 VCCmm WE_n RP_n.2 LPDDR2 12x12 PoP 1-channel x32 package ballout using MO-273 1 A B C 2 DNU DNU VDD2 ADQ4 ADQ5 3 4 5 6 7 8 9 10 11 VDD1 VDD2 12 VSSQ DQ31 13 DQ30 VDDQ 14 DQ29 DQ28 15 VSSQ DQ27 16 DQ26 VDDQ 17 DQ25 18 19 20 21 VSS VDD2 22 DNU DNU DQ15 VDDQ 23 DNU DNU VSSQ DQ14 DQ13 VSSQ DQ10 DQ9 DNU DNU VSS ADQ12 ADQ13 RDY. 23 rows NOTE 2 NOTE 3 NOTE 4 168 Ball Count Top View. CE_n ADQ6 ADQ7 VSSmm OE_n/ RE_n AVD_n.R/B CLK ADQ11 VCCm ADQ10 ADQ9 VCCQmm ADQ8 _n. VSS VDD1 Vref(CA) VDD2 CA8 VDDCA CA6 VDDCA CK_t VDD2 DNU DNU RDY / CMDm R/B_n WAIT_n CLK WE_n OE_n CLKm NC NC NC WE_n RE_n CLE ALE WP_n DQS1_t VSSQ VDDQ DQS1_ c VDD2 Vref(DQ) VDD1 DM1 VSS DM0 RP_n RST_n (v4.

0.12.5mm pitch. Section 3.5mm pitch.3 1 A B C D E F G H J K L M N P R T U V W Y DNU VSSQ_b VDD1_a/b DQ17_b DQ18_b DQ20_b VDDQ_b LPDDR2 14x14 0. internal row partially populated Top View. 27 rows 240 Ball Count Top View A1 in Top Left Corner VSSQ_a DQS2_t_a DQ23_a DQ22_a DQ21_a DQ20_a DQ19_a VDDQ_a VSSQ_a DQ18_a DQ16_a VSSQ_b DQS2_t_b DQS2_c_b VDDQ_b VSSQ_b DQ1_b DQ3_b DQ4_b DQ6_b DQ0_b VDDQ_b VSSQ_b DQ5_b DQ7_b VDDQ_b DQ2_b DM2_b Channel b Channel a Power Ground Do not use ZQ VDDQ_a DQ17_a VSSQ_a VDD2_a/b CA0_b VDD1_a/b VSS_a/b CA1_b CA3_b CA2_b CA4_b CKE0_b CSB0_b CK_c_b VSSCA_b VDDCA_b CSB1_b CKE1_b CK_t_b VDDQ_b DQS0_t_b DQS0_c_b VSSQ_b VSS_a/b DM0_b Vref(DQ)_b VSS_a/b VDD1_a/b VDD1_a/b DM1_b VDDQ_b VDD2_a/b VDDCA_b VSSCA_b VSS_a/b Vref(CA)_b CA5_b VDDCA_b VSSCA_b CA7_b CA6_b CA8_b ZQ_b VDD2_a/b VDD2_a/b VSSQ_b DQ8_b AA DQS1_c_b DQS1_t_b AB AC AD AE AF AG VDDQ_b DQ10_b DQ13_b VDD1_a/b VSSQ_b DNU DQ9_b DQ11_b DQ12_b DQ14_b VDDQ_b VDD2_a/b CA9_b VSS_a/b VSSQ_b DNU DNU DNU VDD1_a/b AC DNU DNU DNU DNU AD AE AF AG VSSQ_b DQ15_b VDDQ_b DQS3_t_b DQ25_b DM3_b DQS3_c_b DQ24_b DQ27_b DQ26_b VDDQ_b DQ28_b VSSQ_b DQ30_b VDDQ_b DQ29_b VSSQ_b VDD2_a/b VSS_a/b CA9_a ZQ_a CA6_a CA7_a CA8_a CA5_a VDDCA_a VSS_a/b VDDCA_a VSSCA_a Vref(CA)_a VSSCA_a VDD2_a/b CK_t_a CK_c_a CKE0_a CKE1_a CA4_a CSB0_a CSB1_a CA2_a CA3_a VSS_a/b VSSCA_a VDDCA_a CA0_a CA1_a DNU VDD2_a/b VDD1_a/b DNU DNU DNU DNU DNU DNU DNU VSS_a/b VDD2_a/b DQ31_b VDD1_a/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NOTE 1 14x14 mm.5 mm ball pitch Dualx32 ChannelPoP ballout using variation VEEBDC for MO-273 2 3 4 5 VDDQ_a DQ29_a DQ28_a JEDEC Standard No. A1 in Top Left Corner See JESD21-C. 209-2E Page 4 6 VSSQ_a DQ27_a 7 DQ26_a VDDQ_a DQ25_a 8 9 10 DM3_a 11 DQ15_a DQ14_a VDDQ_a 12 DQ13_a DQ12_a 13 VSSQ_a DQ11_a DQ10_a 14 VDDQ_a DQ9_a 15 DQ8_a 16 17 18 19 20 VSSQ_a 21 DQ7_a DQ6_a VDDQ_a 22 DQ5_a DQ4_a 23 VSSQ_a DQ3_a DQ2_a 24 25 26 27 DNU VSS_a/b VDD2_a/b VSS_a/b VDD2_a/b DQ31_a VACC DQ16_b VDDQ_b DQ19_b DQ21_b DQ22_b DQ23_b VSSQ_b VSSQ_a DQ30_a DQ24_a DQS3_t_a VSSQ_a Vref(DQ)_a VDD1_a/b VDDQ_a VDDQ_a VDD1_a/b VSSQ_a DQ1_a DQ0_a VACC DM2_a A B C D E F G H J K L M N P R T U V W Y AA AB VSSQ_a DQS3_c_a VSSQ_a VDDQ_a DQS1_c_a VDDQ_a DQS1_t_a VSS_a/b VDD2_a/b DQS0_c_a DM0_a DM1_a DQS0_t_a VDDQ_a DQS2_c_a 14X14 mm. 0.2.2 . 27 rows NOTE 2 NOTE 3 NOTE 4 240 Ball Count.

JEDEC Standard No.2 . 19 rows NOTE 2 136 Ball Count NOTE 3 Top View. 0.12.4 1 A B C LPDDR2 10x10 PoP 1-channel x32 package ballout using variation VAABCB for MO-273 2 DNU DNU VDD1 CA8 VDDCA CA6 VDD2 Vref(CA) VDDCA CK_c VSSCA CKE0 CS0_n CA4 CA2 VSSCA VDD1 VACC DNU VSS VSS VDD2 VSSQ DQ17 DQ16 DQ18 VDDQ VSSQ DQ19 DQ21 DQ20 DQ22 VDDQ VSSQ DQ23 DQS2_t DQS2_c VDDQ DM2 DQ0 VSSQ VDDQ DQ1 DQ3 DQ2 VDD2 DQ4 VSS VSS LPDDR2 DQ LPDDR2 CA Power Ground Do Not Use ZQ Clock 3 VSS VSS 4 VSSQ VDD2 5 DQ31 DQ30 6 VDDQ DQ29 7 DQ28 VSSQ 8 DQ27 DQ26 9 VDDQ DQ25 10 DQ24 VSSQ 11 DQS3_c DQS3_t 12 DM3 VDDQ 13 VSSQ DQ15 14 DQ14 VDDQ 15 DQ13 DQ12 16 DQ11 VDD2 17 VSS VSS 18 DNU DNU VDD1 DQ9 VSSQ DQS1_t VDDQ VDD2 VSS Vref(DQ) VDD1 VDD2 VDDQ DQS0_t VSSQ DQ6 VDD1 DNU DNU 19 DNU DNU DQ10 VDDQ DQ8 DQS1_c DM1 VSSQ VDD2 VSS VDD1 VSSQ DM0 DQS0_c DQ7 VDDQ DQ5 DNU DNU DNU DNU ZQ CA9 VSSCA CA7 CA5 VDD1 VSS CK_t VSS CKE1 CS1_n CA3 VDDCA CA1 CA0 DNU DNU D E F G H J K L M N P R T U V W NOTE 1 10x10 mm.5mm pitch. A1 in Top Left Corner NOTE 4 See JESD21-C. Section 3. 209-2E Page 5 2.

1 .5 79-ball x16 LPDDR2 0.JEDEC Standard No. 209-2E Page 6 2.5mm pitch. A1 in Top Left Corner NOTE 4 The ZQ-ball used when operating above 200 MHz is limited to a 5pF load (typically 2 die using CKE0. Section 3.12.1 and CS0.1) NOTE 5 See JESD21-C. 11 rows NOTE 2 79 Ball Count NOTE 3 Top View.5mm pitch package ballout (Discrete/MCP) 1 A B C 2 CA9 CA8 CA6 3 VDD2 ZQ 4 VDD1 VSS 5 VSSQ DQ15 6 DQ14 DQ13 7 DQ12 VDDQ 8 VDD2 VSSQ DQ10 9 NC DQ11 DQ9 LPDDR2 DQ LPDDR2 CA Power Ground Do Not Use/No Connect ZQ Clock NC CA7 CA5 D VDDCA VSSCA CKE2 CS3_n CKE1 CKE0 CS1_n CS2_n VSSQ DQS1_t DQ8 VDDQ E F G H J K L VDD2 VSS VDDCA CK_c CA4 CA2 NC Vref(CA) VSSCA CK_t CS0_n CA3 CA1 CA0 VACC VDD2 VDDQ VSS VSSQ VDDQ DQS1_c VDD1 DQS0_c DQS0_t DM1 VDD2 DM0 DQ7 DQ5 VSS Vref(DQ) VDD1 VDDQ DQ6 DQ4 NC VSS VDD1 DQ0 VSSQ DQ2 DQ1 VDDQ DQ3 VSSQ VDD2 NOTE 1 0.

1 . Section 3. 17 rows NOTE 2 134 Ball Count NOTE 3 Top View.6 134-ball x16/x32 LPDDR2 package ballout (Discrete/MCP) 1 2 3 4 5 6 7 8 9 10 A DNU DNU NB NB NB NB NB NB DNU DNU B DNU NC VACC NB VDD2 VDD1 DQ31 NC DQ29 NC DQ26 NC DNU Ball Definition where 2 labels are present C VDD1 VSS ZQ1 NB VSS VSSQ VDDQ DQ25 NC VSSQ VDDQ 1st Row 2nd Row x32 device x16 device D VSS VDD2 ZQ0 NB VDDQ DQ30 NC DQ27 NC DQS3_t NC DQS3_c NC VSSQ E VSSCA CA9 CA8 NB DQ28 NC DQ24 NC DM3 NC DQ15 VDDQ VSSQ F VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ G VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ H VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB J VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB K CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB LPDDR2 DQ L CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ LPDDR2 CA M CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ Power N VSSCA VDDCA CA1 NB DQ19 NC DQ23 NC DM2 NC DQ0 VDDQ VSSQ Ground P VSS VDD2 CA0 NB VDDQ DQ17 NC DQ20 NC DQS2_t NC DQS2_c NC VSSQ Do Not Use/NC/No Ball R VDD1 VSS VACC NB VSS VSSQ VDDQ DQ22 NC VSSQ VDDQ ZQ T DNU NC NC NB VDD2 VDD1 DQ16 NC DQ18 NC DQ21 NC DNU Clock U DNU DNU NB NB NB NB NB NB DNU DNU NOTE 1 0.5mm (x32) or 0. 209-2E Page 7 2. A1 in Top Left Corner NOTE 4 See JESD21-C.65mm pitch (x32. x16).JEDEC Standard No.12.

20 rows NOTE 2 162 Ball Count NOTE 3 Top View. A1 in Top Left Corner NOTE 4 See JESD21-C.1 .65mm pitch (x32.JEDEC Standard No.12. Section 3.5mm (x32. 209-2E Page 8 2. x16).7 162-ball x16/x32 LPDDR2 and SDR-Flash package ballout 1 2 3 WP_n WP_n DAT0 IO11 DQS DAT1 NB IO3 DQ3 VSSQm 4 CLE CLE DAT6 ALE ALE DAT7 NB WE_n WE_n NC 5 VCCN VCCN VDDIm RE_n RE_n CLKm NB R/B_n R/B_n CMD 6 IO4 DQ4 DAT5 IO5 DQ5 DAT4 NB IO6 DQ6 NC 7 IO7 DQ7 DAT3 8 9 10 A DNU DNU VCCN VCCN VCCm DNU DNU B DNU VCCN VCCN VCCm IO14 NC DAT2 IO15 NC VCCQm VSS DNU C IO10 NC RST_n IO1 DQ1 NC NB NB NB NB SDR NVM Ball Definition where 3 labels are present D IO8 NC NC IO0 DQ0 NC IO2 DQ2 NC CE_n CE_n NC IO12 NC NC IO13 NC NC NB NB NB NB 1st Row 2nd Row 3rd Row NVM device ONFI device eMMC device E VSS IO9 NC NC VACC NB VDD2 VDD1 DQ31 NC DQ29 NC DQ26 NC DNU LPDDR2 Ball Definition where 2 labels are present F VDD1 VSS ZQ1 NB VSS VSSQ VDDQ DQ25 NC VSSQ VDDQ 1st Row 2nd Row x32 device x16 device G VSS VDD2 ZQ0 NB VDDQ DQ30 NC DQ27 NC DQS3_t NC DQS3_c NC VSSQ H VSSCA CA9 CA8 NB DQ28 NC DQ24 NC DM3 NC DQ15 VDDQ VSSQ J VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ K VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ L VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB M VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB Flash Memory  (eMMC/NVM/ONFI) ADD/CTRL N CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB LPDDR2 DQ P CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ LPDDR2 CA R CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ Power T VSSCA VDDCA CA1 NB DQ19 NC DQ23 NC DM2 NC DQ0 VDDQ VSSQ Ground U VSS VDD2 CA0 NB VDDQ DQ17 NC DQ20 NC DQS2_t NC DQS2_c NC VSSQ Do Not Use/NC/No Ball V VDD1 VSS VACC NB VSS VSSQ VDDQ DQ22 NC VSSQ VDDQ ZQ W DNU NC NC NB VDD2 VDD1 DQ16 NC DQ18 NC DQ21 NC DNU Clock Y DNU DNU NB NB NB NB NB NB DNU DNU NOTE 1 0. x16) or 0.

x16) or 0. x16). 22 rows NOTE 2 180 Ball Count NOTE 3 Top View.12.1 .65mm pitch (x32. and e-MMC package ballout 1 2 3 4 5 6 7 8 9 10 A DNU DNU WP_n CLE VCCN IO4 DQ4 IO7 DQ7 VCCN DNU DNU B DNU VCCN IO11 DQS ALE RE_n IO5 DQ5 IO14 NC IO15 NC VSS DNU C IO10 NC IO1 DQ1 IO3 DQ3 WE_n R/B_n IO6 DQ6 NB NB NB NB SDR NVM Ball Definition where 2 labels are present D IO8 NC IO0 DQ0 IO2 DQ2 CE_n IO12 NC IO13 NC NB NB NB NB 1st Row 2nd Row NVM device ONFI device E VSS IO9 NC VACC NB VDD2 VDD1 DQ31 NC DQ29 NC DQ26 NC DNU LPDDR2 Ball Definition where 2 labels are present F VDD1 VSS ZQ1 NB VSS VSSQ VDDQ DQ25 NC VSSQ VDDQ 1st Row 2nd Row x32 device x16 device G VSS VDD2 ZQ0 NB VDDQ DQ30 NC DQ27 NC DQS3_t NC DQS3_c NC VSSQ H VSSCA CA9 CA8 NB DQ28 NC DQ24 NC DM3 NC DQ15 VDDQ VSSQ J VDDCA CA6 CA7 NB VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ K VDD2 CA5 Vref(CA) NB DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ L VDDCA VSS CK_c NB DM1 VDDQ NB NB NB NB M VSSCA NC CK_t NB VSSQ VDDQ VDD2 VSS Vref(DQ) NB N CKE0 CKE1 CKE2 NB DM0 VDDQ NB NB NB NB P CS0_n CS1_n CS2_n NB DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ Flash Memory  (eMMC/NVM/ONFI) ADD/CTRL R CA4 CA3 CA2 NB VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ LPDDR2 DQ T VSSCA VDDCA CA1 NB DQ19 NC DQ23 NC DM2 NC DQ0 VDDQ VSSQ LPDDR2 CA U VSS VDD2 CA0 NB VDDQ DQ17 NC DQ20 NC DQS2_t NC DQS2_c NC VSSQ Power V VDD1 VSS VACC NB VSS VSSQ VDDQ DQ22 NC VSSQ VDDQ Ground W VCCm VDDIm NC NB VDD2 VDD1 DQ16 NC DQ18 NC DQ21 NC DNU Do Not Use/NC/No Ball Y VSS DAT2 CMD DAT6 DAT1 NB NB NB NB NB ZQ AA DNU VCCQm DAT4 CLKm DAT0 VCCm NB NB NB DNU Clock AB DNU DNU DAT3 DAT5 DAT7 VCCQm RST_n VSS DNU DNU NOTE 1 0. 209-2E Page 9 2. Section 3.JEDEC Standard No.5mm (x32. SDR-Flash.8 180-ball x16/x32 LPDDR2. A1 in Top Left Corner NOTE 4 See JESD21-C.

and e-MMC package ballout 1 2 3 DAT2 ADQ9 DQ2 4 DAT5 ADQ2 DQ5 5 VDDI VCCQ 6 7 8 9 10 11 A NC NC VCC VDD2 VSS VDDQ NC NC B NC VSSx DAT3 ADQ1 DQ3 DAT6 ADQ11 DQ6 DAT7 ADQ3 DQ7 VSSx VDD1 DQ15 DQ14 VSSQ NC SDR NVM Ball Definition where 3 labels are present C VCCQ DAT0 ADQ8 DQ0 DAT4 ADQ10 DQ4 CLK e CLK o. SDR Flash-NVM. CLK RE_n.12. W/R_n CE_n ALE WP_n VSSx represents common Flash VSS NOTE 1 0.n.f RE_n n.i INT o WP_n f.i DQ3 DQ2 VSSQ P NC VSSCA CA0 CKE2 CKE1 VACC VPP DQ0 DQ1 DQ4 VSSQ NC R NC NC VSS VDD2 VDD1 VSS VDD2 VSS VDDQ NC NC Ball C5 C6 C7 F7 G6 G7 N6 N7 eMMC (e) DAT[7:0] CLK CMD RST_n - OneNAND (o) AAD NOR (f) ADQ[15:0] CLK RDY / WAIT RP_n/RST_n WE_n OE_n CE_n AVD_n/AVD_n INT / WP_n NAND (n) DQ[15:0] R/B_n CLE WE_n RE_n CE_n ALE WP_n NAND DDR (i) DQ[15:0] DQS R/B_n CLE WE_n.f RP_n o CLE n.9 121-ball x16 LPDDR2.2 .JEDEC Standard No.i RST_n e.i W/R_n i CE_n DQS1_c DM1 VDDQ LPDDR2 CA H VDDCA CA5 ADQ13 DQ13 ADQ6 DQ11 ADQ4 DQ9 Vref(DQ) VDD2 Power J VDD2 Vref(CA) VSS ADQ14 DQ14 ADQ7 DQ10 ADQ5 DQ8 DQS0_c DM0 VDD1 Ground K CK_t CK_c ADQ15 DQ15 VSSx VCCn DQS0_t VDDQ Do Not Use/NC/No Ball L CS0_n CS1_n CS2_n DQ7 DQ6 VSSQ ZQ M CA4 CA3 DQ5 VDDQ Clock N VDDCA CA2 CA1 CKE0 AVD_n o ADV_n f ALE n.f DQS i CMD e RDY o WAIT f R/B_n n.5mm pitch.i DQ11 DQ12 DQ13 1st Row 2nd Row 3rd Row eMMC (e) OneNAND (o) / AAD Nor (f) Raw NAND (n) / ONFI2 (i) D VDD2 DAT1 ADQ0 DQ1 DQ10 VSSQ E VSS ZQ CA9 DQ8 DQ9 VDDQ Flash Memory  (eMMC/Raw NAND/OneNAND) F VDD1 CA8 VCCn VSSx WE_n CLK i DQS1_t VSSQ LPDDR2 DQ G VSSCA CA7 CA6 ADQ12 DQ12 OE_n o. Section 3. A1 in Top Left Corner NOTE 4 See JESD21-C. 209-2E Page 10 2. 15 rows NOTE 2 121 Ball Count NOTE 3 Top View.

including within the package and on the PCB. NOTE 3 CA pads and DQ pads shall be separated on opposite sides of die from top of silicon view. NOTE 2 Ordering of DQ bits shall be maintained in the system.10 LPDDR2 Pad Sequence CA Pad Sequence S4 S2A S2B N-A N-B VDD2 VSS VSS VDD1 VDD2 VSS VSS VDD1 VDD2 VSS VSS VDD1 VDD2 VSS VSS VDD1 VDD2 VSS VSS VDD1 VDD2 VSS Table 1 — LPDDR2 Pad Sequence x32 S4 S2A S2B N-A N-B VDD2 VSS VSS*1 VDD1 VDDQ VSSQ DQ31 DQ30 VDDQ DQ29 DQ28 VSSQ DQ27 DQ26 VDDQ DQ25 DQ24 VSSQ VSS VSS*1 VDD1 VSSQ DQ31 DQ30 VDDQ DQ29 DQ28 VSSQ DQ27 DQ26 VDDQ DQ25 DQ24 VSSQ VDD2 VSS VSS*1 VDD1 VSSQ DQ31 DQ30 VDDQ DQ29 DQ28 VSSQ DQ27 DQ26 VDDQ DQ25 DQ24 VSSQ VSS VSS*1 VDD1 VSSQ DQ31 DQ30 VDDQ DQ29 DQ28 VSSQ DQ27 DQ26 VDDQ DQ25 DQ24 VSSQ VDD2 VSS VSS*1 VDD1 VSSQ DQ31 DQ30 VDDQ DQ29 DQ28 VSSQ DQ27 DQ26 VDDQ DQ25 DQ24 VSSQ DQ Pad Sequence x16 x8 S4 S2A S2B N-A N-B S2A S2B N-A N-B VDD2 VSS VSS*1 VDD1 VSS VSS*1 VDD1 VDD2 VSS VSS*1 VDD1 VSS VSS*1 VDD1 VDD2 VSS VSS*1 VDD1 VSS VSS*1 VDD1 VDD2 VSS VSS*1 VDD1 VSS VSS*1 VDD1 VDD2 VSS VSS*1 VDD1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 DQS3_t DQS3_t DQS3_t DQS3_t DQS3_t DQS3_c DQS3_c DQS3_c DQS3_c DQS3_c VDDQ DM3 VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ ZQ CA9 CA8 VSSCA VDDCA CA7 CA6 CA5 VDD2 VSS VDDCA CK_c CK_t VSSCA CKE CS_N CA4 CA3 CA2 VDDCA VSSCA CA1 CA0 VSS VDDCA CK_c CK_t VSSCA CKE CS_N CA4 CA3 CA2 VDDCA VSSCA CA1 CA0 CA9 CA8 VSSCA VDDCA CA7 CA6 CA5 VDD1 VDD2 VSS VDDCA CK_c CK_t VSSCA CKE CS_N CA4 CA3 CA2 VDDCA VSSCA CA1 CA0 VSS VDDCA CK_c CK_t VSSCA CKE CS_N CA4 CA3 CA2 VDDCA VSSCA CA1 CA0 CA9 CA8 VSSCA VDDCA CA7 CA6 CA5 ZQ CA9 CA8 VSSCA VDDCA CA7 CA6 CA5 VDD1 VDD2 VDD2 VSS VSS VSS VDDCA CK_c CK_t VSSCA CKE CS_N CA4 CA3 CA2 VDDCA VSSCA CA1 CA0 VDDQ VSSQ DM0 VDDQ VSS VDD2 VDD1 VSS VSS VDD2 VDD1*1 VDDQ VSSQ DM0 VDDQ VSS VSS VDD2*1 VSS VDD2 VDD1 VSS VSS VDD2 VDD1*1 VSS VSS VDD2*1 VDD1 VSS VSS VDD2 VDD1*1 VSS VSS VDD2*1 ZQ CA9 CA8 VSSCA VDDCA CA7 CA6 CA5 DQ9 DQ8 VSSQ VDDQ DM3 VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VDDQ DM3 VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VDDQ DM3 VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VDDQ DM3 VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ VSSQ DQ15 DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ9 DQ8 VSSQ DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_t DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c DQS1_c VDDQ DM1 VSSQ VDDQ VDDQ DM1 VDDQ DM1 VDDQ DM1 VDDQ DM1 VDDQ DM1 VSSQ VDDQ VDD2 VSS VSS VDDQ DM1 VDDQ DM1 VDDQ DM1 VDDQ DM1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDD1 VDD2 VSS VSS*1 VDD1 VDD2 VSS*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDD1 VDD2 VSS VSS*1 VDD1 VDD2 VSS*1 VSS VDD1 VDD2 VSS VSS*1 VDD1 VDD2 VSS Vref(CA) Vref(CA) Vref(CA) Vref(CA) Vref(CA) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) Vref(DQ) VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 VSSQ*1 DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ DM0 VDDQ DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_c DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t DQS0_t VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DM2 VDDQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DM2 VDDQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DM2 VDDQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DM2 VDDQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DM2 VDDQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ VSSQ DQ7 DQ6 VDDQ DQ5 DQ4 VSSQ DQ3 DQ2 VDDQ DQ1 DQ0 VSSQ DQS2_c DQS2_c DQS2_c DQS2_c DQS2_c DQS2_t DQS2_t DQS2_t DQS2_t DQS2_t VSSQ DQ23 DQ22 VDDQ DQ21 DQ20 VSSQ DQ19 DQ18 VDDQ DQ17 DQ16 VSSQ VSS VDD2 VDD1 VSS VSS VDD2 VDD1 VSS VSS VDD2 VDD1 VSS VSS VDD2 VDD1 VSS VSS VDD2 VDD1 VSS VSS VDD2 VDD1 VSS*1 VSS VDD2 VDD1 VSS*1 VSS VDD1 VSS*1 VSS VDD2 VDDQ VSSQ DQ23 DQ22 VDDQ DQ21 DQ20 VSSQ DQ19 DQ18 VDDQ DQ17 DQ16 VSSQ VSSQ DQ23 DQ22 VDDQ DQ21 DQ20 VSSQ DQ19 DQ18 VDDQ DQ17 DQ16 VSSQ VSSQ DQ23 DQ22 VDDQ DQ21 DQ20 VSSQ DQ19 DQ18 VDDQ DQ17 DQ16 VSSQ VACC VDD1 VSS*1 VSS VSSQ DQ23 DQ22 VDDQ DQ21 DQ20 VSSQ DQ19 DQ18 VDDQ DQ17 DQ16 VSSQ VACC VDD1 VSS*1 VSS VDD2 VDD1 VSS*1 VSS VDD2 VDD1 VSS*1 VSS VDD1 VSS*1 VSS VDD2 VACC VDD1 VSS*1 VSS VACC VDD1 VSS*1 VSS VDD2 VDD1 VSS*1 VSS VDD1 VSS*1 VSS VDD2 VACC VDD1 VSS*1 VSS VACC VDD1 VSS*1 VSS VDD2 VDDQ*1 VDDQ*1 VDDQ*1 VDDQ*1 NOTE 1 Pads with (*1) are optional. DQ byte swapping and DQ bit Swapping are not allowed in the system. .JEDEC Standard No. 209-2E Page 11 2.

See Command Truth Table on page 148 for command code descriptions. DQS1_t and DQS1_c to the data on DQ8 .CA9 Input DQ0-DQ7 I/O (x8) DQ0 . The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c.DM3  (x32) Input Data Mask: For LPDDR2 devices that do not support the DNV feature. Power savings modes are entered and exited through CKE transitions. CK_c Type Input Description Clock: CK_t and CK_c are differential clock inputs.JEDEC Standard No. Single Data Rate (SDR) inputs.DQ15. For x16. Although DM is for input only.DQ15. It is output with read data and input with write data. DM1 is the input data mask signal for the data on DQ8-15. the DM loading shall match the DQ and DQS_t (or DQS_c). DQS0_t and DQS0_c correspond to the data on DQ0 . 209-2E Page 12 2.DQ7. See Command Truth Table on page 148 for command code descriptions. For x32 devices. CK_t and CK_c. Clock is defined as the differential pair. DQS1_t and DQS1_c to the data on DQ8 . CA is considered part of the command code. See Command Truth Table on page 148 for command code descriptions. Data Inputs/Output: Bi-directional data bus CKE Input CS_n Input CA0 .DQ23. DQS0_c (x8) DQS0_t.DQ15  (x16) DQ0 . DM0 Input (x8) DM0-DM1 (x16) DM0 .11 Input/output functional description 2. DM0 is the input data mask signal for the data on DQ0-7. DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. CS_n is sampled at the positive Clock edge. DQS1_t. DQS0_t and DQS0_c correspond to the data on DQ0 .DQ7. DQS1_c (x16) DQS0_t DQS3_t.DQ7. Chip Select: CS_n is considered part of the command code. Differential): The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DQS0_c. For x8.DQ31  (x32) DQS0_t. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. are sampled at the positive Clock edge.1 Pad Definition and Description Table 2 — Pad Definition and Description Name CK_t. DQS0_c DQS3_c (x32) I/O Data Strobe (Bi-directional.11. For x16 and x32 devices. DM is sampled on both edges of DQS_t. CKE is considered part of the command code. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. DQS3_t and DQS3_c to the data on DQ24 . DQS2_t and DQS2_c to the data on DQ16 . For x32 DQS0_t and DQS0_c correspond to the data on DQ0 . CS_n and CKE. CKE is sampled at the positive Clock edge. . DDR Command/Address Inputs: Uni-directional command/address bus inputs.DQ31. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. DM is the input mask signal for write data. DQS_t is edge-aligned to read data and centered with write data.

CK_t. CKE. The DM/DNV loading shall match the DQ and DQS_t (or DQS_c) loading. DNV1. DM/DNV is bidirectional (used for write and read data). DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. DM1 is the input data mask signal for the data on DQ8-15. and DQS3 respectively. LPDDR2-S4 and  LPDDR2-N-B devices. For x16 and x32 devices. DM/DNV is the input mask signal for write data and is an output signal validating a read burst. Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-9. DNV0. For data read accesses: See “LPDDR2: Data Not Valid” on page 92 for detailed description of DNV functionality. input with write data. DNV2. CKE.JEDEC Standard No. VDD1 VDD2 VDDCA VDDQ VACC Supply Core Power Supply 1: Core power supply for LPDDR2-N and LPDDR2-SX devices. For x32 devices. When not used for NVM device specific functionality. Supply Core Power Supply 2: Core power supply for LPDDR2-S2B. Supply Input Receiver Power Supply: Power supply for CA0-9. VACC enables some NVM device specific functionality.  For data write accesses: Input data is masked when DM/DNV is sampled HIGH coincident with DQ input data during a WRITE access. CS_n. CS_n. DM0 is the input data mask signal for the data on DQ0-7. and DNV3 are driven coincident with output read data. DNV1. DNV2. 209-2E Page 13 Name Type Description Input Data Mask/Data Not Valid: For LPDDR2 devices that support the DNV feature. Supply I/O Power Supply: Power supply for Data input/output buffers. DQS1. DQS2. DNV0. It is output with read data. and CK_c input buffers. VACC shall be driven to a level of VDD1. Supply NVM Acceleration Supply: NVM device specific embedded operation acceleration. and DNV3 are driven with the same value and shall be sampled with DQS0. Supply Ground Supply Ground for Input Receivers Supply I/O Ground I/O Reference Pin for Output Drive Strength Calibration DM0/DNV0 I/0 (x8) DM0/DNV0DM1/DNV1 (x16) DM0/DNV0 DM3/DNV3  (x32) VREF(CA) VREF(DQ) VSS VSSCA VSSQ ZQ NOTE 1 Data includes DQ and DM. and CK_c input buffers. . CK_t. Supply Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.

and is implied to be zero.12 LPDDR2 SDRAM Addressing Table 3 — LPDDR2 SDRAM Addressing Items Device Type Number of Banks Bank Addresses tREFI(us)*2 x8 Row Addresses Column Addresses x16 Row Addresses Column Addresses x32 Row Addresses Column Addresses *1 *1 *1 64Mb S2/S4 4 128Mb S2/S4 4 256Mb S2/S4 4 512Mb S2/S4 4 S2 4 1Gb S4 8 S2 4 2Gb S4 8 4Gb S2/S4 8 8Gb S2/S4 8 BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA1 BA0-BA2 BA0-BA1 BA0-BA2 BA0-BA2 BA0-BA2 15. all Row Buffers are in the Idle state. part of a row address (driven on the CA input pins) is stored in a Row Address Buffer (RAB) selected by BA2-BA0.9 R0-R13 C0-C10 R0-R13 C0-C9 R0-R13 C0-C8 3.9 R0-R14 C0-C10 R0-R14 C0-C9 R0-R14 C0-C8 3. Upon completion of Device Auto-Initialization. the remainder of the row address is driven on the CA input pins. RDB} pair selected by BA2-BA0 is referred to as a Row Buffer (RB). The Preactive command is optional when the desired RAB already contains the desired partial row address. Meanwhile. During a Read or Write command BA2-BA0 selects an RDB. The Activate command is optional when the desired RDB already contains the desired memory content. An {RAB. The Command Truth Table on page 148 defines the required assignment of logical address bits to CA pins. .” 2.13 LPDDR2 NVM Addressing 2.8 R0-R12 C0-C9 R0-R12 C0-C8 R0-R12 C0-C7 7.9 R0-R13 C0-C11 R0-R13 C0-C10 R0-R13 C0-C9 3. NOTE 2 tREFI values for all bank refresh is Tc = -25~85 C. Tc means Operating Case Temperature NOTE 3 Row and Column Address values on the CA bus that are not used are “don’t care. Activate also causes internal sensing circuits to transfer that memory content into a Row Data Buffer (RDB) also selected by BA2-BA0. During an Activate command. Scrambling of the logical address bits in any order different than those described in the Command truth table is prohibited. BA2-BA0 do not address any portion of the array and only select an RAB into which address is placed and/or an RDB into which data is placed. and the column address is driven on the CA input pins to choose the starting address of the read or write burst.1 Three-Phase Addressing The memory controller delivers an array address to the memory in three phases (See Figure 1 on page 15 and Figure 2 on page 16).6 R0-R11 C0-C9 R0-R11 C0-C8 R0-R11 C0-C7 7. 209-2E Page 14 2.6 R0-R11 C0-C8 R0-R11 C0-C7 R0-R11 C0-C6 15. BA2-BA0 select an RAB to retrieve the first part of the row address. The controller may use any value of BA2-BA0 for any array location.8 R0-R12 C0-C10 R0-R12 C0-C9 R0-R12 C0-C8 7.JEDEC Standard No.9 R0-R14 C0-C11 R0-R14 C0-C10 R0-R14 C0-C9 NOTE 1 The least-significant column address C0 is not transmitted on the CA bus. These two parts of the row address select one row from the memory array.8 R0-R12 C0-C10 R0-R12 C0-C9 R0-R12 C0-C8 3. During a Preactive command.8 R0-R13 C0-C10 R0-R13 C0-C9 R0-R13 C0-C8 7.13. and RABs contain 0x0000 and all RDBs contain indeterminate values.

NOTE 2 (RDB). 209-2E Page 15 2. NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus. RDB} pair selected by BA[2:0] is referred to as a Row Buffer (RB). NOTE 4 An {RAB. the lower order row address bit a[x] is dependent on the size of the Row Data Buffer NOTE 3 In the Read phase. column address bit C[y] is dependent on the size of the Row Data Buffer (RDB) and the data bus width.13.JEDEC Standard No. RDB} pair can be associated with any portion of the memory array.1 Three-Phase Addressing (cont’d) NVM Preactive Phase a[max:20] RAB #0 RAB #1 RAB #2 RAB #3 RAB #7 Activate Phase a[19:x] Upper Row Address BA[2:0] BA[2:0] Read Phase C[y:1] DQ Output State Machine BA[2:0] RDB #0 RDB #1 RDB #2 RDB #3 RDB #7 Sense Amplifiers Lower Row Address Row Decoder Memory Array Figure 1 — LPDDR2-N: Three-Phase Address Read NOTE 1 In the Preactive phase. In the Activate phase. a[max] is dependent on the density of the NVM device. . NOTE 6 An {RAB.

a[max] is dependent on the density of the NVM device. column address bit C[y] is dependent on the size of the Row Data Buffer (RDB) and the data bus width. RDB} pair selected by BA[2:0] is referred to as a Row Buffer (RB).4 RDB size*1 Table 5 — 128 Mb Addressing Configuration # of Row Buffers*2.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 8 Mb x 8 4 a22-a20 a19-A5 a4-a1 (C4-C1) 32 Bytes 4 Mb x 16 4 a22-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 2 Mb x 32 4 a22-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Column Address (READ/WRITE)*1. the lower order row address bit a[x] is dependent on the size of the Row Data Buffer NOTE 3 In the Write phase. NOTE 5 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.JEDEC Standard No.1 Three-Phase Addressing (cont’d) NVM Preactive Phase a[max:20] RAB #0 RAB #1 RAB #2 RAB #3 RAB #7 Activate Phase a[19:x] Upper Row Address BA[2:0] BA[2:0] Write Phase C[y:1] DQ Input State Machine BA[2:0] RDB #0 RDB #1 RDB #2 RDB #3 RDB #7 Sense Amplifiers Lower Row Address Row Decoder Memory Array Figure 2 — LPDDR2-N: Three-Phase Address Write NOTE 1 In the Preactive phase.13. In the Activate phase. 209-2E Page 16 2. NOTE 4 An {RAB. NOTE 2 (RDB).3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1.4 RDB size*1 16 Mb x 8 4 a23-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 8 Mb x 16 4 a23-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 4 Mb x 32 4 a23-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes . Table 4 — 64 Mb Addressing Configuration # of Row Buffers*2.

13.4 RDB size*1 32 Mb x 8 4 a24-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 16 Mb x 16 4 a24-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 8 Mb x 32 4 a24-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Table 7 — 512 Mb addressing Configuration # of Row Buffers*2.4 RDB size *1 Table 8 — 1 Gb addressing Configuration # of Row Buffers*2.4 RDB size *1 512 Mb x 8 4 a28-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 256 Mb x 16 4 a28-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 128 Mb x 32 4 a28-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes .4 RDB size *1 Table 9 — 2 Gb addressing Configuration # of Row Buffers*2.JEDEC Standard No.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1. 209-2E Page 17 2.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 128 Mb x 8 4 a26-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 64 Mb x 16 4 a26-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 32 Mb x 32 4 a26-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Column Address (READ/WRITE)*1.4 RDB size *1 256 Mb x 8 4 a27-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 128 Mb x 16 4 a27-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 64 Mb x 32 4 a27-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Table 10 — 4 Gb addressing Configuration # of Row Buffers*2.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 64 Mb x 8 4 a25-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 32 Mb x 16 4 a25-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 16 Mb x 32 4 a25-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Column Address (READ/WRITE)*1.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1.1 Three-Phase Addressing (cont’d) Table 6 — 256 Mb addressing Configuration # of Row Buffers*2.

BA0-BA2 (CA7r-CA9r).3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1.” . NOTE 4 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus. 209-2E Page 18 2.4 RDB size *1 The following notes apply to Table 4 through Table 13 (Tables 4-13) NOTE 1 All tables above show examples using minimum 32 Byte RDB Size. NOTE 5 Row and Column Address values on the CA bus that are not used are “don’t care. selected by Buffer Address.4 RDB size *1 1 Gb x 8 4 a29-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 512 Mb x 16 4 a29-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 256 Mb x 32 4 a29-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Table 12 — 16 Gb addressing Configuration # of Row Buffers*2.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 4 Gb x 8 4 a31-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 2 Gb x 16 4 a31-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 1 Gb x 32 4 a31-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Column Address (READ/WRITE)*1.4 RDB size *1 2 Gb x 8 4 a30-a20 a19-a5 a4-a1 (C4-C1) 32 Bytes 1 Gb x 16 4 a30-a20 a19-a5 a4-a2 (C3-C1) 32 Bytes 512 Mb x 32 4 a30-a20 a19-a5 a4-a3 (C2-C1) 32 Bytes Table 13 — 32 Gb addressing Configuration # of Row Buffers*2.JEDEC Standard No. NOTE 3 One Row Buffer consists of a pair of one Row Address Buffer (RAB) and one Row Data Buffer (RDB).13. A controller may use a smaller number of Row Buffers provided that the appropriate most significant BA addresses are driven to “0”. NOTE 2 The number of Row Buffers can be 4 or 8.1 Three-Phase Addressing (cont’d) Table 11 — 8 Gb addressing Configuration # of Row Buffers*2.3 Upper Row Address (PREACTIVE) Lower Row Address (ACTIVE)*1 Column Address (READ/WRITE)*1. see Table 14 on page 19 for other RDB sizes.

1 Three-Phase Addressing (cont’d) Table 14 — Addressing Dependent on RDB Size RDB Size 32 Byte Configuration Lower Row Address Column Address 64 Byte Lower Row Address Column Address 128 Byte Lower Row Address Column Address 256 Byte Lower Row Address Column Address 512 Byte Lower Row Address Column Address 1 KB Lower Row Address Column Address 2 KB Lower Row Address Column Address 4 KB Lower Row Address Column Address x8 a19-a5 a4-a1(C4-C1) a19-a6 a5-a1(C5-C1) a19-a7 a6-a1(C6-C1) a19-a8 a7-a1(C7-C1) a19-a9 a8-a1(C8-C1) a19-a10 a9-a1(C9-C1) a19-a11 x16 a19-a5 a4-a2(C3-C1) a19-a6 a5-a2(C4-C1) a19-a7 a6-a2(C5-C1) a19-a8 a7-a2(C6-C1) a19-a9 a8-a2(C7-C1) a19-a10 a9-a2(C8-C1) a19-a11 x32 a19-a5 a4-a3(C2-C1) a19-a6 a5-a3(C3-C1) a19-a7 a6-a3(C4-C1) a19-a8 a7-a3(C5-C1) a19-a9 a8-a3(C6-C1) a19-a10 a9-a3(C7-C1) a19-a11 a10-a1(C10-C1) a10-a2(C9-C1) a10-a3(C8-C1) a19-a12 a19-a12 a19-a12 a11-a1(C11-C1) a11-a2(C10-C1) a11-a3(C9-C1) NOTE 1 The least significant column address C0 is implied to be zero and is not transmitted on the CA bus.” .13. NOTE 2 Row and Column Address values on the CA bus that are not used are “don’t care.JEDEC Standard No. 209-2E Page 19 2.

296 bits 8 Gb has 8. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins.912 bits 1 Gb has 1. one clock cycle data transfer at the internal SDRAM/NVM core and four corresponding n-bit wide.869. command description and device operation. the LPDDR2 must be initialized.967. reads and writes to Overlay Window within the array memory space access the Overlay Window. accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The following section provides detailed information covering device initialization. LPDDR2-N is a high-speed Non-Volatile Memory device. LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation.934.728 bits 256 Mb has 268. one-half-clock-cycle data transfers at the I/O pins. Prior to normal operation.648 bits 4 Gb has 4. operations other than “array reads” are performed by accessing an overlay window that is mapped over the array space of the memory. These devices contain the following number of bits: 64 Mb has 67. When the overlay window is enabled. which is then followed by a Read or Write command. The address bits registered coincident with the Read or Write command are used to select the Row Buffer and the starting column location for the burst access. one-halfclock-cycle data transfers at the I/O pins. . The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed.738.870. accesses begin with the registration of an Preactive command.217. For LPDDR2-N devices.108. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. register definition.179. The 10-bit CA bus contains command.864 bits 128 Mb has 134.JEDEC Standard No. internally configured to have 4 or 8 Row Buffers.184 bits 32 Gb has 34. all array accesses map to the memory array.456 bits 512 Mb has 536. A single read or write access for the LPDDR2-S4 and LPDDR2-N effectively consists of a single 4n-bit wide. Each command uses one clock cycle. 209-2E Page 20 3 Functional description LPDDR2-S is a high-speed SDRAM device internally configured as a 4 or 8-Bank memory. accesses begin with the registration of an Activate command. Read and write accesses to the LPDDR2 are burst oriented.359. followed by an Activate command. address.824 bits 2 Gb has 2.147. which is then followed by a Read or Write command.483. For LPDDR2-SX devices.592 bits  The following densities apply to LPDDR2-NVM devices only: 16 Gb has 17. When the overlay window is disabled.589.741. LPDDR2-S4 and LPDDR2-N also use a double data rate architecture on the DQ pins to achieve high speed operation.435. during which command information is transferred on both the positive and negative edge of the clock. one clock cycle data transfer at the internal SDRAM core and two corresponding n-bit wide. and Bank/Row Buffer information.294.368 bits All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the system. A single read or write access for the LPDDR2-S2 effectively consists of a single 2n-bit wide. The address and BA bits registered coincident with the Preactive and Activate commands are used to select the row and the Row Buffer to be accessed. For LPDDR2-NVM devices. The Overlay Window Base Address (OWBA) is programmed using the Mode Registers.073. The overlay window is enabled and disabled by using the Mode Register.

the information provided by the state diagram should be integrated with the truth tables and timing specification. For the command definition. The truth tables provide complementary information to the state diagram.1 Simplified LPDDR2 Bus Interface State Diagram The simplified LPDDR2 bus interface state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. see “LPDDR2 Command Definitions and Timing Diagrams” on page 81. they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. . For a complete definition of the device behavior. 209-2E Page 21 3.JEDEC Standard No.

PRA*2 BST WR Writing WRA WRA*2 *2 Active*4 WR RD BST RD Reading RDA*2 RDA*2 PREACT*1 PR*2. not all details. NOTE 6 Resetting duration is variable. one or more Row Buffers have been activated. It is intented to provide a floorplan of the possible state transitions and commands to control them. NOTE 5 Use caution with this diagram. PRA*2 PR(A) = Precharge*2 (All) PREACT = Preactive*1 ACT = Activate WR(A) = Write (with Autoprecharge*2) RD(A) = Read (with Autoprecharge*2) BST = Burst Terminate Reset = Reset is achieved through MRW command MRW = Mode Register Write MRR = Mode Register Read PD = Enter Power Down PDX = Exit Power Down SREF = Enter Self Refresh*2 SREFX = Exit Self Refresh*2 DPD = Enter Deep Power Down*2 DPDX = Exit Deep Power Down*2 REF = Refresh*2 Writing with Autoprecharge Reading with Autoprecharge Precharging*2 Preactivating*1 SDRAM only*2 NVM only*1 NVM + SDRAM Figure 3 — LPDDR2: Simplified Bus Interface State Diagram NOTE 1 These transitions apply for LPDDR2-N devices only. In particular. NOTE 2 These transitions apply for LPDDR2-SX devices only. NOTE 4 For LPDDR2-NVM in the Active state. NOTE 3 For LPDDR2-SDRAM in the Idle state. 209-2E Page 22 3.1 Simplified LPDDR2 Bus Interface State Diagram (cont’d) Power Applied Resetting MR Reading Power On Reset MRR Resetting PD Resetting Power Down PDX Reset MRR Idle MR Reading Reset*1 MRW PDX MR Writing ACT Idle Power Down Idle*3 REF*2 Refreshing DPD*2 SREF*2 SREFX*2 Self Refreshing DPDX*2 Deep Power Down Automatic Sequence Command Sequence PD Active Power Down MRW*1 ACT*1 PDX PD MRR Active MR Reading PREACT*1 PR*2.JEDEC Standard No. NOTE 7 Reset command sets all Row Address Buffers to 0x0000. situations involving more than one Bank/Row Buffer are not captured in full detail. Poll DAI status bit to detect state transition to Idle. . all banks are precharged.

see “LPDDR2 Command Definitions and Timing Diagrams” on page 81.2 Simplified LPDDR2-SX State Diagram LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. .JEDEC Standard No. they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. The truth tables provide complementary information to the state diagram. 209-2E Page 23 3. For a complete definition of the device behavior. the information provided by the state diagram should be integrated with the truth tables and timing specification. For the command definition.

all banks are precharged.JEDEC Standard No. 209-2E Page 24 3. PRA Reading with Autoprecharge Precharging Figure 4 — LPDDR2-S: Simplified Bus Interface State Diagram NOTE 1 For LPDDR2-SDRAM in the Idle state.2 Simplified LPDDR2-SX State Diagram (cont’d) Power Applied Resetting MR Reading Power On Reset MRR Resetting PD Resetting Power Down PDX Reset MRR Idle MR Reading MRW PDX MR Writing ACT Idle Power Down Idle REF Refreshing DPD SREF SREFX Self Refreshing DPDX Deep Power Down Automatic Sequence Command Sequence PD Active Power Down PDX PD MRR Active MR Reading PR. PRA BST WR Writing WRA WRA WR Active*1 RD BST RD Reading RDA RDA Writing with Autoprecharge PR(A) = Precharge (All) ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) BST = Burst Terminate Reset = Reset is achieved through MRW command MRW = Mode Register Write MRR = Mode Register Read PD = Enter Power Down PDX = Exit Power Down SREF = Enter Self Refresh SREFX = Exit Self Refresh DPD = Enter Deep Power Down DPDX = Exit Deep Power Down REF = Refresh PR. .

209-2E Page 25 3. Idle MR Reading. 3. the information provided by the state diagram should be integrated with the truth tables and timing specification. The duration of Resetting.3. which are entered with a command and exited automatically. For the command definition see section See “LPDDR2 Command Definitions and Timing Diagrams” on page 81 LPDDR2-NVM has two types of states: stable states. Active. where each state transition. and transitory states. Activate and Enter Power Down. tINIT5. All Row Buffers return to the Idle state after tMRW. MR Writing. the following commands are allowed: Reset. which are entered and exited with a command. LPDDR2-NVM stable states are: Power-on. Preactive. (8) Mode Register Read command brings the Row Buffer to the Idle MR Reading state.3 Simplified LPDDR2-N Simplified Bus State Diagram LPDDR2-NVM simplified bus interface state diagram provides a simplified illustration of allowed bus interface state transitions and the related commands to control them. (9) Preactive command brings the Row Buffer to the Preactivating state. Mode Register Write. The device enters in Resetting Mode Register Reading state when MRR command is registered. see “Power-down” on page 138. (3) Mode Register Read (MRR) command can be issued from the Resetting state. (7) Mode Register Write command brings all Row Buffers to the MR Writing state.2 Idle state From the Idle state. Idle Power Down.JEDEC Standard No. LPDDR2-NVM transitory states are: Resetting. Mode Register Read. (5) Exit Power Down command brings all Row Buffers from the Resetting Power Down state back to the Resetting state after tXP. 3. and goes back automatically to Resetting state after tMRR. The Row Buffer goes automatically back to the Idle state after tRP. For the complete description of Power Down entry. is device specific and it is not defined in this document. The memory controller shall poll DAI bit to determine the completion of the device initialization. is represented with a numbered arc. Follows the description of all the allowed commands for any given state. Active MR Reading. memory characteristics. and Active Power Down. MRR allows retrieving useful information such as: memory type. Resetting MR Reading. . The arc number of each transition is included in the description in parenthesis. Resetting Power Down. LPDDR2-NVM state diagram is shown in Figure 5 on page 27. (4) Enter Power Down command brings all Row Buffers into the Resetting Power Down state. The Row Buffer goes automatically back to the Idle state after tMRR. and when issued. all Row Buffers are in the Idle state and all RABs have a default value of 0x0000. (6) Reset command brings all Row Buffers into the Resetting state after tINIT4. due to a command. (2) The Reset command is the only command allowed in this state.1 Power On and Resetting states (1) After power up. Idle. For a more detalied definition of the device bus interface. or the Resetting status through the DAI bit. see “Power-down” on page 138. Upon completion of device initialization. the device goes in the Power On state. it brings all Row Buffers (RB) into the Resetting state after tINIT4. Writing and Preactivating.3. Reading. For the complete description of Power Down exit.

(18) Read command moves the Row Buffer to the Reading state. 3. Write and Enter Power Down. or after a Burst Terminate command. (12) Exit Power Down command brings the Row Buffer from the Idle Power Down state back to the Idle state after tXP. Activate or Enter Power Down commands that might occur. Mode Register Write. Mode Register Read. For the complete description of power down exit see “Power-down” on page 138. Mode Register Write. Mode Register Read. the Row Buffer remains in the Reading state. or after a Burst Terminate command. the following commands are allowed: Reset. See “Burst Read Command” on page 86 for timing restrictions to apply between the Read command and a following Read. Activate or Enter Power Down commands that might occur.3. (15) Mode Register Read command brings the Row Buffer to the Active MR Reading state. which is not explicitly shown in the state diagram. All Row Buffers return to the Idle state after tMRW. If a new Read command is issued within BL/2 clock cycles. (17) Activate command brings the Row Buffer from the Active state to the Row Activating state. (13) Reset command brings all Row Buffers into the Resetting state after tINIT4. The Row Buffer goes automatically from the Row Activating state to the Active state after tRCD. which is not explicitly shown in the state diagram. . Write. (20) Enter Power Down command brings the Row Buffer into the Active Power Down state. (16) Preactive command brings the Row Buffer to the Preactivating state. The Row Buffer goes automatically back to the Active state after tMRR. For the complete description of power down entry see “Power-down” on page 138.JEDEC Standard No. Read. Activate. For the complete description of power down entry see “Power-down” on page 138. Preactive. See “Burst Write Operation” on page 94 for timing restrictions to apply between the Write command and the following Write. Mode Register Write. The Row Buffer goes automatically back to the Row Active state after BL/2 clock cycles. The Row Buffer goes automatically back to the Active state after tRCD. Mode Register Read. (14) Mode Register Write command brings all Row Buffers to the MR Writing state.2 Idle state (cont’d) (10) Activate command brings the Row Buffer from the Idle state to the Row Activating state. The Row Buffer goes automatically to the Idle state after tRP. Read. (11) Enter Power Down command brings the Row Buffer into the Idle Power Down state. Preactive. The Row Buffer goes automatically back to the Row Active state after BL/2 clock cycles. Preactive.3. For the complete description of power down exit see “Power-down” on page 138.3 Active state From the Active state. (19) Write command moves the Row Buffer to the Writing state. the Row buffer remains in the Writing state. If a new Write command is issued within BL/2 clock cycles. 209-2E Page 26 3. (21) Exit Power Down command brings the Row Buffer from the Active Power Down state back to the Row Active state after tXP.

one or more Row Buffers have been activated. situations involving more than one Row Buffer are not captured in full detail.3.3 Active state (cont’d) 1 Power Applied Resetting MR Reading Power On 2 Reset MRR Resetting 4 PD Resetting Power Down PDX 5 6 Reset 8 MRR Idle MR Reading Reset 13 Idle Automatic Sequence Command Sequence 3 7 MRW PDX 12 MR Writing 10 ACT PD 11 Idle Power Down 9 Active Power Down 14 MRW 21 PDX 20 PD 17 ACT 15 MRR Active MR Reading PREACT BST WR Writing 19 WR Active 18 RD BST RD Reading 16 PREACT PREACT = Preactive ACT = Activate WR = Write RD = Read BST = Burst Terminate Reset = Reset is achieved through MRW command MRW = Mode Register Write MRR = Mode Register Read PD = Enter Power Down PDX = Exit Power Down Preactivating Figure 5 — LPDDR2-N: Simplified Bus Interface State Diagram NOTE 1 For LPDDR2-NVM in the Active state. 209-2E Page 27 3. NOTE 3 Resetting duration is variable. It is intented to provide a floorplan of the possible state transitions and commands to control them. NOTE 2 Use caution with this diagram. . Poll DAI status bit to detect state transition to Idle. not all details. NOTE 4 Reset command sets all Row Address Buffers to 0x0000.JEDEC Standard No. In particular.

Furthermore. On or before the completion of the power ramp (Tb) CKE must be held low. CKE and clock: Beginning at Tb.200 mV. The memory controller may optionally issue a Precharge-All command (for LPDDR2-SX) or Preactive (for LPDDR2-N) prior to the MRW Reset command. 209-2E Page 28 3. Reset command: After tINIT3 is satisfied. NOTE VDD2 is not present in some systems.  The clock period shall be within the range defined for tCKb (18 ns to 100 ns). (Td). tIH) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges).1 Power Ramp and Device Initialization The following sequence shall be used to power up an LPDDR2 device. VDD1 and VDD2 must be greater than VDDCA . tDQSCK) may have relaxed timings (e. 2. and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. Power ramp duration tINIT0 (Tb . Unless specified otherwise. and VSSCA pins may not exceed 100 mV. after which it may be asserted high. Reference voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are met. VSSQ. CKE shall be held at a logic low level (=< 0. S4 and N devices.1 on page 160.Ta) must be no greater than 20 ms. a MRW(Reset) command shall be issued (Td). CK_t. . tDQSCKb) before the system is appropriately configured. The following conditions apply: Ta is the point where any power supply first reaches 300 mV.  While keeping CKE high.200 mV. The above conditions apply between Ta and power-off (controlled or uncontrolled).JEDEC Standard No. After Ta is reached.2 x VDDCA). see Table 7. CK_c. 1.200 mV. and Power-Off LPDDR2 Devices must be powered up and initialized in a predefined manner. Wait for at least tINIT4 = 1 s while keeping CKE asserted and issuing NOP commands. CS_n and CA inputs must observe setup and hold time (tIS. DM. CKE. Clock must be stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc). DQ. Power Ramp While applying power (after Ta). CS_n. and Table 71 on page 160.4 Power-up. Table 70 on page 160. 3. issue NOP commands for at least tINIT3 = 200 us.g. the subsequent MRW Reset command will set each Row Address Buffers (RAB) to 0x0000 overwriting the value stored by the previous preactive command. After Ta is reached.4. The voltage difference between any of VSS. Initialization. CKE must remain low for at least tINIT1 = 100 ns.g. 3. VDD1 must be greater than VDD2 . if any Mode Register Reads are performed. Tb is the point when all supply voltages are within their respective min/max operating conditions. VREF must always be less than all other supply voltages. After Ta is reached. For LPDDR2-N devices. After Ta is reached. some AC parameters (e. VDD1 and VDD2 must be greater than VDDQ . these steps are mandatory and apply to S2. For supply and reference voltage operating conditions. Rules related to VDD2 in those cases do not apply. Operational procedures other than those specified may result in undefined operation. all other inputs shall be between VILmin and VIHmax. DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up.

Optionally.). the controller must not overlap ZQ Calibration commands. MR1. For LPDDR2 devices which do not support the ZQ Calibration command. After the DAI-bit (MR0. This command is used to calibrate the LPDDR2 output drivers (RON) over process. See the Mode Register section of this specification for default values. ZQ Calibration:  After tINIT5 (Tf).  As the memory output buffers are not properly configured yet. CKE may go low in accordance to Power-Down entry and exit specification (see “Powerdown” on page 138).  Therefore. 6. and temperature.  The LPDDR2 device will now be in IDLE state and ready for any valid command. Normal Operation: After tZQINIT (Tg). MR2. To support simple boot from the NVM. 209-2E Page 29 3. this command shall be ignored. the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. . Specifically. The memory controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding. 5. In systems in which more than one LPDDR2 device exists on the same bus.   For NVM devices. To obtain the shortest boot up time and ensure compatibility with any future NVM device it is recommended to not rely on any predetermined tINIT5 value.  After Tg.1 Power Ramp and Device Initialization (cont’d) 4.JEDEC Standard No. after Te. some Mode Registers are reset to default values during Device Auto-Initialization. MRW commands shall be used to properly configure the memory. an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). A Value for tINIT5 value is not defined for NVMs in this document because it is device dependent. it is recommended to determine the device type and other device characteristics by issuing MRR commands (MR0 “Device Information” etc.  All SDRAM devices will set the DAI-bit no later than tINIT5 (10 us) after the Reset command. voltage. the clock frequency may be changed according to the clock frequency change procedure described in section “Input clock stop and frequency change” on page 146 of this specification.  After the DAI-Bit is set. Mode Registers Reads and Device Auto-Initialization (DAI) polling:  After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed.  The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the memory controller shall wait a minimum of tINIT5 before proceeding. The only way to determine when Device Auto-Initialization is complete is to poll DAI. for example the output buffer driver strength.4. repetitive polling of the DAI-Bit is required to determine when this bit has internally been set to zero “DAI complete“ by the memory device. the device is in idle state (Tf). latencies etc. “DAI”) is set to zero “DAI complete“ by the memory device. The state of the DAI status bit can be determined by an MRR command to MR0. and MR3 shall be set to configure the memory for the target frequency and memory configuration. some AC parameters may have relaxed timings before the system is appropriately configured. The device is ready for normal operation after tZQINIT.

1 Power Ramp and Device Initialization (cont’d) Table 15 — Timing Parameters for initialization Symbol tINIT0 tINIT1 tINIT2 tINIT3 tINIT4 tINIT5 tZQINIT tCKb 1 18 100 100 5 200 1 S: 10 N: vendor Value min max 20 Unit ms ns tCK s s s s s ns Comment Maximum Power Ramp Time Minimum CKE low time after completion of power ramp Minimum stable clock before first CKE high Minimum Idle time after first CKE assertion Minimum Idle time after Reset command Maximum duration of  Device Auto-Initialization ZQ Initial Calibration for LPDDR2-S4 and LPDDR2-N devices Clock cycle time during boot Ta Tb Tc tINIT2 = 5 tCK (min) Td Te Tf Tg CK_t / CK_c tINIT0 = 20 ms (max) Supplies tINIT3 = 200 us (min) tINIT1 = 100 ns (min) CKE tISCKE tINIT5 PD tZQINIT tINIT4 = 1 us (min) CA* RESET MRR ZQC Valid DQ * Midlevel on CA bus means: valid NOP Figure 6 — Power Ramp and Initialization Sequence 3. the reinitialization procedure shall begin with step 3 (Td).2 Initialization after Reset (without Power ramp): If the RESET command is issued outside the power up initialization sequence. .4. 209-2E Page 30 3.JEDEC Standard No.4.

all embedded operations must be finished or aborted and the device must be in the ready state (Status Register. Between Tx and Tz. any power supply current capacity must be zero. CKE shall be held at a logic low level (=< 0.1 on page 160. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low.JEDEC Standard No.5 V/usec between Tx and Tz. these steps are mandatory and apply to S2. VREF must always be less than all other supply voltages.4. Tz is the point where all power supply first reaches 300 mV. Table 70 on page 160. The relative level between supply voltages are uncontrolled during this period. VDD1 and VDD2 must be greater than VDDQ . see Table 7. VDD1 and VDD2 must be greater than VDDCA .4 Uncontrolled Power-Off Sequence The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition. S4 and N devices. DQ. The voltage difference between any of VSS. 209-2E Page 31 3. . For supply and reference voltage operating conditions. and VSSCA pins may not exceed 100 mV. bit 7 = “1”) prior to Power-off. After turning off all power supplies. The time between Tx and Tz (tPOFF) shall be less than 2s. VSSQ. The time between Tx and Tz (tPOFF) shall be less than 2s. and CA input levels must be between VSSCA and VDDCA during power off sequence to avoid latch-up. DQS_t. Between Tx and Tz. VDD1 and VDD2 shall decrease with a slope lower than 0. Uncontrolled power off sequence can be applied only up to 400 times in the life of the device. the device is powered off. Between Tx and Tz. Unless specified otherwise. CK_c. S4 and N devices. and Table 71 on page 160. DM. all other inputs shall be between VILmin and VIHmax.4.200 mV. and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid latch-up.2 x VDDCA). VDD1 must be greater than VDD2 . CS_n. the device is powered off. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. While removing power.200 mV. NOTE VDD2 is not present in some systems. The following conditions apply: Between Tx and Tz. CK_t. these steps are mandatory and apply to S2. Unless specified otherwise. Tz is the point where all power supplies are below 300 mV.3 Power-off Sequence The following sequence shall be used to power off the LPDDR2 device. After Tz. After Tz.200 mV. Rules related to VDD2 in those cases do not apply. except for any static charge remaining in the system. Table 16 — Timing Parameters Power-Off Symbol tPOFF Value min max 2 Unit s Comment Maximum Power-Off ramp time 3. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. For LPDDR2-N devices.

NVM Temp. 209-2E Page 32 3. Alert Basic Config-1 Basic Config-2 Basic Config-3 Basic Config-4 Test Mode IO Calibration (reserved) Access OP7 R W W W R R R R R R W W I/O width TUF TUF OP6 (RFU) nWR (for AP) (RFU) (RFU) (RFU) (RFU) OP5 OP4 OP3 OP2 OP1 DI BL RL & WL DS Refresh Rate NVM Temp. Alert OP0 DAI Link go to MR0 go to MR1 go to MR2 go to MR3 go to MR4 go to MR5 go to MR6 go to MR7 Type go to MR8 go to MR9 go to MR10 go to MR11 RZQI DNVI (optional) WC BT LPDDR2 Manufacturer ID Revision ID1 Revision ID2 Density Vendor-Specific Test Mode Calibration Code (RFU) Table 18 — Mode Register Assignment in LPDDR2 SDRAM/NVM (SDRAM part) MR# 16 17 18-19 MA <7:0> 10H 11H 12H-13H Function PASR_Bank (S4) PASR_Bank (S2) PASR_Seg (Reserved) access OP7 W W OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link go to MR16 go to MR17 go to MR18 Bank Mask (RFU) Segment Mask (S4 SDRAM only) (RFU) PASR .JEDEC Standard No.5 3. Mode Register Read command shall be used to read a register. Additionally Table 20 shows RFU mode registers and Reset Command. Device Feature 1 Device Feature 2 I/O Config-1 SDRAM Refr.1 Mode Register Definition Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM Table 17 shows the 16 common mode registers for LPDDR2 SDRAM and NVM. Table 17 — Mode Register Assignment in LPDDR2 SDRAM/NVM(Common part) MR# 0 1 2 3 4 5 6 7 8 9 10 11:15 MA <7:0> 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH~0FH Function Device Info.5. Mode Register Write command shall be used to write a register. and “R/W” if it can be read and written. “W” if it can be written but not read. R. Each register is denoted as “R” if it can be read but not written. Table 18 shows only LPDDR2 SDRAM mode registers and Table 19 shows only LPDDR2 NVM mode registers.

DQS_c shall be toggled. NOTE 2 RFU bits shall be read as ‘0’ during Mode Register reads. NOTE 4 All Mode Registers that are specified as RFU shall not be written. NOTE 5 See Vendor Device Datasheets for details on Vendor Specific Mode Registers.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) Table 19 — Mode Register Assignment in LPDDR2 SDRAM/NVM (NVM part) MR# 20 21 22-23 24 25 26 27 28 29 30-31 MA <7:0> 14H 15H 16H-17H 18H 19H 1AH 1BH 1CH 1DH 1EH-1FH Function NVM Geometry NVM tRCD (Reserved) Overlay Window Enable OW Base-Addr 1 OW Base-Addr 2 OW Base-Addr 3 (Reserved) DNV Long Delay (Reserved) R R/W R/W R/W R/W (RFU) OW base-addr 31 (a19 ~ a13) OW base-addr 2 (a27 ~ a20) (RFU) (RFU) OW base-addr 3 (a31 ~ a28) go to MR28 go to MR29 go to MR30 access OP7 R R OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link go to MR20 go to MR21 go to MR22 OWD OWE go to MR24 0 go to MR25 (RFU) RB tRCD De-Rating Number RDB size tRCD Value (2nd order) tRCD Value (1st order) (RFU) tDNV Value (2nd order) tDNV Value (1st order) (RFU) Table 20 — Mode Register Assignment in LPDDR2 SDRAM/NVM (DQ Calibration and Reset Command) MR# 32 33:39 40 41:47 48:62 63 127 MA <7:0> 20H 21H~27H 28H 29H~2FH 30H~3EH 3FH 7FH Function DQ Calibration Pattern A (Do Not Use) DQ Calibration Pattern B (Do Not Use) (Reserved) Reset (Reserved) (Do Not Use) (Reserved for Vendor Use) (Do Not Use) (Reserved for Vendor Use) (Do Not Use) (RFU) (RFU) W (RFU) X (RFU) R See “DQ Calibration” on page 130 access OP7 R OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link go to MR32 go to MR33 go to MR40 go to MR41 go to MR48 go to MR63 go to MR64 go to MR127 go to MR128 go to MR191 go to MR192 go to MR255 See “DQ Calibration” on page 130 64:126 40H~7EH 128:190 80H~BEH 191 BFH 192:254 C0H~FEH 255 FFH The following notes apply to tables 17-20: NOTE 1 RFU bits shall be set to ‘0’ during Mode Register writes.JEDEC Standard No. 209-2E Page 33 3. . NOTE 6 Writes to read-only registers shall have no impact on the functionality of the device.5. NOTE 3 All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t.

209-2E Page 34 3. NOTE 5 In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4).JEDEC Standard No. NOTE 2 If DNV functionality is not implemented. .5. OP[4:3] shall be set to 01. NOTE 4 If ZQ is connected to VDDCA to set default calibration. will be set upon completion of the MRW ZQ Initialization Calibration command.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR0_Device Information (MA<7:0> = 00H): OP7 OP6 (RFU) OP5 OP4 OP3 OP2 OP1 DI OP0 DAI RZQI (optional) DNVI DAI (Device Auto-Initialization Status) Read-only OP0 DI (Device Information) Read-only OP1 1B: DAI still in progress 0B: S2 or S4 SDRAM 1B: NVM 0B: DAI complete DNVI (Data Not Valid Information) Read-only OP2 0B: DNV not supported 1B: DNV supported 00B: RZQ self test not supported 01B: ZQ-pin may connect to VDDCA or float 10B: ZQ-pin may short to GND 11B: ZQ-pin self test completed. NOTE 6 In the case of the ZQ self-test returning a value of 11b. this result indicates that the device has detected a resistor connection to the ZQ pin. if supported. It is recommended that the assembly error is corrected. and will ignore ZQ calibration commands. the LPDDR2 device will default to factory trim settings for RON.2 RZQI (Built in Self Test for RZQ Information) Read-only OP4:OP3 3 NOTE 1 LPDDR2 SDRAM will not implement DNV functionality. either OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error.e. NOTE 3 RZQI. If ZQ is not connected to VDDCA. the device shall not drive the DM/DNV signals. However. no error condition detected (ZQpin may not connect to VDDCA or float nor short to GND) 1. this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i. 240-ohm +/-1%). In either case. the system may not function as intended.

interleaved is not an official combination to be supported. . It is determined by RU(tWR/tCK).JEDEC Standard No. NOTE 4 OP7:OP5 are reserved for LPDDR2-NVM. NOTE 2 Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. 209-2E Page 35 MR1_Device Feature 1 (MA<7:0> = 01H): OP7 OP6 OP5 OP4 WC OP3 BT OP2 OP1 BL OP0 nWR (for AP) BL Write-only OP<2:0> 011B: BL8 010B: BL4 (default) 100B: BL16 All others: reserved BT WC Write-only OP<3> OP<4> 0B: Sequential (default) 0B: Wrap (default) 1B: Interleaved (allowed for SDRAM only) 1B: No wrap (allowed for SDRAM BL4 only) 010B: nWR=4 011B: nWR=5 001B: nWR=3 (default) 1 Write-only nWR Write-only OP<7:5> 101B: nWR=7 110B: nWR=8 All others: reserved 100B: nWR=6 2 NOTE 1 BL 16. NOTE 3 BL16 is not supported by LPDDR2-NVM with Row Data Buffer size equal to 32-Byte and Data Bus Width equal to 32-bit.

C0. 2. For BL=4. It is implied zero. 209-2E Page 36 3. For BL=16. the burst address represents C3 . C0 input is not present on CA bus.JEDEC Standard No.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) Table 21 — Burst Sequence by BL. and WC C3 C2 C1 C0 WC BT BL X X X X 0B 0B X 1B 0B X X 0B wrap any nw any Burst Cycle Number and Burst Address Sequence 1 0 4 2 y 0 2 seq 4 6 wrap 8 0 2 int 4 6 nw any 0 2 4 seq 16 A C E int nw any B D F C E 0 D F 1 E F 0 1 2 3 0 1 2 3 4 5 2 3 4 5 6 7 4 6 8 5 7 9 6 8 A 7 9 B 8 A C 9 B D 6 8 1 3 5 7 9 2 4 6 8 A 3 5 7 9 B 2 1 3 3 2 0 4 3 1 5 6 7 8 9 10 11 12 13 14 15 16 y+1 y+2 y+3 1 3 5 7 1 3 5 7 2 4 6 0 2 0 6 4 3 5 7 1 3 1 7 5 4 5 6 7 6 7 0 1 0 1 2 3 2 3 4 5 4 5 6 7 6 7 4 5 0 1 2 3 2 3 0 1 illegal (not allowed) 4 5 6 7 8 9 6 7 8 9 A B 8 9 A B C D A B C D E F C D E F 0 1 A C E 0 2 B D F 1 3 C E 0 2 4 D F 1 3 5 E 0 2 4 6 F 1 3 5 7 X 0B 0B 0B X 0B 1B 0B X 1B 0B 0B X 1B 1B 0B X 0B 0B 0B X 0B 1B 0B X 1B 0B 0B X 1B 1B 0B X X X 0B 0B 0B 0B 0B 0B 0B 1B 0B 0B 1B 0B 0B 0B 1B 1B 0B 1B 0B 0B 0B wrap 1B 0B 1B 0B 1B 1B 0B 0B 1B 1B 1B 0B X X X X X 0B X 0B illegal (not allowed) illegal (not allowed) 1.C0. 3. For BL=8. the burst address represents C2 . The variable y may start at any address with C0 equal to 0 and may not start at any address in Table 22 below for the respective density and bus width combinations.5. .C0. the burst shall not cross the page boundary and shall not cross sub-page boundary. 4. the burst address represents C1 . 5. BT. For no-wrap (nw). BL4.

00. 000. 001 Not across sub page boundary 07E. BFF. 80. 01 1FE. 301 5FE. 01 7E. 081 0FE. 400. 601 BFE. 001 FE. 000. C00. 200.5. 0FF.6-ohm typical 0110B: 80-ohm typical 0111B: 120-ohm typical (optional) All others: reserved . 1FF. 3FF. 000. 201 3FE. 200. 3FF.JEDEC Standard No. 01 1FE. 200. 0FF. 17F.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) Table 22 — LPDDR2-SX Non Wrap Restrictions 64Mb x8 x16 x32 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb Not across full page boundary 1FE. 100. 600. 100. 201 3FE. 181 2FE. 000. 101 1FE. 001 3FE. 3FF. 001 7FE. 401 7FE. 81 None 0FE. 001 FFE. 180. 001 FE. FF. 209-2E Page 37 3. 001 3FE. 000. 0FF. 400. 100. 001 7FE. 400. 7FF. 2FF. 5FF. 07F. 1FF. MR2_Device Feature 2 (MA<7:0> = 02H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) RL & WL 0001B: RL = 3 / WL = 1 (default) 0010B: RL = 4 / WL = 2 0011B: RL = 5 / WL = 2 RL & WL Write-only OP<3:0> 0100B: RL = 6 / WL = 3 0101B: RL = 7 / WL = 4 0110B: RL = 8 / WL = 4 All others: reserved MR3_I/O Configuration 1 (MA<7:0> = 03H): OP7 OP6 OP5 OP4 OP3 OP2 DS 0000B: reserved 0001B: 34. 7FF. C01 7E. FF. 3FF. 1FF. 7FF. 000. FFF. 101 1FE. 080. 000. 3FF. 00. 00.3-ohm typical 0011B: 48-ohm typical DS Write-only OP1 OP0 (RFU) 0010B: 40-ohm typical (default) OP<3:0> 0100B: 60-ohm typical 0101B: reserved for 68. 401 x8 x16 x32 0FE. 800. 1FF. 1FF. 001 3FE. 401 None None None NOTE 1 Non-wrap BL=4 data-orders shown above are prohibited. 000. 201 3FE. 7F. 801 17E. 300. 000. 3FF. 7F. 1FF. 101 1FE.

NOTE 8 LPDDR2-NVM devices shall be de-rated by adding the value found at location OP5:OP4 in MR20 to the following core timing parameters: tRCD. tDQSCK shall be de-rated according to the tDQSCK de-rating in Table 103 on page 197. NOTE 3 If OP2 equals ‘1’. tRP. do not de-rate NVM AC timing (<=85C) Temperature Read-only OP<2:0> 100B: Temperature Alert not active. tRAS.25x tREFIpb. de-rate SDRAM AC timing 010B: 2x tREFI. NOTE 1 A Mode Register Read from MR4 will reset OP7 to ‘0’. 2x tREFIpb.25x tREFIpb. tRC. NOTE 9 See “Temperature Sensor” on page 129 for information on the recommended frequency of reading MR4.25x tREFI. 1B: OP<2:0> value has changed since last read of MR4. 2x tREFW 001B: 4x tREFI.JEDEC Standard No. NOTE 5 LPDDR2 might not operate properly when OP[2:0] = 000B or 111B. 0. tRC. do not de-rate NVM AC timing 111B: NVM High temperature operating limit exceeded Temperature Update Read-only Flag (TUF) OP<7> 110B: Temperature Alert active.25x tREFI. de-rate NVM AC timing Alert 101B: Temperature Alert active. 209-2E Page 38 3. de-rate NVM AC timings 0B: OP<2:0> value has not changed since last read of MR4. 1x tREFIpb.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) OP7 TUF TUF OP6 OP5 OP4 OP3 OP2 OP1 OP0 MR4_Device Temperature (MA<7:0> = 04H) (RFU) (RFU) SDRAM Refresh Rate NVM Temperature Alert 011B: 1x tREFI. 0. 0. Prevailing clock frequency spec and related setup and hold timings remain unchanged.25x tREFW. NOTE 4 OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4. 4x tREFW 000B: SDRAM Low temperature operating limit exceeded 010B: Reserved NVM 011B: Temperature Alert not active. do not de-rate SDRAM AC timing 111B: SDRAM High temperature operating limit exceeded 001B: Reserved 000B: NVM Low temperature operating limit exceeded 110B: 0. 4x tREFIpb. NOTE 2 OP7 is reset to ‘0’ at power-up. the device temperature is greater than 85C.25x tREFW. and tRRD. NOTE 7 LPDDR2-SX devices shall be de-rated by adding 1. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. 0. 1x tREFW (<=85C) SDRAM Read-only OP<2:0> Refresh Rate 100B: Reserved 101B: 0. tDQSCK shall be de-rated according to the tDQSCK de-rating in Table 103 on page 197.5. NOTE 6 For specified operating temperature range and maximum operating temperature refer to Table 72 on page 161. . and tRRD. OP<2:0> bits are undefined after power-up. tRAS.875 ns to the following core timing parameters: tRCD.

JEDEC Standard No.5. . 209-2E Page 39 3. MR7_Basic Configuration 3 (MA<7:0> = 07H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID2 Revision ID2 Read-only OP<7:0> 00000000B: A-version NOTE 1 MR7 is Vendor Specific.1Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR5_Basic Configuration 1 (MA<7:0> = 05H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 LPDDR2 Manufacturer ID 0000 0000B 0000 0001B 0000 0010B 0000 0011B 0000 0100B 0000 0101B 0000 0110B 0000 0111B 0000 1000B 0000 1001B 0000 1010B 0000 1011B 0000 1100B 0000 1101B 0000 1110B 1111 1110B 1111 1111B All Others : : : : : : : : : : : : : : : : : : Reserved Samsung Qimonda Elpida Etron Nanya Hynix Mosel Winbond ESMT Reserved Spansion SST ZMOS Intel Numonyx Micron Reserved LPDDR2 Manufacturer ID Read-only OP<7:0> MR6_Basic Configuration 2 (MA<7:0> = 06H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID1 Revision ID1 Read-only OP<7:0> 00000000B: A-version NOTE 1 MR6 is Vendor Specific.

JEDEC Standard No. the device operates with default calibration. either the ZQ calibration function (see “Mode Register Write ZQ Calibration Command” on page 135) or default calibration (through the ZQreset command) is supported. NOTE 6 Optionally. In both cases.5. the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connec- tion. and ZQ calibration commands are ignored. . If ZQ is connected to VDDCA. NOTE 3 See AC timing table for the calibration latency. 209-2E Page 40 3. NOTE 5 LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration command. NOTE 4 If ZQ is connected to VSSCA through RZQ.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR8_Basic Configuration 4 (MA<7:0> = 08BH): OP7 OP6 OP5 OP4 OP3 OP2 OP1 Type OP0 I/O width Density 00B: S4 SDRAM Type Read-only OP<1:0> 01B: S2 SDRAM 10B: N NVM 11B: Reserved 0001B: 128Mb 0010B: 256Mb 0100B: 1Gb 0011B: 512Mb 0101B: 2Gb 0110B: 4Gb 0000B: 64Mb Density Read-only OP<5:2> 0111B: 8Gb 1001B: 32Gb 00B: x32 I/O width Read-only 1000B: 16Gb all others: reserved 01B: x16 10B: x8 11B: not used OP<7:6> MR9_Test Mode (MA<7:0> = 09H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific Test Mode MR10_Calibration (MA<7:0> = 0AH): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Calibration Code 0xFF: Calibration command after initialization 0xAB: Long calibration Write-only OP<7:0> 0x56: Short calibration 0xC3: ZQ Reset others: Reserved Calibration Code NOTE 1 Host processor shall not write MR10 with “Reserved” values NOTE 2 LPDDR2 devices shall ignore calibration command when a “Reserved” value is written into MR10. the ZQ connection shall not change after power is applied to the device.

default) 1B: refresh blocked (=masked) 1 1. OP 0 1 2 3 4 5 6 7 Bank Mask XXXXXXX1 XXXXXX1X XXXXX1XX XXXX1XXX XXX1XXXX XX1XXXXX X1XXXXXX 1XXXXXXX 4-Bank S4 SDRAM Bank 0 Bank 1 Bank 2 Bank 3 - 8-Bank S4 SDRAM Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 .JEDEC Standard No. BA2=0 for 8-banks OP<1:0> 10B: 1/4 array .BA1=0 for 4-banks. For 4-bank S4 SDRAM. 209-2E Page 41 3.5. BA2=BA1=0 for 8-banks 11B: 1/8 array .Not used for 4-banks.BA1=BA0=0 for 4-banks. only OP<3:0> are used. BA2=BA1=BA0=0 for 8-banks S4 SDRAM: Bank <7:0> Mask Write-only OP<7:0> 0B: refresh enable to the bank (=unmasked.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR11:15_(Reserved) (MA<7:0> = 0BH-0FH): MR16_PASR_Bank Mask (MA<7:0> = 010H): S2 and S4 SDRAM only OP7 S2 SDRAM S4 SDRAM OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) Bank Mask (4-bank or 8-bank) PASR S2 SDRAM: 00B: Full array (default) PASR Map Write-only 01B: 1/2 array .

013H): MR20_NVM Geometry (MA<7:0> = 014H): NVM only OP7 OP6 OP5 OP4 OP3 RB Number OP2 OP1 RDB size OP0 (RFU) tRCD De-Rating 000B: 32B 001B: 64B 010B: 128B RDB Size Read-only OP<2:0> 100B: 512B 011B: 256B 101B: 1024B 110B: 2048B 111B: 4096B RB Number Read-only OP<3> 0B: 4 Row Buffers 1B: 8 Row Buffers 00B: 0 ns tRCD De-rating (tNVMDERATING) Read-only OP<5:4> 01B: 1.4Gb R13:11 000B 001B 010B 011B 100B 101B 110B 111B 8Gb R14:12 OP 0 1 2 3 4 5 6 7 Segment Mask XXXXXXX1 XXXXXX1X XXXXX1XX XXXX1XXX XXX1XXXX XX1XXXXX X1XXXXXX 1XXXXXXX R12:10 NOTE This table indicates the range of row addresses in each masked segment.5.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR17_PASR_Segment Mask (MA<7:0> = 011H): 1Gb ~ 8Gb S4 SDRAM only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment Mask Segment <7:0> Mask 0B: refresh enable to the segment (=unmasked.5 ns .JEDEC Standard No.75 ns 11B: 7. 209-2E Page 42 3. default) 1B: refresh blocked (=masked) Write-only OP<7:0> 1Gb Segment 0 1 2 3 4 5 6 7 2Gb.875 ns 10B: 3. X is do not care for a particular segment . MR18-19_Reserved (MA<7:0> = 012H .

5. 209-2E Page 43 3.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR21_NVM tRCD (MA<7:0> = 15H): NVM only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 tRCD Value (2nd order) tRCD Value (1st order) 0010B: 2ns tRCD Value (1st order = value ns) Read-only 0000B: 0ns 0001B: 1ns 0101B: 5ns 1001B: 9ns 0111B: 7ns 0011B: 3ns 0100B: 4ns OP<3:0> 1000B: 8ns 0110B: 6ns 1010B: 10ns 1100B: 12ns 0000B: 0ns 1110B: 14ns 1101B: 13ns 1111B: 15ns 0001B: 16ns 0101B: 80ns 0011B: 48ns 1011B: 11ns 0010B: 32ns tRCD Value (2nd order = valuex16 ns) Read-only 0100B: 64ns OP<7:4> 1000B: 128ns 1010B: 160ns 1100B: 192ns 0110B: 96ns 1001B: 144ns 1101B: 208ns 1111B: 240ns 1011B: 176ns 0111B: 112ns 1110B: 224ns NOTE 1 tRCD value is obtained adding 1st order value to the 2nd order value MR22:23_(Reserved) (MA<7:0> = 16H:17H): .JEDEC Standard No.

NOTE 2 Overlay Window Enable (OP0) shall be set to enable the Overlay Window (See Section on the NVM Overlay Window for more details). 209-2E Page 44 3. . NOTE 4 Only one bit is allowed to be set during any single MRW. unused row address bits outside of the device address space shall return ‘0’. When read. NOTE 2 Mode Registers 25-27 are readable are writeable NOTE 3 Only the value ‘0’ can be written to RFU bit. When read. When read RFU bit shall output ‘0’.The Overlay Window is aligned on a 8-Kbyte boundary. OP0 will reflect whether the Overlay Window is enabled (OP0 = “1”) or disabled (OP0 = “0”).1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR24_Overlay Window Enable (MA<7:0> = 18H): NVM Only OP7 OP6 OP5 OP4 (RFU) OP3 OP2 OP1 OWD OP0 OWE Overlay Window Disable (OWD) Read OP<1> Write Read OP<0> Write Reserved 0B: Nop 1B: Disable Overlay Window 0B: Overlay Window Disabled (Default) 1B: Overlay Window Enabled 0B: Nop 1B: Enable Overlay Window Overlay Window Enable (OWE) NOTE 1 Overlay Window Disable (OP1) shall be set to disable the Overlay Window (See Section on the NVM Overlay Window for more details). NOTE 6 When read. OP0 is set by an MRW command with OP0 = “1”.5. MR25:27_OW Base Address 1~3 (MA<7:0> = 19H-1BH): NVM only MR 25 26 27 19H 1AH 1BH OP7 a19 a27 OP6 a18 a26 OP5 a17 a25 OP4 a16 a24 OP3 a15 a23 a31 OP2 a14 a22 a30 OP1 a13 a21 a29 OP0 0 a20 a28 (RFU) NOTE 1 a12 .a0 are implied to be 0. “0”. OP1 returns as a reserved value. When read. NOTE 5 Only the value ‘0’ can be written to unused row address bits outside of the device address space. OP0 returns the status of the Overlay Window. NOTE 4 Only the value ‘0’ can be written to OP0 in MR25.JEDEC Standard No. OP1 is set by an MRW command with OP1 = “1”. NOTE 3 All values for MR24 are reset by the device to “0” during Device Auto-Initialization.

MR33:39_(Do Not Use) (MA<7:0> = 21H-27H): MR40_DQ Calibration Pattern B (MA<7:0> = 28H): Reads to MR40 return DQ Calibration Pattern “B”.JEDEC Standard No. . See “DQ Calibration” on page 130. See “DQ Calibration” on page 130. MR41:47_(Do Not Use) (MA<7:0> = 29H-2FH): MR48:62_(Reserved) (MA<7:0> = 30H-3EH): MR63_Reset (MA<7:0> = 3FH): MRW only OP7 OP6 OP5 OP4 X OP3 OP2 OP1 OP0 NOTE 1 For additonal information on MRW RESET see “Mode Register Write Command” on page 132.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR28_(Reserved) (MA<7:0> = 1CH): MR29_NVM tDNV (MA<7:0> = 1DH): NVM only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 tDNV Value (2nd order) tDNV Value (1st order) 0010B: 2us tDNV Value (1st order = value ns) 0100B: 4us Read-only 0000B: 0us 0001B: 1us 0101B: 5us 1001B: 9us 0111B: 7us 0011B: 3us OP<3:0> 1000B: 8us 0110B: 6us 1010B: 10us 1100B: 12us 0000B: 0us 1110B: 14us 1101B: 13us 1111B: 15us 0001B: 16us 0101B: 80us 0011B: 48us 1011B: 11us 0010B: 32us tDNV Value (2nd order = valuex16 us) 0100B: 64us Read-only OP<7:4> 1000B: 128us 1010B: 160us 1100B: 192us 0110B: 96us 1001B: 144us 1101B: 208us 1111B: 240us 1011B: 176us 0111B: 112us 1110B: 224us MR30:31_(NVM Reserved) (MA<7:0> = 1EH-1FH): MR32_DQ Calibration Pattern A (MA<7:0> = 20H): Reads to MR32 return DQ Calibration Pattern “A”.5. 209-2E Page 45 3.

209-2E Page 46 3.1 Mode Register Assignment and Definition in LPDDR2 SDRAM and NVM (cont’d) MR64:126_(Reserved) (MA<7:0> = 40H-7EH): MR127_(Do Not Use) (MA<7:0> = 7FH): MR128:190_(Reserved for Vendor Use) (MA<7:0> = 80H-BEH): MR191_(Do Not Use) (MA<7:0> = BFH): MR192:254_(Reserved for Vendor Use) (MA<7:0> = C0H-FEH): MR255_(Do Not Use) (MA<7:0> = FFH): .JEDEC Standard No.5.

Row Data Buffers are considered to be write through structures and any write issued to an Overlay Window register is completed when the issuing Write command is completed. OWE bit is automatically cleared to ‘0’. The Overlay Window can be enabled by setting the OWE bit of MR24 to ‘1’.  The Overlay Window can be positioned only at a 8-KByte aligned address within the address map.1 LPDDR2-N Software Interface Overlay Window LPDDR2-NVM functions are controlled using memory-mapped registers in an Overlay Window. system software can write to (and/or read from) each memory-mapped control register at the address OWBA+RegisterStaticOffset according to register definitions shown on the Overlay Window: Control Register Offsets and Definitions Table on page 48. The Overlay Window region contains: program buffer. registers to control memory array operation. Activate. memory-mapped control registers are located at static offsets from the base address (OWBA). the address region associated with the overlay window is accessed by the memory controller like any other section of memory in the array. the memory-mapped registers are not available. 209-2E Page 47 4 4. device information. While the Overlay Window is disabled. If OWE bit and OWD bit are set to ‘0’ the Overlay Window status does not change. System software can locate the Overlay Window within the memory address range of the device by setting Overlay Window Base Address (OWBA) in Mode Registers 25.JEDEC Standard No. Once the Overlay Window has been enabled. 26 and 27. etc. Within the Overlay Window. When the Overlay Window is enabled. . Preactive. While the Overlay Window is enabled. For LPDDR2-NVM devices. and Read/Write commands are used to access the Overlay Window. and it can be disabled by setting OWD bit of MR24 to ‘1’. If OWD bit is set to ‘1’. read accesses to addresses outside the Overlay Window region will access the memory array. Write commands to addresses outside the Overlay Window may not be allowed.

0x0D0 0x0FF – 0x0E0 Vendor-Specific Vendor-Specific # of bytes (decimal) 2 2 2 2 2 2 2 2 2 2 12 2 2 26 2 64 2 2 4 4 4 4 44 2 6 2 2 2 2 16 32 Vendor-Specific Vendor-Specific Type R R R R R R R Register Item Overlay Window Query String “P” Overlay Window Query String “F” Overlay Window Query String “O” Overlay Window Query String “W” Overlay Window ID Overlay Window Revision Overlay Window Size Reserved for JEDEC Default Value (hex) 0x00 . NOTE 5 Program-Buffer Size is the number of bytes in the Program-Buffer in this Overlay Window.0x20 Vendor-Specific Vendor-Specific Notes 3 1.0x80 Vendor-Specific Reserved for Vendor Use Vendor-Specific Program-Buffer NOTE 1 System Software shall not write to any Reserved register any value other than 0.2 R R Program-Buffer Offset Program-Buffer Size Reserved for JEDEC Vendor-Specific Vendor-Specific 4 5 1.10 Vendor-Specific 0x00 . 209-2E Page 48 4.1 Map of Control Registers (offsets and definitions) Table 23 describes the Overlay Window register map.2 0x00 .0x0CC 0x0CF .0x00 0x00 .0x00 1. NOTE 8 Multi-Purpose Register is used as DataCount[31:0] in the buffer-program command. NOTE 4 Program-Buffer Offset is the byte-addressing offset of the beginning of the Program-Buffer in this Overlay Window.0x03E 0x07F – 0x040 0x081 – 0x080 0x083 – 0x082 0x087 – 0x084 0x08B – 0x088 0x08F – 0x08C 0x093 – 0x090 0x0BF .0x00 6 1. Table 23 — Overlay Window: Control Register Offsets and Definitions Byte-Addressing Offset (hex) 0x001 – 0x000 0x003 – 0x002 0x005 – 0x004 0x007 – 0x006 0x009 – 0x008 0x00B – 0x00A 0x00D – 0x00C 0x00F – 0x00E 0x011 – 0x010 0x013 – 0x012 0x01F – 0x014 0x021 – 0x020 0x023 – 0x022 0x03D – 0x024 0x03F . NOTE 6 The memory shall reset this register to Default Value after Device Auto-Initialization.2 R R JEDEC Manufacturer ID JEDEC Device ID Reserved for JEDEC Vendor-Specific Vendor-Specific 1.2 2. and after complettion of prior command NOTE 7 Command Address = a[31:0] of byte-address.2 8 1.0x4F 0x00 .0x50 0x00 .0x0C2 0x0C9 . NOTE 3 Number of bytes in this Overlay Window.0x57 0x00 .0x0C0 0x0C7 . DataCount[31:0] = number of contiguous bytes to .2 W Reserved for JEDEC Vendor-Specific Reserved for Vendor Use W Command Code Reserved for JEDEC R/W W Command Data Command Address Reserved for JEDEC W Multi-Purpose Register Reserved for JEDEC W Command Execute Reserved for JEDEC R/W R/W R/W Suspend Abort Status Register Reserved for JEDEC Reserved for Vendor Use Reserved for Vendor Use 7 1.2 0x00 . Reserved registers and Write-Only registers will return indeterminate data.JEDEC Standard No. NOTE 2 When read.0x0CA 0x0CD .0x0CE 0x0DF . System software shall write “0” to any most-significant bits of a[31:23] not used by the memory device.0x46 0x00 .0x00 0x00 .1.0x094 0x0C1 .0x0C8 0x0CB .

it shall be loaded with the number of contiguous bytes to be programmed during a buffered program operation. Table 24 — Command Code Register Byte-Addressing Offset (hex) 0x081 – 0x080 # of bytes (decimal) 2 Type W Register Item Command Code Default Value (hex) 0x00 .1. DataCount. See “LPDDR2-NVM Operations” on page 54.1 Command Code Register Device command codes (e.4 Multi-Purpose Register The Multi-Purpose Register is used in several operations. 209-2E Page 49 be programmed using the Program-Buffer.JEDEC Standard No.g. Command execution occurs only after 0x0001 is written to the Command Execute Register. System software shall write “0” to any most-significant bits of a[31:23] not used by the memory device. the block address for erase operation) is written to this registers. the first data address for buffered program operation. Table 27 — Multi-Purpose Register Byte-Addressing Offset (hex) 0x093 – 0x090 # of bytes (decimal) 4 Type W Register Item Multi-Purpose Register Default Value (hex) . in conjunction with Command Address. and the Status Register. Abort. The address value (a[31:0]) shall be in byte units. but some products may not require.0x03F is a Write-Only register that is reserved. system software to write to this register. Suspend..1.g.1. NOTE 9 Only one of the following registers may be written to with a value other than 0x0000 during any Write burst: Command Execute.0x00 4.1.3 Command Address Register The command address (e. Table 26 — Command Address Register Byte-Addressing Offset (hex) 0x08B – 0x088 # of bytes (decimal) 4 Type W Register Item Command Address Default Value (hex) 4.1. Table 25 — Command Data Register Byte-Addressing Offset (hex) 0x087 – 0x084 # of bytes (decimal) 4 Type R/W Register Item Command Data Default Value (hex) 4. When read. Results of queries might be provided through this register.1.2 Command Data Register Command data might be written to this register.1. for a examples of how the Overlay Window Registers are used. For example. All products allow.. 0x0020 for Block Erase) are written to this register. this location will return indeterminate data.1. It shall be loaded with the last block address during a block lock/unlock/lock-down operation. 4. This register is cleared to its default value after command execution is completed.  NOTE 10 Overlay Window location 0x03E . shall not cause data to wrap beyond the end of the Program-Buffer.

Once the device is suspended. the Suspend register is reset by the device and returns “0x0000” when read.6=1 indicates erase suspend was successful. Refer to section “Program/Erase Suspend” on page 75 for additional details.0x0C0 # of bytes (decimal) 2 Type W Register Item Command Execute Default Value (hex) 0x00 . SR. It is allowed only to write “0x0001” to this register . The device executes the current command in the Command Code register.writing any another value is prohibited. Also. Suspend feature is optional. . Table 28 — Command Execute Register Byte-Addressing Offset (hex) 0x0C1 . 209-2E Page 50 4.5 Command Execute Register Command execution begins when “0x0001” is written to this register. Once the embedded operation has suspended (or completed).JEDEC Standard No. Writing to this register is effective only while the device is busy performing an erase or program operation .1.6=0. Otherwise.1.2=1 indicates program suspend was successful. Table 29 — Suspend Register Byte-Addressing Offset (hex) 0x0C9 . Before writing “0x0001” to the Command Execute register. The Suspend register returns “0x0000” in all other cases.6 Suspend Register When “0x0001” is written to this register. system software should test all Status Register flags to be certain. The Suspend register returns “0x0001” from the time a Suspend command is written until the device is ready (DRB = “1”). if the suspend request was not successful (SR. If LPDDR2-NVM does not support suspend feature. Suspend Register can be set only to ‘0x0000’.0x00 The Status Register shall be read to check if the suspend request was successful: SR. successful completion of any on-going program or erase operation will clear this register.writing any other value can result in undefined operation.1.2=0). It is allowed to write this register only when the device is ready (DRB = “1”). and may result in undefined operation.writes during other times are ignored. It is allowed only to write “0x0001” to this register . an on-going erase or program operation is suspended. and when read Suspend Register shall output the value ‘0x0000’. the user can change the contents of the Command Code register (and any related parameters) any number of times.0x0C8 # of bytes (decimal) 2 Type R/W Suspend Register Item Default Value (hex) 0x00 . the ongoing program or erase operation may have completed successfully before the suspend could take effect.1. SR. The Suspend Register resets to its default value after suspending the program or erase operation.0x00 4. the Resume command must be issued in order to continue the program or erase operation.

and Block Lock Status (SR. Refer to section “Abort” on page 78 for additional details. Writing to this register is effective only while the device is busy performing an embedded operation . Table 30 — Abort Register Byte-Addressing Offset (hex) 0x0CB .writes during other times are ignored. If LPDDR2-NVM does not support abort feature.0x00 The Abort register returns “0x0001” from the time a Abort command is written until the device is ready (DRB = “1”). an on-going embedded operation is aborted. Only the value ‘0’ shall be written to this bits.0x80 In particular.6). SR.5. their value will not change. .7 = ’1’ indicates the device is Ready.4). SR. the Abort register is reset by the device and returns “0x0000” when read.6. which will be ignored.5). 4. If these bits are written with a ‘0’. one or more error flags will be set in SR (SR. SR. SR. Voltage Supply Error Status (SR.0x0CA # of bytes (decimal) 2 Type R/W Abort Register Item Default Value (hex) 0x00 . 8. Erase Suspended (SR.1. and SR.7 = ’0’ indicates the device is Busy. SR. 209-2E Page 51 4. and status of program.JEDEC Standard No.3).8 Status Register The Status Register (SR) indicates the state (Ready or Busy) of the device. Program Status (SR.7). It is allowed only to write “0x0001” to this register . Abort feature is optional.0x0CC # of bytes (decimal) 2 Type R/W Register Item Status Register Default Value (hex) 0x00 .7 indicates the state of the device: SR.1. Note that the embedded operation may have completed successfully before the abort could take effect. These bits are cumulative and can only be cleared by writing a ‘1’ to the Status Register bit to be cleared (W12C is an acronym for “write one to clear”). Once Activated. erase. The following Status Register bits are related to the current state of any in process embedded operation: Device Busy (SR. Status Register bit SR. a Row Data Buffer (RDB) containing the Status Register shall be automatically updated by the LPDDR2-N device and shall reflect the current state for the Status Register. Erase Status (SR.1. SR.2).4. SR.1. These bits are set by the device. SR. and when read Abort Register shall output the value ‘0x0000’.9 are invalid while SR. The following Status Register bits are related to the results of embedded operations: Control Mode Status Bit (SR. and the other embedded operations. If any embedded operation is aborted and does not complete due to that abort.2. This register resets to its default value by the device after all embedded operations have ceased and the device becomes ready (SR. Object Mode Status Bit (SR.7 = “1”). Once the embedded operation has aborted (or completed).9).1.writing any other value can result in undefined operation.3.1).4 and/or SR.7 Abort Register When “0x0001” is written to this register. and Program Suspended (SR. The Abort register returns “0x0000” in all other cases.8). These bits are set and cleared by the device. Table 31 — Status Register Byte-Addressing Offset (hex) 0x0CD .7 = ‘0’ (DRB = ‘0’).5). Abort Register can be set only to ‘0x0000’.

JEDEC Standard No.1. If the block is locked. 0 = Erase operation successful 1 = Erase Error PSB SR. 0 = Unlocked 1 = Aborted Write attempt on a locked block SR. Description CMSB SR.9 are invalid while DRB = ‘0’. After receiving a Suspend command.5 and SR.4) is set to ‘1’ if a program operation is aborted by writing “0x0001” to the Abort Register. SR.15 : SR. A Command Sequence Error is indicated when SR. After issuing a Suspend command. ESSB remains set until the device receives a Resume command.2 Program Suspend Status Bit R Only embedded controller halts execution and sets to ‘1’ DSB and PSSB.2. the embedded controller sets to ‘1’ BLSB and aborts the operation.OMSB] = 11 --> Programming Error: programming attempt using illegal command PSB will also be set along with [CMSB.OMSB] = 01 --> Programming Error: programming attempt to an Object Mode Programming Region OMSB SR. DRB SR. or other embedded operation completion in the device. Refer to Vendor Datasheets for a complete description of the NVM Status Register . 0 = Operation in progress/completed 1 = Operation suspended ESB SR.7 are set. SR. operation aborted PSSB indicates whether the device is in Program Suspend.OMSB] indicates additional error conditions for LPDDR2-NVM devices which support programming operations based on Programming Region.2) is reserved if a device does not support program suspend. They are reserved in case programming region modes are not supported.6. NOTE 3 ESSB (SR. SR.5 Erase Status Bit W12C ESB is set to ‘1’ if an attempted Erase failed.5 and SR.3.0 (Reserved) R Only Reserved for future use. NOTE 1 The “W12C” Status Register bits type are set by the device and can be cleared by writing ‘1’ to them (W12C is an acronym for “write one to clear”) NOTE 2 The “R only” Status Register bits type can be written only with the value ‘0’ when clearing the status bits. SR.9) and OMSB (SR.6) and ESB (SR. and shall be written with ‘0’. NOTE 9 LPDDR2-N devices may implement Vendor Specific features.1 Block Lock Status Bit W12C BLSB indicates whether Program or Erase was attempted on a locked block.4. SR.8) are used to indicate error conditions for LPDDR2-NVM devices which support programming region modes. 0 = VACC valid voltage level 1 = VACC invalid voltage level. which remains set until a Resume command is received. 8. 0 = Program operation successful 1 = Program Error VSESB SR.1. 209-2E Page 52 4. 0 = Operation in progress/completed 1 = Operation suspended BLSB SR. [CMSB. the PSSB SR. SR. NOTE 8 All Reserved bits are driven to ‘0’ by the device.1. NOTE 5 ESB (SR.5) is set to ‘1’ if an erase operation is aborted by writing “0x0001” to the Abort Register. and SR.OMSB] = 10 --> Programming Error: programming attempt to an invalid Programming Region Element. ESSB indicates whether the device is in Erase Suspend.3 Voltage Supply Error Status Bit W12C VSESB indicates whether the VACC level is valid voltage.8 Status Register (cont’d) Table 32 — Status Register details Bit SR.7 Device Ready Bit R Only DRB indicates Erase. NOTE 6 PSB (SR. SR.10 Name (Reserved) Type R Only Reserved for future use.4 Program Status Bit W12C PSB is set to ‘1’ if an attempted program failed.5) are reserved if a device does not require Erase features NOTE 4 PSSB (SR.6 Erase Suspend Status Bit R Only ded controller halts and sets to ‘1’ DRB and ESSB.7 are set.SR.OMSB] = 00 -->Programming successful [CMSB.9 Control Mode Status Bit W12C [CMSB.OMSB] for the above error conditions. Program. NOTE 7 CMSB (SR. A Command Sequence Error is indicated when SR. the embed- ESSB SR. [CMSB.8 Object Mode Status Bit W12C [CMSB.5.4.4. 0 = Embedded controller is Busy 1 = Embedded controller is Ready bit SR.

JEDEC Standard No. 2-byte. examples for 1-byte. In particular. 209-2E Page 53 4. x16 and x32 LPDDR2-NVM.2 Data Byte Lane Assignment for Overlay Window Register Registers included in the Overlay Window might have various size: 1-byte.1.9 Program-Buffer The Program-Buffer is used during Buffered Program operation to input the data to be written in memory array. Table 34 — Overlay Window Register Byte Lane Assignment Byte-Addressing Offset (hex) # of bytes (decimal ) 1 1 1 1 Register C1 C0 OneByte_Reg_A[7:0] OneByte_Reg_B[7:0] OneByte_Reg_C[7:0] OneByte_Reg_D[7:0] 00 01 10 11 x8 DQ DQ[7:0] 00 0x001 0x002 0x003 DQ[7:0] DQ[7:0] 01 DQ[7:0] DQ[15:8] DQ[31:24] DQ[15:8] 00 DQ[7:0] DQ[23:16] DQ[15:8] C1 C0 Data Bus Width x16 DQ DQ[7:0] C1 C0 x32 DQ DQ[7:0] 0x000 TwoBytes_Reg_A[7:0] 0x001 – 0x000 2 TwoBytes_Reg_A[15:8] 2 0x003 – 0x002 TwoBytes_Reg_B[15:8] TwoBytes_Reg_B[7:0] 00 01 10 11 DQ[7:0] 00 DQ[7:0] DQ[7:0] 01 DQ[7:0] DQ[7:0] DQ[15:8] 00 DQ[7:0] DQ[15:8] DQ[7:0] DQ[15:8] DQ[23:16] DQ[31:24] FourBytes_Reg_A[7:0] FourBytes_Reg_A[15:8] 0x003 – 0x000 4 FourBytes_Reg_A[23:16] FourBytes_Reg_A[31:24] 00 01 10 11 DQ[7:0] 00 DQ[7:0] DQ[7:0] 01 DQ[7:0] DQ[7:0] DQ[15:8] 00 DQ[7:0] DQ[15:8] DQ[7:0] DQ[15:8] DQ[23:16] DQ[31:24] . etc. The Program-Buffer shall be filled prior writing “0x0001” to the Command Execute Register. DQ[15:8]. Table 34 describes how each byte of an Overlay Window Register is mapped to data byte lane (DQ[7:0].1. DQ[23:16] and DQ[31:24]) in case of x8. Refer to Vendor Datasheets for information about Program-Buffer offset and Program-Buffer size. 4-byte. 2-byte and 4-byte registers are shown. To properly access the Overlay Window Register it is necessary to ensure the correct assignment of each data bit. Table 33 — Program-Buffer Byte-Addressing Offset (hex) Vendor-Specific # of bytes (decimal) Vendor-Specific Type Register Item Default Value (hex) Vendor-Specific Program-Buffer 4.

Suspend. During the execution of an embedded operation. Based on this standard memory vendors will define their own memory specification. the device will become busy and then ready without executing any operation (NOP). adding all necessary details for the proper use of the device.JEDEC Standard No. It is recommended to refer to the device specification for the complete description. and Abort. VACC shall not change during the period starting from at least 1us prior to the initiation of any embedded operation until that embedded operation is complete. Command Execute. Block Lock. Block Lock-Down. An embedded controller handles all timings and verifies the correct execution of LPDDR2-NVM operations. Some possible exceptions to the standard are mentioned. Buffered Program. NOTE 3 Single Word Overwrite and Buffered Overwrite are optional and are only supported by some NVM technologies and some LPDDR2-NVM devices. NOTE 2 Single Word Program is optional. The scope of this section is to provide a standard for some aspects of LPDDR2-NVM software interface. This section includes the following commands: NOP. If the Command Execute Register is set to ‘0x0001’ when Command Code Register is at the default value (0x0000).3 LPDDR2-NVM Operations LPDDR2-NVM can be produced from a variety of memory array technologies. The commands can be initiated when the embedded controller is not busy (DRB = “1”). The Device Ready Bit (DRB) is read as part of the Status Register. 209-2E Page 54 4. Resume. that might be in common among most of NVM technologies. see Power Down section for detailed description on how to enter and exit Power Down. Block Erase. . Table 35 defines the command code values to be written to the Command Code Register within the Overlay Window (see Overlay Window register map table). Table 35 — Command Codes Operation NOP Code 0x0000 0x0041 Program 0x0042 0x00E9 0x00EA Erase Block Lock Block Unlock Block Lock-Down Resume 0x0020 0x0061 0x0062 0x0063 0x00D0 Command No Operation Single Word Program Single Word Overwrite Buffered Program Buffered Overwrite Block Erase Block Lock Block Unlock Block Lock-Down Resume 3 Note 1 2 3 NOTE 1 The Command Code Register default value is 0x0000 (NOP). the device can be placed in Power Down mode by driving CKE low. Block Unlock. Single Word Program. These details are technology dependant and not easy to predict for emerging or completely new technologies. This section is not intended to describe full details of LPDDR2-NVM operations.

4 Nomenclature Table 36 — Definition of terms Term Block Definition A group of bits that erase with one erase command Main Array A group of blocks used for storing code or data Partition A group of blocks that share common program and erase circuitry . 209-2E Page 55 4.JEDEC Standard No.

.OP1... 209-2E Page 56 4... OP1.JEDEC Standard No.1..OP7 OP0..5 Acronyms Table 37 — Definition of acronyms Term MR MRR MRW Mode Register Mode Register Read Mode Register Write Definition OP0.....7 of a Mode Register CFI DU RFU SR OW OWBA NVM DDR SDR Common Flash Interface Don’t Use Reserved for Future Use Status Register Overlay Window Overlay Window Base Address Non Volatile Memory Double Data Rate Single Data Rate . OP7 represent bit 0..

209-2E Page 57 4. MR22.g. MR22) It represents bit ‘k’ of Mode Register ‘j’ (e.g. OWBA+0x088) Definition . such address bus (e.048. such an address bit (e.576 bytes It represents a logical address bit (e.048. FirstAdd7) It denotes the address value obtained adding ‘offset’ to ‘OWBA’ (e. FirstAdd[31:0]) It denotes the element ‘k’ of a group of signals.g.OPk A[m:n] Ak OWBA+offset Hexadecimal number prefix Binary number prefix 8 bits 2 bytes = 16 bits 1024 bits 1024 bytes 1.g.g. a5) It represents Mode Register number ‘j’ (e.g.OP4) It denotes a group of similarly named signals.576 bits 1.6 Conventions Table 38 — Definition of conventions Term 0x 0b Byte Word Kbit KByte Mbit MByte lower case ‘a’ MRj MRj.JEDEC Standard No.

MR26 and MR25. MR27-MR25 shall be set as follows: MR27[OP7:OP0] = {0.0} OWBA[12:0] value is assumed to be 0x0000.7 Overlay Window Enable and Disable When the Overlay Window is enabled.0. If the Overlay Window is enabled and the device is busy (DRB = ‘0’). refer to device datasheet for complete information. it overlaps a portion of the memory array area.OWBA[31:28]} Set MR26 to OWBA[27:20] Set MR25 to {OWBA[19:13].OWBA[31:28]} MR26[OP7:OP0] = {OWBA[27:20]} MR25[OP7:OP0] = {OWBA[19:13].0.JEDEC Standard No. MR27.OP0 is ‘0’ (OWE). Overlay Window Enable Overlay Window Disable Locate the Overlay Window Set MR27 to {0. Some OW locations may have valid content only with device ready. it may keep the Overlay Window open continuously on a fixed location of the memory map. To enable the Overlay Window the value 0x01 shall be written to MR24.0. Software may open the Overlay Window. The Overlay Window Base Address shall be stored to MR27. In particular. MR26 and MR25 shall be written only if the Overlay Window is disabled. therefore the Overlay Window can be positioned only at a 8-KByte aligned address.0. If the Overlay Window is enabled and the device is busy (DRB = ‘0’).0. if OWBA[31:0] is the desired Overlay Window base address. Alternatively. read access to the Overlay Window is allowed. 209-2E Page 58 4.0} Disable the Overlay Window Set MR24 to 0x02 (OWD=1) End Enable the Overlay Window Set MR24 to 0x01 (OWE=1) End NOTE OWBA is the byte address of the desired Overlay Window Base Address Figure 7 — Overlay Window Enable and Disable . write access to the Overlay Window is not allowed expect for the Suspend and Abort registers.0. OWBA shall be changed only if the MR24. and close it immediately after it has accessed it. To disable the Overlay Window the value 0x02 shall be written to MR24.

otherwise the result of this operation is unpredictable. the addresses in the Command Address Register and Multi-Purpose Register are not used and are “Do Not Care”. • Write any address within the desired stop block to the Multi-Purpose Register. reset is achieved by writing MR63. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. The status of a locked block can be changed to unlocked using the Block Unlock command. Block Unlock and Block LockDown is aborted by writing 0x0001 to the Abort Register. For LPDDR2-N devices that only support locking all blocks.1 Block Lock Command The Block Lock command is used to lock a block. In LPDDR2 memory. while other LPDDR2-N devices may only support locking all blocks. Locked blocks are fully protected from program or erase operations. Users shall refer to the device datasheet for complete information. • Write any address within the desired start block to the Command Address Register. Block Lock operations cannot be suspended. a consecutive range of blocks. • Write 0x0001 to the Command Execute Register. The Command Sequence is: • Write 0x0061 to the Command Code Register. Some NVM technologies might not have the notion of block. .7.JEDEC Standard No. because they do not require and support the erase operation. Any program or erase operations attempted on a locked block will return an error in the Status Register. Block Lock operation is performed by the embedded processor. All blocks are locked after power-up or reset. Some LPDDR2-N devices may support locking single blocks or a range of blocks. or all blocks and prevents program or erase operations from changing the data within this range. 209-2E Page 59 4. NVM vendors may implement additional security features not described in the JEDEC spec. Block Lock operation shall not be interrupted by reset or abort (if supported). Block Lock status does not change if an ongoing operation other than Block Lock.

This step is not required for devices that only support locking all blocks with the Block Lock command. Figure 8 — Block Lock Command Flowchart . 209-2E Page 60 4.1 Block Lock Command (cont’d) Lock a range of contiguous blocks Provide Command Code Write (0x0061) to address (OWBA+0x080) Provide Command Addresses (First and Last) Write FirstBlockAddr[31:0] to address (OWBA+0x088) Write LastBlockAddr[31:0] to address (OWBA+0x090) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue Block Lock command. Refer to vendor datasheets for complete information on the Block Lock command.JEDEC Standard No. NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being locked. This step is not required for devices that only support locking all blocks with the Block Lock command. NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the address written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and the Status Register bits PSB and ESB are set.7. NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being locked. NOTE 7 Some LPDDR2-N devices will lock all blocks with the Block Lock command. This error check is not required for devices that only support locking all blocks with the Block Lock command.

The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. Users shall refer to the device datasheet complete information. • Write 0x0001 to the Command Execute Register. otherwise the result of this operation is unpredictable. Block Lock status does not change if an ongoing operation other than Block Lock. allowing the block to be programmed or erased. Some NVM technologies might not have the notion of block. • Write any address within the desired start block to the Command Address Registers. Block Unlock operations cannot be suspended. The status of a unlocked block can be changed to locked using the Block Lock command. Block Unlock and Block LockDown is aborted by writing 0x0001 to the Abort Register. NVM vendors may implement additional security features not described in the JEDEC spec. 209-2E Page 61 4. For these devices. The Command Sequence is: • Write 0x0062 to the Command Code Register. . Some LPDDR2-N devices may only support unlocking a single block or a range of blocks at any given time. Block Unlock operation shall not be interrupted by reset or abort (if supported). Block Unlock operation is performed by the embedded processor.7. All blocks are locked after power-up or reset. because they do not require and support the erase operation. reset is achieved by writing MR63. • Write any address within the desired stop block to the Multi-Purpose Registers. the blocks not selected by the Block Unlock command will be changed to locked after the completion of the Block Unlock command. In LPDDR2 memory.JEDEC Standard No.2 Block Unlock Command The Block Unlock command is used to unlock a block or a consecutive range of blocks.

NOTE 7 Some LPDDR2-N devices will unlock only one block or a range of blocks selected by the Block Unlock command. NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being unlocked.7. NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. All other blocks will be locked by these devices.JEDEC Standard No. Figure 9 — Block Unlock Flowchart .2 Block Unlock Command (cont’d) Unlock a range of contiguous blocks Provide Command Code Write (0x0062) to address (OWBA+0x080) Provide Command Addresses (First and Last) Write FirstBlockAddr[31:0] to address (OWBA+0x088) Write LastBlockAddr[31:0] to address (OWBA+0x090) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue Block Unlock command. NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being unlocked. Refer to vendor datasheets for complete information on the Block Unlock command. 209-2E Page 62 4. NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the address written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and the Status Register bits PSB and ESB are set.

Block Lock status does not change if an ongoing operation other than Block Lock. otherwise the result of this operation is unpredictable. • Write any address within the desired stop block to the Multi-Purpose Registers. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. 209-2E Page 63 4.JEDEC Standard No. reset is achieved by writing MR63. Block Lock-Down operation shall not be interrupted by reset or abort (if supported). In LPDDR2 memory.3 Block Lock-Down Command The Block Lock-Down command is used to lock-down a block or a consecutive range of blocks. • Write 0x0001 to the Command Execute Register. Block Lock-Down operation is performed by the embedded processor. All blocks are locked after power-up or reset. NVM vendors may implement additional security features not described in the JEDEC document. and Block LockDown is aborted by writing 0x0001 to the Abort Register. Any program or erase operations attempted on a locked-down block will return an error in the Status Register. The status of a locked-down block is reset to the default locked state only after removing and applying again the power supply.7. • Write any address within the desired start block to the Command Address Registers. Locked-Down blocks are fully protected from program or erase operations. Users shall refer to the device datasheet for complete information. Block Lock-Down operations cannot be suspended. because they do not require and support the erase operation. . and prevent program or erase operations from changing the data in it. The Command Sequence is: • Write 0x0063 to the Command Code Register. Some NVM technologies might not have the notion of block. Block Unlock.

209-2E Page 64 4. NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence.JEDEC Standard No.3 Block Lock-Down Command (cont’d) Lock-Down a range of contiguous blocks Provide Command Code Write (0x0063) to address (OWBA+0x080) Provide Command Addresses (First and Last) Write FirstBlockAddr[31:0] to address (OWBA+0x088) Write LastBlockAddr[31:0] to address (OWBA+0x090) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue Block Lock-Down command.7. NOTE 4 FirstBlockAddr[31:0] is any byte address within the first block being locked NOTE 5 LastBlockAddr[31:0] is any byte address within the last block being locked NOTE 6 If the address written at the location OWBA+0x088 (FirstBlockAddr[31:0]) is greater than the address written at the location OWBA+0x090 (LastBlockAddr[31:0]) the block lock status will not change and the Status Register bits PSB and ESB are set. Figure 10 — Block Lock-Down Command Flowchart .

the erase operation will abort. If the Block is locked. Erase operation abort. All previous data in the Block is lost. If a block being erased is locked during an erase suspend.JEDEC Standard No. The erase operation is performed by the embedded controller. Write any address within the desired block to the Command Address Registers. VACC not at appropriate level for Erase operation. or writing 0x0001 to the Abort Register (if supported). Attempting to erase a block during Program Suspend. 209-2E Page 65 4. Attempting to erase a block during Erase Suspend and Program Suspend. Erase operation abort. Write 0x0001 to the Command Execute Register The erase operation can be suspended. Table 39 — Block Erase Error Conditions 7 DRB 1 1 6 ESSB 0 0 5 ESB 1 1 4 PSB 0 0 3 VSESB 0 0 2 PSSB 0 0 1 BLSB 0 1 0 0 0 Description Erase operation failure Erase operation abort. As data integrity cannot be guaranteed when the Block Erase operation is aborted. Attempting to erase a block during Erase Suspend.7. Note that some NVM technologies do not need Erase command. An erase operation was attempted on a locked block.4 Block Erase Command The Block Erase command is used to erase a Block. It sets all the bits within the selected Block to ’1’. Erase operation abort. Erase operation abort. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. The erase is aborted by writing MR63. The Command Sequence is: Write 0x0020 to the Command Code Register. the data in the Block will not be changed and the Device Status Register will output the error. Block address outside the LPDDR2-NVM address space. Erase operation abort. the Block must be erased again. therefore some NVM devices will not support it. 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 . the operation will complete normally when it is resumed.

Figure 11 — Block Erase Flowchart . NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. For more details refer to “Row Data Buffer Incoherency” on page 79. NOTE 4 BlockAddr[31:0] is any byte address within the block being erased NOTE 5 RDB invalidation may be required to avoid risk of incoherency between memory array content and RDB content.4 Block Erase Command (cont’d) Figure 11 shows the Block Erase Flowchart.  Erase one block Provide Command Code Write (0x0020) to address (OWBA+0x080) Provide Command Address Write BlockAddr[31:0] to address (OWBA+0x088) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) Invalidate RDB (5) End NOTE 1 The Overlay Window must be open to issue Block Erase command.JEDEC Standard No.7. 209-2E Page 66 4.

JEDEC Standard No. 209-2E Page 67 4.7.5 Single Word Program Command

The Single Word Program command is used to program a single word (2-byte data) to the memory array. This is a legacy command and it is optional. The program operation is performed by the embedded controller. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. The Command Sequence is: Write 0x0041 (or 0x0040) to the Command Code Register, Write desired location address to the Command Address Register, Write desired program data to the Command Data Register (Command Data[15:0] only), Write 0x0001 to the Command Execute Register. Programming can be performed in one block at a time. The Status Register DRB bit, indicates the progress of the Program operation. It should be read to check whether the operation has completed or not. After completion of the Program operation (DRB= 1), one of the Status Register error bits (4,3 and 1) going High means that an error was detected: either a failure occurred during programming, VACC is outside the allowed voltage range or an attempt to program a locked Block was made. See Section Device Status Register for detailed information. The program operation can be suspended. The program is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity cannot be guaranteed when the program operation is aborted, the data must be reprogrammed. Some NVM technologies support the Single Word Program command only under particular conditions. For example, for LPDDR2-NVM device that has the notion of program region, Single Word Program Command is supported only by program regions configured in the Control Program mode, and with Command Address value belonging to a particular portion of the program region. If a Single Word Program command is issued to a Program Region configured in the Object Program mode, the Program operation is aborted and PSB and OMSB Status Register bits are set. For details about program region and program method see the application note.

Table 40 — Single Word Program Error Conditions
7
DRB

6 (1)
ESSB

5
ESB

4
PSB

3
VSESB

2
PSSB

1
BLSB

0
-

Description Single Word Program operation failure. Single Word Program operation abort. An program operation was attempted on a locked block. Single Word Program operation abort. VACC not at appropriate level for Program operation. Single Word Program operation abort. Program address outside the LPDDR2-NVM address space Single Word Program operation abort. Attempting to program during Program Suspend.

1 1 1 1 1

0 0 0 0 0

0 0 0 1 1

1 1 1 1 1

0 0 1 0 0

0 0 0 0 1

0 1 0 0 0

0 0 0 0 0

NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.

JEDEC Standard No. 209-2E Page 68 4.7.5 Single Word Program Command (cont’d)

Program using Single Word Program

Provide Command Code Write (0x0041) to address (OWBA+0x080)

Provide Command Addresses Write ProgrAddr[31:0] to address (OWBA+0x088)

Provide Command Data Write ProgrData[15:0] to address (OWBA+0x084)

Execute (Begin) Write (0x0001) to address (OWBA+0x0C0)

Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready)

Invalidate RDB (6)

End

NOTE 1 The Overlay Window must be open to issue Single Word Program command. NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. NOTE 4 ProgrAddr[31:0] is the target byte address of the programming operation, and ProgrAddr[0] shall be ‘0’. NOTE 5 ProgrData[15:0] is the desired 2-byte data to be programmed. NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79. Figure 12 — Single Word Program Flowchart

JEDEC Standard No. 209-2E Page 69 4.7.6 Single Word Overwrite Command

Single Word Overwrite is supported only by some NVM technologies and some LPDDR2-NVM devices. The Single Word Overwrite command is used to write a single word (2-byte data) to the memory array. The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’. With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’ are not. The overwrite operation is performed by the embedded controller. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. The Command Sequence is: Write 0x0042 to the Command Code Register, Write desired location address to the Command Address Register, Write desired program data to the Command Data Register (Command Data[15:0] only), Write 0x0001 to the Command Execute Register. Overwriting can be performed in one block at a time. The Status Register DRB bit, indicates the progress of the Overwrite operation. It should be read to check whether the operation has completed or not. After completion of the overwrite operation (DRB= 1), one of the Status Register error bits (4, 3 and 1) going High means that an error was detected: either a failure occurred during overwriting, VACC is outside the allowed voltage range or an attempt to overwrite a locked Block was made. See “Status Register” on page 51 for detailed information. The overwrite operation may be suspended. The overwrite is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity cannot be guaranteed when the overwrite operation is aborted, the data must be rewritten.
7
DRB

6 (1)
ESSB

Table 41 — Single Word Overwrite Error Conditions
5
ESB

4
PSB

3
VSESB

2
PSSB

1
BLSB

0
-

Description Single Word Overwrite operation failure. Single Word Overwrite operation abort. An overwrite operation was attempted on a locked block. Single Word Overwrite operation abort. Program voltage violation. Single Word Overwrite operation abort. Overwrite address outside the LPDDR2-NVM address space Single Word Overwrite operation abort. Attempting to program during Overwrite Suspend or Program Suspend.

1 1 1 1

0 0 0 0

0 0 0 1

1 1 1 1

0 0 1 0

0 0 0 0

0 1 0 0

0 0 0 0

1

0

1

1

0

1

0

0

NOTE 1

ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.

JEDEC Standard No. 209-2E Page 70 4.7.6 Single Word Overwrite Command (cont’d)

Overwrite using Single Word Overwrite

Provide Command Code Write (0x0042) to address (OWBA+0x080)

Provide Command Addresses Write OverwAddr[31:0] to address (OWBA+0x088)

Provide Command Data Write OverwData[15:0] to address (OWBA+0x084)

Execute (Begin) Write (0x0001) to address (OWBA+0x0C0)

Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready)

Invalidate RDB (6)

End

NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5

The Overlay Window must be open to issue Single Word Overwrite command. OWBA is the byte address of the Overlay Window Base Address The device must be Ready (DRB==’1’) before starting the command sequence. OverwAddr[31:0] is the target byte address of the overwriting operation, and OverwAddr[0] shall be ‘0’. OverwData[15:0] is the desired 2-byte data to be overwritten.

NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79 . Figure 13 — Single Word Overwrite Flowchart

JEDEC Standard No. 209-2E Page 71 4.7.7 Buffered Program Command

The Buffered Program Command makes use of the device’s Program Buffer to speed up programming. The Buffered Program command dramatically reduces in-system programming time compared to other non-buffered program commands. If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program Buffer and programmed into the specified N-Byte aligned location in the main array. The region is determined by bit [31: K] of the Command Address Register value, where N=2k.  The first word data of the Program Buffer to be programmed depends on bit [K-1:0] of Command Address value. The programming operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data Count value is in units of bytes and written in the Multi-Purpose Registers. If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (Nbyte), the programming operation ends without programming the memory array and the Status Register will show an error (0xB0). The programming operation doesn't wrap within the program buffer and doesn't cross into the next programming region. The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence. The Command Sequence is: Write the starting address to the Command Address registers, Write the Data Count value (number of bytes to be programmed) to the Multi-Purpose Registers, Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space, Write 0x00E9 to the Command Code Register, Write 0x0001 to the Command Execute Register. If the Block being programmed is locked an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The Buffered Program operation can be suspended. The program is aborted by writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity cannot be guaranteed when the program operation is aborted, the memory array content must be considered invalid. Table 42 — Buffered Program Error Conditions
5
ESB

7
DRB

6

(1)

4
PSB

3
VSESB

2
PSSB

1
BLSB

0
-

Description Buffered Program operation failure. Buffered Program operation abort. An program operation was attempted on a locked block. Buffered Program operation abort. Invalid VACC voltage. Buffered Program operation abort. Program address outside the LPDDR2-NVM address space Buffered Program operation abort. Attempting to program during Program Suspend. Buffered Program operation abort. Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (it is greater than N byte).

ESSB

1 1 1 1 1

0 0 0 0 0

0 0 0 1 1

1 1 1 1 1

0 0 1 0 0

0 0 0 0 1

0 1 0 0 0

0 0 0 0 0

1

0

1

1

0

0

0

0

NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.

JEDEC Standard No. 209-2E Page 72 4.7.7 Buffered Program Command (cont’d)

Figure 14 shows the Buffered Program Flowchart.

Program using Program Buffer

Provide Command Address Write ProgrAddr[31:0] to address (OWBA+0x088)

Provide Data Count Write DataCount[31:0] to address (OWBA+0x090)

Fill the Program Buffer Write program data to the program buffer

Provide Command Code Write (0x00E9) to address (OWBA+0x080)

Execute (Begin) Write (0x0001) to address (OWBA+0x0C0)

Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready)

Invalidate RDB (6)

End

NOTE 1 The Overlay Window must be open to issue Buffered Program command. NOTE 2 OWBA is the byte address of the Overlay Window Base Address NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. NOTE 4 DataCount[31:0] is amount of byte being programmed NOTE 5 ProgrAddr[31:0] is the target byte address of the programming operation. NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and RDB content. For more details refer to “Row Data Buffer Incoherency” on page 79.

Figure 14 — Buffered Program Flowchart

JEDEC Standard No. 209-2E Page 73 4.7.8 Buffered Overwrite Command

This is a command supported only by some NVM technologies and LPDDR2-NVM devices. The Buffered Overwrite Command makes use of the device’s Program Buffer to speed up overwriting data to the memory array. The Buffered Overwrite command reduces in-system overwriting time compared to other nonbuffered overwrite commands. The overwrite command allows to change the status of each bit from ‘1’ to ‘0’ or from ‘0’ to ‘1’. With the overwrite command the data is written to the memory array allowing to change each bit to ‘0’ or to ‘1’. With the program command only the data bits equal to ‘0’ are written to the memory array, while the data bits equal to ‘1’ are not. If N is the size of the Program Buffer within the Overlay Window, up to N-Bytes can be loaded into the Program Buffer and overwritten into the specified N-Byte aligned location in the main array. The region is determined by bit [31: K] of the Command Address Register value, where N=2k. The first word data of the Program Buffer to be overwritten depends on bit [K-1:0] of Command Address value. The overwriting operation proceeds for a contiguous number of bytes equal to the Data Count value. The Data Count value is in units of bytes and written in the Multi-Purpose Registers. If the Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (Nbyte), the overwriting operation ends without overwriting the memory array and the Status Register will show an error (0xB0). The overwriting operation doesn't wrap within the program buffer and doesn't cross into the next programming region. The Overlay Window must be open and the device must be ready (DRB= 1) before starting the command sequence. The Command Sequence is: Write the starting address to the Command Address Registers, Write the Data Count value (number of bytes to be overwritten) to the Multi-Purpose Registers, Write data into the Program Buffer. The Program Buffer fits within the N-byte aligned array space, Write 0x00EA to the Command Code Register, Write 0x0001 to the Command Execute Register. If the Block being overwritten is locked an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The Buffered Overwrite operation can be suspended. The overwrite is aborted writing MR63, or writing 0x0001 to the Abort Register (if supported). As data integrity cannot be guaranteed when the overwrite operation is aborted, the memory array content must be considered invalid.
7
DRB

6 (1)
ESSB

Table 43 — Buffered Overwrite Error Conditions
5
ESB

4
PSB

3
VSESB

2
PSSB

1
BLSB

0
-

Description Buffered Overwrite operation failure. Buffered Overwrite operation abort. An overwrite operation was attempted on a locked block. Buffered Overwrite operation abort. Invalid VACC voltage. Buffered Overwrite operation abort. Overwrite address outside the LPDDR2-NVM address space Buffered Overwrite operation abort. Attempting to overwrite during Overwrite Suspend or Program Suspend. Buffered Overwrite operation abort. Command Address [K-1:0] value plus the Data Count Register value exceeds the program buffer boundary (it is greater than N byte).

1 1 1 1

0 0 0 0

0 0 0 1

1 1 1 1

0 0 1 0

0 0 0 0

0 1 0 0

0 0 0 0

1

0

1

1

0

1

0

0

1

0

1

1

0

0

0

0

NOTE 1 ESSB Status Register bit is ‘1’ in case of command issued during Erase Suspend.

Overwrite using Program Buffer Provide Command Address Write OverwAddr[31:0] to address (OWBA+0x088) Provide Data Count Write DataCount[31:0] to address (OWBA+0x090) Fill the Program Buffer Write overwrite data to the program buffer Provide Command Code Write (0x00EA) to address (OWBA+0x080) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) Invalidate RDB (6) End NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5 The Overlay Window must be open to issue Buffered Overwrite command. OWBA is the byte address of the Overlay Window Base Address The device must be Ready (DRB==’1’) before starting the command sequence. For more details refer to “Row Data Buffer Incoherency” on page 79 .JEDEC Standard No. NOTE 6 RDB invalidation may be required to avoid risk of incoherency between memory array content and RDB content. Figure 15 — Buffered Overwrite Flowchart .7. 209-2E Page 74 4.8 Buffered Overwrite Command (cont’d) Figure 15 shows the Buffered Overwrite Flowchart. DataCount[31:0] is amount of byte being overwritten OverwAddr[31:0] is the target byte address of the overwriting operation.

or writing 0x0001 to the Abort Register (if supported).7. suspend the program operation. For example: suspend an erase operation. refer to the device datasheet. see Power Down section for detailed description on how to enter and exit Power Down.JEDEC Standard No. therefore some NVM devices will not support it.9 Program/Erase Suspend The Program/Erase Suspend request pauses a program or block erase operation. Program/Erase is aborted by writing MR63. The Program/Erase Suspend request is issued by writing ‘0x0001’ to ‘1’ the Suspend Register. start a program operation. The Program/Erase Resume command is required to restart the suspended operation. . the device can be placed in Power Down mode by driving CKE low. The following operations shall be allowed during Program/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended block or program-suspended locations is not valid)  Additionally. 209-2E Page 75 4. During an erase suspend the Block being erased can be protected by issuing the Block Lock. the erase operation cannot be resumed until the program operation has completed. If a Program command is issued during a Block Erase Suspend. then read the array. It is possible to accumulate multiple suspend operations. During a program suspend it is not allowed to write the program buffer. Note that some NVM technologies do not need Erase command. When the Program/Erase Resume command is issued the operation will complete. bits DRB. if the suspended operation was a Block Erase then the following commands are also accepted: – Single Word Program (except in erase-suspended Block) – Buffered Program (except in erase suspended Block) – Block Lock – Block Unlock For the complete list of supported commands during Program or Erase Suspend refer to the device datasheet. For the complete list of embedded operations that can be suspended. Commands not supported during Program or Erase Suspend shall be ignored. During a Program/Erase Suspend. Program or erase operations can be suspended. ESSB and/or PSSB of the Status Register are set to ‘1’. Once the Embedded Controller has paused.

7.JEDEC Standard No.0=1 Write (0x0001) to address (OWBA+0x0C8) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue the Program/Erase Suspend command. 209-2E Page 76 4. Suspend Request Suspension Set SUS.9 Program/Erase Suspend (cont’d) Figure 16 shows the Program/Erase Suspend Request flowchart. Figure 16 — Program/Erase Suspend Request Flowchart . NOTE 2 OWBA is the byte address of the Overlay Window Base Address.

10 Program/Erase Resume Command The Program/Erase Resume command is used to restart a previously suspended program or erase operation.JEDEC Standard No. therefore some NVM devices will not support it. It is allowed to issue the Program/Erase resume command only when the embedded controller is in the Ready state and if a program or erase operations has been suspended.   The command doesn’t require to load any value to the Command Address Register within the Overlay Window. then the erase cannot be resumed until the program operation has completed. If an Erase and a Program operation are suspended. Note that some NVM technologies do not need Erase command. Figure 17 — Program/Erase Resume Command Flowchart . The Command Sequence is:  Write 0x00D0 to the Command Code Register Write 0x0001 to the Command Execute Register. 209-2E Page 77 4.7. If a Program command is issued during a Block Erase Suspend. A Resume command when no operation is suspended will be ignored. NOTE 2 OWBA is the byte address of the Overlay Window Base Address. NOTE 3 The device must be Ready (DRB==’1’) before starting the command sequence. the Resume command will Resume the Program command. The Overlay Window must be open and the device must be ready (DRB = 1) before starting the command sequence. Resume Provide Command Code Write (0x00D0) to address (OWBA+0x080) Execute (Begin) Write (0x0001) to address (OWBA+0x0C0) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue the Resume command. refer to the device datasheet. For the complete list of embedded operations that can be resumed. Figure 17 shows the Program/Erase Resume command flowchart.

the device will remain in the same status. Abort request issued during erase and program suspend. Abort request issued while erase suspend. Abort Register may be written only with 0x0000. Table 44 — Abort Error Conditions 7 DRB 6 ESSB 5 ESB 4 PSB 3 VSESB 2 PSSB 1 BLSB 0 - Description Abort request issued during program operation. the program will be aborted but the device will remain in erase suspend.JEDEC Standard No. and when read it shall output the value 0x0000. Abort request issued during erase operation. The Abort request is issued by writing ‘0x0001’ to the Abort Register. Abort request issued while program suspend. In particular. Once the embedded controller has completed the abort request. 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 Figure 18 shows the Abort Request flowchart. Abort request issued during program operation and erase suspend. The Abort request is ignored if the Abort Register is written when the device is ready (DRB = “1”).7. Figure 18 — Abort Request Flowchart .  Therefore. if the device is in program or/and erase suspend. Abort feature is optional. Abort Abort Request Write (0x0001) to address (OWBA+0x0CA) Poll Device Ready bit Repeat: 1) Read (OWBA+0x0CC) (Status Register) 2) Test only bit 7 (DRB) Until DRB == 1 (Ready) End NOTE 1 The Overlay Window must be open to issue the Abort command. 209-2E Page 78 4. the operation will fail and one or more Status Register bits will be set. if the device is executing a program operation (DRB = “0”) while it is in erase suspend. If LPDDR2-NVM does not support abort feature. bit DRB of the Status Register is set to ‘1’ and the Abort Register is set to ‘0x0000’ by the LPDDR2-NVM device. If any embedded operation is aborted and does not complete due to an abort request.11 Abort The Abort request ends all embedded operations. NOTE 2 OWBA is the byte address of the Overlay Window Base Address.

generating an incoherency between Row Data Buffer and memory array. and manage it in hardware or/and software. the host may program.7. .12 Row Data Buffer Incoherency The ACTIVATE command copies a row content from the memory array to the Row Data Buffer selected by the row. While a row is open in one Row Data Buffer. LPDDR2-NVM device will not update  the Row Data Buffer with the new row content. 209-2E Page 79 4. The host shall be aware of this incoherency risk.JEDEC Standard No.  BA signals. overwrite or erase operation is completed (DRB = ‘1’). overwrite or erase that particular   Once the program.

NOTE 2 Programming may occur during erase suspended. so the device can have one block in erase suspend mode. NOTE 3 LPDDR2-NVM will output invalid data if the read operation occurs in the memory area that is being programmed. For the complete list of dual operations allowed. one programming. NOTE 5 Not allowed in the block that is being erased.8 Dual operations and multiple partition architecture In some LPDDR2-NVM devices.JEDEC Standard No. Table 45 — Simultaneous operations allowed in the same partition Operations allowed in the same partition Status of partition Read (1) Yes (2) Buffered Program Yes No No No Yes (5) Block Erase Yes No No No No Idle Programming Erasing Program suspended Erase suspended No No Yes (3) Yes (4) NOTE 1 Depending on the Overlay Window status and the target read address. NOTE 4 LPDDR2-NVM will output invalid data if the read operation occurs in the block that is being erased. refer to the device datasheet. data may come from the memory array or from the overlay window. Table 46 — Simultaneous operations allowed in other partitions Operations allowed in another partition Status of partition Read (1) Yes (2) Buffered Program Yes No No No Yes Block Erase Yes No No No No Idle Programming Erasing Program suspended Erase suspended Yes Yes Yes Yes NOTE 1 Depending on the Overlay Window status and the target read address. the program or erase operation can be suspended. . The dual operations feature means that while programming or erasing in one partition. read operations are possible in another partition with zero latency (only one partition at a time is allowed to be in program or erase mode). if the suspended operation is erase then a program command can be issued to another block. Refer to vendor datasheets to determine support for multiple partition architecture. The dual operations feature simplifies the software management of the device by allowing code to be executed from one partition while another partition is being programmed or erased. Also. NOTE 2 Programming may occur during erase suspended. and other partitions available for read operations. 209-2E Page 80 4. data may come from the memory array or from the overlay window. which is programming or erasing. LPDDR2-NVM devices that support multiple partition architecture provide greater flexibility for software developers to split the code and data spaces within the memory array. the memory array may be divided into two or more partitions (multiple partition architecture). If a read operation is required in a partition.

which is greater than tRPpb.1. in the case of REFpb) in a rolling tFAW window. As an example of the rolling window.JEDEC Standard No. • 8-bank device Precharge All Allowance : tRP for a Precharge All command for an 8-bank device shall equal tRPab. Certain restrictions on operation of the 8-bank devices must be observed.1 LPDDR2 Command Definitions and Timing Diagrams Activate Command LPDDR2-SX: Activate Command The SDRAM Activate command is issued by holding CS_n LOW. 209-2E Page 81 5 5. There are two rules.BA2 are used to select the desired bank. The bank active and precharge times are defined as tRAS and tRP. The Activate command must be applied before any Read or Write operation can be executed. REFpb also counts as bank-activation for the purposes of tFAW. while a Single Bank Precharge command uses tRPpb timing. In this figure. The minimum time interval between successive Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). if RU{ (tFAW / tCK) } is 10 clocks. and rounding up to next integer value. Once a bank has been activated it must be precharged before another Activate command can be applied to the same bank. The bank addresses BA0 . One for restricting the number of sequential Activate commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows: • 8-bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated (or refreshed. tRRD = 2 NOTE 1 A Precharge-All command uses tRPab timing. and an activate command is issued in clock N. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate command is sent. no more than three further activate commands may be issued at or between clock N+1 and N+9. The minimum time interval between Activate commands to different banks is tRRD.RAS delay time = tRRD [Cmd] Activate Nop Activate Bank Active = tRAS Read Precharge Nop Nop Activate Row Cycle time = tRC Figure 19 — LPDDR2-SX: Activate command cycle: tRCD = 3.1 5. SDRAM CK_t / CK_c T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CA0-9 Bank A Row Addr Row Addr Bank B Row Addr Row Addr RAS-CAS delay = tRCD Bank A Col Addr Bank A Col Addr Bank A Row Addr Row Addr Read Begins Bank Precharge time = tRP RAS . and CA1 HIGH at the rising edge of the clock. respectively. Converting to clocks is done by dividing tFAW[ns] by tCK[ns]. CA0 LOW. The row address R0 through R14 is used to determine which row to activate in the selected bank. tRP = 3. . tRP is used to denote either an All-bank Precharge or a Single Bank Precharge.

The activate and preactive times are defined as tRAS and tRP.JEDEC Standard No. 209-2E Page 82 5. The Row Buffer (RB) addresses BA0 . RDB} Selected {RAB. respectively.2 LPDDR2-N: Activate Command The NVM Activate command is issued by holding CS_n LOW. The LPDDR2 NVM can accept a read or write command at time tRCD after the activate command is sent. RDB} (8-RB devices) (4-RB devices) RB 0 RB 1 RB 2 RB 3 RB 0 RB 1 RB 2 RB 3 RB 0 RB 1 RB 2 RB 3 RB 4 RB 5 RB 6 RB 7 .BA2 are used to select the desired {RAB. It is recommended to open any single row in only one Row Buffer. If a memory controller issues an Activate command that causes a single row to be open in more than one RDB.1 SDRAM CK_t/CK_c CA0-9 [Cmd] LPDDR2-SX: Activate Command (cont’d) Tn Tn+1 Tm Tm+1 Tx Tx+1 Ty Ty+1 Ty+2 Tz Tz+1 Tz+2 Bank A Bank A Bank B Bank B Bank C Bank C Bank D Bank D Bank E Bank E ACT Nop ACT Nop ACT Nop ACT Nop Nop Nop ACT Nop tRRD tRRD tRRD tFAW Figure 20 — LPDDR2-SX: tFAW timing NOTE 1: For 8-bank devices only. 5. or after WL+BL/2+1+RU(tWRA/tCK) clock cycles after a previous Write command. The Activate command must be applied before any Read or Write operation can be executed.1.1. No more than 4 banks may be activated in a rolling tFAW window. Table 47 — Row Address Buffer selection for Preactive by BA inputs BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected {RAB. The minimum time interval between Activate commands to different Row Buffer pairs is tRRD. RDB} pair. Row address a5 through a19 is used in conjunction with the selected RAB contents to determine which row to load into the destination RDB. the controller may use any value of BA0 . Devices may have four or eight Row Buffer pairs. Row Buffers do not correspond directly to any portion of the array. CA0 LOW and CA1 HIGH at the rising edge of the clock.BA2 for any array location. then only the last Row Data Buffer activated for that given row is valid. The minimum time interval between successive Activate commands to the same Row Buffer pair is determined by the RAS cycle time of the device (tRC). The Activate command may be issued only after BL/2 clock cycles after a previous Read command.

2 NVM CK_t/CK_c RAS-CAS delay = tRCD LPDDR2-N: Activate Command (cont’d) T0 T1 T2 T3 Tx Tx+1 Tx+2 Tx+3 Tx+4 CA0-9 [Cmd] RAB A Row Addr Row Addr RB A Row Addr Row Addr RB B Row Addr Row Addr RDB A Col Addr Col Addr RB A Row Addr Row Addr Preactive Nop Activate Nop Activate Read Nop Activate Nop RAS .2. 209-2E Page 83 5.2 5.JEDEC Standard No. Figure 22 — LPDDR2: Command Input Setup and Hold Timing .1 LPDDR2 Command Input Signal Timing Definition LPDDR2 Command Input Setup and Hold Timing T0 CK_t/CK_c tIS CS_n VIL(AC) T1 T2 T3 tIH VIL(DC) tIS VIH(AC) tIH VIH(DC) tIS CA0-9 [Cmd] CA Rise CA Fall CA Rise tIH CA Fall tIS CA Rise CA Fall tIH CA Rise CA Fall Nop Command Nop Command HIGH or LOW (but a defined logic level) NOTE Setup and hold conditions also apply to the CKE pin.RAS delay time = tRRD Bank Preactive time = tRP Row Cycle time = tRC Read to Activate = BL/2 Figure 21 — LPDDR2-N: Activate command cycle: tRP = 2. See section related to power down for timing diagrams related to the CKE pin. BL = 4 5.1.

JEDEC Standard No. CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width). CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width). Figure 23 — LPDDR2: Command Input Setup and Hold Timing .2 LPDDR2 CKE Input Setup and Hold Timing T0 CK_t/CK_c tIHCKE CKE VIHCKE VILCKE T1 Tx Tx+1 tIHCKE VIHCKE VILCKE tISCKE HIGH or LOW (but a defined logic level) tISCKE NOTE 1: After CKE is registered LOW. NOTE 2: After CKE is registered HIGH. 209-2E Page 84 5.2.

CA0 HIGH. a read or write cycle can be executed. .JEDEC Standard No. For LPDDR2-N devices. Reads may interrupt Reads and Writes may interrupt Writes. 8 for 4 bit burst. In case of BL = 8 and BL = 16 settings.3. 5.1 Read and Write access modes LPDDR2-SX: Read and Write access modes After a bank has been activated. The boundary of the burst cycle is restricted to specific segments of the Row Data Buffer (RDB) size. 4 for 8 bit burst.3 5. In case of BL = 8 and BL = 16 settings. a read or write cycle can be executed. CA2 must also be defined at this time to determine whether the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW).2 LPDDR2-N: Read and Write access modes After an RB has been activated. CA0 HIGH. 4. The LPDDR2 SDRAM provides a fast column access operation. and 2 for 16 bit burst respectively. This is accomplished by setting CS_n LOW. Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met. and CA1 LOW at the rising edge of the clock. provided that tCCD is met. a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. This is accomplished by setting CS_n LOW. if the size of the RDB is 64 Bytes and the device has a 16 bit data bus interface. 4 or 2 groups beginning with the column address supplied to the device during the Read or Write Command (C1-C4). and CA1 LOW at the rising edge of the clock. The minimum CAS to CAS delay is defined by tCCD. CA2 must also be defined at this time to determine whether the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW). For LPDDR2-S2 devices. the page size of 512 bits is divided into 8. For example. a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. A single Read or Write Command will initiate a burst read or write operation on successive clock cycles. Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met. The minimum CAS to CAS delay is defined by tCCD. A 4-bit. 209-2E Page 85 5. 8-bit or 16-bit burst operation will occur entirely within one of the 8. or 2 uniquely addressable boundary segments depending on burst length. For LPDDR2-S4 devices. The LPDDR2 NVM provides a fast column access operation. A single Read or Write Command will initiate a burst read or write operation on successive clock cycles.3.

CA0 HIGH.1 CK_c CK_t tLZ(DQS) DQS_c RL tCH tCL RL + BL/2 tHZ(DQS) tDQSCKmin tQSH tQSL DQS_c DQS_t DQS_t tRPRE tRPST Q tDQSQmax tLZ(DQ) tQH Q Q tDQSQmax tQH tHZ(DQ) Q DQ Figure 25 — Data output (read) timing (tDQSCKmin) NOTE 1 An effective Burst Length of 4 is shown. .JEDEC Standard No. The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. 209-2E Page 86 5. CA5r-CA6r and CA1f-CA9f. Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement. The command address bus inputs. RL . DQS_c. CA1 LOW and CA2 HIGH at the rising edge of the clock.4 Burst Read Command The Burst Read command is initiated by having CS_n LOW. An effective Burst Length of 4 is shown. The first bit of the burst is synchronized with the first rising edge of the data strobe. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. RL .1 CK_c CK_t tHZ(DQS) RL tCH tCL RL + BL/2 tLZ(DQS) tDQSCKmax DQS_c tQSH tQSL DQS_c DQS_t DQS_t tRPRE tRPST Q tDQSQmax tLZ(DQ) tQH tHZ(DQ) Q Q tDQSQmax tQH Q DQ Figure 24 — Data output (read) timing (tDQSCKmax) NOTE 1 NOTE 2 tDQSCK may span multiple clock periods. determine the starting column address for the burst. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers.

tDQSCK > tCK . tDQSCK > tCK SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop tDQSCK Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 27 — LPDDR2-SX: Burst read: RL = 3. 209-2E Page 87 5. BL = 4.4 SDRAM Burst Read Command (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCK Nop Nop Nop DQS_c DQS_t DQs RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Figure 26 — LPDDR2-SX: Burst read: RL = 5.JEDEC Standard No. BL = 8. BL = 4. tDQSCK < tCK NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t/CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCK Nop Nop Nop DQS_c DQS_t RL = 5 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 Figure 28 — LPDDR2-N: Burst read: RL = 5.

1. tDQSCK < tCK Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CK_t/CK_c CA0-9 [Cmd] DQS_c DQS_t DQs Col Addr Col Addr Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCKn Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCKm RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 32ms maximum tDQSCKDL = | tDQSCKn – tDQSCKm | Figure 30 — LPDDR2: tDQSCKDL timing NOTE 1 tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn .tDQSCKm} pair within any 1. BL = 8. 209-2E Page 88 5.JEDEC Standard No.tDQSCKm) for any {tDQSCKn.6us rolling window. Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CK_t/CK_c CA0-9 [Cmd] DQS_c DQS_t DQs Col Addr Col Addr Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCKn Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCKm RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 .tDQSCKm} pair within any 32ms rolling window.tDQSCKm) for any {tDQSCKn . .4 NVM Burst Read Command (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t/CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr Read Nop Nop Nop tDQSCK Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 29 — LPDDR2-N: Burst read: RL = 3.6us maximum tDQSCKDM = | tDQSCKn – tDQSCKm | Figure 31 — LPDDR2: tDQSCKDM timing NOTE 1 tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn .

JEDEC Standard No. WL = 1.160ns maximum tDQSCKDS = | tDQSCKn – tDQSCKm | Figure 32 — LPDDR2: tDQSCKDS timing NOTE 1 tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn .tDQSCKm} pair for reads within a consecutive burst within any 160ns rolling window. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Bank A Col Addr Col Addr Read Nop Nop Nop tDQSCK Nop Nop BL/2 Write Nop tDQSSmin Nop DQS_c DQS_t DQs RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 WL = 1 DIN A0 DIN A1 DIN A2 Figure 33 — LPDDR2-SX: Burst read followed by burst write: RL = 3. 209-2E Page 89 5.4 Burst Read Command (cont’d) Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CK_t/CK_c CA0-9 [Cmd] DQS_c DQS_t DQs Col Addr Col Addr Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCKn Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop RL = 5 tDQSCKm RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A0 DOUT A2 DOUT A3 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 .tDQSCKm) for any {tDQSCKn . BL = 4 .

JEDEC Standard No.WL clock cycles. WL = 1. BL = 4. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Bank N Col Addr B Col Addr B Read Nop tCCD = 2 Read Nop Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Figure 35 — LPDDR2-SX: Seamless burst read: RL = 3. 209-2E Page 90 5. Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 . tCCD = 2 . BL = 4 The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and the Burst Length (BL).4 NVM Burst Read Command (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr RDB A Col Addr Col Addr Read Nop Nop Nop tDQSCK Nop Nop BL/2 Write Nop tDQSSmin Nop DQS_c DQS_t DQs RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 WL = 1 DIN A0 DIN A1 DIN A2 Figure 34 — LPDDR2-N: Burst read followed by burst write: RL = 3. the effective burst length of the truncated read burst should be used as “BL” to calculate the minimum read to write delay. Note that if a read burst is truncated with a Burst Terminate (BST) command.

and every 8 clocks for BL=16 operation. 209-2E Page 91 5. read burst interrupt function is only allowed on burst of 8 and burst of 16. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Bank N Col Addr B Col Addr B Read Nop tCCD = 2 Read Nop Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5 Figure 37 — LPDDR2-SX: Read burst interrupt example: RL = 3. For LPDDR2-NVM. . provided that tCCD is met. NOTE 7 The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. NOTE 6 Read burst with Auto-Precharge is not allowed to be interrupted. this operation is allowed regardless of whether the accesses read the same or different RDBs as long as the RDBs are activated.JEDEC Standard No.4. NOTE 4 Reads can only be interrupted by other reads or the BST command. burst read can be interrupted by another read on even clock cycles after the Read command. NOTE 3 For LPDDR2-S2 devices. provided that tCCD is met. provided that tCCD is met. tCCD = 2 NOTE 1 For LPDDR2-S4 devices. BL = 8. this operation is allowed regardless of whether the accesses read the same or different banks as long as the banks are activated.4 NVM Burst Read Command (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB N Col Addr A Col Addr A RDB N Col Addr B Col Addr B Read Nop tCCD = 2 Read Nop Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Figure 36 — LPDDR2-N: Seamless burst read: RL = 3. For LPDDR2-SDRAM. BL = 4. 5. every 4 clocks for BL = 8 operation. For LPDDR2-S2 devices. NOTE 5 Read burst interruption is allowed to any bank inside DRAM. tCCD = 2 The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation.1 Reads interrupted by a read For LPDDR2-S4 and LPDDR2-N devices. read burst interrupt may only occur on even clock cycles after the previous read commands. read burst interrupt may occur on any clock cycle after the intial read command. NOTE 2 For LPDDR2-S4 devices. provided that tCCD is met. burst reads may be interrupted by other reads on any subsequent clock.

4. Table 48 on page 92 displays DNV retry options. see “Write data mask” on page 70. provided that tCCD is met.2 LPDDR2: Data Not Valid LPDDR2 devices will implement Data Not Valid (DNV) signal if they set MR0 OP2 bit to “1”. DNV1. A retry earlier than the pre-specified time may result in receiving another DNV signal. when implemented. and 2 are driven high. it indicates a currently reserved mode. 5.JEDEC Standard No. DNV0. and for long retry (DNV=LOW). DNV2. The DNV signal and the Data Mask signal (DM) share the same pin. (DNV = LOW) for immediate retry or (DNV = HIGH) for retry after a pre-specified time in micro seconds in Mode Register 29 (MR29) on page 45. NOTE 2 For LPDDR2-N devices. DNV shall be driven to zero during the first data beat. NOTE 5 The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. Beat 1 of DNV indicates how the controller may retry the request. Beat 3 is not used. beat 1 DNV. beat 2 DNV. Table 48 — LPDDR2: Data Not Valid DNV. read burst interrupt may only occur on even clock cycles after the previous read commands. Beat 2 for immediate retries indicates whether the immediate retry should be with read command (DNV=LOW) or active command (DNV=HIGH). 1. beat 0 DNV. and DNV3 timings are referenced to DQS0. Beat 0 of the DNV signal shall be driven HIGH if the data in the burst is invalid. DNV signal. DNV signals follow the same timings as the DQ signals for read bursts. DNV shall be driven to zero during the first data beat during MRR operations. NOTE 2 Retry Long indicates that the controller should wait for the pre-specified time before retrying the Read. DQS1. The beat 0 of the DNV signal shall be driven LOW if the data in the burst is valid. and will not implement Data Not Valid signal if they set MR0 OP2 bit to “0”. For information on the DM signal usage. Optionally. is outputted from the memory device with DQ data. LPDDR2 devices that support Data Not Valid shall drive all DNV signal(s) to the same level for each data beat during read bursts. NOTE 4 Read burst interruption is allowed to any RDB inside the NVM.4. read burst interrupt function is only allowed on burst of 8 and burst of 16. beat 3 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 X X X X X Read Burst Valid Immediate Retry with Read Immediate Retry with Activate Retry Long with Read Reserved Notes 3 1 1 2 NOTE 1 Immediate Retry indicates the controller may retry the request immediately with read or active command as specified. BL = 8. NOTE 3 Reads can only be interrupted by other reads or the BST command. and DQS3 respectively. The DNV signal(s) are valid only the first four beats of a read burst. DQS2. 209-2E Page 92 5. a Preactive command may be issued before the Active command. An Active must be issued before the retry Read command. LPDDR2-SX devices will not implement DNV.1 NVM Reads interrupted by a read (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB N Col Addr A Col Addr A RDB N Col Addr B Col Addr B Read Nop tCCD = 2 Read Nop Nop Nop Nop Nop Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5 Figure 38 — LPDDR2-N: Read burst interrupt example: RL = 3. When DNV signal for beats 0. NOTE 3 In case of Mode Register Read (MRR) command. . tCCD = 2 NOTE 1 For LPDDR2-N devices. For devices that implement Data Not Valid.

BL = 8 T0 CK_t/CK_c T1 T2 T3 T4 T5 T6 T7 T8 CA0-9 [Cmd] Row/Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop Nop Nop Nop DQS_c/ DQS_t RL = 3 DQs DM/DNV DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 40 — LPDDR2: DNV with invalid data.4. BL = 8 .2 LPDDR2: Data Not Valid (cont’d) T0 CK_t/CK_c T1 T2 T3 T4 T5 T6 T7 T8 CA0-9 [Cmd] Row/Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop Nop Nop Nop DQS_c/ DQS_t RL = 3 DQs DM/DNV DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 39 — LPDDR2: DNV with valid data: RL = 3.JEDEC Standard No. 209-2E Page 93 5. retry with Read: RL = 3.

which is 4. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. The burst data are sampled on successive edges of the DQS_t. determine the starting column address for the burst. tWRA must be satisfied before an Activate command to the same RDB may be issued after a burst write operation. The data bits of the burst cycle must be applied to the DQ pins tDS prior to the respective edge of the DQS_t.JEDEC Standard No. DQS_c until the burst length is completed. Input timings are measured relative to the crosspoint of DQS_t and its complement. For LPDDR2-N devices. The data strobe signal (DQS) should be driven LOW tWPRE prior to the data input. DQS_c. The command address bus inputs. For LPDDR2-SDRAM devices. A Preactive command may be sent at any time after a Write command. BL = 4 . CA0 HIGH. CA5r-CA6r and CA1f-CA9f. 209-2E Page 94 5. DQS_c and held valid until tDH after that edge. tWR must be satisfied before a precharge command to the same bank may be issued after a burst write operation. DQS_c tDQSH tDQSL DQS_c DQS_t DQS_t tWPRE tWPST DQ tDS VIH(ac) VIL(ac) D D tDS VIH(ac) VIH(dc) VIL(dc) D D tDH tDH VIH(dc) DM DMin DMin VIL(ac) DMin DMin VIL(dc) Figure 41 — Data input (write) timing SDRAM T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Bank A Col Addr Bank A Row Addr Row Addr Write Nop tDQSSmax Nop tDSS Nop tDSS Nop Precharge Nop Activate Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t DQs WL = 1 tWR DIN A0 tDSH DIN A1 DIN A2 tDSH DIN A3 tRP tDQSSmin Case 2: with tDQSS (min) DQS_c DQS_t DQs WL = 1 DIN A0 DIN A1 DIN A2 DIN A3 tWR Figure 42 — LPDDR2-SX: Burst write : WL = 1. The first valid datum shall be driven WL * tCK + tDQSS from the rising edge of the clock from which the Write command is issued. or 16 bit burst.5 Burst Write Operation The Burst Write command is initiated by having CS_n LOW. 8. CA1 LOW and CA2 LOW at the rising edge of the clock.

BL = 4 NOTE 1 A Preactive command may be issued on any clock cycle after a Write command and does not affect the ongoing burst. NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr RB A Row Addr Row Addr Write Nop tDQSSmax Nop tDSS Nop tDSS Nop Nop Activate Nop Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t WL = 1 DQs Case 2: with tDQSS (min) tDQSSmin DIN A0 tDSH DIN A1 DIN A2 tDSH DIN A3 tWRA DQS_c DQS_t DQs WL = 1 DIN A0 DIN A1 DIN A2 DIN A3 Figure 44 — LPDDR2-N: Burst write followed by Activate: WL = 1. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the Activate command is [WL + 1 + BL/2 + RU( tWRA/tCK)]. . 209-2E Page 95 5.JEDEC Standard No.5 NVM Burst Write Operation (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr RAB A Row Addr Row Addr Write Preactive tDQSSmax Nop tDSS Nop tDSS Nop Nop Nop Nop Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t WL = 1 DQs Case 2: with tDQSS (min) tDQSSmin DIN A0 tDSH DIN A1 DIN A2 tDSH DIN A3 DQS_c DQS_t DQs WL = 1 DIN A0 DIN A1 DIN A2 DIN A3 Figure 43 — LPDDR2-N: Burst write followed by Preactive: WL = 1. the effective burst length of the truncated write burst shall be used as “BL” to calculate the minimum write to Activate delay. NOTE 2 If a write burst is truncated with a Burst Terminate (BST) command.

NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A RDB N Col Addr B Col Addr B Write WL = 1 Nop Nop Nop Nop Nop Read Nop RL = 3 Nop DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 tWTR Figure 46 — LPDDR2-N: Burst write followed by burst read: RL=3.5 SDRAM Burst Write Operation (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank N Col Addr B Col Addr B Write WL = 1 Nop Nop Nop Nop Nop Read Nop RL = 3 Nop DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 tWTR Figure 45 — LPDDR2-SX: Burst write followed by burst read: RL=3. 209-2E Page 96 5. the effective burst length of the truncated write burst should be used as “BL” to calculate the minimum write to read delay. NOTE 2 tWTR starts at the rising edge of the clock after the last valid input datum. WL = 1. the effective burst length of the truncated write burst should be used as “BL” to calculate the minimum write to read delay.JEDEC Standard No. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU( tWTR/tCK)]. NOTE 2 tWTR starts at the rising edge of the clock after the last valid input datum. NOTE 3 If a write burst is truncated with a Burst Terminate (BST) command. . WL = 1. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the burst read command for any RDB is [WL + 1 + BL/2 + RU( tWTR/tCK)]. NOTE 3 If a write burst is truncated with a Burst Terminate (BST) command.

burst write can only be interrupted by another write on even clock cycles after the Write command. BL = 4 NOTE 1: The seamless burst write operation is supported by enabling a write command every other clock for  BL = 4 operation. every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. tCCD = 2 NOTE 1: The seamless burst write operation is supported by enabling a write command every other clock for  BL = 4 operation. For LPDDR2-S2 devices. provided that tCCD(min) is met.1 Writes interrupted by a write For LPDDR2-S4 and LPDDR2-N devices. NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A RDB N Col Addr B Col Addr B Write Nop Write Nop Nop Nop Nop Nop Nop DQS_c DQS_t WL = 1 DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Figure 48 — LPDDR2-N: Seamless burst write: WL = 1. every four clocks for BL = 8 operation. or every eight clocks for BL=16 operation. provided that tCCD(min) is met. .JEDEC Standard No. or every eight clocks for BL=16 operation. BL = 4. This operation is allowed regardless of same or different Row Buffers as long as the Row Buffers are activated. 209-2E Page 97 5.5.5 SDRAM Burst Write Operation (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank N Col Addr B Col Addr B Write Nop tCCD = 2 Write Nop Nop Nop Nop Nop Nop DQS_c DQS_t WL = 1 DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Figure 47 — LPDDR2-SX: Seamless burst write: WL = 1. 5. burst writes may be interrupted on any subsequent clock.

NOTE 3 Writes can only be interrupted by other writes or the BST command. NOTE 5 The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. provided that tCCD(min) is met. NOTE 3 For LPDDR2-S2 devices.JEDEC Standard No. 209-2E Page 98 5. write burst interrupt function is only allowed on burst of 8 and burst of 16. write burst interrupt may only occur on even clock cycles after the previous write commands. NOTE 2 For LPDDR2-S4 devices. provided that tCCD(min) is met. write burst interrupt may only occur on even clock cycles after the previous write commands. BL = 8. NOTE 7 The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. NOTE 2 For LPDDR2-N devices. tCCD = 2 NOTE 1 For LPDDR2-N devices. NOTE 6 Write burst with Auto-Precharge is not allowed to be interrupted. . tCCD = 2 NOTE 1 For LPDDR2-S4 devices. NOTE 4 Write burst interruption is allowed to any RDB inside the NVM. write burst interrupt may occur on any clock after the initial write command. write burst interrupt function is only allowed on burst of 8 and burst of 16. NOTE 5 Write burst interruption is allowed to any bank inside DRAM. BL = 8. NOTE 4 Writes can only be interrupted by other writes or the BST command.5.1 SDRAM Writes interrupted by a write (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank N Col Addr B Col Addr B Write Nop tCCD = 2 Write Nop Nop Nop Nop Nop Nop DQS_c DQS_t WL = 1 DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 Figure 49 — LPDDR2-SX: Write burst interrupt timing: WL = 1. provided that tCCD(min) is met. NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A RDB N Col Addr B Col Addr B Write Nop tCCD = 2 Write Nop Nop Nop Nop Nop Nop DQS_c DQS_t WL = 1 DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 Figure 50 — LPDDR2-N: Write burst interrupt timing: WL = 1.

6 Burst Terminate The Burst Terminate (BST) command is initiated by having CS_n LOW. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. a Burst Terminate command may only be issued up to and including BL/2 . The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. the effective burst length of the truncated burst should be used as “BL” to calculate the minimum read to write or write to read delay. CA2 LOW. S2 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Write BST Nop WL * tCK + tDQSS Nop Nop Nop Nop Nop Nop WL = 1 DQS_c DQS_t DQs DIN A0 DIN A1 Figure 51 — LPDDR2-S2: Write burst truncated by BST: WL = 1. The effective burst length of a Read or Write command truncated by a BST command is as follows:  Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command} Note that if a read or write burst is truncated with a Burst Terminate (BST) command.JEDEC Standard No. the 2-bit prefetch architecture allows the BST command to be issued in any cycle after a Write or Read command. For LPDDR2-S2 devices. NOTE 2 Additional BST commands are not allowed after T1 and may not be issued until after the next Read or Write command. Therefore. A Burst Teminate command may only be issued to terminate an active Read or Write burst. CA1 HIGH. CA0 HIGH. and CA3 LOW at the rising edge of clock.1 clock cycles after a Read or Write command. The BST command only affects the most recent read or write command. . BL = 16 NOTE 1 The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. 209-2E Page 99 5.

NOTE 2 NOTE 3 For LPDDR2-S4 devices. BL = 4 NOTE 1 The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. . 209-2E Page 100 5. For LPDDR2-S4 and LPDDR2-N devices. S4 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Write Nop Nop Nop BST Nop WL * tCK + tDQSS Nop Nop Nop BST not allowed WL = 1 DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A6 DIN A7 Figure 53 — LPDDR2-S4: Burst Write truncated by BST: WL = 1. NOTE 2 Additional BST commands are not allowed after T1 and may not be issued until after the next Read or Write command. BL = 16 NOTE 1 The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued.6 Burst Terminate (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 S2 SDRAM CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Read BST Nop Nop Nop Nop Nop Nop Nop RL * tCK + tDQSCK + tDQSQ DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 Figure 52 — LPDDR2-S2: Read burst truncated by BST: RL = 3. BST can only be issued an even number of clock cycles after the Write command.JEDEC Standard No. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. the 4-bit prefetch architecture allows the BST command to be issued on an even number of clock cycles after a Write or Read command. Therefore. the effective burst length of a Read or Write command truncated by a BST command is an integer multiple of 4.

BL = 16 NOTE 1 The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. . 209-2E Page 101 5.6 Burst Terminate (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 S4 SDRAM CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Read Nop Nop Nop BST Nop Nop Nop Nop BST not allowed DQS_c DQS_t RL = 3 RL * tCK + tDQSCK + tDQSQ DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 54 — LPDDR2-S4: Burst Read truncated by BST: RL=3. NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. BL = 16 NOTE 1 The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. BST can only be issued an even number of clock cycles after the Read command. T0 T1 T2 T3 T4 T5 T6 T7 T8 NVM CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A Write Nop Nop Nop BST Nop WL * tCK + tDQSS Nop Nop Nop BST not allowed WL = 1 DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A6 DIN A7 Figure 55 — LPDDR2-N: Burst Write truncated by BST: WL = 1. NOTE 2 For LPDDR2-S4 devices.JEDEC Standard No. NOTE 2 For LPDDR2-N devices. BST can only be issued an even number of clock cycles after the Write command.

NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.JEDEC Standard No. NOTE 2 For LPDDR2-N devices. .6 NVM Burst Terminate (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Read Nop Nop Nop BST Nop Nop Nop Nop BST not allowed RL * tCK + tDQSCK + tDQSQ DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 56 — LPDDR2-N: Burst Read truncated by BST: RL=3. BST can only be issued an even number of clock cycles after the Read command. 209-2E Page 102 5. BL = 16 NOTE 1 The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued.

Each data mask (DM) may mask its respective data byte (DQ) for any given cycle of the burst. SDRAM Data Mask Timing DQS_c DQS_t DQ VIH(ac) VIL(ac) VIH(dc) VIL(dc) VIH(ac) VIL(ac) VIH(dc) VIL(dc) DM tDS CK_c CK_t [CMD] Case 1: min tDQSS DQS_c DQS_t DQ DM Case 2: max tDQSS DQS_c DQS_t DQ DM tDH tDS tDH Data Mask Function. BL = 4 shown. is internally loaded identically to data bits to insure matched system timing. second DQ masked Write WL = 2 tDQSSmin tWR tWTR 0 1 2 3 tDQSSmax 0 1 2 3 Figure 57 — LPDDR2-SX: Write data mask .7 Write Data Mask One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices. See Table 51 on page 115 for Write to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Write to Precharge timings for LPDDR2-S2.JEDEC Standard No. WL = 2. consistent with the implementation on LPDDR SDRAMs. though used as input only. Data mask has identical timings on write operations as the data bits. 209-2E Page 103 5.

JEDEC Standard No. BL = 4 shown. 209-2E Page 104 5.7 NVM Write Data Mask (cont’d) Data Mask Timing DQS_c DQS_t DQ VIH(ac) VIL(ac) VIH(dc) VIL(dc) VIH(ac) VIL(ac) VIH(dc) VIL(dc) DM tDS tDH tDS tDH Data Mask Function. WL = 2. second DQ masked CK_c CK_t [CMD] Case 1: min tDQSS DQS_c DQS_t DQ DM Case 2: max tDQSS DQS_c DQS_t DQ DM tDQSSmax Write WL = 2 tDQSSmin tWRA tWTR Figure 58 — LPDDR2-N: Write data mask .

therefore the controller may use any RAB for any partial row address. Therefore. Note that the row size of the NVM device may differ from the row size for an SDRAM.BA2. Each RAB is coupled with one specific Row Data Buffer (RDB) selected by BA0 . The Preactive command addresses one Row Address Buffer (RAB). Therefore. Table 49 — Row Address Buffer selection for Preactive by BA inputs BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected RAB (4-RB devices) RAB 0 RAB 1 RAB 2 RAB 3 RAB 0 RAB 1 RAB 2 RAB 3 Selected RAB (8-RB devices) RAB 0 RAB 1 RAB 2 RAB 3 RAB 4 RAB 5 RAB 6 RAB 7 . Preactive is optional when the desired RAB already holds the desired partial row-address value. The Preactive command is used to load the upper part of a row address into one RAB selected by BA0 . CA1 HIGH. CA0 HIGH. Each RAB is persistent until a MRW Reset command is issued or power loss occurs. Devices may have four or eight RABs. All RABs shall be reset to 0x0000 by the memory during the initialization procedure. RDB} pair is referred to as a Row Buffer (RB).JEDEC Standard No. The Preactive command does not invoke internal sensing. The address subset stored in an RAB will later be combined with the lower portion of the row address sent with the Activate command to load one row of the memory array or Overlay Window content into an RDB. Each RAB is not restricted to any portion of the device address space. the memory controller shall issue an Activate command to the corresponding RB before issuing a Read or Write command to the respective RDB. including storing the same partial row address value in multiple RABs concurrently. after issuing a Preactive command to any RAB and then satisfying tRP. CA2 LOW. 209-2E Page 105 5. the target Row Buffer will return to the Idle state once the minimum Preactive latency (tRP) is satisfied and any ongoing Read or Write operation is complete.8 LPDDR2-N: Preactive operation The Preactive command is initiated by having CS_n LOW. An {RAB.BA2. and CA3 HIGH at the rising edge of clock. After issuing a Preactive command. or until a new Preactive command is issued to that RAB.

A Preactive command may be issued at any time following a Read command. BL = 4 NOTE 1 If a read burst is truncated with a Burst Terminate (BST) command. For an untruncated burst. BL is the complete burst length selected in the Mode Registers. An Activate command to the same Row Buffer pair may not be issued earlier than BL/2 cycles after the Read command.JEDEC Standard No. BL = 4 NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A RB M Row Addr Row Addr Read Nop BL/2 Activate Nop Nop Nop Nop Nop Nop DQS_c DQS_t DQs RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Figure 60 — LPDDR2-N: Burst read operation followed by Activate: RL = 3. Read bursts are not impacted by Preactive or Activate commands to different Row Buffer pairs. NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB M RAB M Col Addr A Col Addr A Row Addr Row Addr RB M Row Addr Row Addr Read Preactive Nop Nop Activate Nop Nop Nop Nop DQS_c DQS_t DQs RL = 3 DOUT A0 tRP DOUT A1 DOUT A2 DOUT A3 Figure 59 — LPDDR2-N: Burst read operation followed by Preactive: RL = 3. 209-2E Page 106 5. Following the Preactive command. a subsequent command to the same Row Buffer shall not be issued until tRCD is met. a Read burst may be followed by a Preactive or Activate command to the same Row Buffer pair.8.1 LPDDR2-N: Burst Read operation followed by Activate or Preactive For LPDDR2-N devices. the effective burst length of the truncated read burst shall be used as “BL” to calculate the minimum Read to Activate delay . For a truncated burst. BL is the effective burst length. Following the Activate command. only BST may be issued to the same Row Buffer until tRP is met.

209-2E Page 107 5. For an untruncated burst.8.2 LPDDR2-N: Burst Write operation followed by Activate or Preactive A Preactive command may be issued at any time after a Write command. BL = 4 . An Activate command to the same RDB may be issued tWRA after the completion of the last burst write cycle. BL is the value from the Mode Register.JEDEC Standard No. Minimum Write to Activate command spacing to the same Row Buffer equals WL + BL/2 + 1 + RU(tWRA/tCK) clock cycles. For an truncated burst. No Activate command to the same RDB should be issued prior to the tWRA delay. NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr RAB A Row Addr Row Addr Write Preactive tDQSSmax Nop Nop Nop Nop Nop Nop Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t WL = 1 DQs Case 2: with tDQSS (min) WL = 1 tDQSSmin DIN A0 DIN A1 DIN A2 DIN A3 DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 Figure 61 — LPDDR2-N: Burst write followed by Preactive: WL = 1. BL is the effective burst length.

the effective burst length of the truncated write burst shall be used as “BL” to calculate the minimum write to Activate delay. NOTE 2 If a write burst is truncated with a Burst Terminate (BST) command. 209-2E Page 108 NVM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr RB A Row Addr Row Addr Write Nop tDQSSmax Nop Nop Nop Nop Activate Nop Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t WL = 1 DQs Case 2: with tDQSS (min) WL = 1 tDQSSmin DIN A0 DIN A1 DIN A2 DIN A3 tWRA DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 Figure 62 — LPDDR2-N: Burst write followed by Activate: WL = 1. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the Activate command is [WL + 1 + BL/2 + RU( tWRA/tCK)].JEDEC Standard No. .

3 LPDDR2-N: Auto Precharge (AP) bit The AP bit (CA0f) is ignored during READ and WRITE commands. BA1. Figure 19 on page 81 shows Activate to Precharge timing. For 4-bank devices. CA1 HIGH.8. are used to determine which bank(s) to precharge.9 LPDDR2-SX: Precharge operation The Precharge command is used to precharge or close a bank that has been activated. CA2 LOW. and the bank address bits. For 4-bank devices. and CA3 HIGH at the rising edge of the clock. In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices. the Row Precharge time (tRP) for an AllBank Precharge (tRPab) is equal to the Row Precharge time for a Single-Bank Precharge (tRPpb). Table 50 — Bank selection for Precharge by address bits AB (CA4r) 0 0 0 0 0 0 0 0 1 BA2 (CA9r) 0 0 0 0 1 1 1 1 DON’T CARE BA1 (CA8r) 0 0 1 1 0 0 1 1 BA0 (CA7r) 0 1 0 1 0 1 0 1 Precharged Bank(s) Precharged Bank(s) 4-bank device 8-bank device Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All Banks DON’T CARE DON’T CARE . BA0 and BA1. The Precharge Command can be used to precharge each bank independently or all banks simultaneously.JEDEC Standard No. the Row Precharge time (tRP) for an All-Bank Precharge for 8-bank devices (tRPab) will be longer than the Row Precharge time for a Single-Bank Precharge (tRPpb). the AB flag. are used to determine which bank(s) to precharge. 209-2E Page 109 5. the AB flag. For 8-bank devices. The bank(s) will be available for a subsequent row access tRPab after an All-Bank Precharge command is issued and tRPpb after a Single-Bank Precharge command is issued. BA0. CA0 HIGH. and the bank address bits. and BA2. The Precharge command is initiated by having CS_n LOW. 5.

the effective “BL” shall be used to calculate when tRTP begins.This time is called tRTP (Read to Precharge). For LPDDR2-S2 devices. BL is the value from the Mode Register. For a truncated burst. the minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read command. tRTP begins BL/2 . For LPDDR2-S4 devices.1 clock cycles after the Read command. For LPDDR2-S2 devices.JEDEC Standard No.1 LPDDR2-SX: Burst Read operation followed by Precharge For the earliest possible precharge. BL = 8. For LPDDR2-S4 devices. tRTP(min) <= tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 SDRAM CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Bank M Row Addr Row Addr Read Nop Nop BL/2 Nop tRTP Precharge Nop Nop Activate Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 tRP DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 64 — LPDDR2-S4: Burst read followed by Precharge: RL = 3. 209-2E Page 110 5. See Table 51 on page 115 for Read to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Read to Precharge timings for LPDDR2-S2. BL = 8.2 clock cycles after the Read command. A precharge command cannot be issued until after tRAS is satisfied. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Bank M Row Addr Row Addr Read Nop Nop BL/2 Nop tRTP Precharge Nop Nop Activate Nop DQS_c DQS_t RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 tRP DOUT A4 DOUT A5 DOUT A6 DOUT A7 Figure 63 — LPDDR2-S2: Burst read followed by Precharge: RL = 3. A new bank active (command) may be issued to the same bank after the Row Precharge time (tRP). the precharge command may be issued BL/2 clock cycles after a Read command. For an untruncated burst. RU(tRTP(min)/tCK) = 2 . If the burst is truncated by a BST command or a Read command to a different bank. BL is the effective burst length. tRTP begins BL/2 . the minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 2-bit prefetch of a Read command.9.

RU(tRTP(min)/tCK) = 3 . BL = 4.1 SDRAM LPDDR2-SX: Burst Read operation followed by Precharge 9cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Bank M Row Addr Row Addr Read Nop BL/2 Nop Precharge Nop Nop Activate Nop Nop DQS_c DQS_t RL = 3 DQs tRTP = 2 DOUT A0 DOUT A1 tRP DOUT A2 DOUT A3 Figure 65 — LPDDR2-S2: Burst read followed by Precharge: RL = 3.JEDEC Standard No. BL = 4. RU(tRTP(min)/tCK) = 2 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Bank M Row Addr Row Addr Read Nop BL/2 Nop Precharge Nop Nop Activate Nop Nop DQS_c DQS_t DQs RL = 3 tRTP = 3 DOUT A0 DOUT A1 tRP DOUT A2 DOUT A3 Figure 66 — LPDDR2-S4: Burst read followed by Precharge: RL = 3. 209-2E Page 111 5.9.

For LPDDR2-S2 devices.3 LPDDR2-SX: Auto Precharge operation Before a new row in an active bank can be opened. . This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or Write latency) thus improving system performance for random data access. then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst. the AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. BL is the effective burst length. LPDDR2-S2 devices write data to the array in prefetch pairs (prefetch = 2) and LPDDR2-S4 devices write data to the array in prefetch quadruples (prefetch = 4).9. BL = 4 5.9. then the auto-precharge function is engaged. See Table 51 on page 115 for Write to Precharge timings for LPDDR2-S4 and Table 52 on page 116 for Write to Precharge timings for LPDDR2-S2. The beginning of an internal write operation may only begin after a prefetch group has been latched completely.JEDEC Standard No. Therefore. For an truncated burst. SDRAM T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Bank A Col Addr Bank A Row Addr Row Addr Write Nop tDQSSmax Nop Nop Nop Precharge Nop Activate Nop Case 1: with tDQSS (max) Completion of Burst Write DQS_c DQS_t WL = 1 tWR DIN A0 DIN A1 DIN A2 DIN A3 >= tRP DQs Case 2: with tDQSS (min) WL = 1 tDQSSmin DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 tWR Figure 67 — LPDDR2-SX: Burst write followed by precharge: WL = 1. If AP is LOW when the Read or Write command is issued. For an untruncated burst. No Precharge command to the same bank should be issued prior to the tWR delay. minimum Write to Precharge command spacing to the same bank is WL + RU(BL/2) + 1 + RU(tWR/tCK) clock cycles. minimum Write to Precharge command spacing to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. When a Read or a Write command is given to the LPDDR2 SDRAM. For LPDDR2-S4 devices. a delay must be satisfied from the time of the last valid burst input data until the Precharge command may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of the burst write to the precharge command. the write recovery time (tWR) starts at different boundaries for LPDDR2-S2 and LPDDR2-S4 devices. 209-2E Page 112 5. the active bank must be precharged using either the Precharge command or the auto-precharge function. BL is the value from the Mode Register. If AP is HIGH when the Read or Write command is issued.2 LPDDR2-SX: Burst Write followed by Precharge For write cycles.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously.9. The RAS cycle time (tRC) from the previous bank activation has been satisfied. LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 . RU(tRTP(min)/tCK) = 1 .2 + RU(tRTP/tCK) clock cycles later than the Read with AP command.JEDEC Standard No.1 + RU(tRTP/tCK) clock cycles later than the Read with AP command. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. BL = 4.1 LPDDR2-SX: Burst Read with Auto-Precharge If AP (CA0f) is HIGH when a Read Command is issued. Refer to Table 52 on page 116 for equations related to Auto-Precharge for LPDDR2-S2. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Row Addr Row Addr Read Nop BL/2 Nop Nop Nop Activate Nop Nop Nop DQS_c DQS_t RL = 3 DQs tRTP >= tRPpb DOUT A0 DOUT A1 DOUT A2 DOUT A3 Figure 68 — LPDDR2-S4: Burst read with Auto-Precharge: RL = 3. RU(tRTP(min)/tCK) = 2 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Col Addr A Col Addr A Bank M Row Addr Row Addr Read Nop BL/2 Nop Nop Nop Activate Nop Nop Nop DQS_c DQS_t RL = 3 DQs tRTP >= tRPpb DOUT A0 DOUT A1 DOUT A2 DOUT A3 Figure 69 — LPDDR2-S2: Burst read with Auto-Precharge: RL = 3. Refer to Table 51 on page 115 for equations related to Auto-Precharge for LPDDR2-S4.3. LPDDR2-S2 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 . 209-2E Page 113 5. the Read with Auto-Precharge function is engaged. BL = 4. whichever is greater.

The LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is tWR cycles after the completion of the burst write. The RAS cycle time (tRC) from the previous bank activation has been satisfied.9. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied. 209-2E Page 114 5. the Write with Auto-Precharge function is engaged. BL = 4 .JEDEC Standard No.3. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Bank A Row Addr Row Addr Write WL = 1 Nop Nop Nop Nop tWR Nop Nop Activate Nop DQS_c DQS_t DQs DIN A0 DIN A1 DIN A2 DIN A3 tRPpb Figure 70 — LPDDR2-SX: Burst write w/Auto Precharge: WL = 1.2 LPDDR2-SX: Burst write with Auto-Precharge If AP (CA0f) is HIGH when a Write Command is issued.

2 BL/2 + max(2. RU(tRTP/tCK)) . 209-2E Page 115 5. .2 + RU(tRPpb/tCK) Illegal RL + BL/2 + RU(tDQSCKmax/tCK) .2 1 1 BL/2 + max(2. the precharge period should be counted from the latest precharge command. RU(tRTP/tCK)) . RU(tRTP/tCK)) . seamless write operations to different banks are supported.JEDEC Standard No.2 1 1 3 3 3 3 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 NOTE 1 For a given bank. RU(tRTP/tCK)) .2 BL/2 + max(2. seamless read operations to different banks are supported.WL + 1 Illegal BL/2 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + RU(tWR/tCK) + 1 WL + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) Illegal BL/2 Illegal WL + BL/2 + RU(tWTR/tCK) + 1 1 1 1 1 Unit clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks Notes 1 1 1 1 1. NOTE 3 After Read with AP.2 LPDDR2-SX: Burst write with Auto-Precharge (cont’d) Table 51 — LPDDR-S4: Precharge & Auto Precharge clarification From Command Read BST (for Reads) To Command Precharge (to same Bank as Read) Precharge All Precharge (to same Bank as Read) Precharge All Precharge (to same Bank as Read w/AP) Precharge All Activate (to same Bank as Read w/AP) Read w/AP Write or Write w/AP (same bank) Write or Write w/AP (different bank) Read or Read w/AP (same bank) Read or Read w/AP (different bank) Write BST (for Writes) Precharge (to same Bank as Write) Precharge All Precharge (to same Bank as Write) Precharge All Precharge (to same Bank as Write w/AP) Precharge All Activate (to same Bank as Write w/AP) Write w/AP Write or Write w/AP (same bank) Write or Write w/AP (different bank) Read or Read w/AP (same bank) Read or Read w/AP (different bank) Precharge Precharge All Precharge (to same Bank as Precharge) Precharge All Precharge Precharge All Minimum Delay between “From Command” to “To Command” BL/2 + max(2. After Write with AP.2 BL/2 + max(2.3. NOTE 2 Any command issued during the minimum delay time as specified in Table 51 is illegal.9. Read w/AP and Write w/AP may not be interrupted or truncated. either one bank precharge or precharge all. issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. RU(tRTP/tCK)) .

issued to that bank. .JEDEC Standard No.1 BL/2 + RU(tRTP/tCK) . After Write with AP.1 BL/2 + RU(tRTP/tCK) .WL + 1 Illegal BL/2 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + RU(tWR/tCK) + 1 WL + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) Illegal BL/2 Illegal WL + BL/2 + RU(tWTR/tCK) + 1 1 1 1 1 Unit clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks clks Notes 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 NOTE 1 For a given bank. the precharge period should be counted from the latest precharge command.1 + RU(tRPpb/tCK) Illegal RL + BL/2 + RU(tDQSCKmax/tCK) .1 1 1 BL/2 + RU(tRTP/tCK) . either one bank precharge or precharge all. seamless write operations to different banks are supported. 209-2E Page 116 5.2 LPDDR2-SX: Burst write with Auto-Precharge (cont’d) Table 52 — LPDDR-S2: Precharge & Auto Precharge clarification From Command Read BST (for Reads) To Command Precharge (to same Bank as Read) Precharge All Precharge (to same Bank as Read) Precharge All Precharge (to same Bank as Read w/AP) Precharge All Activate (to same Bank as Read w/AP) Read w/AP Write or Write w/AP (same bank) Write or Write w/AP (different bank) Read or Read w/AP (same bank) Read or Read w/AP (different bank) Write BST (for Writes) Precharge (to same Bank as Write) Precharge All Precharge (to same Bank as Write) Precharge All Precharge (to same Bank as Write w/AP) Precharge All Activate (to same Bank as Write w/AP) Write w/AP Write or Write w/AP (same bank) Write or Write w/AP (different bank) Read or Read w/AP (same bank) Read or Read w/AP (different bank) Precharge Precharge All Precharge (to same Bank as Precharge) Precharge All Precharge Precharge All Minimum Delay between “From Command” to “To Command” BL/2 + RU(tRTP/tCK) . The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. Read w/AP and Write w/AP may not be interrupted or truncated. NOTE 2 Any command issued during the minimum delay time as specified in Table 52 is illegal.1 BL/2 + RU(tRTP/tCK) .3. NOTE 3 After Read with AP.9. seamless read operations to different banks are supported.

by Precharge all-bank command). and CA2 HIGH at the rising edge of clock.JEDEC Standard No. Per Bank Refresh is only allowed in devices with 8 banks. All banks have to be in Idle state when REFab is issued (for instance. . CA0 LOW. the REFpb command may not be issued to the memory until the following conditions are met: a) tRFCab has been satisified after the prior REFab command b) tRFCpb has been satisfied after the prior REFpb command c) tRP has been satisified after the prior Precharge command to that given bank tRRD has been satisfied after the prior ACTIVATE command (if applicable. A bank must be idle before it can be refreshed. CA1 LOW. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-12-3-4-5-6-7-0-1-. REFpb performs a refresh operation to the bank which is scheduled by the bank counter in the memory device. When the Per Bank refresh cycle has completed. all banks will be in the Idle state. As shown in Table 53 on page 118. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is initiated by having CA3 HIGH at the rising edge of clock. As shown in Table 53 on page 118.. 209-2E Page 117 5. after issuing REFpb: a) tRFCpb must be satisified before issuing a REFab command b) tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank c) tRRD must be satisified before issuing an ACTIVATE command to a different bank d) tRFCpb must be satisified before issuing another REFpb command An All Bank Refresh command. The bank addressing for the Per Bank Refresh count is the same as established in the single-bank Precharge command (see Table 50 on page 109.”. As shown in Table 53 on page 118.10 LPDDR2-SX: Refresh command The Refresh command is initiated by having CS_n LOW. During the REFpb operation. REFab also synchronizes the bank count between the controller and the SDRAM to zero. for example after activating a row in a different bank than affected by the REFpb command). by resetting bank count to zero. after issuing REFab: a) the tRFCab latency must be satisfied before issuing an ACTIVATE command b) the tRFCab latency must be satisfied before issuing a REFab or REFpb command. The bank count is synchronized between the controller and the SDRAM upon issuing a RESET command or at every exit from self refresh. It is the responsibility of the controller to track the bank being refreshed by the Per Bank Refresh command. The target bank is inaccessable during the Per Bank Refresh cycle time (tRFCpb). any of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write command. A Per Bank Refresh command. the affected bank will be in the Idle state. REFab performs a refresh operation to all banks. “Bank selection for Precharge by address bits”). As shown in Table 53 on page 118.. however other banks within the device are accessable and may be addressed during the Per Bank Refresh cycle. the REFab command may not be issued to the memory until the following conditions have been met: a) tRFCab has been satisified after the prior REFab command b) tRFCpb has been satisified after the prior REFpb command c) tRP has been satisified after prior Precharge commands When the All Bank refresh cycle has completed.

Therefore. 209-2E Page 118 5.RU{tSRF / tREFI} = R . (3) Refresh Requirements and Self-Refresh: If any time within a refresh window is spent in Self-Refresh Mode. where RU stands for the round-up function. For LPDDR2-SDRAM devices supporting Per-Bank-Refresh.10 LPDDR2-SX: Refresh command (cont’d) Table 53 — Command Scheduling Separations related to Refresh Symbol tRFCab minimum delay from REFab to REFab Activate cmd to any bank .JEDEC Standard No. The resulting average refresh interval (tREFI) is given in Table 102 on page 195 and Table 101 on page 195.RU{R * tSRF / tREFW}. REFpb REFab Activate cmd to same bank as REFpb REFpb Activate cmd to different bank than REFpb REFpb affecting an idle bank (different bank than Activate) Activate cmd to different bank than prior Activate Notes tRFCpb REFpb REFpb tRRD Activate 1 NOTE 1 A bank must be in the Idle state before it is refreshed. (2) Burst Refresh limitation: To limit maximum current consumption. . a maximum of 8 REFab commands may be issued in any rolling tREFBW (tREFBW = 4 x 8 x tRFCab). See Mode Register 4 on page 38 for tREFW and tREFI refresh multipliers at different MR4 settings. 5. a REFab command may be replaced by a full cycle of eight REFpb commands.1 LPDDR2 SDRAM Refresh Requirements (1) Minimum number of Refresh commands: The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh Window (tREFW = 32 ms @ MR4[2:0] = “011” or Tcase  85 °C). the number of required Refresh commands in this particular window is reduced to: R* = R .10. See Table 101 on page 195 and Table 102 on page 195 for actual numbers per density.  REFab is not allowed and REFpb is allowed only if it affects a bank which is in the Idle state. after Activate. This condition does not apply if REFpb commands are used.

(e. if they are repeated in every subsequent 32 ms window. until the refresh window is complete.the regular and the burst/pause .1 LPDDR2 SDRAM Refresh Requirements (cont’d) SDRAM A) tREFW tSRF CKE Enter Self-Refresh B) CKE tREFW tSRF Exit Self-Refresh C) CKE tREFW tSRF Exit Self-Refresh D) CKE Enter Self-Refresh tREFW tSRF1 tSRF2 Exit Self-Refresh Enter Self-Refresh tSRF = tSRF1 + tSRF2 Exit Self-Refresh Figure 71 — LPDDR2-SX: Definition of tSRF Several examples on how to tSRF is calculated:  A: with the time spent in Self-Refresh Mode fully enclosed in the Refresh Window (tREFW).JEDEC Standard No. Figure 73 on page 121 shows an example of an allowable transition from a burst pattern to a regular. In the most straight forward case a REFRESH command should be scheduled every tREFI.. then repeating this sequence. The users may choose to deviate from this regular refresh pattern e. as long as the boundary conditions above are met. Therefore it is recommended to enter Self-Refresh-Mode ONLY directly after the burst-phase of a burst/pause refresh pattern as indicated in Figure 75 on page 122 and begin with the burst phase upon exit from Self-Refresh. For several rolling tREFW intervals the minimmun number of REFRESH commands is not satisfied. distributed refresh pattern has to be assumed. The understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is employed). Figure 74 on page 122 shows an example of a non-allowable transition. as in Self-Refresh-Mode a regular. LPDDR2-SX devices allow significant flexibiliy in scheduling REFRESH commends.10. In this case Self-Refresh may be entered at any time. LPDDR2-S4 1Gb) the user may choose to issue a refresh burst of 4096 REFRESH commands with the maximum allowable rate (limited by tREFBW) followed by a long time without any REFRESH commands. B: at Self-Refresh entry C: at Self-Refresh exit D: with several different intervals spent in Self Refresh during one tREFW interval In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices. all rolling tREFW intervalls will have at least the required number of refreshes. If this transition happens directly after the burst refresh phase. for a LPDDR2-S4 1Gb device @ Tcase <= 85C this can be up to 32 ms . The achieveable time without REFRESH commands is given by tREFW .. extreme care must be taken when transitioning from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. distributed pattern.4096 * 4 * 130 ns ~ 30 ms). which is reflected in the equation for R* above.patterns can satisfy the refresh requirements per rolling refresh interval. . to enable a period where no refreshes are required. 209-2E Page 119 5.g.(R / 8) * tREFBW = tREFW . While both .g. In the extreme (e. In this case the regular refresh pattern starts after the completion of the pause-phase of the burst/pause refresh pattern.R * 4 * tRFCab..g.

10.8 us.1 LPDDR2 SDRAM Refresh Requirements (cont’d) tREFI tREFI 0 ms 4‚096 4‚097 32 ms 8‚193 8‚192 12‚288 4. . 209-2E Page 120 5.g. Repetitive Burst Refresh with Subsequent Refresh Pause NOTE 1 For a (e.) LPDDR2-S4 1 Gb device @ Tcase less than or equal to 85C the distributed refresh pattern would have one REFRESH command per 7.52 us followed by ~30 ms without any REFRESH command. the burst refresh pattern would have an average of one refresh command per 0. Distributed Refresh Pattern vs.JEDEC Standard No.096 8‚192 64 ms 12‚288 12‚289 96 ms 16‚384 tREFBW tREFBW Figure 72 — LPDDR2-SX: Regular.

10.) LPDDR2-S4 1 Gb device @ Tcase less than or equal to 85 C the distributed refresh pattern would have one REFRESH command per 7.8 us. Distributed Refresh Pattern NOTE 1 For a (e.52 us followed by ~30 ms without any REFRESH command.g. the burst refresh pattern would have an average of one refresh command per 0. 209-2E Page 121 5.JEDEC Standard No.1 LPDDR2 SDRAM Refresh Requirements (cont’d) tREFI tREFI 0 ms 4‚096 4‚097 32 ms 10‚240 8‚192 64 ms 12‚288 96 ms 16‚384 tREFBW tREFBW Figure 73 — LPDDR2-SX: Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular. .

193 96 ms 12‚288 tREFW = 32 ms tREFBW tREFBW not enough Refresh commands in this refresh window!! Figure 74 — LPDDR2-SX: NOT-Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular.JEDEC Standard No. .1 LPDDR2 SDRAM Refresh Requirements (cont’d) tREFI tREFI 0 ms 4‚096 4‚097 32 ms 8‚192 64 ms 10‚240 8. Distributed Refresh Pattern NOTE 1 Only ~2048 REFRESH commands (<R!!) in the indicated tREFW win-   0 ms 4‚096 4‚097 32 ms 8‚192 Self-Refresh tREFBW tREFBW Figure 75 — LPDDR2-SX: Recommended Self-refresh entry and exit in conjunction with a Burst/Pause Refresh patterns. 209-2E Page 122 5.10.

Figure 77 — LPDDR2-SX: Per Bank Refresh Operation .1 LPDDR2 SDRAM Refresh Requirements (cont’d) SDRAM T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t/CK_c CA0-9 [Cmd] AB Precharge Nop >= tRPab Nop REFab >= tRFCab Nop REFab >= tRFCab Nop ANY Figure 76 — LPDDR2-SX: All Bank Refresh Operation SDRAM T0 T1 Tx Tx+1 Tx+2 Ty Ty+1 Tz Tz+1 CK_t/CK_c CA0-9 [Cmd] AB Bank 1 Row A Row A Precharge Nop Nop >= tRPab REFpb >= tRFCpb REFpb >= tRFCpb ACT Refresh to Bank 0 Refresh to Bank 1 Activate command to Bank 1 NOTE 1 NOTE 2 In the beginning of this example. the REFpb bank is pointing to Bank 0. Operations to other banks than the bank being refreshed are allowed during the tRFCpb period.JEDEC Standard No. 209-2E Page 123 5.10.

209-2E Page 124 5. CA1 LOW. and CA2 HIGH at the rising edge of the clock. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. NOP commands must be registered on each positive clock edge during the Self Refresh exit interval tXSR. LPDDR2SX devices will also manage Self Refresh power consumption when the operating temperature changes. The procedure for exiting Self Refresh requires a sequence of commands.11 LPDDR2-SX: Self Refresh operation The Self Refresh command can be used to retain data in the LPDDR2 SDRAM. When in the Self Refresh mode. Once the command is registered. the clock must be restarted and stable before the device can exit Self Refresh operation. For proper self refresh operation. power supply pins (VDD1. are “don’t care”. The SDRAM initiates a minimum of one all-bank refresh command internally within tCKESR period once it enters Self Refresh mode. See “LPDDR2 IDD Specification Parameters and Operating Conditions” on page 186 for details. However prior to exiting Self-Refresh. Prior to exiting Self-Refresh. VrefDQ and VrefCA may be at any level within minimum and maximum levels (see “Absolute Maximum DC Ratings” on page 159). CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down command. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered. CKE must remain HIGH for the entire Self Refresh exit period tXSR for proper operation except for self refresh re-entry. VDD2. Once Self Refresh Exit is registered. VrefDQ and VrefCA must be within specified limits (see “Recommended DC Operating Conditions” on page 160). Upon exit from Self Refresh. the clock shall be stable and within specified limits for a minimum of 2 tCK prior to the positive clock edge that registers CKE HIGH. however. LPDDR2-SX devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. The LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. VDDQ may be turned off during Self-Refresh. VDDQ must be within specified limits. it is required that at least one Refresh command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh. Once the LPDDR2 SDRAM has entered Self Refresh mode. all of the external signals except CKE.JEDEC Standard No. even if the rest of the system is powered down. . CKE must be held LOW to keep the device in Self Refresh mode. CA0 LOW. a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh mode is tCKESR. The clock is internally disabled during Self Refresh Operation to save power. and VDDCA) must be at valid levels. CS_n LOW. First. The Self Refresh Command is defined by having CKE LOW. the LPDDR2 SDRAM retains data without external clocking. lower at low temperatures and higher at high temperatures.

5.JEDEC Standard No. NOPs shall be issued during tXSR. SDRAM 2 tCK (min) CK_c CK_t tIHCKE CKE tISCKE Input clock frequency may be changed or stopped during Self-Refresh tIHCKE tISCKE CS_n [CMD] Valid Enter SR NOP Exit SR NOP NOP Valid tCKESR(min) Enter Self-Refresh Exit Self-Refresh tXSR(min) Figure 78 — LPDDR2-SX: Self-Refresh Operation NOTE 1 Input clock frequency may be changed or stopped during self-refresh.1 LPDDR2-S2: Partial Array Self-Refresh: Bank Masking LPDDR2-S2 SDRAM keeps the same PASR mapping of LPDDR SDRAM (JESD209). The PASR range becomes effective when the device goes into self refresh mode and determines which bank or banks to be refreshed. 209-2E Page 125 5.11 LPDDR2-SX: Self Refresh operation (cont’d) For LPDDR2 SDRAM. a minimum of 2 clocks of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed grade. tXSR begins at the rising edge of the clock after CKE is driven HIGH. MR16 has to be properly programmed to choose the PASR range (See Mode Register 16 as described on page 41). Table 54 — Bank Masking in LPDDR2-S2 4-Bank devices (64mb-2Gb) PASR Choice Full Array 1/2 Array 1/4 Array No Self-Refresh No Self-Refresh Bank 0 Bank 1 Bank 2 Bank 3 Table 55 — Bank Masking in LPDDR2-S2 8-Bank devices (4Gb-8Gb) PASR Choice Full Array 1/2 Array 1/4 Array 1/8 Array No Self-Refresh No Self-Refresh No Self-Refresh Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 . NOTE 2 NOTE 3 NOTE 4 Device must be in the “All banks idle” state prior to entering Self Refresh mode. since no refresh operations are performed in power-down mode. the maximum duration in power-down mode is only limited by the refresh requirements outlined in section “LPDDR2 SDRAM Refresh Requirements” on page 118. The choice of partial array to be refreshed in self refresh mode allows to reduce the range into lower numbered banks.11. provided that upon exiting self-refresh. A valid command may be issued only after tXSR is satisfied.

a refresh to a bank is determined by the programmed status of segment mask bits. or 512Mb does not support segment masking. Table 56 — Example of Bank and Segment Masking use in LPDDR2-S4 devices Segment Mask Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 (MR17) Bank Mask (MR16) Segment 0 Segment 1 Segment 2 Segment 3 Segment 4 Segment 5 Segment 6 Segment 7 0 0 1 0 0 0 0 1 M M 0 1 M M M M M M M M M M M M M M M M M M 0 0 0 0 0 1 M M M M M M M M NOTE 1 This table illustrates an example of an 8-bank LPDDR2-S4 device. 256Mb. Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place. as well as segment 2 and segment 7 are masked. “unmasked”. If a bank is masked via MRW. The mask bit to the bank controls a refresh operation of entire memory within the bank. “masked”. see Mode Register 17 as described on page 41. For LPDDR2-S4 devices. which is decribed in the following chapter.11. 5. a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. a refresh operation to the address range which is represented by a segment is blocked when the mask bit to this segment is programmed.2 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking LPDDR2-S4 SDRAM has 4 or 8 banks. One more mode register unit may be reserved for future use. For segment masking bit assignments. a coupled mask bit has to be programmed. One mode register unit is used for the programming of segment mask bits up to 8 bits. The number of segments differ by the density and the setting of each segment mask bit is applied across all the banks. When a bank mask bit is unmasked. To enable a refresh operation to a bank. Only bank masking scheme is available. One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status of each bank up to 8 banks. Programming of segment mask bits is similar to the one of bank mask bits.3 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking Segment masking scheme may be used in lieu of or in combination with bank masking scheme in LPDDR2-S4 SDRAM.JEDEC Standard No. For 1Gb and larger densities. LPDDR2 SDRAM whose density is 64Mb. while 1Gb and higher density has 8. These 2 mode register units are noted as “not used” for low-density LPDDR2-S4 SDRAM and a programming of mask bits has no effect on the device operation. 128Mb. 8 segments are used as listed in Mode Register 17 as described on page 41. 209-2E Page 126 5. For bank masking bit assignments. when a refresh operation to bank 1 and bank 7. see Mode Register 16 as described on page 41.11. . For those refresh-enabled banks. 64Mb to 512Mb LPDDR2 SDRAM has 4 banks.

NOTE 5 Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in the section on DQ Calibration. 209-2E Page 127 5. The MRR command has a burst length of four. No command (other than Nop) is allowed during this period. tMRR = 2 NOTE 1 Mode Register Read has a burst length of four. RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Mode Register Read Command is issued. Note that if a read or write burst is truncated with a Burst Terminate (BST) command. Subsequent beats contain valid. The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command. CA2 LOW. NOTE 3 Mode Register data is valid only on DQ[0-7] on the first beat. because read-bursts and write-bursts shall not be truncated by MRR.” . Subsequent data beats contain valid. where subsequent data beats contain valid content as described in “DQ Calibration” on page 130. and CA3 HIGH at the rising edge of the clock. T0 CK_t / CK_c T1 T2 T3 T4 T5 T6 T7 T8 CA0-9 [Cmd] Reg A Reg A Reg B Reg B MRR tMRR = 2 MRR tMRR = 2 DQS_t DQS_c RL = 3 DQ[0-7] DQ[8-max] CMD not allowed DOUT A UNDEF UNDEF UNDEF UNDEF DOUT B UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF Figure 79 — Mode Register Read timing example: RL = 3. The MRR command period (tMRR) is 2 clock cycles. except in the case of the DQ Calibration function DQC. DQS_c shall be toggled.JEDEC Standard No. NOTE 2 Mode Register Read operation shall not be interrupted. Mode Register Reads to reserved and write-only registers shall return valid. CA1 LOW. but undefined data for the duration of the MRR burst. DQ[8-max] contain valid.WL clock cycles.12 Mode Register Read Command The Mode Register Read command is used to read configuration and status data from mode registers for both NVM and SDRAM. DQS_c shall be toggled for the duration of the Mode Register Read burst. NOTE 7 Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles. The Mode Register Read operation (consisting of the MRR command and the corresponding data traffic) shall not be interrupted. the effective burst length of the truncated burst should be used as “BL. CA9rCA4r}. The mode register contents are available on the first data beat of DQ0-DQ7. The Mode Register Read (MRR) command is initiated by having CS_n LOW. but undefined content. The mode register is selected by {CA1f-CA0f. All DQS_t. CA0 LOW. NOTE 4 The Mode Register Command period is tMRR. but undefined data. NOTE 6 Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 . but undefined content on all data beats and DQS_t.

12 Mode Register Read Command (cont’d) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] BA M Col Addr A Col Addr A Reg B Reg B Read BL/2 MRR tMRR = 2 DQS_c DQS_t RL = 3 DQ[0-7] DQ[8-max] CMD not allowed DOUT A0 DOUT A0 DOUT A1 DOUT A1 DOUT A2 DOUT A2 DOUT A3 DOUT A3 DOUT B UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF Figure 80 — LPDDR2: Read to MRR timing example: RL = 3. T0 CK_t / CK_c T1 T2 T3 T4 T5 T6 T7 T8 CA0-9 [Cmd] BA N Col Addr A Col Addr A Reg B Reg B Write MRR RL = 3 DQS_c DQS_t WL = 1 DIN A0 DIN A1 DIN A2 DIN A3 tWTR tMRR = 2 CMD not allowed Figure 81 — LPDDR2: Burst Write Followed by MRR: RL = 3. WL = 1. No command (other than Nop) is allowed during this period. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 + RU( tWTR/tCK)]. tMRR = 2 NOTE 1: The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2. NOTE 2 The Mode Register Read Command period is tMRR. NOTE 2: The Mode Register Read Command period is tMRR. . 209-2E Page 128 5.JEDEC Standard No. No command (other than Nop) is allowed during this period.

For example. the system shall use the maximum TempGradient and the maximum response time of the system using the following equation: TempGradient   ReadInterval + tTSI + SysRespDelay   C Table 57 — Temperature Sensor Parameter Symbol Max/Min Max Max Max Max Max Value System Dependent Unit Notes o System Temperature Gradient TempGradient MR4 Read Interval Temperature Sensor Interval System Response Delay Device Temperature Margin ReadInterval tTSI SysRespDelay TempMargin C/s System Dependent ms 32 ms System Dependent ms 2 o C For example.  ReadInterval + ms + ms   C s In this case. 209-2E Page 129 5. ReadInterval shall be no greater than 167 ms. applications should consider the following factors: TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2o C. LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. SysRespDelay is the maximum time between a read of MR4 and the response by the system. the device temperature status bits shall be no older than tTSI. To assure proper operation using the temperature sensor. LPDDR2 devices shall allow for a 2o C temperature margin between the point at which the device temperature enters the Extended Temperature Range and point at which the controller re-configures the system accordingly. and/or monitor the operating temperature (SDRAM and NVM).JEDEC Standard No. TCASE may be above 85o C when MR4[2:0] equals 011B.1 Temperature Sensor LPDDR2-SX and LPDDR2-N devices feature a temperature sensor whose status can be read from MR4. the actual device case temperature may be higher than the TOPER specification ( See “Operating Temperature Range” on page 161) that applies for the Standard or Extended Temperature Ranges. When using the temperature sensor. This sensor can be used to determine an appropriate refresh rate (SDRAM).12. TempSensorInterval (tTSI) is maximum delay between internal updates of MR4. determine whether AC timing de-rating is required in the Extended Temperature Range (SDRAM and NVM). Upon exiting self-refresh or power-down. if TempGradient is 10oC/s and the SysRespDelay is 1 ms: C --------. . Either the temperature sensor or the device TOPER ( See “Operating Temperature Range” on page 161) may be used to determine whether operating temperature requirements are being met. In order to determine the required frequency of polling MR4. ReadInterval is the time period between MR4 reads from the system.

and DQ[24] for x32 devices. DQ[7:1]. MRR DQ Calibration commands may only occur in the Idle state. and DQ[31:25] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. For x16 devices. For LPDDR2-SX devices. 209-2E Page 130 5.12. A Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the specified pattern on DQ[0] for x8 devices.2 DQ Calibration LPDDR2-SX and LPDDR2-N devices feature a DQ Calibration function that outputs one of two predefined system timing calibration patterns. DQ[0] and DQ[8] for x16 devices. DQ[8]. DQ[23:17]. DQ[7:1] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. DQ[15:9]. For x8 devices.JEDEC Standard No. and DQ[0].1 Temperature Sensor (cont’d) Temp < (tTSI + ReadInterval + SysRespDelay) Device Temp Margin G Temp n radie t 2oC MR4 Trip Level tTSI MR4 = 0x03 Temperature Sensor Update Host MR4 Read MRR MR4 = 0x03 MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x06 Time ReadInterval SysRespDelay MRR MR4 = 0x86 Figure 82 — Temp Sensor Timing 5. For x32 devices. DQ[16].12. Table 58 — Data Calibration Pattern Description Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3 Pattern “A” (MR32) Pattern “B” (MR40) 1 0 0 0 1 1 0 1 .

209-2E Page 131 5.JEDEC Standard No. For x32 devices. NOTE 4 For x8 devices. and DQ[24] shall drive the same information as DQ[0] during the burst. DQ[7:1] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. NOTE 5 The Mode Register Command period is tMRR. DQ[23:17]. NOTE 3 Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. NOTE 2 Mode Register Read operation shall not be interrupted. DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. DQ[8].2 DQ Calibration (cont’d) T0 CK_t / CK_c T1 T2 T3 T4 T5 T6 T7 T8 CA0-9 [Cmd] Reg 32 Reg 32 Reg 40 Reg 40 MRR32 tMRR = 2 MRR40 tMRR = 2 DQS_t DQS_c RL = 3 DQ[0] DQ[7:1] 1 UNDEF 0 UNDEF 1 UNDEF 0 0 UNDEF 0 UNDEF 1 UNDEF 1 x8 1 0 1 0 0 0 1 1 Pattern ”A” DQ[8] DQ[15:9] 1 UNDEF 0 UNDEF 1 UNDEF 0 0 Pattern ”B” UNDEF 0 UNDEF 1 UNDEF 1 x16 1 0 1 0 0 0 1 1 x32 DQ[16] DQ[23:17] 1 UNDEF 0 UNDEF 1 UNDEF 0 0 UNDEF 0 UNDEF 1 UNDEF 1 1 0 1 0 0 0 1 1 DQ[24] DQ[31:25] CMD not allowed 1 UNDEF 0 UNDEF 1 UNDEF 0 0 UNDEF 0 UNDEF 1 UNDEF 1 1 0 1 0 0 0 1 1 Optionally driven the same as DQ0 or to 0b Figure 83 — MR32 and MR40 DQ Calibration timing example: RL = 3. For x16 devices. DQ[15:9]. tMRR = 2 NOTE 1 Mode Register Read has a burst length of four. DQ[7:1]. and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b during the burst.12. No command (other than Nop) is allowed during this period . For x16 devices. DQ[16]. For x32 devices. DQ[8] shall drive the same information as DQ[0] during the burst.

The minimum time from the burst write command to the MRW command is defined by the Write Latency (WL) and the Burst Length (BL). CA1 LOW. 209-2E Page 132 5. The data to be written to the mode register is contained in CA9f-CA2f.13.1 LPDDR2-SX: Mode Register Write For LPDDR2-S devices. the MRW may be issued from the Row Active or Idle states. tMRW = 5 NOTE 1 The Mode Register Write Command period is tMRW. the MRW may only be issued when all banks are in the idle precharge state. CA0 LOW. The minimum time from the burst read command to the MRW command is defined by the Read Latency (RL) and the Burst Length (BL).JEDEC Standard No. The MRW command period is defined by tMRW. Minimum Write to MRW latency is WL + 1 + BL/2 + RU(tWTR/tCK) clock cycles. One method of ensuring that the banks are in the idle precharge state is to issue a Precharge-All command. If the MRW command is issued from the Row Active state. Minimum Read to MRW latency is RL + RU(tDQSCKmax/tCK) + BL/2 clock cycles. Mode Register Writes to read-only registers shall have no impact on the functionality of the device. The mode register is selected by {CA1f-CA0f. the device is in the idle state. 5. CA2 LOW.13 Mode Register Write Command The Mode Register Write command is used to write configuration data to mode registers for both NVM and SDRAM.” . and CA3 LOW at the rising edge of the clock.13. T0 CK_t / CK_c T1 T2 Tx Tx + 1 Tx + 2 Ty Ty + 1 Ty + 2 CA0-9 [Cmd] MR Addr MR Data MR Addr MR Data MRW tMRW MRW ANY tMRW CMD not allowed Figure 84 — Mode Register Write timing example: RL = 3. No command (other than Nop) is allowed during this period. all row buffer contents are invalidated and the device returns to the Idle state. The Mode Register Write (MRW) command is initiated by having CS_n LOW. Note that if a read or write burst is truncated with a Burst Terminate (BST) command. NOTE 2 At time Ty.2 LPDDR2-N: Mode Register Write For LPDDR2-N devices. the effective burst length of the truncated burst should be used as “BL. 5. CA9r-CA4r}.

BL = 4 NOTE 1 The minimum number of clock cycles from the burst read command to the Mode Register Write command is [RL + RU( tDQSCK/tCK) + BL/2]. No command (other than Nop) is allowed during this period. BL = 4 NOTE 1 The minimum number of clock cycles from the burst write command to the Mode Register Write command is [WL + 1 + BL/2 + RU( tWTR/tCK)]. NOTE 2 The Mode Register Write Command period is tMRW. NOTE 2 The Mode Register Write Command period is tMRW.2 LPDDR2-N: Mode Register Write (cont’d) NVM T0 T1 T2 T3 T4 T5 T6 T7 Tx CK_t / CK_c CA0-9 [Cmd] RDB M Col Addr A Col Addr A MR Addr MR Data Write MRW tMRW DQS_c DQS_t WL = 1 DIN A0 DIN A1 DIN A2 DIN A3 tWTR CMD not allowed Figure 85 — LPDDR2-N: Burst Write Followed by MRW: WL = 1. NVM T0 T1 T2 T3 T4 T5 T6 T7 Tx CK_t / CK_c CA0-9 [Cmd] RDB A Col Addr Col Addr MR Addr MR Data Read Nop Nop Nop tDQSCK Nop Nop BL/2 MRW tMRW DQS_c DQS_t DQs RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 CMD not allowed Figure 86 — LPDDR2-N: Burst Read followed by MRW: RL = 3. No command (other than Nop) is allowed during this period. . 209-2E Page 133 5.13.JEDEC Standard No.

13.1).13. In addition. No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4). After MRW Reset. for LPDDR2-N devices.4. this command ends all embedded operations and resets all Overlay Window registers to their default values. This command resets all Mode Registers to their default values. Array data for LPDDR2-SX devices are undefined after the MRW Reset command. The MRW Reset command may be issued from the Idle state for LPDDR2-SX devices and the Idle or Active states for LPDDR2-N devices. 209-2E Page 134 5. refer to Figure 6 on page 30. boot timings must be observed until the device initialization sequence is complete and the device is in the Idle state.JEDEC Standard No. .3 Mode Register Write Reset (MRW Reset) Any MRW command issued to MRW63 initiates an MRW Reset. For the timing diagram related to MRW Reset.2 LPDDR2-N: Mode Register Write (cont’d) Table 59 — Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) Current State SDRAM NVM Command Intermediate State SDRAM NVM Next State SDRAM All Banks Idle (All Banks Idle) Mode Register Writing All Banks Idle All RBs idle MRW (All Banks Idle) Resetting MRW (RESET) (Device Auto-Init) (Resetting) (All RBs Idle) Device Auto-Init All Banks Idle All RBs Idle (All RBs Idle) Mode Register Writing All Banks Idle All RBs Idle NVM All RBs Idle Mode Register Reading Mode Register Reading MRR Mode Register Reading Mode Register Reading MRR (Bank(s) Active) (RB(s) Active) Mode Register Writing Bank(s) Active RB(s) Active MRW Not Allowed (RB(s) Active) Device Auto-Init MRW (RESET) Not Allowed (Resetting) Not Allowed All RBs Idle Not Allowed All RBs Idle Bank(s) Active RB(s) Active 5. The MRW Reset command brings the device to the Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence (step 3 in section 3.

One method for calculating the interval between ZQCS commands. given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the LPDDR2 is subject to in the application. tZQINIT. There is no required quiet time after the ZQ Reset command. This command is used to ensure RON accuracy to +/-30% when ZQCS and ZQCL are not used. a ZQ Calibration command may only be issued when the device is in Idle state with all banks precharged. ZQ Reset overlap is allowed. tZQRESET. There are four ZQ Calibration commands and related timings. This Initialization Calibration achieves a RON accuracy of +/-15%. then the interval between ZQCS commands is calculated as:  --------------------------------------------------------. and tZQCS. In this case. The ZQ Calibration command is used to calibrate the LPDDR2 ouput drivers (RON) over process. If multiple devices share a single ZQ Resistor. is illustrated.13. tZQCL is for long calibration. and temperature. and tZQCS is for short calibration. LPDDR2-S4 and LPDDR2-N devices support ZQ Calibration. In systems that share the ZQ resistor between devices. if TSens = 0. Tdriftrate = 1 oC / sec and  Vdriftrate = 15 mV / sec. ZQ shall be connected permanently to VDDCA. tZQCS. The ZQReset Command resets the RON calibration to a default accuracy of +/-30% across process.20% / mV.5% (ZQCorrection) of RON impedance error within tZQCS for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. only one device may be calibrating at any given time. temperature. voltage. 209-2E Page 135 5. the ZQ Long Calibration may be used to re-calibrate the system to a RON accuracy of +/-15%. If the ZQ resistor is absent from the system.75% / oC. tZQINIT corresponds to the initialization calibration. After initialization. tZQRESET for resetting ZQ setting to default. The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 and LPDDR2-N devices. the LPDDR2 device shall ignore ZQ calibration commands and the device will use the default calibration settings ( See “Output Driver DC Electrical Characteristics without ZQ Calibration” on page 179) . A ZQ Short Calibration may be used periodically to compensate for temperature and voltage drift in the system. No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT. After calibration is achieved. For LPDDR2-N devices. or tZQCL between the devices.= s      +      For LPDDR2-S4 devices. tZQCL. One ZQCS command can effectively correct a minimum of 1. LPDDR2-S2 devices do not support ZQ Calibration and the ZQ Calibration command shall be ignored by these devices. the controller must not allow overlap of tZQINIT. VSens = 0. tZQCL. and voltage.4 Mode Register Write ZQ Calibration Command The MRW command is also used to initiate the ZQ Calibration command. The interval could be defined by the following formula: ZQCorrection ---------------------------------------------------------------------------------------------------------------- TSens  Tdriftrate  +  VSens  Vdriftrate  where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage sensitivities. tZQCS). the LPDDR2 device shall disable the ZQ ball’s current consumption path to reduce power. For example. a ZQ Calibration command may only be issued when the device is in the Idle or Active states. See Mode Register 10 on page 40 for description on the command codes for the different ZQ Calibration commands.JEDEC Standard No. The quiet time on the LPDDR2 data bus helps to accurately calibrate RON.

13. 209-2E Page 136 5. No command (other than Nop) is allowed during this period.JEDEC Standard No. No command (other than Nop) is allowed during this period. NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process. NOTE 2: CKE must be continuously registered HIGH during the calibration period. NOTE 3: All devices connected to the DQ bus should be high impedance during the calibration process. All devices connected to the DQ bus should be high impedance during the calibration process.4 Mode Register Write ZQ Calibration Command (cont’d) T0 CK_t / CK_c T1 T2 T3 T4 T5 Tx Tx + 1 Tx + 2 CA0-9 [Cmd] MR Addr MR Data MRW tZQINIT ANY CMD not allowed Figure 87 — ZQ Calibration Initialization timing example NOTE 1: The ZQ Calibration Initialization period is tZQINIT. T0 CK_t / CK_c T1 T2 T3 T4 T5 Tx Tx + 1 Tx + 2 CA0-9 [Cmd] MR Addr MR Data MRW tZQCL ANY CMD not allowed NOTE 1 NOTE 2 NOTE 3 Figure 89 — ZQ Calibration Long timing example The ZQ Calibration Long period is tZQCL. CKE must be continuously registered HIGH during the calibration period. T0 CK_t / CK_c T1 T2 T3 T4 T5 Tx Tx + 1 Tx + 2 CA0-9 [Cmd] MR Addr MR Data MRW tZQCS ANY CMD not allowed Figure 88 — ZQ Calibration Short timing example NOTE 1: The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period. . NOTE 2: CKE must be continuously registered HIGH during the calibration period.

5.1% tolerance external resistor must be connected between the ZQ pin and ground. No command (other than Nop) is allowed during this peri CKE must be continuously registered HIGH during the calibration period. The total capacitive loading on the ZQ pin must be limited ( See “Input/output capacitance” on page 182).13.JEDEC Standard No.4 Mode Register Write ZQ Calibration Command (cont’d) T0 CK_t / CK_c T1 T2 T3 T4 T5 Tx Tx + 1 Tx + 2 CA0-9 [Cmd] MR Addr MR Data MRW tZQRESET ANY CMD not allowed NOTE 1 NOTE 2 NOTE 3 Figure 90 — ZQ Calibration Reset timing example The ZQ Calibration Reset period is tZQRESET. and Capacitive Loading To use the ZQ Calibration function.4. Tolerance. . All devices connected to the DQ bus should be high impedance during the calibration process.1 ZQ External Resistor Value. a 240 Ohm +/.13. 209-2E Page 137 5. A single resistor can be used for each LPDDR2 device or one resistor can be shared between multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap.

or refresh is in progress. this mode is referred to as idle power-down. this mode is referred to as active power-down. or write operations are in progress. If VDDQ is turned off. autoprecharge.JEDEC Standard No. VDDQ may be turned off during power down. VREF must be maintained at a valid level during power down. 209-2E Page 138 5. as no refresh operations are performed in power-down mode. executable command can be applied with power-down exit latency. CKE LOW must be maintained until tCKE has been satisfied. if power-down occurs when all banks are idle. CKE is allowed to go LOW while any of other operations such as row activation. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register. if power-down occurs when all row buffers are idle. provided that upon exiting power-down. . power-down is synchronously entered when CKE is registered LOW at the rising edge of clock. CKE must be registered HIGH in the previous clock cycle. For LPDDR2 NVM. Power-down exit latency is defined in the timing parameter table of this standard. the clock is stable and within specified limits for a minimum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. CKE HIGH must be maintained until tCKE has been satisfied. if power-down occurs when any row buffer is in the active state. this mode is referred to as idle power-down. A valid. power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the rising edge of clock.14 Power-down For LPDDR2 SDRAM. For LPDDR2 SDRAM. For LPDDR2 NVM. and CKE. The controller shall drive CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. Timing diagrams are shown in the following pages with details for entry into power down. For LPDDR2 SDRAM. but power-down IDD spec will not be applied until finishing those operations. this mode is referred to as active power-down. if power-down occurs when there is a row active in any bank. the maximum duration in power-down mode is only limited by the refresh requirements outlined in section “LPDDR2 SDRAM Refresh Requirements” on page 118. both VDDQ and VREFDQ must be within their respective min/max operating ranges ( See “Recommended DC Operating Conditions” on page 160). The power-down state is exited when CKE is registered HIGH. SDRAM 2 tCK (min) CK_c CK_t tIHCKE CKE tISCKE tIHCKE Input clock frequency may be changed or the input clock stopped during Power-Down tISCKE CS_n [CMD] Valid Enter PD NOP Exit PD NOP Valid Valid tCKE(min) Enter Power-Down mode Exit Power-Down mode tXP(min) tCKE(min) Figure 91 — LPDDR2-SX: Basic power down entry and exit timing diagram NOTE 1 Input clock frequency may be changed or the input clock stopped during power-down. CK_c. precharge. Entering power-down deactivates the input and output buffers. preactive. CKE must be maintained LOW while all other input signals are “Don’t Care”. read. In power-down mode. then VREFDQ must also be turned off. tXP after CKE goes HIGH. Prior to exiting power down. excluding CK_t.

With this pattern. NOTE 2 CS_n is “do not care” for entry into power-down for NVM.JEDEC Standard No. provided that upon exiting power-down.14 NVM Power-down (cont’d) 2 tCK (min) CK_c CK_t tIHCKE CKE tISCKE tIHCKE Input clock frequency may be changed or the input clock stopped during Power-Down tISCKE CS_n [CMD] Valid Enter PD NOP Exit PD NOP Valid Valid tCKE(min) Enter Power-Down mode Exit Power-Down mode tXP(min) tCKE(min) Figure 92 — LPDDR2-N: Basic power down entry and exit timing diagram NOTE 1 Input clock frequency may be changed or the input clock stopped during power-down. CK_c CK_t tCKE CKE tCKE tCKE tCKE Figure 93 — Example of CKE intensive environment SDRAM CK_c CK_t CKE tCKE tXP tCKE REF tCKE tXP REF tCKE [CMD] tREFI NOTE 1 The pattern shown above can repeat over a long period of time. the clock is stable and within specified limits for a minimum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. 209-2E Page 139 5. LPDDR2 SDRAM guarantees all AC and DC timing & voltage specifications with temperature and voltage drift Figure 94 — REF to REF timing with CKE intensive environment for LPDDR2 SDRAM .

209-2E Page 140 5.14 T0 CK_c CK_t [CMD] CKE DQ DQS_t DQS_c T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 RD Power-down (cont’d) T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Read operation starts with a read command and CKE should be kept HIGH until the end of burst operation. tISCKE Q Q Q Q Q Q Q Q Figure 96 — LPDDR2 SDRAM Read with autoprecharge to power-down entry NOTE 1 CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is registered.5 ns & tRAS min satisfied RL Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge [CMD] CKE DQ DQS_t DQS_c RDA BL=8 BL/2 with tRTP = 7.5 ns & tRAS min satisfied RL PRE CKE should be kept HIGH until the end of burst operation.JEDEC Standard No. . RL Q Q Q Q tISCKE [CMD] CKE DQ DQS_t DQS_c RD CKE should be kept HIGH until the end of burst operation. tISCKE Q Q Q Q CKE DQ DQS_t DQS_c T0 T1 T2 Tx BL/2 with tRTP = 7. RL Q Q Q Q Q Q Q Q tISCKE Figure 95 — Read to power-down entry NOTE 1 CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 clock cycles after the clock on which the Read command is registered. SDRAM T0 CK_c CK_t [CMD] T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 RDA BL=4 PRE Start internal precharge CKE should be kept HIGH until the end of burst operation.

JEDEC Standard No. NVM T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 CK_c CK_t [CMD] CKE DQ DQS_c DQS_t T0 T1 Tm Tm+1 Tm+2 Tm+3 WR BL=4 WL D D D D tWRA tISCKE Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 [CMD] CKE DQ DQS_c DQS_t WR BL=8 WL D D D D D D D D tWRA tISCKE Figure 98 — Write to power-down entry NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(tWRA/tCK) clock cycles after the clock on which the Write command is registered. . 209-2E Page 141 5.14 SDRAM Power-down (cont’d) T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 CK_c CK_t [CMD] CKE DQ DQS_t DQS_c T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 WR BL=4 WL D D D D tWR tISCKE [CMD] CKE DQ DQS_t DQS_c WR BL=8 WL D D D D D D D D tWR tISCKE Figure 97 — Write to power-down entry NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) clock cycles after the clock on which the Write command is registered.

JEDEC Standard No.14 SDRAM Power-down (cont’d) T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 CK_c CK_t [CMD] WRA BL=4 PRE Start Internal Precharge CKE DQ DQS_t DQS_c T0 CK_c CK_t [CMD] CKE T1 WL tISCKE D D D D tWR Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 WRA PRE Start Internal Precharge BL=8 DQ DQS_t DQS_c WL D D D D D D D D tWR tISCKE Figure 99 — LPDDR2-SX: Write with autoprecharge to power-down entry NOTE 1 CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the Write command is registered. SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK_c CK_t [CMD] CKE REF tIHCKE tISCKE NOTE 1 Figure 100 — LPDDR2-SX: Refresh command to power-down entry CKE may go LOW tIHCKE after the clock on which the Refresh command is registered. 209-2E Page 142 5. .

T0 CK_c CK_t [CMD] CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 PRE tIHCKE tISCKE Figure 102 — Preactive/Precharge/Precharge-all command to power-down entry NOTE 1 CKE may go LOW tIHCKE after the clock on which the Preactive/Precharge/Precharge-All command is registered. .JEDEC Standard No. RL Q Q Q Q tISCKE Figure 103 — Mode Register Read to power-down entry NOTE 1 CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK) + 4/2 + 1 clock cycles after the clock on which the Mode Register Read command is registered.14 Power-down (cont’d) T0 CK_c CK_t [CMD] CKE T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ACT tIHCKE tISCKE NOTE 1 Figure 101 — Activate command to power-down entry CKE may go LOW tIHCKE after the clock on which the Activate command is registered. 209-2E Page 143 5. T0 CK_c CK_t [CMD] CKE DQ DQS_t DQS_c T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 MRR Mode Register Read operation starts with a MRR command and CKE should be kept HIGH until the end of burst operation.

209-2E Page 144 5.14 Power-down (cont’d) T0 CK_c CK_t [CMD] MRW T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CKE can go to LOW tMRW after a Mode Register Write command CKE tMRW tISCKE NOTE 1 Figure 104 — MRW command to power-down entry CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is .JEDEC Standard No.

all input buffers except CKE. All power supplies must be within specified limits prior to exiting Deep Power-Down. The SDRAM must be fully re-initialized as described in the Power up initialization Sequence. NOTE 2 tINIT3.15 LPDDR2-SX: Deep Power-Down Deep Power-Down is entered when CKE is registered LOW with CS_n LOW. CKE must be held LOW. Vref must be within specified limits ( See “Recommended DC Operating Conditions” on page 160). . read. SDRAM Tc 2 tCK (min) CK_c CK_t tIHCKE Input clock frequency may be changed or the input clock stopped during Deep Power-Down tINIT3 = 200 us (min) CKE tISCKE tISCKE CS_n [CMD] NOP Enter DPD Nop Exit PD NOP RESET tRP tDPD Enter Deep Power-Down mode Exit Deep Power-Down mode Figure 105 — LPDDR2-SX: Deep power down entry and exit timing diagram NOTE 1 Initialization sequence may start at any time after Tc. and Tc refer to timings in the LPDDR2 initialization sequence. NOTE 3 Input clock frequency may be changed or the input clock stopped during deep power-down. During Deep Power-Down. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register. In Deep Power-Down mode. The contents of the SDRAM may be lost upon entry into Deep Power-Down mode. while meeting tISCKE with a stable clock input. and the power supply to internal circuitry may be disabled within the SDRAM. However prior to exiting Deep Power-Down. and Power-Off” on page 28. 209-2E Page 145 5. All banks must be in idle state with no activity on the data bus prior to entering the Deep Power Down mode.JEDEC Standard No. all output buffers. For more detail. The SDRAM is ready for normal operation after the initialization sequence. Initialization. or write operations are in progress. see “Power-up. VrefDQ and VrefCA may be at any level within minimum and maximum levels (see “Absolute Maximum DC Ratings” on page 159). the clock is stable and within specified limits for a minimum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade. and CA2 LOW at the rising edge of clock. CA0 HIGH. The Deep Power-Down state is exited when CKE is registered HIGH. CA1 HIGH. provided that upon exiting deep power-down.

) have been met prior to changing the frequency. or Mode Register Read commands must have executed to completion. • The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. • Refresh Requirements apply during clock frequency change. tWR. tRP) have been met prior to stopping the clock. • During clock stop.) have been met prior to stopping the clock. • The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. Write. • Refresh Requirements apply during clock frequency change. tWR. only REFab or REFpb commands may be executing. tWRA. additional MRW commands may be required to set the WR. • Any Activate. 209-2E Page 146 5. etc. . only REFab or REFpb commands may be executing. • Refresh Requirements apply during clock stop. • CS_n shall be held HIGH during clock clock stop. • During clock frequency change. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. • The related timing conditions (tRCD. Read. • During clock stop. Preactive.16 Input clock stop and frequency change LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions: • tCK(abs)min is met for each clock cycle. or Mode Register Read commands must have executed to completion. only REFab or REFpb commands may be executing. • Any Activate. Precharge. • Any Activate. additional MRW commands may be required to set the WR. • Refresh Requirements apply during clock stop. Preactive. tRP) have been met prior to changing the frequency. After the input clock frequency is changed. or Precharge commands have executed to completion prior to changing the frequency. • The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. tRP. Preactive. • The related timing conditions (tRCD. Precharge. • The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW. Read. After the input clock frequency is changed and CKE is held HIGH. LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions: • tCK(abs)min is met for each clock cycle. • The related timing conditions (tRCD. LPDDR2 devices support clock stop during CKE LOW under the following conditions: • CK_t is held LOW and CK_c is held HIGH during clock stop. • The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW. including any associated data bursts prior to stopping the clock. LPDDR2 devices support clock stop during CKE HIGH under the following conditions: • CK_t is held LOW and CK_c is held HIGH during clock stop. tMRW. Mode Register Write. Write. tRP. • Any Activate. tWRA. only REFab or REFpb commands may be executing. tMRW. tMRR. • CS_n shall be held HIGH during clock frequency change. including any associated data bursts prior to changing the frequency. RL etc. RL etc. • The related timing conditions (tRCD. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.JEDEC Standard No. • During clock frequency change. etc. tMRR. • The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. or Precharge commands have executed to completion prior to stopping the clock. Mode Register Write. Preactive.

2. a NOP command may be issued at clock cycle N. CS_n LOW and CA0. . CS_n HIGH at the clock rising edge N. CA1.JEDEC Standard No. The No Operation command will not terminate a previous operation that is still executing. the LPDDR2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue. such as a burst read or write cycle. Only when the CKE level is constant for clock cycle N-1 and clock cycle N. CA2 HIGH at the clock rising edge N.17 No Operation command The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted command between operations. 209-2E Page 147 5. 5. and after such an event. in order to guarantee proper operation. A NOP command has two possible encodings: 1.18 Truth tables Operation or timing that is not specified is illegal.

209-2E Page 148 5.4 H L C3 L C3 H R7/a12 R13/a13 R14/a14 BA0 C9 BA0 C9 BA0 X/a27 BA1 C10 BA1 C10 BA1 X/a28 BA2 C11 BA2 C11 BA2 X/a29 Write (bank) Write (RDB) H H X L Read (bank) Read (RDB) H H X L Precharge (pre bank. SREF. SREF. DPD (NOP) Maintain Power Down (NOP) L L L X H H H H X X X X X X X X NOP NOP H H X Maintain PD. DPD Exit Power Down X H H X X X .4 H AP3.1 Command Truth Table Table 60 — Command Truth Table SDR Command Pins SDRAM Command NVM Command CKE CK_t(n-1) CK_t(n) CS_N CA0 CA1 CA2 CA3 DDR CA pins (10) CA4 CA5 CA6 CA7 CA8 CA9 CK_t EDGE L MRW MRW H H X L MRR MRR H H X L H H X L MA6 L MA6 L L MA7 L MA7 L L OP0 L L OP1 H MA0 OP2 MA0 MA1 OP3 MA1 X MA2 OP4 MA2 MA3 OP5 MA3 MA4 OP6 MA4 MA5 OP7 MA5 Refresh (per bank)11 H L X X L Refresh (all bank) H H X L L H H X X Enter Self Refresh Enter Power Down H L X L X L L L H X X Activate (bank) Activate (row buffer) L H R8/a15 R9/a16 R10/a17 R11/a18 R12/a19 R2/a7 L C4 H C4 L X/a22 L R3/a8 RFU C5 RFU C5 H X/a23 L X R4/a9 RFU C6 RFU C6 AB/a30 X/a24 R5/a10 C1 C7 C1 C7 X/a31 X/a25 R6/a11 C2 C8 C2 C8 X/a32 X/a26 X BA0 BA1 BA2 H H X L R0/a5 R1/a6 H AP3.JEDEC Standard No. all bank) Preactive (RAB) H H X L X/a20 X/a21 H H BST BST H H X Enter Deep Power Down Enter Power Down H L X L X L H H L X X H H H X X NOP NOP H H X Maintain PD.18. DPD (NOP) Maintain Power Down (NOP) H L L X H L X X H Enter Power Down Enter Power Down L Exit PD. SREF.

BA1. BA2 (BA) determine which bank is to be operated upon. NOTE 12 The least-significant column address C0 is not transmitted on the CA bus. 209-2E Page 149 5. CA1. NOTE 8 CAxr refers to command/address bit “x” on the rising edge of clock. CA2. BA1.1 Command Truth Table (cont’d) Notes to Table 60 NOTE 1 All LPDDR2 commands are defined by states of CS_n. NOTE 4 AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the READ or WRITE command. Bank addresses BA0. CA0. .JEDEC Standard No.18. AP is do-not-care for NVM. Per Bank Refresh is only allowed in devices with 8 banks. NOTE 13 AB “high”during Precharge command indicates that all bank Precharge will occur. and CKE at the rising edge of the clock. and is implied to be zero. BA2 determine a row buffer. NOTE 10 NOTE 11 CS_n and CKE are sampled at the rising edge of clock. BA0. CA3. Bank Address is do-not-care. NOTE 2 For LPDDR2 SDRAM. In this case. For LPDDR2 NVM. NOTE 5 “X” means “H or L (but a defined logic level)” NOTE 6 Self refresh exit and Deep Power Down exit are asynchronous. NOTE 3 AP is significant only to SDRAM. NOTE 9 CAxf refers to command/address bit “x” on the falling edge of clock. NOTE 7 VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation.

NOTE 4 “Command n” is the command registered at clock edge N. 9 Idle Power Down L 6. 10 Bank(s) Active H L H NOP Active Power Down H L H NOP Idle Power Down All Banks Idle H L L Enter Self-Refresh Self Refresh H L L Deep Power Down Deep Power Down Resetting H L H NOP Resetting Power Down H H Refer to the Command Truth Table NOTE 1 “CKEn” is the logic state of CKE at clock rising edge n.JEDEC Standard No. 9. NOTE 7 Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued. NOTE 12 Upon exiting Resetting Power Down. 209-2E Page 150 5. the device will return to the Idle state if tINIT5 has expired. NOTE 3 “Current state” is the state of the LPDDR2 device immediately prior to clock edge n. NOTE 9 The clock must toggle at least twice during the tXP period. NOTE 10 The clock must toggle at least twice during the tXSR time. they clarify the device behavior and the applied restrictions when considering the actual state of all the Banks. and “Operation n” is a result of “Command n”. . NOTE 8 The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description. NOTE 6 Power Down exit time (tXP) should elapse before a command other than NOP is issued. NOTE 5 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. NOTE 2 “CS_n” is the logic state of CS_n at the clock rising edge n. Table 61 — LPDDR2-SX: CKE Table *1 *1 Device Current State*3 CKEn-1 CKEn CS_n*2 Command n*4 X NOP X NOP Operation n*4 Maintain Active Power Down Exit Active Power Down Maintain Idle Power Down Exit Idle Power Down Maintain Resetting Power Down Device Next State Active Power Down Active Idle Power Down Idle Resetting Power Down Idle or Resetting Notes Active Power Down L L L L H L H X H X H 6. 9 L Resetting Power Down L L X X H H NOP Exit Resetting Power Down 6. 12 L Deep Power Down L L Self Refresh L L X X Maintain Deep Power Down Exit Deep Power Down Maintain Self Refresh Exit Self Refresh Enter Active Power Down Enter Idle Power Down Enter Self Refresh Enter Deep Power Down Enter Resetting Power Down Deep Power Down H L H H X H NOP X NOP Power On Self Refresh Idle 8 7. NOTE 11 'X’ means ‘Don’t care’. “CKEn-1” was the state of CKE at the previous clock edge.19 LPDDR2-SDRAM Truth Tables The truth tables provide complementary information to the state diagram.

and start read burst Select column. NOTE 4 The following states must not be interrupted by a command issued to the same bank. No data bursts / accesses and no register accessesare in progress.  Row Activating: starts with registration of an Activate command and ends when tRCD is met. Allowable commands to the other banks are determined by its current state and Table 2. with Auto Precharge disabled. and start read burst Write burst terminate Begin Device Auto-Initialization Read value from Mode Register Next State Current State Active Refreshing (Per Bank) Refreshing(All Bank) MR Writing Idle MR Reading Resetting Precharging Reading Writing Active MR Reading Precharging Reading Writing Active Writing Reading Active Resetting Resetting MR Reading NOTES 6 7 7 Idle MRW MRR Reset Precharge Read 7. 11 10. and has not yet terminated or been terminated. and after tXSR or tXP has been met if the previous state was Power Down. 209-2E Page 151 5. the bank will be in the ‘Active’ state.Command to Bank n Current State Any Command NOP ACTIVATE Refresh (Per Bank) Refresh (All Bank) Operation Continue previous operation Select and activate row Begin to refresh Begin to refresh Load value to Mode Register Read value from Mode Register Begin Device Auto-Initialization Deactivate row in bank or banks Select column. and start write burst Read value from Mode Register Deactivate row in bank or banks Select column. . Once tRP has been met. and tRCD has been met. and start new read burst Select column. the bank will be in the idle state. and start new write burst Select column. and has not yet terminated or been terminated. Once tRCD is met. 14 13 7. NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. 11. Writing: A Write burst has been initiated. the bank will be in the idle state. 9 Reading Write BST Write Writing Read BST Power On Resetting Reset MRR NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH. Reading: A Read burst has been initiated.   Precharging: starts with the registration of a Precharge command and ends when tRP is met. and tRP has been met. 12 13 10. 8 9.19 LPDDR2-SDRAM Truth Tables (cont’d) Table 62 — Current State Bank n . NOTE 3 Current State Definitions: Idle: The bank or banks have been precharged. with Auto Precharge disabled. 11 10.JEDEC Standard No. the bank will be in the idle state. and start write burst Read burst terminate Select column.  Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Active: A row in the bank has been activated. Once tRP is met. 15 Row Active Write MRR Precharge Read 9 10. 11. and according to Table 3.  Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when tRP has been met. NOTE 2 All states and sequences not shown are illegal or reserved. Once tRP is met.

NOTE 9 This command may or may not be bank specific. NOP commands must be applied to each positive clock edge during these states. 209-2E Page 152 5. NOTE 7 NOTE 8 Not bank-specific. regardless of bank. Not bank-specific reset command is achieved through Mode Register Write command. Once tMRR has been met. the bank will be in the Resetting state. Once tMRR has been met. Once tRFCpb is met. .  Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. NOTE 15 If a Precharge command is issued to a bank in the Idle state.  Refreshing (All Bank): starts with registration of an Refresh (All Bank) command and ends when tRFCab is met. the bank will be in the Active state. tRP shall still apply. otherwise. Once tMRR has been met.  Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. the bank will be in the Idle state. requires that the bank is idle and no bursts are in progress. Once tRP is met.JEDEC Standard No. NOTE 14 A Read command may be applied after the completion of the Write burst. they must be in a valid state for precharging. Burst Terminate (BST) command affects the most recent read/write burst started by the most recent Read/Write command. NOTE 13 Not bank-specific. NOTE 6 Bank-specific. requires that all banks are idle and no bursts are in progress. a BST must be used to end the Write prior to asserting a Read command.  MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. If all banks are being precharged. NOTE 11 The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.  Refreshing (Per Bank): starts with registration of an Refresh (Per Bank) command and ends when tRFCpb is met. NOTE 12 A Write command may be applied after the completion of the Read burst.  Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. the bank will be in the idle state. the device will be in an ‘all banks idle’ state. the bank will be in the Idle state. Once tRFCab is met. the bank will be in an ‘idle’ state.  Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. a BST must be used to end the Read prior to asserting a Write command. Once tMRW has been met. NOTE 10 A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled.19 LPDDR2-SDRAM Truth Tables (cont’d) Notes (cont’d) to Table 62 NOTE 5 The following states must not be interrupted by any executable command. otherwise.

  Writing: a Write burst has been initiated.  Reading: a Read burst has been initiated. Active. and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column. 15 8. 209-2E Page 153 5. with Auto Precharge disabled. and tRP has been met. 14 Row Activating. and start read burst from Bank m Select column. and has not yet terminated or been terminated. No data bursts/accesses and no register accesses are in progress. with Auto Precharge disabled. and start read burst from Bank m Select column. Self-Refresh. and has not yet terminated or been terminated.Command to Bank m Current State of Command for Bank n Bank m Any Idle Operation Continue previous operation Any command allowed to Bank m Select and activate row in Bank m Select column. 16 8. and start read burst from Bank m Select column. .JEDEC Standard No.  Active: a row in the bank has been activated. and start write burst to Bank m Deactivate row in bank or banks Read value from Mode Register Read or Write burst terminate an ongoing Read/Write from/to Bank m Select column. and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column. NOTE 3 Current State Definitions:  Idle: the bank has been precharged. NOTE 4 Refresh. it applies to the bank represented by the current state only. NOTE 5 A Burst Terminate (BST) command cannot be issued to another bank. and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Begin Device Auto-Initialization Read value from Mode Register Next State for Bank m Current State of Bank m Active Reading Writing Precharging Idle MR Reading or Active MR Reading Active Reading Writing Active Precharging Reading Writing Active Precharging Reading Writing Active Precharging Reading Writing Active Precharging Resetting Resetting MR Reading NOTES NOP Any Activate Read 18 7 8 8 9 10. and start read burst from Bank m Select column. 15 Reading with Autoprecharge Write Activate Precharge Read 9 8. 15 Writing with Autoprecharge Write Activate Precharge 9 12. 16 8 Writing (Autoprecharge disabled) Write Activate Precharge Read 9 8. and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column. 17 Power On Resetting Reset MRR NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH. 15. NOTE 2 All states and sequences not shown are illegal or reserved. and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 11. or Precharging Write Precharge MRR BST Read Reading (Autoprecharge disabled) Write Activate Precharge Read 9 8. and Mode Register Write commands may only be issued when all bank are idle. and start read burst from Bank m Select column. 13 18 8 8.19 LPDDR2-SDRAM Truth Tables (cont’d) Table 63 — Current State Bank n . and tRCD has been met. 14.

Once tMRR has been met. the next state may be Active and Precharge dependent upon tRCD and tRP respectively. Once tMRR has been met. they must be in a valid state for precharging. NOTE 17 Reset command is achieved through Mode Register Write command. NOTE 9 This command may or may not be bank specific. 209-2E Page 154 5. otherwise a BST must be issued to end the Read prior to asserting a Write command. NOTE 14 A Write command may be applied after the completion of the Read burst.  Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. NOP commands must be applied during each clock cycle while in these states:  Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. if Bank m is in the Row Activating state and Precharging. or Active). NOTE 7 tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m.JEDEC Standard No.  Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. . the bank will be in the Active state. the bank will be in the Idle state. requires that all banks are idle and no bursts are in progress. If all banks are being precharged. Row Activating. the bank will be in the Idle state. Therefore. the bank will be in the Resetting state.  MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRR has been met.) NOTE 11 MRR is allowed during the Precharging state. The reader shall note that the state may be in transition when a MRR is issued. (Precharging starts with registration of a Precharge command and ends when tRP is met. NOTE 8 Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto Precharge disabled. NOTE 10 MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends when tRCD is met. NOTE 12 Not bank-specific. Once tMRW has been met. NOTE 16 A Read command may be applied after the completion of the Write burst. Precharging. NOTE 13 The next state for Bank m depends on the current state of Bank m (Idle.19 LPDDR2-SDRAM Truth Tables (cont’d) Notes (cont’d) to Table 63 NOTE 6 The following states must not be interrupted by any executable command. a BST must be issued to end the Write prior to asserting a Read command. NOTE 18 BST is allowed only if a Read or Write burst is ongoing. otherwise. NOTE 15 Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in Table 51 on page 115 and Table 52 on page 116 are followed.

209-2E Page 155 5. NOTE 3 “Row Buffer Current State” is the state of a particular Row Buffer immediately prior to clock cycle n. the device goes into the Active Power Down state. For additional details on entering and exiting power down.JEDEC Standard No.8 All RBj RBk L H H Idle Active Idle Idle 7. unless explicitly described elsewhere in this standard. NOTE 9 Clock frequency may be reduced. Mode Register Read. NOTE 10 Power Down may not be entered while Read.11 L H H EXIT POWER DOWN EXIT POWER DOWN EXIT POWER DOWN Resetting 7. CKE shall be held low to maintain the Power Down state. If the Enter Power Down command is issued when all Row Buffers are Idle the device goes into the Idle Power Down state. . Table 64 on page 155 describes Power Down transitions for a LPDDR2-NVM.11 All L L X X Resetting Maintain Resetting Power Resetting Power Down Power Down Down Maintain Idle Idle Power Down Power Down Active Maintain Active Power Down Power Down Idle Power Down Exit Resetting Power Down Exit Idle Power Down Resetting Idle Power Down Active Power Down 9 All L L X X 9 RBj RBk All L L X X 9. NOTE 4 “Device Current State” is the state of LPDDR2-NVM immediately prior to clock cycle n. NOTE 5 “Command n” is the command registered at clock cycle n. please refer to section “Power-down” on page 138. if the Enter Power Down command is issued when one or more Row Buffers are Active.8. or Preactive operations are in progress. Write. during ‘Idle Power Down’.8 L H H Exit Active Power Down Not Power Down 7. However. or ‘Active Power Down’ states. and “Operation n” is the result of “Command n”. they clarify the device behavior and the applied restrictions when considering the actual state of all the Row Buffers. When CKE is driven high with CS_n high the device exits the Power Down State. NOTE 11 RBj and RBk refer to different Row Buffer pairs. “CKEn-1” was the state of CKE at the previous clock rising edge. ‘Resetting Power Down’.20 LPDDR2-N: Truth Tables The truth tables provide complementary information to the state diagram. NOTE 6 All states and sequences not shown are illegal or reserved. A Power Down command shall be followed by a NOP command. NOTE 2 “CS_n” is the logic state of CS_n at clock rising edge n. (j) and (k).11 NOTE 1 “CKEn” is the logic state of CKE at clock rising edge n. Table 64 — LPDDR2-N: CKE Table Current State*3 Current State*4 All Resetting Resetting Row Buffer Device Row Buffer Device Notes CKEn-1*1 CKEn*1 CS_n*2 Command n*5 Operation n*5 Next State Next State H L X ENTER POWER DOWN ENTER POWER DOWN Resetting Enter in Resetting Power Resetting Power Down Power Down Down Enter in Idle Idle Power Down Power Down Active Enter in Active Power Down Power Down Idle Power Down Idle Power Down Active Power Down 10 All Idle Idle H L X 10 RBj RBk Active Idle Resetting Power Down Idle Power Down Active Power Down Idle Power Down Resetting Power Down Idle Power Down Active Power Down Idle Power Down Not Power Down Resetting Power Down Idle Power Down Active Power Down Resetting Power Down Idle Power Down Active Power Down H L X ENTER POWER DOWN 10. and/or the clock may be stopped. NOTE 8 The clock must toggle at least twice during the tXP period. NOTE 7 Power Down exit time (tXP) should elapse before a command other than NOP is issued. Mode Register Write.

Once tMRR has been met. the Row Buffer will be in the Active state. NOTE 2 The following states must not be interrupted by a command issued to the same Row Buffer.20 LPDDR2-N: Truth Tables (cont’d) Table 65 on page 156 shows the transition from the current state to the next state of a given Row Buffer due to command issued on the same Row Buffer. NOTE 5 Reset command is achieved through MODE REG. Once tMRR has been met. . and start write burst Load value to Mode Register Read value from Mode Register Begin Device Auto-Initialization Select RDB & column. Only allowed commands are shown. NOTE 4 BURST TERMINATE command affects the read/write burst started by the most recent READ/WRITE command.  Row Activating: starts with registration of an Activate command and ends when tRCD is met. WRITE command. Once tRCD is met. The Row Buffer will return to the Idle state once tRP is satisfied and any ongoing Read or Write operation is complete. NOP commands or allowable commands to other Row Buffer should be issued on any clock cycle occurring during these states. NOTE 3 The following states must not be interrupted by any executable command. and activate RDB Select RDB & column. Table 65 — Current State Row Buffer n . and after tXP has been met if the previous state was Power Down. and start new write burst Begin Device Auto-Initialization Read value from Mode Register Next State Current State Preactivating Active MR Writing Idle MR Reading Resetting Preactivating Active Reading Writing MR Writing Active MR Reading Resetting Reading Active Active Writing Resetting Resetting MR Reading Notes Idle MRW MRR Reset PREACTIVE ACTIVATE READ 6 7 Active WRITE MRW MRR Reset READ 6 Reading BST BST Writing 4 4 WRITE Power On Resetting Reset MRR 6 NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH.JEDEC Standard No. and start read burst Select RDB & column. Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. 209-2E Page 156 5. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met. and start new read burst Read burst terminate Write burst terminate Select RDB & column. NOTE 6 tRC must be met between Activate command to Row Buffer n and subsequent Activate command to Row Buffer n. Reset command sets all Row Address Buffers to 0x0000. the Row Buffer will be in the Idle state.Command to Row Buffer n Current State Any Command NOP PREACTIVE ACTIVATE Operation Continue previous operation Load RAB Select RAB & RDB. and activate RDB Load value to Mode Register Read value from Mode Register Begin Device Auto-Initialization Load RAB Select RAB & RDB. all other commands are illegal or reserved for the given Row Buffer state. Once tMRR has been met. the Row Buffer will be in the Idle state. NOP commands must be applied to each clock cycle during these states. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Preactivating: starts with the registration of a Preactive command and ends when tRP is met. the Row Buffer will be in the Row Active state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. For the state definition refer to section LPDDR2-NVM state diagram. the Row Buffer will be in the Resetting state.

unless explicitly described elsewhere in this standard. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. . the Row Buffer will be in the Active state. Table 66 — Current State Row Buffer n . Once tMRW has been met. and start read burst from RDBm Select RABm & RDBm. Once tMRR has been met. NOTE 9 BST is allowed only if a Read or Write burst is ongoing. Note that the state may be in transition when a MRR is issued. Row Activating. NOTE 2 The following states must not be interrupted by any executable command. and start write burst to RDBm Select RABm & RDBm. (Preactivating starts with registration of an Preactivate command and ends when tRP is met. NOTE 6 MRR is allowed during the Row Activating state and MRW is prohibited during the Row Activating state. and activate row in RDB m Load RABm Begin Device Auto-Initialization Read value from Mode Register Next State for Row Buffer m Current State of Row Buffer m Active Reading Active Writing Preactivating MR Writing Idle MR Reading or Active MR Reading Resetting Reading Active Preactivating Writing Active Preactivating Resetting Resetting MR Reading Notes NOP Any ACTIVATE READ BST 9 5 3.) NOTE 8 The next state for Row Buffer m depends on the current state of Row Buffer m (Idle.) NOTE 7 MRR is allowed during the Preactivating state and MRW is prohibited during the Preactivating state. the Row Buffer will be in the Idle state. Once tMRR has been met. Table 66 on page 157 shows allowed commands to another Row Buffer (m). 7 6.JEDEC Standard No. NOTE 3 BURST TERMINATE command affects the read/write burst started by the most recent READ/WRITE command. (Row Activating starts with registration of an Activate command and ends when tRCD is met. For the state definition refer to section LPDDR2-NVM state diagram. or Preactivating WRITE PREACTIVE MRW MRR Reset READ 6. 8 4 Reading ACTIVATE PREACTIVE WRITE Writing ACTIVATE PREACTIVE Power On Resetting Reset MRR 4 NOTE 1 The table applies when both CKEn-1 and CKEn are HIGH. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. 209-2E Page 157 5. Reset command sets all Row Address Buffers to 0x0000. NOP commands must be applied during each clock cycle while in these states:  Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. and after tXP has been met if the previous state was Power Down. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. NOTE 4 Reset command is achieved through MODE REGISTER WRITE command. and start write burst to RDBm Load RABm Load value to Mode Register Read value from Mode Register Begin Device Auto-Initialization Select RDBm & column. all Row Buffers will be in the Idle state. and start read burst from RDBm Read or Write burst terminate an ongoing Read/Write from/to Row Buffer m Select RDBm & column. or Active). Active. 7. NOTE 5 tRRD must be met between Activate command to Row Buffer n and a subsequent Activate command to Row Buffer m. Therefore. the next state may be Active dependent upon tRCD. the Row Buffer will be in the Resetting state.20 LPDDR2-N: Truth Tables (cont’d) Given the state of a Row Buffer (n). 9 Row Activating. all other commands are illegal or reserved for the given Row Buffer state.Command to Row Buffer m Current State of Command for Row Buffer n Row Buffer m Any Idle Operation Continue previous operation Any command allowed to Row Buffer m Select RABm & RDBm. and the corresponding next state. Once tMRR has been met. if Row Buffer m is in the Row Activating state. Only allowed commands are shown. and activate row in RDB m Load RABm Select RDBm & column. and activate row in RDB m Select RDBm & column.

209-2E Page 158 5.JEDEC Standard No.21 Data Mask Truth Table Table 67 on page 158 provides the data mask truth table. Table 67 — DM truth table Name (Functional) Write enable Write inhibit DM L H DQs Valid X Note 1 1 NOTE 1 Used to mask write data. . provided coincident with the corresponding data.

6 1. NOTE 6 Refer to vendor datasheet for VACC absolute maximum value.4 -0. NOTE 5 Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. Initialization. VREFCA may be  VDDCA provided that VREFCA  300mV. This is a stress rating only. please refer to JESD51-2 standard.6 V V V V 6 2 2. 209-2E Page 159 6 6. Exposure to absolute maximum rating conditions for extended periods may affect reliability.3 Min Max Units Notes -0.6 x VDDCA. and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.6 1.35V) VDD2 supply voltage relative to VSS VDD2 (1. however.4 TSTG -55 C 5 NOTE 1 Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. VREFDQ may be  VDDQ provided that VREFDQ  300mV. however.6 x VDDQ.3 1. .4 1.1 Absolute Maximum Ratings Absolute Maximum DC Ratings Stresses greater than those listed may cause permanent damage to the device. and Power-Off” on page 28 for relationships between power supplies.2V) VDDCA supply voltage relative to VSSCA VDDQ supply voltage relative to VSSQ VDDCA VDDQ VACC (9 V) VACC supply voltage relative to VSS VACC (VAP) Voltage on any ball relative to VSS Storage Temperature -0. For the measurement conditions.6 125 V V -0.4 7 1. X X NOTE 4 VREFCA  0.4 11.4 -0. Table 68 — Absolute Maximum DC Ratings Parameter VDD1 supply voltage relative to VSS Symbol VDD1 VDD2 (1.JEDEC Standard No.4 -0. Exposure to absolute maximum rating conditions for extended periods may affect reliability NOTE 2 See “Power-Ramp” section in “Power-up. NOTE 3 X X VREFDQ  0.4 2.8 V V 2 2 -0.5 VIN. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. VOUT -0.4 2.

.2 1. VDD1 uses significantly less current than VDD2 N/A(Not available) Table 70 — Recommended LPDDR2-S4 DC Operating Conditions Symbol VDD1 VDD2 VDDCA VDDQ LPDDR2-S4A Min 1.20 1.5 VAP-0.2 0.4 1.14 Typ 1. the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue.14 1. NOTE 2 The maximum time for the device to be in the Acceleration Power range for VACC is 80 hours.4 V VAP+0.95 1.14 1.4 1. program and erase functions are disabled and will not be executed.95 9.14 1.70 N/A 1.0 1.35 1.7 N/A 1. 7.70 1.3 V.3 1. NOTE 3 Refer to vendor datasheet for VACC acceleration power supply value and VAP value.7 8.20 Min 1.20 1.4 1.28 1.95 1.4 V NOTE 1 When VACC is in the lockout voltage range.14 1.4 1.3 1.14 1.5 NVMem Core Power Core Power 2 Input Buffer Power I/O Buffer Power Lockout Voltage Normal Operation Acceleration Power Unit V V V V V V V VACC(3) 8.3 1.3 1.14 1. in order to guarantee proper operation.7 LPDDR2-N-B Max 1.JEDEC Standard No.14 LPDDR2-S2B Max 1.2 0.42 1.20 1.4 V Typ 1.2 1.95 N/A 1.3 1.3 1.80 1.14 LPDDR2-S4B Max 1.20 1.14 -0.20 1.8 N/A 1.3 DRAM Core Power1 Core Power2 Input Buffer Power I/O Buffer Power Unit V V V V NOTE 1 When VDD2 is used.80 N/A 1.95 N/A 1.3 Typ 1.2 1.80 1. VAP shall not be less than 3.3 1.70 1.20 Max 1.5 VAP-0.14 1.4 V VAP+0.95 1.3 0.3 1.14 1.20 Min 1. 209-2E Page 160 7 AC & DC Operating Conditions Operation or timing that is not specified is illegal.8 9 VAP Min 1.8 1.70 1.3 0.95 9.80 1.3 Typ 1.14 Typ 1.3 DRAM Core Power1 Core Power2 Input Buffer Power I/O Buffer Power Unit V V V V NOTE 1 VDD1 uses significantly less power than VDD2 Table 71 — Recommended LPDDR2-N DC Operating Conditions Symbol VDD1 VDD2 VDDCA VDDQ Voltage LPDDR2-N-A Min 1.1 Recommended DC Operating Conditions Table 69 — Recommended LPDDR2-S2 DC Operating Conditions Symbol VDD1 VDD2 VDDCA VDDQ LPDDR2-S2A Min 1. The lockout voltage range provides hardware program and erase protection for the LPDDR2-NVM array.20 1.3 1.95 1. and after such an event.14 -0.14 1.0 1.5 Typ 1.7 1.20 Max 1.8 9 VAP Max 1.

the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification.3 Operating Temperature Range Table 73 — Operating Temperature Range Parameter/Condition Standard TOPER Extended 85 105 Symbol Min -25 Max 85 Unit oC o C NOTE 1 Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. CKE. some derating is neccessary to operate in this range. NOTE 3 Either the device case temperature rating or the temperature sensor ( See “Temperature Sensor” on page 129) may be used to set an appropriate refresh rate (SDRAM). NOTE 2 Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range between 85 oC and 105 oC case temperature. TCASE may be above 85 oC when the temperature sensor indicates a temperature of less than 85 oC. For LPDDR2 devices. The leakage current on VREFCA and VREFDQ pins should be minimal. 209-2E Page 161 7. 7. . determine the need for AC timing de-rating (SDRAM and NVM) and/or monitor the operating temperature (SDRAM and NVM). When using the temperature sensor. please refer to JESD51-2 standard. See MR4 on page 40. CS_n. CK_t. CK_c IL -2 2 uA 2 Symbol Min Max Unit Notes X X Any input 0V  VIN  VDDCA (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 (All other pins not under test = 0V) IVREF -1 1 uA 1 NOTE 1 The minimum limit requirement is for testing purposes.2 Input Leakage Current Table 72 — Input Leakage Current Parameter/Condition Input Leakage current For CA.JEDEC Standard No. For example. NOTE 2 Although DM is for input only. the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For the measurement conditions.

130 VSSCA Vref .49 * VDDQ 0. DM inputs NOTE 1 For DQ input only pins.1 8.8 * VDDCA Note 1 Max Note 1 0.200 VDDQ DC input logic high V VILDQ(DC) VSSQ Vref . VDDCA/2 +/.51 * VDDCA NOTE 1 For CA and CS_n input only pins. .0.0.200 VDDCA Vref . 5 1 1 3. +/.12 mV).3 See “Overshoot and Undershoot Specifications” on page 174 AC and DC Input Levels for Single-Ended Data Signals Table 76 — Single-Ended AC and DC Input Levels for DQ and DM LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Min Symbol VIHDQ(AC) Parameter Max Min Max Unit Notes 1. 209-2E Page 162 8 8. NOTE 2 See “Overshoot and Undershoot Specifications” on page 174 NOTE 3 The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than +/-1% VDDQ (for reference: approx.0. 2 1 1 3.0.49 * VDDCA Symbol VIHCA(AC) VILCA(AC) VIHCA(DC) VILCA(DC) VRefCA(DC) Max Min Max Unit Notes V V V V V 1.0. NOTE 2 See “Overshoot and Undershoot Specifications” on page 174 NOTE 3 The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1% VDDCA (for reference: approx.130 VSSCA 0.1 AC and DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended CA and CS_n Signals Table 74 — Single-Ended AC and DC Input Levels for CA and CS_n Inputs Parameter AC input logic high AC input logic low DC input logic high DC input logic low Reference Voltage for CA and CS_n inputs LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Min Vref + 0. 5 1.51 * VDDQ 0.300 AC input logic low V VIHDQ(DC) Vref + 0.220 Note 2 Vref + 0.51 * VDDCA 0.300 VDDCA Vref + 0.49 * VDDCA 0. 4 Vref + 0.220 Note 2 Vref + 0.12 mV).130 VSSQ Vref .12 mV.51 * VDDQ Reference Voltage for V DQ. 2 1. 2. 4 Note 2 Vref + 0.1. Vref = VrefCA(DC). Vref = VrefDQ(DC).1.49 * VDDQ 0.0.220 Note 2 Vref . 8.12 mV.200 0.300 Note 2 AC input logic high V VILDQ(AC) Note 2 Vref .0.300 Note 2 Vref .130 VDDQ Vref + 0.2 AC and DC Input Levels for CKE Table 75 — Single-Ended AC and DC Input Levels for CKE Symbol VIHCKE VILCKE Parameter CKE Input High Level CKE Input Low Level Min 0. +/.200 DC input logic low V VRefDQ(DC) 0.1. VDDQ/2 +/. 2.JEDEC Standard No. NOTE 4 For reference: approx.2 * VDDCA Unit Notes V V 1 1 Note 1 8.220 Note 2 Vref .0. NOTE 4 For reference: approx.

VIH(DC). VDD stands for VDDCA for VRefCA and VDDQ for VRefDQ.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC input levels from instantaneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs Table on page 162 and Single-Ended AC and DC Input Levels for DQ and DM on page 171. : voltage VDD VRef ac-noise VRef(DC) VRef(t) VRef(DC)max VDD/2 VRef(DC)min VSS time Figure 106 — Illustration of VRef(DC) tolerance and VRef ac-noise limits The voltage levels for setup and hold time measurements VIH(AC). 1 sec).2 Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in Figure 106. system timing and voltage budgets need to account for VREF deviations outside of this range. (VRef stands for VRefCA and VRefDQ likewise). as defined in Figure 106. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in LPDDR2 timings and their associated deratings. .44 x VDDQ (or VDDCA) and 0. VRef(DC) is the linear average of VRef(t) over a very long period of time (e. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA also over a very long period of time (e. VIL(AC) and VIL(DC) are dependent on VRef. It shows a valid reference voltage VRef(t) as a function of time. Vref(t) cannot track noise on VDDQ or VDDCA if this would send Vref outside these specifications. 209-2E Page 163 8.g. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/. This average has to meet the min/max requirements in Table 74. Devices will function correctly with appropriate timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.g. “VRef “ shall be understood as VRef(DC). This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured.) Therefore. This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise.1% VDD.JEDEC Standard No.

JEDEC Standard No. 209-2E Page 164 8.3 Input Signal
VIL and VIH Levels With Ringback 1.550V VDD + 0.35V

1.200V

VDD

Minimum VIL and VIH Levels 0.820V VIH(AC) 0.820V VIH(AC)

0.730V

VIH(DC)

0.730V

VIH(DC)

0.624V 0.612V 0.600V 0.588V 0.576V

0.624V 0.612V 0.600V 0.588V 0.576V

VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise

0.470V

VIL(DC)

0.470V

VIL(DC)

0.380V

VIL(AC)

0.380V

VIL(AC)

0.000V

VSS

-0.350V

VSS - 0.35V

Figure 107 — LPDDR2-466 to LPDDR2-1066 Input Signal NOTE 1 Numbers reflect nominal values. NOTE 2 For CA0-9, CK_t, CK_c,and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c, VDD stands for VDDQ. NOTE 3 For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c, VSS stands for VSSQ.

JEDEC Standard No. 209-2E Page 165 8.3 Input Signal (cont’d)

VIL and VIH Levels With Ringback 1.550V VDD + 0.35V

1.200V

VDD

Minimum VIL and VIH Levels 0.900V VIH(AC) 0.900V VIH(AC)

0.800V

VIH(DC)

0.800V

VIH(DC)

0.624V 0.612V 0.600V 0.588V 0.576V

0.624V 0.612V 0.600V 0.588V 0.576V

VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise

0.400V

VIL(DC)

0.400V

VIL(DC)

0.300V

VIL(AC)

0.300V

VIL(AC)

0.000V

VSS

-0.350V

VSS - 0.35V

Figure 108 — LPDDR2-200 to LPDDR2-400 Input Signal NOTE 1 Numbers reflect nominal values NOTE 2 For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c, VDD stands for VDDQ. NOTE 3 For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c, VSS stands for VSSQ.

JEDEC Standard No. 209-2E Page 166 8.4 8.4.1 AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC

differential voltage

VIHDIFF(AC)MIN

VIHDIFF(DC)MIN CK_t - CK_c DQS_t - DQS_c

0.0

VILDIFF(DC)MAX

VILDIFF(AC)MAX half cycle tDVAC

time

Figure 109 — Definition of differential ac-swing and “time above ac-level” tDVAC 8.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c)
Table 77 — Differential AC and DC Input Levels
LPDDR2-1066 to LPDDR2-466 Min 2 x (VIH(dc) - Vref) Note 3 2 x (VIH(ac) - Vref) note 3 Max note 3 2 x (VIL(dc) - Vref) Note 3 2 x (VIL(ac) - Vref) LPDDR2-400 to LPDDR2-200 Min 2 x (VIH(dc) - Vref) Note 3 2 x (VIH(ac) - Vref) note 3 Max note 3 2 x (VIL(dc) - Vref) Note 3 2 x (VIL(ac) - Vref)

Symbol

Parameter

Unit Notes V V V V 1 1 2 2

VIHdiff(dc) Differential input high VILdiff(dc) Differential input low VIHdiff(ac) Differential input high ac VILdiff(ac) Differential input low ac

NOTE 1 Used to define a differential signal slew-rate. For CK_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here. NOTE 2 For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. NOTE 3 These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 174. NOTE 4 For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).

JEDEC Standard No. 209-2E Page 167 8.4.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c) (cont’d) Table 78 — Allowed time before ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c tDVAC [ps] Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 @ |VIH/Ldiff(ac)| = 440mV min 175 170 167 163 162 161 159 155 150 150 tDVAC [ps] @ |VIH/Ldiff(ac)| = 600mV min 75 57 50 38 34 29 22 13 0 0

JEDEC Standard No. 209-2E Page 168 8.4.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle. DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.

VDDCA or VDDQ

VSEH(ac) VSEH(ac)min

VDDCA/2 or VDDQ/2

CK_t, CK_c DQS_t, or DQS_c

VSEL(ac)max VSEL(ac) VSSCA or VSSQ
Figure 110 — Single-ended requirement for differential signals. Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_c and VDDCA/2 for CK_t, CK_c; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. The signal ended requirements for CK_t, CK_c, DQS_t, and DQS_c are found in tables 74 and 76, respectively. Table 79 — Single-ended levels for CK_t, DQS_t, CK_c, DQS_c
Symbol VSEH(AC) VSEL(AC) Parameter Single-ended high-level for strobes Single-ended high-level for CK_t, CK_c Single-ended low-level for strobes Single-ended low-level for CK_t, CK_c LPDDR2-1066 to LPDDR2-466 Min (VDDQ / 2) + 0.220 (VDDCA / 2) + 0.220 note 3 note 3 Max note 3 note 3 (VDDDQ / 2) - 0.220 (VDDCA / 2) - 0.220 LPDDR2-400 to LPDDR2-200 Min (VDDQ / 2) + 0.300 (VDDCA / 2) + 0.300 note 3 note 3 Max note 3 note 3 (VDDQ / 2) - 0.300 (VDDCA / 2) - 0.300 Unit Notes V V V V 1, 2 1, 2 1, 2 1, 2

time

NOTE 1 For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use VIH/VIL(ac) of DQs. NOTE 2 VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here NOTE 3 These values are not defined, ho\wever the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 174

120 NOTE 1 The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device.JEDEC Standard No. CK_c and DQS_t. For DQS_t and DQS_c. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. and VIX(AC) is expected to track variations in VDD. 209-2E Page 169 8. each cross point voltage of differential input signals (CK_t. Vref = VrefDQ(DC). VDDCA or VDDQ CK_c. CK_c Differential Input Cross Point Voltage relative to VDDQ/2 for DQS_t.2 1. Vref = VrefCA(DC).5 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe. DQS_c VIX VDDCA/2 or VDDQ/2 VIX VIX CK_t. DQS) Symbol Parameter LPDDR2-1066 to LPDDR2-200 Min Max 120 120 Unit mV mV Notes 1.120 . DQS_t Figure 111 — Vix Definition VSSCA or VSSQ Table 80 — Cross point voltage for differential input signals (CK. DQS_c) must meet the requirements in Table 79. NOTE 2 For CK_t and CK_c. . DQS_c .2 VIXCA VIXDQ Differential Input Cross Point Voltage relative to VDDCA/2 for CK_t. VIX(AC) indicates the voltage at which differential input signals must cross.

DQS_c) are defined and measured as shown in Table 81 and Figure 112.CK_c and DQS_t . 8. Differential input slew rate for falling edge VIHdiffmin VILdiffmax [VIHdiffmin .e.VILdiffmax] / DeltaTRdiff (CK_t .DQS_c). NOTE 1 The differential signal (i.e.DQS_c. CK_c and DQS_t. See “Data Setup. Hold and Derating” on page 206 for single-ended slew rate definitions for address and command signals.CK_c and DQS_t .6 Slew Rate Definitions for Single-Ended Input Signals See “CA and CS_n Setup.CK_c and DQS_t .DQS_c) must be linear between these thresholds.VILdiffmax] / DeltaTFdiff (CK_t .DQS_c). Table 81 — Differential Input Slew Rate Definition Description Measured from to Defined by Differential input slew rate for rising edge VILdiffmax VIHdiffmin [VIHdiffmin . Differential Input Voltage (i. 209-2E Page 170 8. CK_t . DQS_c and CK_t.CK_c) Delta TRdiff VIHdiffmin 0 VILdiffmax Delta TFdiff Figure 112 — Differential Input Slew Rate Definition for DQS_t. DQS_t . CK_c . Hold and Slew Rate Derating” on page 212 for single-ended slew rate definitions for data signals. CK_t .JEDEC Standard No.7 Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK_t.

Table 82 — Single-ended AC and DC Output Levels Symbol VOH(DC) VOL(DC) VOH(AC) VOL(AC) IOZ Parameter DC output high measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output slew rate ) AC output low measurement level (for output slew rate ) Output Leakage current (DQ.JEDEC Standard No. 209-2E Page 171 9 9.1mA.1mA. VOHdiff(AC) AC differential output high measurement level (for output SR) VOLdiff(AC) AC differential output low measurement level (for output SR) NOTE 1 IOH = -0. NOTE 2 IOL = 0.9 x VDDQ 0.20 x VDDQ . DQS_c are disabled.0. 9. DM. DQS_c).1 AC and DC Output Measurement Levels Single Ended AC and DC Output Levels Table 82 shows the output levels used for measurements of single ended signals.0. 0V  VOUT  VDDQ Max LPDDR2-1066 to LPDDR2-200 0.12 -5 5 -15 15 Unit Notes V V V V uA uA % % 1 2 MMPUPD Delta RON between pull-up and pull-down for DQ/DM Min Max NOTE 1 IOH = -0.12 VREFDQ . DQS_c) Min X X (DQ. DQS_t.1mA .2 Differential AC and DC Output Levels Table 83 — Differential AC and DC Output Levels Symbol Parameter LPDDR2-1066 Unit Notes to LPDDR2-200 + 0.1 x VDDQ VREFDQ + 0. DQS_t.20 x VDDQ V V Table 83 shows the output levels used for measurements of differential signals (DQS_t.1mA. NOTE 2 IOL = 0.

3 Single Ended Output Slew Rate With the reference load for timing measurements.VOL(AC)] / DeltaTRse [VOH(AC) . Delta TRse Single Ended Output Voltage (i.5 1.7 Max 3. over the entire temperature and voltage range. it represents the maximum difference between pull-up and pull-down drivers due to process variation. NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage. 209-2E Page 172 9. .30%) Single-ended Output Slew Rate (RON = 60 +/.VOL(AC)] / DeltaTFse Output slew rate is verified by design and characterization. output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 84 and Figure 113. For a given output. Query-Output) se: Single-ended Signals Symbol SRQse SRQse LPDDR2-1066 to LPDDR2-200 Min 1.30%) Output slew-rate matching Ratio (Pull-up to Pull-down) Description: SR: Slew Rate Q: Query Output (like in DQ.4 Units V/ns V/ns NOTE 1 Measured with output reference load.JEDEC Standard No. DQ) VOH(AC) VREF VOL(AC) Delta TFse Figure 113 — Single Ended Output Slew Rate Definition Table 85 — Output Slew Rate (single-ended) Parameter Single-ended Output Slew Rate (RON = 40 +/. NOTE 4 Slew rates are measured under normal SSO conditions. NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). which stands for Data-in.0 0.5 2.5 1. and may not be subject to production test.e. Table 84 — Single-ended Output Slew Rate Definition Description Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge NOTE 1 Measured from VOL(AC) VOH(AC) to VOH(AC) VOL(AC) Defined by [VOH(AC) . with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low.

Query-Output) diff: Differential Signals Symbol SRQdiff SRQdiff LPDDR2-1066 to LPDDR2-200 Min 3. 209-2E Page 173 9. output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 86 and Figure 114.VOLdiff(AC)] / DeltaTFdiff NOTE 1 Output slew rate is verified by design and characterization.0 Max 7. Delta TRdiff Differential Output Voltage (i.0 2. NOTE 3 Slew rates are measured under normal SSO conditions. Table 86 — Differential Output Slew Rate Definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge Measured from VOLdiff(AC) VOHdiff(AC) to VOHdiff(AC) VOLdiff(AC) Defined by [VOHdiff(AC) . NOTE 2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low.e.0 Units V/ns V/ns NOTE 1 Measured with output reference load.0 5.JEDEC Standard No.30%) Description: SR: Slew Rate Q: Query Output (like in DQ.30%) Differential Output Slew Rate (RON = 60 +/. which stands for Data-in. and may not be subject to production test.VOLdiff(AC)] / DeltaTRdiff [VOHdiff(AC) . DQS_t .DQS_c) VOHdiff(AC) 0 VOLdiff(AC) Delta TFdiff Figure 114 — Differential Output Slew Rate Definition Table 87 — Differential Output Slew Rate Parameter Differential Output Slew Rate (RON = 40 +/. .4 Differential Output Slew Rate With the reference load for timing measurements.

VDD stands for For CA0-9. DM/DNV) NOTE 1 VDDQ. VDD stands for VDDCA. CK_c. Maximum Amplitude Overshoot Area VDD Volts VSS (V) Undershoot Area Maximum Amplitude Time (ns) NOTE 1 VDDQ. DM/DNV.15 0.5 Overshoot and Undershoot Specifications Table 88 — AC Overshoot/Undershoot Specification Parameter Maximum peak amplitude allowed for overshoot area. and VSSCA levels.20 0. DM/DNV. CK_c. For CA0-9.20 0. (See Figure 115) Maximum peak amplitude allowed for undershoot area.  (See Figure 115) Max 1066 933 800 667 533 466 400 333 266 200 Units V 0.30 0.24 0. (See Figure 115) Maximum area above VDD. DQS_c. For DQ. CK_c.24 0.15 0. CK_t. For DQ. DM/DNV. DQS_t. NOTE 3 For CA0-9. NOTE 2 VSSQ.35 Max 0. VDDCA.35 0.JEDEC Standard No. and CKE. DQ.40 0. CS_n. DQS_t. DQS_t.80 V-ns (CA0-9.17 0.48 0.  (See Figure 115) Maximum area below VSS. CK_t. NOTE 2 VSSQ. For DQ. For DQ. and DQS_c. 209-2E Page 174 9. CKE. CS_n. and DQS_c.40 0. and CKE.80 V-ns Max 0. VSS stands for Values are referenced from actual VDDQ. DQS_t. CK_c. and DQS_c. and CKE. DQS_t. VDD stands for For CA0-9. CS_n.30 0. and CKE. CK_t. CS_n.60 0. VSS stands for VSSCA. CS_n.60 0.35 V Max 0. DM/DNV. CK_t. and DQS_c. VSS stands for VSSCA. VDD stands for VDDCA. CK_c.17 0.48 0. VSSQ. CK_t.35 0. VSS stands for Figure 115 — Overshoot and Undershoot Definition .

Figure 116 — HSUL_12 Driver Output Reference Load for Timing and Slew Rate . generally one or more coaxial transmission lines terminated at the tester electronics. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment.6. This reference load is also used to report slew rate.5 x VDDQ Cload = 5pF NOTE 1 All output timing parameter values (like tDQSCK.5 x VDDQ RTT = 50  VTT = 0.1 Output buffer characteristics HSUL_12 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester.JEDEC Standard No.) are reported with respect to this reference load. VREF LPDDR2 SDRAM/NVM Output 0.6 9. tRPRE etc. tQHS. Manufacturers correlate to their production test conditions. 209-2E Page 175 9. tHZ. tDQSQ.

. 209-2E Page 176 9.7 RONPU and RONPD Resistor Definition  VDDQ – Vout  RONPU = ---------------------------------------ABS  Iout  NOTE 1: This is under the condition that RONPD is turned off Vout RONPD = -------------------------ABS  Iout  NOTE 1: This is under the condition that RONPU is turned off Chip in Drive Mode Output Driver IPU To other circuitry like RCV..JEDEC Standard No. RONPU IOut RONPD IPD VDDQ DQ VOut VSSQ Figure 117 — Output Driver: Definition of Voltages and Currents . .

2.4.15 1.15 1. 209-2E Page 177 9. .2.0 80. Table 89 — Output Driver DC Electrical Characteristics with ZQ Calibration RONNOM 34.3.00 1.5 x VDDQ 0.4 1.0 120. NOTE 4 Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ 0.3.4 1.3.5 x VDDQ 0. NOTE 3 The tolerance limits are specified after calibration with fixed voltage and temperature.3.3.7.15 1.5 x VDDQ 0.00 1.00 1.85 0.4 1.5 x VDDQ 0.JEDEC Standard No.00 1.5 x VDDQ 0.4 1.4 1.2. see following section on voltage and temperature sensitivity.2.0 48. NOTE 2 RZQ = 240.00 1.5 x VDDQ 0.15 1.5 x VDDQ 0.15 +15.2.5 x VDDQ: RONPU – RONPD MMPUPD = -----------------------------------------------.5 40. with MMPUPD(max) = 15% and RONPD = 0.85 0. Nominal RZQ is 240.00 1.85 0.3.0 (optional) Mismatch between pull-up and pull-down NOTE 1 Across entire operating temperature range.15 1.00 1.00 Max 1.2.4 1.15 1.2.3.4 1.3.3.  RONNOM For example.00 1.85 0. after calibration.00 1.3 Resistor RON34PD RON34PU RON40PD RON40PU RON48PD RON48PU RON60PD RON60PU RON80PD RON80PU RON120PD RON120PU MMPUPD Vout 0.15 1.85 -15. RONPU must be less than 1.3. NOTE 5 Measurement definition for mismatch between pull-up and pull-down. For behavior of the tolerance limits if temperature or voltage changes after calibration. both at 0.85 0.15 1. MMPUPD: Measure RONPU and RONPD.3.4 1.85 0.2.2.3.85 0.4 1.15 1.1 RONPU and RONPD Characteristics with ZQ Calibration Output driver impedance RON is defined by the value of the external reference resistor RZQ.00 Nom 1.00 1.2.2.5 x VDDQ Min 0.5 x VDDQ 0.00 1.3.15 1.5 x VDDQ.0 60.5 x VDDQ 0.85 0.15 1.85 0.4 1.85 0.2.85.4 1.4 1.0.5 x VDDQ 0.2.85 0.00 Unit RZQ/7 RZQ/7 RZQ/6 RZQ/6 RZQ/5 RZQ/5 RZQ/4 RZQ/4 RZQ/3 RZQ/3 RZQ/2 RZQ/2 % Notes 1.

the tolerance limits widen according to the Tables shown below. V = V – V (@ calibration) NOTE 2 dRONdT and dRONdV are not subject to production test but are verified by design and characterization.2  –  dRONdT  T  –  dRONdV  V   +  dRONdT  T  +  dRONdV  V  NOTE 1 T = T – T (@ calibration).00 0. Table 90 — Output Driver Sensitivity Definition Resistor RONPD 0.JEDEC Standard No.00 Max 0.5 x VDDQ RONPU Vout Min Max Unit % Notes 1.2 Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration. Table 91 — Output Driver Temperature and Voltage Sensitivity Symbol dRONdT dRONdV Parameter RON Temperature Sensitivity RON Voltage Sensitivity MIn 0.20 Unit %/C % / mV Notes .7.75 0. 209-2E Page 178 9.

5 x VDDQ 0.5 x VDDQ Min 24 24 28 28 33.5 x VDDQ 0.0 RON80PD RON80PU 120. .5 x VDDQ