NTD3055L104 Power MOSFET

12 Amps, 60 Volts, Logic Level NChannel DPAK

Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
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V(BR)DSS 60 V RDS(on) TYP 104 mW NChannel D ID MAX 12 A

PbFree Packages are Available Lower RDS(on) Lower VDS(on) Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

Typical Applications
G S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 MW) GatetoSource Voltage, Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1) Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance, JunctiontoCase JunctiontoAmbient (Note 1) JunctiontoAmbient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID Value 60 60 "15 "20 12 10 45 48 0.32 2.1 1.5 55 to +175 61 Unit Vdc Vdc Vdc 1 2 Adc Apk W W/C W W C mJ 1 3 4 DPAK CASE 369C STYLE 2

MARKING DIAGRAMS
4 Drain AYW 55L104 2 1 3 Drain Gate Source 4 Drain 4 AYW 55L104 1 2 3 Gate Drain Source 55L104 A Y W = Device Code = Assembly Location = Year = Work Week DPAK3 CASE 369D STYLE 2

IDM PD

TJ, Tstg EAS

RqJC RqJA RqJA TL

3.13 71.4 100 260

C/W

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

Semiconductor Components Industries, LLC, 2005

January, 2005 Rev. 5

Publication Order Number: NTD3055L104/D

NTD3055L104
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 3) (VGS = 5.0 Vdc, ID = 6.0 Adc) Static DraintoSource OnVoltage (Note 3) (VGS = 5.0 Vdc, ID = 12 Adc) (VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (VDS = 48 Vdc ID = 12 Adc Vdc, Adc, VGS = 5.0 Vdc) (Note 3) 50 (VDD = 30 Vdc, ID = 12 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 3) td(on) tr td(off) tf QT Q1 Q2 VSD trr ta tb QRR 9.2 104 19 40.5 7.4 2.0 4.0 0.95 0.82 35 21 14 0.04 20 210 40 80 20 1.2 mC Vdc ns nC ns (VDS = 25 Vdc VGS = 0 Vdc Vdc, Vdc, f = 1.0 MHz) Ciss Coss Crss 316 105 35 440 150 70 pF VGS(th) Vdc 1.0 1.6 4.2 89 0.98 0.86 9.1 2.0 104 Vdc 1.50 mhos mV/C mW V(BR)DSS Vdc 60 70 62.9 1.0 10 100 mV/C mAdc Symbol Min Typ Max Unit

IDSS

IGSS

nAdc

RDS(on) VDS(on)

gFS

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time y (IS = 12 Adc, VGS = 0 Vdc) (Note 3) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) (IS = 12 Adc VGS = 0 Vdc Adc, Vdc, dIS/dt = 100 A/ms) (Note 3)

Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures.

ORDERING INFORMATION
Device NTD3055L104 NTD3055L104G NTD3055L1041 NTD3055L1041G NTD3055L104T4 NTD3055L104T4G Package DPAK DPAK (PbFree) DPAK3 DPAK3 (PbFree) DPAK DPAK (PbFree) Shipping 75 Units/Rail 75 Units/Rail 75 Units/Rail 75 Units/Rail 2500 Tape & Reel 2500 Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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NTD3055L104
24 ID, DRAIN CURRENT (AMPS) 20 16 12 8 4 0 VGS = 10 V 8V 6V 5V ID, DRAIN CURRENT (AMPS) 4.5 V 24 VDS 10 V 20 16 12 8 4 0 1 1.5

4V

3.5 V 3V

TJ = 25C TJ = 100C 2 2.5 3

TJ = 55C 3.5 4 4.5 5 5.5 6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

RDS(on), DRAINTOSOURCE RESISTANCE (W) 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 0 0 4 8 12 16 20 24 RDS(on), DRAINTOSOURCE RESISTANCE (W) 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 0 0

Figure 2. Transfer Characteristics

VGS = 5 V

VGS = 10 V

TJ = 100C

TJ = 100C

TJ = 25C TJ = 55C

TJ = 25C TJ = 55C

12

16

20

24

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 50 25 1 0 25 50 75 100 125 150 175 ID = 6 A VGS = 5 V IDSS, LEAKAGE (nA) 1000 10,000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 0 V TJ = 150C

100 TJ = 100C

10

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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NTD3055L104
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 800 600 Crss 400 200 0 Crss 10 5 VGS 0 VDS 5 10 15 20 25 Ciss Coss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VDS = 0 V VGS = 0 V Ciss

TJ = 25C

C, CAPACITANCE (pF)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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NTD3055L104
VGS , GATETOSOURCE VOLTAGE (VOLTS) 6 5 4 3 2 1 0 ID = 12 A TJ = 25C 0 2 4 6 QG, TOTAL GATE CHARGE (nC) 8 1 1 QT Q1 Q2 t, TIME (ns) 100 tr tf 10 td(off) td(on) VDS = 30 V ID = 12 A VGS = 5 V 100 1000

VGS

10 RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

16 IS, SOURCE CURRENT (AMPS) 14 12 10 8 6 4 2 0 0.3 0.4 0.6 0.7 0.8 0.9 0.5 VSD, SOURCETODRAIN VOLTAGE (VOLTS) 1 TJ = 150C TJ = 25C VGS = 0 V

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RqJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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NTD3055L104
SAFE OPERATING AREA
EAS , SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 100 I D, DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C 10 100 ms 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 10 ms dc 10 ms 70 60 50 40 30 20 10 0 25 175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) ID = 11 A

0.1

10 1 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

100

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 0.1 t1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) TC = P(pk) RqJC(t)

0.01

10

Figure 13. Thermal Response

di/dt IS trr ta tb TIME tp IS 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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NTD3055L104
PACKAGE DIMENSIONS
DPAK CASE 369C01 ISSUE O
T B V R
4 SEATING PLANE INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 0.035 0.050 0.155 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 0.89 1.27 3.93

C E
DIM A B C D E F G H J K L R S U V Z

A
1 2 3

Z U

K F L D G
2 PL

J H 0.13 (0.005) T

STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN

SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118

SCALE 3:1

mm inches

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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NTD3055L104
PACKAGE DIMENSIONS
DPAK3 CASE 369D01 ISSUE B
B V R
4

C E Z

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93

S T
SEATING PLANE

A
1 2 3

F D G
3 PL

H
M

0.13 (0.005)

STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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NTD3055L104/D