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DESIGN AND IMPLEMENTATION OF FOUR SWITCH DC-DC DC DC CONVERTER WITH ZVS

Presented by N.RAMCHANDER N RAMCHANDER Asst Professor EEED-BVRIT.

ABSTRACT
The Th new Four-switch DC-DC converter t l F it h DC DC t topology is i especially well suited for power converters operating from high input voltage; it imposes only half of the input voltage across each of the four switches. The two legs of a full-bridge converter are connected in series with each other across the dc input source, instead of the other, source usual topology in which each leg is connected across the dc source. The topology reduces turn-off switching losses by providing gy g y g capacitive snubbing of the turn-off voltage transient, and eliminates capacitor-discharge turn-on losses by providing zero-voltage turnon. on Switching losses are especially important in converters operating at high input voltage because turn-on losses are proportional to the square of the input voltage.

The topology is suitable for resonant and non-resonant p gy converters. It adds one bypass capacitor and one commutating inductor to the minimum-topology full-bridge converter and contains a dc-blocking capacitor in series with the output dc blocking transformer, primary winding, and some non-resonant converters. The commutating inductor is present in many present-day converters, to provide zero-voltage turn-on, or is associated , p g , with one or two capacitors to provide resonant operation and the bypass capacitor is already present in resonant power converters. converters In this project work four switch dc-dc converter has been implemented using PSPICE, turn-on and turn-off i l d i PSPICE d ff characteristics are studied.

INTRODUCTION
Conventional full bridge converter Proposed full bridge converter Introduction to Zero-Voltage-Switching Zero Voltage Switching Advantages of zero-voltage-switching g g g Objectives of the Project Work

Four Switch DC DC C F S it h DC-DC Converter :t


Four-switch full-bridge dc-dc converter topology is especially well suited for power converters operating from high input voltage. This topology is suitable for both resonant and nonresonant converters. Various modes of operation of proposed converter.

Conventional full-bridge converter

The new converter can be presented following a sequence of The modifications in the connection of components. First, a capacitor is added in series with the transformer as , p shown below

Full-bridge converter with capacitor in series with transformer primary winding

Considering two independent input voltage sources, the connection between the two legs can be eliminated as p g presented in the below figure

Separation of legs

The polarity of the voltage source and switches in the right leg The are reversed in the below figure

Reverse polarities of battery and switches in the right leg.

Rotating the right leg in 180o and connecting below the left leg g g g g g as shown in the below figure

Rotation of the right leg

The proposed converter can be obtained, substituting the input voltage sources by two input capacitors as below l b i i b l

The proposed converter

The proposed converter description: Switches S1,S2 & S3,S4 - Metal Oxide Semiconductor switches (MOSFETs). C1-C4 C1 C4 - th MOSFET i t the internal capacitances l it providing capacitive turn-off snubbing Cin1&Cin2 Cin1&Cin2 - input capacitors to bypass the input voltage and generate a bypassed dc mid-point voltage(Vin/2) p g ( ) Cs - dc-blocking capacitor Lr - resonant inductor TRF - transformer Dr1,Dr2 - rectifying diodes Lo & Co L C - fil circuit filter i i Ro - load

Principle of Operation:The following are the assumptions made: All components are ideal. The ripple in the dc voltage across the series capacitor Cs and the input capacitors Cin1 and Cin2 is negligibly small. small A current sink Io replaces the output filter and load. y primary side y The analysis is based on the circuit reflected to the p of the transformer, where Lm represents the mutual inductance in the transformers T equivalent circuit and the leakage inductance is absorbed into Lr. Lr The output rectifier is replaced by four rectifier diodes.

Modes of Operation:
The converter operation can be divided into certain modes: Mode1:Cin1 S2 D2 C2 Dr3 Dr1 D1 C1 S1 Lr

Vin
Lm Dr4 S3 C3 D3 Cin2 Vcs

Io Dr2

S4

C4 D4

Cs

Operation of Mode1 ( t0<t<t1 ) O ti f M d 1 t0 t t1

D1 S1

C1

Lr Cin1 S2 D2 C2 I Lr Dr3 Dr1

Io Lm Dr4 Dr2

Vin

I Lm

S3 Cin2

D3

C3

Cs

Vcs S4 D4 C4

Operation of Mode2 ( t1<t<t2 )

S1 D1 C1

Cin1
S2 D2 C2

Lr

Dr3

Dr1

Io

Vin
S3 C3 D3

ILm

Lm

Dr4

Dr2

Cin2 Ci 2
Vcs S4 C4 D4 Cs

Operation of Mode3 ( t2<t<t3 )

S1 D1 Cin1 C1

Lr I Lr D2 C2 Dr3 Dr1

S2

Io

Vin

I Lm

Lm Dr4 Dr2

S3 Cin2

D3

C3

Vcs

S4

D4

Cs

Operation of Mode4 ( t3<t<t4 ) p

S 1

D1

C1

Cin1 S2 D2 C2

Lr I Lr

Dr3 Io Lm Dr4

Dr1

Vin
S 3 Cin2 Vc s S 4 D4 C4 D3 C3

Dr2

- Cs

Operation of Mode5 ( t4<t<t5 )

S1 D1 C1

Lr Cin1 S2 D2 C2 Dr3 Dr1

Vin
Lm Dr4 S3 D3 Cin2 Vcs C3

Io

Dr2

S4 D4 C4 Cs

Operation of Mode6 ( t5<t<t6 )

S1

D1 C1

Lr Cin1 I Lr S2 s2 Vin I Lm Lm D2 C2 Dr3 Dr1

Io

Dr3 S3 D3 Cin2 Vcs C3

Dr2

S4 D4 C4 Cs

Operation of Mode7 ( t6<t<t7 )

S1 D1 C1

Lr Cin1 I Lr D2 C2 Dr3 Dr1

S2 Vin I Lm Lm

Io

Dr3 S3 D3 Cin2 Vcs C3

Dr2

S4

D4

C4

Cs

Operation of Mode8 ( t7<t<t8 ) p

D1 C1 S1

Lr Cin1 S2 D2 C2 I Lr Dr3 Dr1

Io Vin I Lm Lm

Dr3 S3 D3 Cin2 Vcs C3

Dr2

S4

D4

C4

Cs

Operation of Mode 9( t8<t<t9 )

D1 S1 C1

Lr Cin1 S2 D2 C2 I Lr Dr4 Dr1

Io Vin I Lm Lm

Dr3 S3 D3 Cin2 Vcs C3

Dr2

S4

D4

Cs

Operation of Mode10 (t9<t<t10 )

Theoretical Waveforms:-

Analysis:At first, temporarily neglecting the reduction of duty ratio caused by the conduction gap that allows the zero-voltage turn-on, the average voltage at the load (Vo) is

where

1 D D Vo = .(Vin Vcs) . +Vcs. ----------------------------(1) ( ) n 2 2

Vin - input voltage; Vcs - series capacitor voltage; n - transformer turns ratio ( Np/Ns) D/2 - ( 4)/ /2 (t7-t4)/T. The voltage on the dc-blocking capacitor (Vcs) is
V
cs

V in = 2

------------------------(2) (2)

Then, the output voltage is -----------------------------(3) But the output voltage is controlled by an effective duty ratio that is smaller than the nominal duty ratio is given by ----------------------------(4) (4) Deff = D
o

V in D = . n 2

where is the reduction of duty ratio caused by the conduction gap

Current through the resonant inductor during stages 5 and 6 is g g g given by Io V in ---------------------(5) .(t 6 t 4 ) iL r =
At i A time t6, iLr=-Io/n 6 iL I /

2.L r .

(t6 t 4) =

4.Lr. Vin

Io n.

----------------------------(6)

t6 t4 = 2. T
= 8 .L
r .

---------------------(7) -------------------------(8) ------------------------(9) (9)

f .
in

Io n .

Vo

The final output voltage equation in terms of rectifierdiode s The rectifierdiodes forward conduction threshold voltage(VF)
.Io 4. 4 Lr..Fs. Vin D n R int .Io Vf . ----------------------(10) Vo = . 2 2 Vin

Io 4 .L r . F s. V in D n . = . n 2 V in

DESIGN EXAMPLE:The input data for the design of an example converter are as follows. Input voltage I t lt Output Voltage Output power Output current : Vin =600 V. Vi 600 V : Vo=60 V. : Po=1500 W. : Io=25 A.

Switching f S it hi frequency : f = 50 kHz. kH

Simulation of Designed Circuit


BRIEF INTRODUCTION OF PSPICE:
SPICE (Simulation Program with Integrated Circuit Emphasis) was developed at the University of California at Berkely. As the electronics industry advanced, several companies began to sell PC and Macintosh compatible versions of SPICE. One O such company, ORCAD C h Corporation, a PC compatible version called i ibl i ll d PSPICE. Electronic circuit design requires accurate methods for evaluating circuit performance. Because of the enormous complexity of modern integrated circuits, f B f h l i f d i d i i computer aided circuit analysis is essential and can provide information about circuit performance that is impossible to obtain with laboratory prototype measurements. measurements PSPICE is a general-purpose circuit program that simulates electronic circuits. PSPICE can perform various analyses of electronic circuits. It is a versatile program and is widely used both in industries and universities universities.

Types of analysis: DC analysis is used for circuits with time-invariant source (e.g., steady state dc sources) It calculates all node voltages and branch currents over a range of sources). values and their quiescent (dc) values are the outputs. T Transient Analysis is used for circuits with time - variant sources (e.g., ac i A l i i df i i ih i i ( sources and switched dc sources). It calculates all node voltages and branch current over a time interval and their instantaneous values are the outputs. AC Analysis is used for small - signal analysis of circuits with sources of variable frequencies. It calculates all node voltages and branch currents over a range of frequencies, and their magnitudes and phase angles are the outputs. ff i d th i it d d h l th t t

Advantages:
Evaluating the effects of variation in elements such as register, transformers and other analog elements elements. Assessment of performance, improvement, degrading. Evaluating the effect of noise and signal distortion. Sensitivity analysis to determine the permissible bounds due to tolerance one each element value or parameter of active elements. Fourier analysis without expensive wave analysers. Evaluating effects non-linear elements on the circuit performance Optimisation the design of electronics circuits in terms circuit parameter.

Simulated Circuit

Description of Components Used in Simulation Description MOSFETS DIODES (Dc1 & Dc2) DIODES (Dr1 & Dr2) CAPACITORS (C12 & C13) Component Number IRFP460 MUR140 MUR1540 3uF, 3uF 400V

SIMULATION RESULTS
400V

1 10V

200V

V ol ta ge (v ol ts)

0V

0V

-200V -10V >> -400V 352us 1

356us 360us 364us 368us 372us V(M1:g,M1:s) 2 V(M1:d,M1:s) Time

376us

380us

384us

388us

Time (us)

Voltage across switch M1 (Zero Voltage Switching) (Zero-Voltage

400V

Vo 10V lta ge (v 0V olt s) )


-10V

200V

0V

-200V

>> -400V 352us 1

356us 360us V(M2:g,M2:s) 2

364us 368us V(M2:d,M2:s)

372us Time

376us

380us

384us

388us 392us

Time (us)

Voltage across switch M2 (Zero-Voltage Switching).

1 10V

2 200V

V ol ta ge ( (v ol ts)

0V

0V

-10V >>

-200V

352us 1

356us 360us V(M3:g,M3:s) 2

364us 368us V(M3:d,M3:s)

372us Time

376us

380us

384us

388us 392us

Voltage across switch M3 (Zero-Voltage Switching).

1 10V

400V

Vo lta ge (v olt s)

200V

0V

0V

-200V -10V >> -400V 352us 1

356us 360us 364us 368us 372us V(M4:g,M4:s) 2 V(M4:d,M4:s) Time

376us

380us

384us

388us

Voltage across switch M4 (Zero-Voltage Switching).

300V

Vo lta ge (vo lts)

200V

100V

0V 900us 910us 920us V(C2:1,C2:2)

930us

940us

950us Time

960us

970us

980us

990us1000us

Voltage across dc blocking capacitor(Cs)

400V

Vo lta ge 0V (vo lts)-200V


-400V 900us 910us 920us V(TX1:1,TX1:3)

200V

930us

940us

950us Time

960us

970us

980us

990us 1000us

Voltage across primary winding of the transformer

Cu C 20A rre nt 10A (A mp 0A s)


-10A 900us 910us ID(M1) 920us

Current througheswitch M1. g Time

930us

940us

950us

960us

970us

980us

990us1000us

Cu rre nt (A mp s)

20A

0A

-20A 910us 900us ID(M2)

920us

930us

940us

950us Time

960us

970us

980us

990us1000us

Current through switch M2

20A

Cu C rre nt (A mp s)

10A

0A

-10A 910us 900us ID(M3)

920us

930us

940us

950us Time

960us

970us

980us

990us1000us

Current through switch M3


Cu rre nt (A mp p s)
10A

0A

-10A 910us 900us ID(M4)

920us

930us

940us

950us Time

960us

970us

980us

990us1000us

Current through switch M4

20A

Cu C rre nt (A mp s)

10A

0A

-10A 0.99ms 1.00ms I(L1)

1.01ms

1.02ms

1.03ms

1.04ms Time

1.05ms

1.06ms

1.07ms

1.08ms

Current through the resonant inductor (Lr)


200V

Vo lta ge (vo lts)

100V

0V

-100V 100V 0.99ms 1.00ms 1.01ms V(R1:2,D7:1)

1.02ms

1.03ms

1.04ms Time

1.05ms

1.06ms

1.07ms

1.08ms

Voltage across the rectifier diode.

1.0KV

Vo lta ge (vo lts)

0V

-1.0KV 0.99ms 1.00ms 1.01ms V(TX1:1,TX1:3)

1.02ms

1.03ms

1.04ms Time Ti

1.05ms

1.06ms

1.07ms

1.08ms

Voltage across the primary winding of the transformer eliminating the clamping diodes Dc1 and Dc2
500V

Vo lta ge (vo lts)

0V

-500V 0.99ms 1.00ms 1.01ms V(R1:2,D7:1)

1.02ms

1.03ms

1.04ms Time

1.05ms

1.06ms

1.07ms

1.08ms

Voltage across the rectifier diode eliminating the clamping diodes Dc1 and Dc2

80V

Vol 40V tag e (vo lts) 0V

-40V 0s 0.5ms V(R3:2,0) 1.0ms 1.5ms 2.0ms Time 2.5ms 3.0ms 3.5ms 4.0ms

Output Voltage of the Proposed converter

40A

Cu rre nt (A mp s)

20A

0A

-20A 0s -I(R3) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms

Output current of the Proposed converter

2.0KW

Po P we r ( W att s)

1.0KW

0W 0s W(R3) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms

Output Power of Proposed converter. converter

CONCLUSIONS
The Four Switch DCDC Converter with ZVS has been described with modes of operation and ideal waveforms. The circuits have been analysed. The simulation was done for Full bridge inverter. The inverter simulation results are presented such as the timing sequence of control signals, transformer primary voltage and the waveforms of ZVS t transition etc. iti t This new four-switch power-circuit topology is well suited to economical realization of full-bridge dc-dc converters to be g operated from dc input voltages of up to twice the maximum voltage that is allowed to be imposed on each switch in the power circuit. circuit

SCOPE FOR FUTURE WORK

In this project work Four-switch dc-dc converter with ZeroVoltage Switching has been simulated and simulation results are presented but hardware implementation has not been done. So, Hardware Implementation can be taken up as further scope of the project work.

REFERENCES

1)

Barbi .I, Gules .R, Redl .R and Sokal ,.N.O, DC/DC converter for High input voltage; four switches with peak voltage of Vin/2 capacitive turn off snubbing and zero voltage turn on , IEEE Trans on Power Electronics Vol 19 PP 918Electronics, 19. 918 927, July 2004. Duarte C.M.C and Barbi I., An improved family of ZVS-PWM DC-DC converter, IEEE Trans on Power Electronics, Vol 17. PP 1-7, Jan 2002 Jang Y, Jovonaic M and Yu-Wing Chang, A New ZVS-PWM full-bridge converter, IEEE Trans on Power Electronics, Vol 18. PP 1122-1129, Sep 2003. Jeon S J and G J S.J d Gyu-Jtyeong Cho, A Zero Voltage and Zero Current Switching Jt Ch Z V lt d Z C t S it hi full-bridge DC-DC converter with transformer isolation, IEEE Trans on Power Electronics, Vol 16. PP 573-580, Sep 2001. Lee C.Y and Kwang-hwa.Liu, Zero Voltage Switching technique in DC-DC converters, converters IEEE Trans on Power Electronics, Vol 5. PP 293-304, July 1990 Electronics 5 293 304 1990. www.colorado.edu. www.power designers.com

2)

3)

4)

5)

6) 7)

Determination of Passive Components:-

Transformer Turns Ratio: Assuming ideal switches and diodes and considering the following. Nominal duty-ratio: D = 0.8. Maximum duty ratio reduction: 15% of the nominal value of D: = 0.15.D = 0.15.0.8 = 0.12 The transformer turns ratio is calculated as
D 0.8 0.12 Vin. 600v . Vo 2 n= = = 3.4.. Vo 60v

Resonant Inductor Lr: The resonant inductor Lr is defined by the maximum y duty ratio reduction specified and is calculated as
* Vin *. 0.12 * 600V 0 12 = = 24.5 H . Io 25 A 8* f * 8 * 50.kHz * n 3.4

Lr =

Series Capacitor Cs: The required value of Cs is calculated as a function of the maximum allowable ripple voltage. The relationship between the ripple voltage and the current in Cs is

iCS = Cs
where
t = T 1 = 2 2. f

Vcs t

iC S

Io = n

Then the series capacitor is calculated as

Cs =

Io 2. 2 n. f .Vcs

Limiting the Li iti th peak ripple on the capacitor to 3.5% of the dc value yields k i l th it t 3 5% f th d l i ld

Vin 600V Vcs = 3.5% = 3.5% =10.5V . . 2 2


Cs 25A = 7F. 2*3.4*50kHz *10.5V

Input Capacitors: The input capacitors Cin1 and Cin2 can be calculated by the same method used above for Cs. V cin i C in = C in . t where
t =

(1 D) *T (1 D)
2 = 2* f

i C in

Io = 2 * n

Then th i Th the input capacitors are calculated as : t it l l t d

Cin1 = Cin2

Io *(1 D) 4 4*n* f *VCin

Allowing 5% voltage ripple, we have

VCin =5%*300V =15 V


Then the input capacitors are

Cin1 = Cin2 =

25A*(10.8) 4*3.4*50kHz *15V

= 0.5F.

Output Filter: The inductance and capacitance of the filter are calculated with below equations to provide a maximum current ripple Io of 10% and maximum voltage ripple Vo of 1%
L O min = Vin 16 * f * io * n

600 V LOmin = =88.23H 16*50kH *34*25A z*3.4*2.5


CO min = Io 8 * f * Vo

2.5A O =10.4F. C min = 8*50kH *0.6 z V Maximum allowable series resistance of output capacitor Co

Vo 0.6V Rser max = = =024 0.24 . Io 2.5A

Switches Voltage and Current Stresses: Active Switches: The maximum voltage across the off switches is
VSoff = Vin 600V = = 300V 2 2

The average and rms currents through S1 and S3 are calculated as

I S 1 avg = I S 3 avg
IS1avg = IS 3avg =

Io D . = n 2

25 A 0 8 0.8 . = 2.94 A 3.4 2

I S 1 rm s = I S 3 rm s =
IS1rms = IS 3rms =

Io D . 2 n

25A 0.8 . = 4.65A 3.4 34 2

The Th average and rms currents through S2 and S4 are d t th h d

I S 2 a vg = I S 4 a vg
IS2avg = IS4avg =

Io = 2 .n

I25A = 3.67A 2*3.4 2*34

IS 2rms = IS 4rms =
IS2rms = IS4rms =

Io n. 2
= 5.2A.

25A 3.4 34* 2

Output R tifi O t t Rectifier: F th out put rectifier shown in main power circuit, the For the t t tifi h i i i it th diode reverse voltage is calculated as
Vin 1 600V 1 Vdr = 2 . = 2 2. 2. . =17647V. 176.47 2 n 2 3.4

The rectifier-diode average and rms currents are needed for the same reasons as rectifier diode are the switch currents. They are given by

Io 25A Idravg = = = 12.5A 2 2


Idrrms = Io 2 = 25A 2 =17.667A.