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In most types of logic design, termed static logic, there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS this principle can be rephrased as a statement that there is always a low-impedance path between the output and either the supply voltage or the ground. As a side note, there is of course an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic. In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle.

AN EXAMPLE FOR DYNAMIC LOGIC: dynamic D-latch circuit



The circuit consists of two cascaded inverters and one nMOS pass transistor driving the input of the primary inverter stage. Cx is the output parasitic capacitance; it plays an important role in the circuit. The input pass transistor is driven by the clk input. When the clock is high, the pass transistor on and whatever be the input that will transfer to the nod Vx. When the clock is low pass transistor is off. Since there is no current path from the intermediate node X to either Vdd or ground, the amount charge stored in Cx during the previous cycle determines the output voltage level Q.


Now we are going to discuss different examples of synchronous dynamic circuits implemented using depletion-load nMOS, enhancement-load nMOS and CMOS as building blocks. DYNAMIC PASS TRANSISTOR CIRCUITS: The circuit consists of cascaded combinational logic stages, which are interconnected through nMOS pass transistors. All the inputs of each combinational logic block are driven by a single clock signal. Individual capacitances are not shown in the fig for simplicity, but the operation of circuit obviously depends on temporary charge storage in the parasitic input capacitances.

Comb. Logic1 Comb. Logic2

Comb. Logic3


1 C

2 D

As shown in the fig for odd no. of stages we are giving clock 1 and for even no. of stages we are giving clock 2. The nonoverlapping property of the clocks guarantees only odd no. of stages or even no. of stages active at a time. The signal timing scheme is called two-phase clocking. The fig below shows depletion-load dynamic shift register circuit, in which the input data are inverted once and transferred, or shifted to the next stage during each clock phase. During the active phase of 1 input Vin is transferred to the input capacitance Cin1, thus the output will be determined as the inverse of Vin . Only when the 2 is active first stage output is given to the second stage as input, at the same time the first stage input capacitance continue to retain its voltage level. When 1 is active again second

stage output is given to first stage, and the new set of input can be applied at the input. VDD VDD

1 Vin

Now consider a different implementation of the simple shift register circuit, using enhancement-load nMOS inverters. One important difference is the, instead of biasing the load transistors with a constant gate voltage, we apply the clock signal to the gate of the load transistor as well. It can be shown that the power dissipation and the silicon area can be reduced significantly by using this dynamic (clocked) load approach. Two variants of the dynamic enhancement-load logic will be examined in the following. Where in each stage the input pass transistors and the load transistors are driven by opposite clock phases, 1 and 2. 1 2 1


nMOS logic stage1

nMOS logic stage1

2 Z
nMOS logic stage1


nMOS logic stage1

The first one is dynamic ratioed logic, since the VOL of each stage depend on the driver to load ratio. But the second one is ratioless logic. DYNAMIC CMOS CIRCUIT TECHNIQUES: Here, CMOS transmission gates are used for transferring the output levels of one stage to input levels of next stage and CMOS gates are used for implementing the logic block. Each transmission gates has clock and its complement. So in two phase clocking, CMOS transmission gate logic requires four clock signals. The operation is similar to that of nMOS pass transistor logic 1 2

CMOS logic stage1

CMOS logic stage1

C D 1 2

PRECHARGE-EVALUATE LOGIC: In this logic we can significantly reduce the number of transistors used. The circuit is based on first precharging the output node capacitance and then in evaluation phase output may or may not discharge according to the logic we implemented in the pull down logic. Precharge- evaluate logic has several advantages, but an overwhelming limitation in the form of erraneus output when two or more stages are cascaded overshadows all of these. This severe limitation undermines all other advantages of the precharge evaluatelogic.Theerroneousoutputconditionisillustratedbelow.

The precharge evaluate logic works by discharging the charge on the capacitor if required during the evaluate phase. The problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.

Solution: Domino Logic One solution to this problem is the domino logic. The cascading problem is created when one of the inputs to the NMOSs undergoes a 1 to 0 transition during the evaluate phase of the clock. If we can avoid this one to zero transition we can effectively solve this problem. This is done by adding an inverter to the output of the prechage evaluate logic. This ensures that there are no 1 to 0 transitions in the input gates of the NMOS at any subsequent stage.

Limitations: 1. Only non inverting structures can be implemented using domino logic. If necessary, inversion must be done using conventional CMOS inverters. 2. If the intermediate node capacitances are comparable to the output node capacitor, charge sharing will occur across these capacitors, resulting n a lower voltage level at the output. This can cause erroneous output if the charge at the output node dips below that of the threshold of the inverter. 3. This can be solved by adding a weak pull-up CMOS(with a low W/L value) to keep the output node charged to Vdd in the absence of a strong discharge path. 4. Another solution would be to precharge all the intermediate capacitor to Vdd. But this would considerably increase the delay to reach a stable output state as all these will have to be discharged during the evaluate phase.

In fact, by applying Elmores RC delay formula to series connected nMOS structures, one can determine if a reduction of nMOS transistor size will improve the transient response. Vdd


DUAL-RAIL DOMINO LOGIC: A major limitation of domino logic is that only non-inverting logic can be implemented. One approach to this problem is rearranging the logic using simple booliean transformation (such as De-Morgans law). But generalized approach to this problem is dual rail domino. The concept is similar to DCVL structure, but uses a precharged load instead of static cross coupled-pMOS load. Here we have the function and its compliment as output, it comes in the expense of increased power