European Journal of Scientific Research ISSN 1450-216X Vol.72 No.2 (2012), pp. 184-194 © EuroJournals Publishing, Inc.

2012 http://www.europeanjournalofscientificresearch.com

Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits
R. Udaiyakumar Associate Professor, Department of ECE Sri Krishna College of Technology, Coimbatore, India 641042 E-mail: udai.skct@gmail.com Tel: +91 9626273374 K. Sankaranarayanan Dean, Department of ECE Easa College of Engineering and Technology, Coimbatore, India 641 105 E-mail: kkd_sankar@yahoo.com Tel: +91 9443126363 Abstract To limit the ever increasing trend of energy and power dissipation in Complementary metal Oxide (CMOS) Technology, Supply voltage has to be continuously scaled. The amount of power reduction depend not only on supply voltage (Vdd) but also on the threshold voltage (Vth), to sustain the reduction of component delay, which is crucial for high speed digital circuit design. Continuous scaling down of these parameters poses several challenges to circuit designers. Particularly threshold voltage reduction leads to increase in sub-threshold leakage current leading to tremendous increase of static power consumption in CMOS circuits, which is otherwise considered as a negligible contributor to the overall power consumption. Hence it is inevitable to identify proper leakage current reduction techniques suitable for nanoscale CMOS circuits, which reduces the leakage current particularly in sub-threshold region of operation. In this paper, the performance of a CMOS Tri-State buffer using Multi Threshold CMOS (MTCMOS) and Forced Transistor Stacking (FTS) leakage reduction techniques are analyzed and propose a new technique called Dual Threshold Transistor Stacking (DTTS) is proposed for efficient reduction of leakage power. From the results, it is observed that the proposed technique combines the advantage of multiple threshold and stacking effects in MOSFETs. Keywords: CMOS, Threshold Voltage, Static Power dissipation, leakage current, Multiple Threshold, Transistor stack, DTTS, DFF, Predictive Technology Model

1. Introduction
The International Technology Roadmap for Semiconductors (ITRS), 2010 report [1] mention that continuous scaling down of Gate oxide thickness makes gate tunneling current as an important factor

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in the design of power efficient nanoscale CMOS circuits. Gate leakage and subthreshold leakage currents are the most dominant leakage mechanisms particularly in the nanoscale CMOS circuits. Gate leakage is mainly due to electron tunneling from the gate to the substrate, but subthreshold leakage is caused by many other factors [2]. As a result, the leakage control techniques are to be employed as an integral part of conventional CMOS circuits to keep the leakage power in control. Over the years, many leakage current reduction techniques have been proposed in order to minimize the total power consumption of CMOS circuits. Some techniques are used when the circuits are in active mode and others are employed during standby mode. Standby leakage current flows when the circuit is in idle state and active leakage current exists during the circuit in use. Generally, these leakage reduction techniques are applied at both device and circuit levels [2]. This paper is organized as follows: Section 2 presents an overview of different leakage current mechanisms of Nanoscale CMOS circuits. A brief review of various circuit level leakage reduction techniques are given in section 3. In section 4, a new technique called Dual Threshold Transistor stacking (DTTS) is proposed. Section 5 describes about the experimental setup made for performance analysis. Results of average power, leakage current, leakage power, delay, percentage of average and leakage power reduction are discussed in section 6. Finally, conclusions are presented in section 7.

2. Leakage Current Components of Nanoscale CMOS Circuits
Leakage currents are mainly due to reduction in Threshold voltage, Channel length and Oxide thickness. Six short-channel leakage mechanisms are illustrated in Figure 1. a) Iı is the reverse-bias p-n junction leakage; b) I2 is the sub threshold leakage; c) I3 is the oxide tunneling current; d) I4 is the gate current due to hot-carrier injection; e) I5 is the Gate- induced drain leakage current and f) I6 is the channel punch through current. Currents I2, I5 and I6 are off-state leakage mechanisms, while Iı and I3 occur in both ON and OFF states. I4 can occur in the off state, but typically occurs during the transistor bias states in transition.
Figure 1: Leakage Current mechanisms in Short Channel MOSFETs [3]

Among these, subthreshold leakage current components create a major impact on static power consumption of short channel MOSFETs [3]. In this section, these are briefly discussed.

186 2.1. Sub-Threshold Leakage Current (Isub)

R. Udaiyakumar and K. Sankaranarayanan

The Subthreshold conduction or the subthreshold leakage or the subthreshold drain current is the current that flows between the source and drain of a MOSFET when the transistor is operated in subthreshold region due to weak inversion layer (gate-to-source voltages below the threshold voltage). Figure 2 shows sub threshold leakage mechanism in which the gate is driven with zero volts, also Vs and VB are driven with 0 Volts (zero body bias) and VD is kept at 0.9V. Unlike in strong inversion region due to drift current, Sub threshold conduction is dominated by diffusion current. In the past, the subthreshold conduction of transistors has been very small, but as transistors have been scaled down, leakage from all sources got increased. For a technology generation with threshold voltage of 0.2 V, leakage can exceed 50% of total power consumption. The reason for a growing importance of subthreshold conduction is that the supply voltage has continually scaled down, both to reduce the dynamic power consumption of integrated circuits and to keep electric fields inside small devices low, to maintain device reliability. The amount of subthreshold conduction is set by the threshold voltage, which lies between ground and the supply voltage, and so has to be reduced along with the supply voltage [4].
Figure 2: Sub Threshold leakage mechanism
 
Vs=0V VG=0V VD=0.9

n+

ISUB

n+

VB=0V

According to BSIM4 [5], drain current equation in sub-threshold region for short channel MOSFETs can be modeled as
⎡ ⎛ V ⎞⎤ ⎡ V − V th − V O FF ⎤ I sub = I 0 ⎢1 − exp ⎜ − dt ⎟ ⎥ exp ⎢ gs ⎥ nv t ⎝ vt ⎠⎦ ⎣ ⎦ ⎣

(1) (2)

Where I 0 = μ W
L

qs si N dep 2ϕ s

v2 t

Vds is the drain to source voltage, Vt is thermal voltage and equal to KBT/q, Vth is the threshold voltage, VOFF’ is the offset voltage = VOFF + VOFFL/Leff which determines the channel current at Vgs = 0, n is the sub-threshold swing parameter. µ, W, L are mobility, Width and Length of the transistor respectively. Ndep is the substrate doping concentration at depletion edge at Vbs = 0, where Vbs is bulk to source potential. q, εsi, φs are intrinsic charge carrier, permittivity of silicon and surface charge potential respectively.

3. Existing Circuit Level Leakage Reduction Techniques
For a CMOS circuit, the total power dissipation includes dynamic and static components during the active mode of operation. In the standby mode, the power dissipation is due to the standby leakage current. Dynamic power dissipation consists of two components. One is the switching power due to charging and discharging of load capacitance. The other is the short circuit power due to the nonzero

Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits

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rise and fall time of input waveforms. The static power of a CMOS circuit is determined by the leakage current through each transistor [6]. Hence, to suppress the power consumption in low-voltage circuits, it is necessary to reduce the leakage power in both the active and standby modes of operation. The reduction in leakage current has to be achieved using both process and circuit-level techniques. Standby leakage current is the current wasted when the circuit is in idle state while the active leakage current flows when the circuit is in use. At the device level, leakage current can be suppressed by controlling the doping concentration and profile of the semiconductor and carefully changing the physical dimension of transistors. Whereas at the circuit level, leakage current is being effectively kept under control by employing multiple threshold transistors and adopting different biasing schemes for the MOSFETS used in the circuit [710]. Some of the already proposed circuit level leakage current reduction techniques are i) Multi Vth Technique (MTCMOS)[11-15], ii) Super Cut-off CMOS (SCCMOS)[16], iii) Dynamic Threshold Voltage technique (DTCMOS)[17-18], v) Dual Vdd Technique [19-20], vi) Forced Transistor Stacking (FTS)[21-22], vii) Sleepy Stack Transistor insertion Technique (SS)[23-24], viii) Adaptive Body Bias Scheme (ABB)[25-27] and ix) Input Vector Control Technique (IPV)[28]. Whereas at the device level, works were reported previously related to transform the fabrication platform from bulk technology to Silicon On Insulator (SOI) technology with strained silicon[29-30], Separation by Implantation of Oxygen (SIMOX)[31] and fabricating novel devices such as Single Electron Transistor (SET)[32] and Double Gate MOSFET/FinFET[33].

4. Proposed Work
In this paper, a new technique called Dual threshold Transistor Stacking (DTTS) is proposed, which combines the advantages of employing multiple threshold Voltage devices which is a standby mode leakage reduction technique and active mode stacked structure leakage reduction technique. Employing multiple threshold devices for leakage reduction is called as Multi-threshold CMOS (MTCMOS) [1115] technique, in which high threshold voltage MOSFETs are employed to reduce the leakage current. Several MTCMOS techniques like insertion of PMOS only, NMOS only and both PMOS and NMOS were already proposed.
Figure 3: CMOS Inverter with MTCMOS Technique
VbP Vdd Q1 Vsleep Q2 Vin Q4 Vout

Q3 Vsleepba Vss Vbn

A CMOS inverter employed with MTCMOS technique is illustrated In Figure 3. Q1 and Q3 are high threshold PMOS and NMOSFETs respectively. PMOS, NMOS pair of Q2 and Q4 FETs form the basic CMOS inverter designed with nominal threshold value. When sleep signal is high both Q1 and Q3 goes OFF and the CMOS inverter is cut-off from the power supply as it is connected between virtual power rails instead of main power rails. During this sleep mode, both PMOS and NMOS need to

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dissipate lower leakage power hence the high threshold value is desired. When sleep signal is inactive, both Q1 and Q3 are ON and CMOS inverter is connected between Vdd and Vss, hence full logic swing output is obtained. Forced Transistor Technique is based on the fact that natural stacking of MOSFETs helps in achieving reduction of leakage current. Stack effect or Self-Reverse bias effect is the phenomenon where leakage current decreases due to two or more series transistors that are turned off. Figure 4 illustrates this concept.
Figure 4: CMOS inverter with Forced Transistor Stacking (FTS) Technique
Vdd Q1 Q2 Vin Q4 Vout

Q3

Vss

Stacking of transistors is an effective way to reduce leakage power in active mode [21-22]. Leakage is dependent on the voltages of all the four terminals. Transistor stacking technique exploits the dependence of ISUB on the source terminal voltage Vs. If Vs of the transistor is increased, the subthreshold leakage current reduces exponentially. This would happen due to the following reasons: a. The Gate-to-Source voltage Vgs would reduce and if the input applied is grounded, it would turn negative. This would reduce ISUB exponentially. b. Threshold voltage increases due to body effect (Self reverse bias). In this paper, a new technique called Dual Threshold Transistor Stacking (DTTS) is proposed, in which the advantages of the above two techniques are obtained. A topology is designed in which, the MOSFETs which are placed close to the power rails are redesigned with stack effect. The width of the transistor is reduced by half and two transistors are designed out of one. The transistor which is put next to the power rail is designed as a High Threshold transistor by connecting the bulk to a differential potential such that Vsb ≠ 0, to introduce reverse body bias condition. Figure 5 illustrates the circuit topology for the proposed technique.
Figure 5: CMOS Inverter with Dual Threshold Transistor Stacking (DTTS) Technique
VbP Vdd Q1 Q2 Vin Q4 Vout

Q3

Vss VbN

Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits

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5. Experimental Setup
A CMOS Tri-state buffer is considered as a base model. The Circuit for a CMOS Tri-state buffer is illustrated in Figure 6. Six MOSFETs are used to design a simple but full logic swing circuit. Q4 and Q6 are used as dataflow control FETs and Q1 and Q2 forms the basic CMOS inverter. Q3 and Q5 form the output inverter to provide a non-inverted output of given input. All the circuits are designed using 16nm Berkley’s Predictive Technology Model Files [34-35] considering High K dielectric, Metal Gate, Strained silicon, Silicon on Insulator (SOI) technology. Since all the parameters are derived using Berkley Short Channel Insulated Gate FET simulation model, the simulated results are expected to be very close to actual results. For simulation of output waveforms and power estimation, Tanner SPICE v 13.0 is used.
Figure 6: CMOS Tri-State Buffer
V1 Q2 Q5 Q6

Enbar Vin En Q1

Q4 Vout Q3

Figure 7 illustrate the CMOS Tri-state buffer designed with proposed technique. Basic MOSFETs which form the CMOS inverters are reduced to half width size and designed as two MOSFETS instead of one and stacked to introduce the stacking effects. MOSFETs which are near the power rails (Q8, Q9, Q7, and Q10) are designed as High Threshold devices by reverse biasing their source-body (NMOS), body-source (PMOS) connections with Vsb = 0.3V.
Figure 7: DTTS CMOS Tri-State Buffer
V2 V1 Q8 Q2 Q9 Q5 Q6

Enbar Vin En Q1 Q7

Q4 Vout Q3 Q10

V3

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6. Results and Discussion
In this section, snapshot of Simulation results of output waveform for four circuits (conventional, MTCMOS, FTS and proposed) and the leakage power results are given. Figure 8(a) to Figure 11(a) illustrates the simulation output waveforms and Figures 8(b) to 11(b) illustrates the leakage power results. Table 1 gives the performance comparison of various techniques.
Figure 8 (a): Simulation results of CMOS Tri-state buffer Figure 8 (b): Leakage Power results

Figure 9(a): Simulation results of MTCMOS circuit

Figure 9(b): Leakage Power results

Figure 10 (a): Simulation Results of FTS circuit

Figure 10(b): Leakage Power results

Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits
Figure 11(a): Simulation results of proposed technique Figure 11(b): Leakage Power results

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Table 1:

Performance Comparison of various circuit techniques
Pdyn(avg) (in nW) 19.78 09.75 18.43 18.21 Pstatic(avg) (in pW) 97.98 00.87 85.16 76.33 Delay (in ns) 0.107 0.286 1.152 1.113 Power Delay Product (fJ) 0.00211 0.00278 0.02123 0.02026 % reduction Pavg -50.70 06.82 07.93 Pstatic -standby 13.08 22.09

Circuit Description Conventional MTCMOS FTS Proposed

Figure 12: Techniques vs. dynamic power (nW)

Figure 13: Techniques vs. static Power (pW)

Figure 14: Techniques vs. delay (ns)

Figure 15: Techniques vs. PDP (fJ)

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It is observed from that (Table 1), with the conventional design, CMOS Tri-state buffer consumes 19.78nW of power during active mode and when the inputs are static, the power consumption is reduced to 97.98pW. When MTCMOS technique is employed the static power is reduced considerably during standby mode to 00.87pW against the average power of 9.75nW. Forced Transistor Stacking method reduces the average power to 18.43nW against 19.78nW consumed by conventional buffer but static power reduction is very much lower when compared to MTCMOS technique. Proposed method consumes less average and static power when compared to forced transistor stacking method and also delay involved is lower when compared to forced transistor stacking. The power delay product is 0.02026fJ (femto Joules) for the proposed case where it is 0.02123fJ for FTS technique. Various bar charts are given in Figures 12-15.

7. Conclusion
From the results, it is evident that the proposed method consumes the lowest leakage power without sacrificing the delay when compared to FTS technique. By observing the simulation results of output waveform, all these reduction techniques affect the delay and the best value (0.107 ns) is reported with conventional circuit and worst case (1.152 ns) is reported with the FTS technique. But in case of static power consumption, proposed method (DTTS) consumes lesser static power (76.33pW) against FTS technique which consumes (95.70 pW). Proposed technique does not demand for any area penalty when compared to FTS technique. Hence the proposed method may be considered as an alternate for FTS technique and suitable when the speed performance is non-critical compared to static power dissipation.

Acknowledgements
Authors thank the SKCT management and acknowledge the immense help received from the scholars whose articles are cited and included in references of this manuscript. The authors are also grateful to authors / editors / publishers of all those articles, journals and books from where the literature for this article has been reviewed and discussed.

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