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DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit

June 1992

DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit
General Description
The ’LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations

Features
Y Y

Y

Provides 16 arithmetic operations add subtract compare double plus twelve other arithmetic operations Provides all 16 logic operations of two variables exclusive-OR compare AND NAND OR NOR plus ten other logic operations Full lookahead for high speed arithmetic operation on long words

Connection Diagram
Dual-In-Line Package

TL F 9821 – 1

Order Number DM54LS181J DM54LS181W or DM74LS181N See NS Package Number J24A N24A or W24C

Pin Names A0 – A3 B0 – B3 S0–S3 M Cn F0– F3 AeB G P Cn a 4

Description Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output

C1995 National Semiconductor Corporation

TL F 9821

RRD-B30M115 Printed in U S A

Absolute Maximum Ratings (Note)
Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS Storage Temperature Range 7V 7V 0 C to a 70 C
b 65 C to a 150 C

Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation

Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature
b 55

DM54LS181 Min 45 2 07
b0 4

DM74LS181 Min 4 75 2 08
b0 4

Units Max 5 25 V V V mA mA C

Max 55

Nom 5

4 125 0

8 70

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH Parameter Input Clamp Voltage High Level Output Voltage VOL Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC e Min IOH e Max VIL e Max VCC e Min IOL e Max VIH e Min IOL e 4 mA VCC e Min II Input Current Input Voltage Max VCC e Max VI e 7V VI e 10V (DM54) DM54 DM74 DM54 DM74 DM74 M input An Bn Sn Cn M input An Bn Sn Cn M input An Bn Sn Cn
b 20

Min

Typ (Note 1)

Max
b1 5

Units V V

25 27 04 0 35 0 25 05 04 01 03 04 05 20 60 80 100
b0 4 b1 2 b1 6 b2 0 b 100

V

mA

IIH

High Level Input Current

VCC e Max VI e 2 7V

mA

IIL

Low Level Input Current

VCC e Max VI e 0 4V

mA

IOS ICC

Short Circuit Output Current Supply Current

VCC e Max (Note 2) VCC e Max Bn Cn e GND Sn M An e 4 5V DM54 DM74

mA mA

35 37

Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second

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Switching Characteristics
DM54 DM74LS Symbol Parameter Conditions Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Cn a 4 Propagation Delay Cn to F Propagation Delay A or B to G (Sum) Propagation Delay A or B to G (Diff) Propagation Delay A or B to P (Sum) Propagation Delay A or B to P (Diff) Propagation Delay Ai or Bi to Fi (Sum) Propagation Delay Ai or Bi to Fi (Diff) Propagation Delay A or B to F (Logic) Propagation Delay A or B to Cn a 4 (Sum) Propagation Delay A or B to Cn a 4 (Diff) Propagation Delay A or B to A e B M e GND M e GND M S1 S2 e GND S1 S3 e 4 5V M S0 S3 e GND S1 S2 e 4 5V M S1 S2 e GND S0 S3 e 4 5V M S0 S3 e GND S1 S2 e 4 5V M S1 S2 e GND S0 S3 e 4 5V M S0 S3 e GND S1 S2 e 4 5V M e 4 5V M S1 S2 e GND S0 S3 e 4 5V M S0 S3 e GND S1 S2 e 4 5V M S0 S3 e GND S1 S2 e 4 5V RL e 2 kX to 5 0V CL e 15 pF Max 27 20 26 20 29 23 32 26 30 30 30 33 32 25 32 33 33 29 38 38 41 41 50 62 ns ns ns ns ns ns ns ns ns ns ns ns Units

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Sum Mode Test Table I
Symbol Input Under Test

Function Inputs S0 e S3 e 4 5V
Other Input Same Bit Apply 4 5V Bi Ai B A None None None None None Apply GND None None None None B A B A None

S1 e S2 e M e 0V Output Under Test

Other Data Inputs Apply 4 5V Remaining A and B Remaining A and B None None Remaining B Remaining B Remaining B Remaining B All A Apply GND Cn Cn Remaining A and B Cn Remaining A and B Cn Remaining A Cn Remaining A Cn Remaining A Cn Remaining A Cn All B S0 e S3 e M e 0V

tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL

Ai Bi A B A B A B Cn

Fi Fi P P G G Cn a 4 Cn a 4 Any F or Cn a 4

Diff Mode Test Table II
Symbol Input Under Test

Function Inputs S1 e S2 e 4 5V
Other Input Same Bit Apply 4 5V None A None A B None None A B None None Apply GND B None B

Other Data Inputs Apply 4 5V Remaining A Remaining A None None None None Remaining A Remaining A None None All A and B 4 Apply GND Remaining B Cn Remaining B Cn Remaining A and B Cn Remaining A and B Cn Remaining A and B Cn Remaining A and B Cn Remaining B Cn Remaining B Cn Remaining A and B Cn Remaining A and B Cn None

Output Under Test

tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL

A B A B A B A B A B Cn

Fi Fi P P G G AeB AeB Cn a 4 Cn a 4 Cn a 4

None None A B None None A None

Logic Mode Test Table III
Symbol Input Under Test

Function Inputs S1 e S2 e M e 4 5V
Other Input Same Bit

S0 e S3 e 0V Output Under Test

Other Data Inputs Apply 4 5V None None Apply GND Remaining A and B Cn Remaining A and B Cn

Apply 4 5V B A

Apply GND None None

tPLH tPHL tPLH tPHL

A B

Any F Any F

Functional Description
The ’LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU) Controlled by the four Function Select inputs (S0 – S3) and the Mode Control input (M) it can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands The Function Table lists these operations When the Mode Control input (M) is HIGH all internal carries are inhibited and the device performs logic operations on the individual bits as listed When the Mode Control input is LOW the carries are enabled and the device performs arithmetic operations on the two 4-bit words The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn a 4 output or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate) In the ADD mode P indicates that F is 15 or more while G indicates that F is 16 or more In the SUBTRACT mode P indicates that F is zero or less while G indicates that F is less than zero P and G are not affected by carry in When speed requirements are not stringent it can be used in a simple ripple carry mode by connecting the Carry output (Cn a 4) signal to the Carry input (Cn) of the next unit For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit One carry lookahead package is required for each group of four ’LS181 devices Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths The A e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode The A e B output is open-collector and can be wired-AND with other A e B outputs to give a comparison for more than four bits The A e B signal can also be used with the Cn a 4 signal to indicate A l B and A k B The Function Table lists the arithmetic operations that are performed without a carry in An incoming carry adds a one to each operation Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied Because subtraction is actually performed by complementary addition (1s complement) a carry out means borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow As indicated this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs For either case the table lists the operations that are performed to the operands labeled inside the logic symbol

Function Table Mode Select Inputs S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H Active LOW Operands Fn Outputs Logic (M e H) A AB AaB Logic 1 AaB B AZB AaB AB AZB B AaB Logic 0 AB AB A Arithmetic (M e L) (Cn e L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A a B) AB plus (A a B) A minus B minus 1 AaB A plus (A a B) A plus B AB plus (A a B) AaB A plus A AB plus A AB minus A A Active HIGH Operands Fn Outputs Logic (M e H) A AaB AB Logic 0 AB B AZB AB AaB AZB B AB Logic 1 AaB AaB A Arithmetic (M e L) (Cn e H) A AaB AaB minus 1 A plus AB (A a B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A a B) plus AB AB minus 1 A plus A (A a B) plus A (A a B) plus A A minus 1

Each bit is shifted to the next most significant position Arithmetic operations expressed in 2s complement notation

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Logic Symbols
Active High Operands

TL F 9821 – 3

Active Low Operands

TL F 9821 – 4

VCC e Pin 24 GND e Pin 12

6

Logic Diagram

7

TL F 9821 – 5

8

Physical Dimensions inches (millimeters)

Package (J) Order Number DM54LS181J NS Package Number J24A

24-Lead Molded Dual-In-Line Package (N) Order Number DM74LS181N NS Package Number N24A

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DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit

Physical Dimensions inches (millimeters) (Continued)

Package (W) Order Number DM54LS181W NS Package Number W24C

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