# Mount Zion College of Engineering & Technology

To Make Man Whole!!
An ISO 9001:2008 Certified Institution

Encl. 35 a. : QUESTION BANK EC2203
UNIT I TB 1 TB 2 TB 3 TB 4 Qs. No. TLP No.1 1. 2. 3. 4. 5. 6. 7. 8. TLP No.2 9. 10. 11. 12. 13. 14.

DIGITAL ELECTRONICS
MINIMIZATION TECHNIQUES AND LOGIC GATES

M.Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003. S.Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas Publishing House Pvt. Ltd, New Delhi, 2006 John F. Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006 A.P.Godse and D.A.Godse, Digital electronics Ans Textbook Questions Page Mark No. Nos. MINIMIZATION TECHNIQUES - BOOLEAN POSTULATES AND LAWS

State and prove Commutative Law. What is identity element? Give example. State and prove Associative Law. State and prove Distributive law. Demonstrate by means of truth tables the validity of the following identity: the distributive law : x + yz = ( x + y ) ( x + z ) What are the basic laws of Boolean algebra Prove that AB + BC + BC = AB + C Complement the expression AB + CD
DE – MORGAN’S THEOREM

TB 1 TB 1 TB 1 TB 1 TB 1 TB 1 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2

34 34 33 33 37 33 45 45 44 44 44 46 44 44

(2) (2) (2) (2) (2) (2) (2) (2) (2) (8) (2) (4) (10) (16)

15. TLP No.3 16. 17. TLP No.4 18. TLP No.5 19. TLP No.6 20. 21. 22. 23. 24. TLP No.7 25. 26. 27. 28. 29. 30. TLP No.8 31. 32.

State De – Morgan’s Theorem. State De – Margon’s Theorems which convert a sum into a product form and vice versa. Prove De - Morgan’s theorem for a 4- variable function. Simplify the expression ((AB’ + ABC )’ + A ( B + AB’))’ Apply DeMorgan’s Theorem to each of the given expressions: (a) (A(B+C))’ (b) (AB)’ + (CD)’ (c) (AB + CD)’ (d) (A+B’) (C’ + D) Apply DeMorgan’s theorem to the given expressions : (a) ((AB’)+(C+D’))’ (b) (AB(CD+EF))’ (c) ((A+B’+C+D’)’ + (ABCD’)’) (d) ((A’+B+C+D)’ + (AB’C’D)’)’ (e) ((AB)’(CD + E’F)((AB)’+(CD)’))’ If A’B + CD’ = 0, then prove that AB + C’ ( A’ + D’ ) = AB + BD + B’D’ + A’C’D
PRINCIPLE OF DUALITY

TB 2 TB 2 TB 2

49 44 44 113 39 50 50 51 51 52 52 52 53 53 54 54

(8) (2) (2) (8) (2) (8) (2) (2) (4) (4) (8) (2) (2) (4) (4) (8) (2) (2)

State Principle of Duality. What is Dual expression
BOOLEAN EXPRESSION

What is Boolean expression? Give examples
MINIMIZATION OF BOOLEAN EXPRESSIONS

TB 1 TB 2 TB 2 TB2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2

State the methods used to simplify the equations
MINTERM

Explain Minterm What is Minterm? What is Minterm canonical form? What are the steps followed to obtain canonical sum of product form of a logic function? Obtain the canonical sum of product form of the function Y (A,B,C) = A+ BC
MAXTERM

Explain Maxterm What is Maxterm What is Maxterm canonical form? What are the steps followed to obtain canonical Product of Sum form of a logic function? Obtain the canonical sum of product form of the function Y (ABC) = (A+B’)(B+C)(A+C’) Express the function Y = A+B’C in (a) Canonical SOP and (b) Canonical POS form
SUM OF PRODUCTS (SOP)

What is Sum of Products (SOP) Define Product term

TB 2 TB 2

50 50

Pilivalam P.O, Pudukkottai Dt., Tamil Nadu. Pin - 622 507, Fax: 04333 – 277125, Ph: 04322 - 320801, 320802, Website: www.mzcet.in, Email: info@mzcet.in Page 1 of 3

Mount Zion College of Engineering & Technology
To Make Man Whole!!
An ISO 9001:2008 Certified Institution

Encl. 35 a. : QUESTION BANK EC2203
UNIT I 33. 34. TLP No.9 36. 37. TLP No.10 38. 39. TLP No.11 40. 41. 42.

DIGITAL ELECTRONICS
MINIMIZATION TECHNIQUES AND LOGIC GATES

Define Sum term Derive the Sum of Product (SOP) expressions from a truth table
PRODUCT OF SUM (POS)

TB 2 TB 2 TB 2 TB 2 TB 2 TB 2

50 55 50 55 59 59

(2) (8) (2) (8) (8) (8)

What is Product of Sum (POS) Derive the Product of Sum (SOP) expressions from a truth table
KARNAUGH MAP

Simplify the following expression using the Karnaugh Map for the 4 – Variables A, B, C, D. Y = m1 + m2 + m3 + m5 + m7 + m8 + m9 + m12 + m13 Using the K – map method, obtain the minimal sum of product expression of the following function. Y = Σ( 0, 2,3,6,7,8,10,11,12,15)
DON’T CARE CONDITIONS

What are don’t care combinations? What are incompletely simplified functions? Determine don’t care condition in the following Boolean expression BE + B’DE’ which is a simplified version of the expression A’BE + BCDE + BC’D’E + A’B’DE’ + B’C’DE’
QUINE – McCLUSKEY METHOD OF MINIMIZATION

TB 2 TB 2 TB 2

65 65 65

(2) (2) (16)

43. 44.

What are the steps followed in the Quine – McCluskey method of minimization Find the minimal sum of Products for the Boolean expression, f = Σ(1,2,3,7,8,9,10,11,14,15), using the Quine – McCluskey method of minimization
LOGIC GATES: AND, OR, NOT, NAND, NOR, EXCLUSIVE–OR AND EXCLUSIVE–NOR

TB 2 TB 2

67 68

(2) (16)

TLP NO.12 45. 46. 47. 48. 49. 50. 51. 52. TLP NO.13 53. 54. 55. 56. 57. 58. TLP NO.14 59. 60. 61. 62. 63. 64. 65. 66. 67. 68.

Write the truth table and logic symbol of a three – input OR gate. What is the only condition under which an OR gate output will be 0? Under what conditions will the output of an AND gate be 0? Write the expression for a 4-input AND gate. Construct the complete truth table showing the output for all possible cases. Differentiate positive and negative logic system Define the NAND and NOR gates through their truth tables Explain the function of an OR gate using diodes? Explain the function of an AND gate using diodes.
IMPLEMENTATIONS OF LOGIC FUNCTIONS USING GATES

TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB2 TB 2 TB 2 TB 2

79 79 81 81 77 82 78 80 77 87 90 88 84 84 84 85 87 78 81 78 82 89 89 86

(2) (2) (2) (4) (2) (4) (6) (6) (8) (8) (2) (8) (4) (4) (6) (6) (8) (8) (3) (6) (6) (2) (2) (12)

What is a logic gate? Explain logic designation. Draw the logic diagram of an Ex-OR gate and discuss its operation. What is an Ex-NOR gate? Write its truth table. Using only NAND gates, design a circuit to provide an output of logic1 when only one of three inputs is logic 1. Explain the term “Universal Gates”. Name the gates that are used as universal gates. Explain.
NAND–NOR IMPLEMENTATIONS

69.

Explain how the basic gates can be realized using NAND gates. Explain how the basic gates can be realized using NOR gates. Give the action of the 2- input Ex-OR gate and construct it using NAND gates. Write a short note on Logic gates. Explain the transistor inverter circuit and verify its truth table. Verify that the following operations are commutative and associative (a) AND, (b) OR, (c) Ex-OR Verify that the following operations are commutative but not associative (a)NAND, (b) NOR Realise the logic expression Y=A B C using Ex-OR gates. Realise the logic expression Y=A B C D using Ex-OR gates. State and explain DeMorgan’s theorems which transform a sum into a product form and vice versa. Draw the logic equivalent circuits representing the theorems using basic gates. Obtain the minimal sum of products expression for the following function and implementation the same using universal gates. F(A,B,C,D)=Σ(0,2,3,5,7,8,13)+Σd (1,6,12)

TB 2

54,92

(12)

Pilivalam P.O, Pudukkottai Dt., Tamil Nadu. Pin - 622 507, Fax: 04333 – 277125, Ph: 04322 - 320801, 320802, Website: www.mzcet.in, Email: info@mzcet.in Page 2 of 3

Mount Zion College of Engineering & Technology
To Make Man Whole!!
An ISO 9001:2008 Certified Institution

Encl. 35 a. : QUESTION BANK EC2203
UNIT I 70.

DIGITAL ELECTRONICS
MINIMIZATION TECHNIQUES AND LOGIC GATES

71. 72. 73. 74. 75. 76. 77. 78. TLP NO.15 79. 80. TLP NO.16 81. 82. TLP NO.17 83. 84. 85. TLP NO. 18 86.

Obtain the minimal sum of products expression for the following function and implementation the same using NAND gates. F(A,B,C,D)=Σ(1,4,7,8,9,11)+Σd (0,3,5) Draw a logic circuit for the following function using NOR gates. (A+B)(B+C)(A+C) What is mixed logic? Compare positive, negative and mixed logics. Give the mixed logic symbol pairs of AND, OR, and NOT gates. Draw the alternate gate symbols for basic and universal gates. Explain the concept of mixed logic with necessary diagrams. Explain assertion levels. How polarities can be indicated in different ways?
MULTI LEVEL GATE IMPLEMENTATIONS

TB 2

54,92

(12)

TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2 TB 2

91 95 77,95 97 97 75 98 98 99 100 99, 108 102

(4) (2) (6) (6) (8) (12) (10) (2) (2) (2) (4) (8)

What is level of a gate network? What are the advantages and disadvantages of multilevel gate network?
MULTI OUTPUT GATE IMPLEMENTATIONS

Differentiate multilevel and multi- output gate networks. Write down the procedure to convert a given multilevel AND-OR gate network to all NAND gates network.
TTL AND CMOS LOGIC AND THEIR CHARACTERISTICS

Write notes on i. Noise immunity ii. Fan-out iii. Transition times Propagation delays Write down the TTL parameters. Write down the TTL output connections TRISTATE GATES What is a tri-state gate?

iv.

TB 2 TB 2 TB 2 TB 2

114 128 125 127

(10) (2) 2 (2)

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Pilivalam P.O, Pudukkottai Dt., Tamil Nadu. Pin - 622 507, Fax: 04333 – 277125, Ph: 04322 - 320801, 320802, Website: www.mzcet.in, Email: info@mzcet.in Page 3 of 3