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ELE 312 Digital Electronics

Textbooks
DeMassa and Ciccone, Digital Integrated Circuits, John Wiley & Sons. Taub and Schilling, Digital Integrated Electronics, McGraw-Hill

Contents
Basic Properties of Digital Integrated Circuits Diode Digital Circuits BJT Digital Circuits
Ebers & Moll equations Transistor modelling State of transistor in a circuit

Resistor-Transistor Logic (RTL) Diode-Transistor Logic (DTL) Transistor-Transistor Logic (TTL) Schottky Transistor Transistor Logic (STTL) Different TTL Gates Emitter-Coupled Logic (ECL) MOS Digital Circuits NMOS Gates CMOS Gates

Properties of Digital Integrated Circuits

Most important elements: Inverter and Noninverter

Idealized Inverter and Voltage Transfer Characteristics( VTCs)

Propagation Delays

Rise and fall times and turn-on and turn-off times

Power dissipation

Logic Element Equivalent Circuit and Fan-out

Power - Delay Product:

Speed-power product = (Average Power Diss) x (Propagation Delay)

PD = PDISS(avg) x tP(avg)

Diode Digital Circuits

Diodes

Shockleys Eq

I D = IS (e VD /VT 1)

for Forward Bias VD V0 = 0.7 V

IV Characteristics

for PN Junction diodes

for MN Schottky diodes

SPICE model

ID = IS (e VD /VT 1)

Basic Logic Gates: AND

Basic Logic Gates: OR

Clamping Diodes

Level shifting diodes

Level Shifting Diode AND Gate

Level Shifting Diode OR Gate

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BJT Transistors

BJT Fabrication Example

Multi-Emitter Fabrication Examples

NPN BJT

Ebers-Moll NPN BJT Model


I E = I D ,BE R I D ,BC I C = F I D ,BE I D ,BC
IB = IE IC

I D ,BE = I ES (e VBE / VT 1) I D ,BC = I CS (e VBC / VT 1)

Reciprocity theorem

IS = F I ES = R I CS
transport saturation current

BJT Modes of Operation


BE junction Reverse Forward Forward Reverse BC junction Reverse Reverse Forward Forward Cutoff Mode
(OFF)

Forward active (FA) Saturation (SAT) Reverse active (RA)

Reduced models of the operation modes


F =
1F

(a) Cutoff
I C = F I B

(b) Forward active

R =

1R

(c) Saturation

(d) Reverse active

IV Characteristics

Modes of Operation

Examples

F = 65 IC, IB = ?

Base and emitter voltages = ?

TTL Circuit Design

Output-High Pull-up Driver

Output-Low Pull-down Driver

Discharge path and Base-Driving circuitry

Power Dissipation Example

Resistor-Transistor Logic (RTL)

INVERTER

Voltage Transfer Characteritics (VTC)

VIL = VBE ( FA )

VIH = VBE (SAT ) +

VCC VCE (SAT )

FR C

RB

NAND

NOR

RTL Fan-out

RTL fan-out analysis

RTL fan-out analysis

Maximum fan-out?
I N = OUT I IN

I OUT =

VCC VOUT RC

I IN =

VOUT VBE (SAT ) RB

VOUT = VIH
VCC VCE (SAT )

VIH = VBE (SAT ) +

FR C

RB

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RTL NONINVERTER

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AND

OR

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RTL with Active Pull-up

Fan-out of RTL with Active Pull-up


Determined by the output high state as QS is cut-off for low-inputs

Simplified output high state

Simplified input high state

Simplified output-high fan-out configuration

I OUT = I EP

VCC VCE (SAT ) VOUT R CP

I N = OH I IH

VOUT (min) = VIH

I IN =

VOUT VBE (SAT ) RB / 2

VIH = VBE (SAT ) +

VCC VCE (SAT )

FR C

RB

Diode-Transistor Logic (DTL)

Basic DTL Inverter

Basic DTL NAND Gate

Diode Modified DTL Inverter

Transistor Modified DTL Inverter

VTC of Transistor Modified DTL Inverter

VOH = VCC VOL = VCE,O(SAT)

VIL = VBE,O(FA) + VBE,L(FA) VIH = VBE,O(SAT) + VBE,L(FA)

DTL Fan-out

Determined by the output low state as DI is off for high-inputs

Cascaded DTL

I OL = I C,O (SAT ) I RC

I B,O = I E ,L I RD

I N = OL I IL

I RC =

VCC VCE ,O (SAT ) RC

I RD =
Path 2
I E ,L I IL =

VBE ,O (SAT ) RD
R B
RB

VCC VBE ,L ( FA ) VD ,L ( ON ) VBE ,O (SAT )

I C ,O (SAT ) = F I B,O (SAT )


For maximum fan-out = 1

VCC VD ,I ( ON ) VCE ,O (SAT )

Path 3

Example: Calculate the DTL fan-out for F = 49 and = 0.85.

Power Dissipation

Example: Calculate the average power dissipation for the above example?

Tansistor-Transistor Logic (TTL)

Basic TTL Inverter

Basic DTL Inverter (compare)

Basic TTL NAND Gate

Actual TTL NAND Gate with Totem Pole Output

VTC of an actual TTL Inverter

VOH = VCC VBE,P(FA) VD,L(ON) VOL = VCE,O(SAT)


VOB = VCC IRCRC VBE,P(FA) VD,L(ON)
I RC = I RD = VBE ,O ( FA ) RD

VIL = VBE,S(FA) VCE,I(SAT)) VIH = VBE,O(SAT) + VBE,S(SAT) VCE,I(SAT) VIB = VBE,O(FA) + VBE,S(FA) VCE,I(SAT)

States of diodes and BJTs

EOC: Edge of conduction

TTL Fan-out

Determined by the output low state as QI is cut-off for high-inputs

Cascaded TTL
Path 1
I IL = VCC VBE ,I (SAT ) VCE ,O (SAT ) RB

I E ,S(SAT ) = I B,S + I C,S


I OL = I C,O (SAT ) = F I B,O (SAT )
I C ,S = VCC VCE ,S(SAT ) VBE ,O (SAT ) RC

I N = OL I IL

I B,O (SAT ) = I E ,S(SAT ) I RD


I RD = VBE ,O (SAT ) RD

Path 2

I B,S = I C,I ( RA ) = (1 + R )I B,I


I B, I = VCC VBC,I ( RA ) VBE ,S(SAT ) VBE ,O (SAT ) RB

For maximum fan-out = 1

Example (TTL Fan-out) Example: Calculate the TTL fan-out for F = 25, = 0.85 and R = 0.1
IRB(OL) = 675 A IRC(OL) = 2.5 mA IIL= IRB(OH) = 1 mA IOL= 51.9 mA
I N = OL = 51 I IL

Example (Power Dissipation) Example: Calculate the average power dissipation for the above example?
PCC(avg) = 10.4 mW

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Open-Collector TTL

Mostly used in data busses where multiple gate outputs must be ANDed.
This can be accomplished by using a single pull-up resistor with open-collector TTL gates This type of connection is referred to as wired-AND.

Low Power TTL (LTTL)

Accomplished simply by increasing the resistance values. However this results in


Decreased fan-out Longer transient-response times

LTTL Example

Compare the power dissipation of the LTTL and TTL gates. IRB(OL) = 67.5 A IRC(OL) = 200 A TTL vs LTTL power dissipation ratio = 10.4 / 0.919 = 11.3 IRB(OH) = 100 A PCC(avg) = 919 W

High Speed TTL (HTTL)

Accomplished simply by decreasing the resistance values. However this results in


Increased power dissipation

Schottky Tansistor-Transistor Logic (STTL)

Schottky Barrier MN diode

Schottky-clamped BJT (Schottky Transistor)

Multi-Emitter Fabrication Examples

Modes of Operation for SBJT 1. 2. 3. 4. OFF FA On Hard Reverse Schottky

Example (SBJT)
Example: Draw the VTC graph of the SBJT inverter shown below

STTL NAND Gate

STTL NAND Gate (VTC)

VOH = VCC VBE,P(FA) VBE,P2(FA) VOL = VCE,O(HARD)

VIL = VBE,O(FA) + VBE,S(FA) VCE,I(HARD) VIH = VBE,O(HARD) + VBE,S(HARD) VCE,I(HARD)

STTL NAND Gate (Device states)

Device state table

STTL Fan-out

Determined by the output low state as QI is cut-off for high-inputs

Cascaded STTL
Path 1
I IL = VCC VBE ,I ( HARD) VCE ,O ( HARD) RB

I E ,S( HARD) = I B,S + I C,S


I OL = I C,O ( HARD) = F I B,O ( HARD)
I C ,S = VCC VCE ,S( HARD) VBE ,O ( HARD )

RC I N = OL I B,O ( HARD) = I E ,S( HARD) I C,D ( HARD) Path 2, 3 I B,S = I C,I ( RS) = ISBD I IL V V
I C ,D ( HARD ) =
BE ,O ( HARD ) CE , D ( HARD )

R CD

ISBD =

VCC VBC,I ( RS) VBE ,S( HARD) VBE ,O ( HARD) RB

Example (TTL Fan-out) Example: Calculate the STTL maximum fan-out for F = 49.
IRB(OL) = 1.11 mA IRC(OL) = 4.11 mA IRCD(OL) = 1.20 mA IE,S(OL) = 4.22 mA IR,O(OL) = 4.02 mA IOL= 197 mA IIL= IRB(OH) = 1.32 mA
I N = OL = 149 I IL

Example (Power Dissipation) Example: Calculate the average power dissipation for the above example?
IE,P(OL) = 0.182 mA IE,P(OH) = 1.3 mA PCC(avg) = 20.05 mW

Low Power STTL (LSTTL)

Accomplished by 1. Increasing the resistance value 2. Diode input section 3. Pull-down enhancements

Low Power STTL (LSTTL)

LSTTL Example

Compare the power dissipation of the LSTTL and STTL gates. IRB(OL) = 170 A IRC(OL) = 463 A STTL vs LSTTL power dissipation ratio = 20.05 / 2.11 = 9.5 IRB(OH) = 210 A PCC(avg) = 2.11 mW

Advanced Schottky TansistorTransistor Logic (ASTTL)

Advanced Schottky Transistor Logic


Advanced Low-Power Schottky TTL (ALSTTL) Fairchild Advanced Schottky TTL (FAST) Advanced Schottky TTL (ASTTL)

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ALSTTL

ALSTTL VTC

VOH = VCC VBE,P(FA) VOL = VCE,O(HARD) VIL = VBE,O(FA) + VEB,IPA(FA) VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VBE,IPA(FA)

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ALSTTL VTC

FAST

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FAST VTC

VOH = VCC VBE,P(FA) VOL = VCE,O(HARD) VIL = VBE,O(FA) + VBE,S(FA) + VBE,SB(FA) VD,IA(ON) VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VD,IA(ON)

ASTTL

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ASTTL

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Other TTL Gates

Other TTL Gates

AND gates NOR gates OR gates AND-OR-INVERT (AOI) gates XOR gates Schmitt Trigger Inverters and NAND gates Tri-State buffers

TTL AND gate

TTL AND gate - VTC

TTL NOR gate

TTL NAND gate

Power Dissipation Example


IRB(IL) = 1 mA ICC(LL) = 2 mA ICC(HL) = 4.175 mA IRB(IH) = 675 A ICC(LH) = 4.175 mA ICC(HH) = 3.85 mA PCC(avg) = 17.75 mW IRC(OL) = 2.5 mA

TTL OR gate

Example: Noise margins VNMH , VNML?

TTL AND gate

Complex Logic TTL Gate Design 1. ANDing of signals Multi-emitter input BJT sections 2. ORing of signals Multiple input sections (QI and RB) Multiple drive splitting BJTs (QS) 3. If non-inverting ORing is desired Addional logic inversion circuitry 4. Totem-pole output branch

AND-OR-INVERT (AOI) gate

Example Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF

Example Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF

TTL XOR gate

Hysteresis and Schmitt Trigger Gates

Hysteresis

Hysteresis Base-Emitter coupled Schmitt Trigger Non-inverting circuit

VOHS = VCC
VCC VBE (SAT ) VCC VCE (SAT ) VOLS = R eq + VCE (SAT ) R CS1 R CS2

VCC VBE (SAT ) VCC VCE (SAT ) R eq + VBE ,S1( FA ) VIUS = R CS1 R CS2

VIDS =

VCC + VBE ,S1(SAT ) VBE ,S2 ( FA )


= R CS1 +1 RE

R eq = R CS1 || R CS 2 || R E

Example

Find the VOHS, VOLS, VIUS and VIDS points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.

VOHS = 5V

Req = 606 ICS1 = 1.05mA ICS1 = 1.92mA

VOLS = 2V

VIUS = 2.5V VIDS = 1.66V

TTL Schmitt Trigger NAND gate

Example

Find the VOH, VOL, VIU and VID points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.

VOH = 3.6V VOL = 0.2V

VIUS = 2.5V VIDS = 1.66V

VIU = 1.8V VID = 0.96V

TTL Tri-state Buffers

TTL Tri-state Buffers

Connecting TTL Tri-state buffers to a Bus

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Emitter-Coupled Logic (ECL)

Basic ECL Inverter/Non-inverter (ECL Current Switch)

Basic ECL Inverter/Non-inverter VTC

According to inverting output: VINV VOH = VCC


V OL = V CC V IH V BE ( ECL ) + V EE RE

VIL = VBB 0.05 VIH = VBB + 0.05


V CC + V BC ( SAT ) +

R CI VS =

R CI ( V BE ( SAT ) V EE ) RE R 1 + CI RE

Example

Calculate the critical VTC points for the ECL current switch VCC = 5V, VEE = 0V, VBB = 2.6V, RCI = RCR = RE = 1k, VBE(ECL) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V
VOH = 5V VOL = 3.10V VIL = 2.55V VIH = 2.65V VS = 3.2V VINV (VIN = VS) = 2.6V

Basic ECL NOR/OR Gate

MECL I NOR/OR Gate

V OH = V OL =

V EE V BE ( ECL ) R CI + ( F + 1) R DN RE

R CI V BE ( ECL ) R CI V BE ( ECL )

V IH V BE ( ECL ) + V EE

Example

Find the logical swing, noise margins and noise immunities for the MECL I circuit above. F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V VOH = 0.76V VOL = 1.55V VLS = 0.79V VIL = 1.225V VIH = 1.125V VNMH = 0.365V VNML = 0.325V VNIH = 0.53V VNIL = 0.475V VS = 0.29V

MECL I Fanout

I OH = I E ,BN ( FA ) I RDN

I N = OH I IH

I RDN =

VOH + VEE R DN I E ,BN ( FA ) = ( F + 1)I B,BN VOH VBE ,BN ( ECL ) I B,BN = R CI

I IH = I RE =

I RE F +1 VE + VEE RE

VE = VOH VBE ( ECL )

Fan-out Example

Find the maximum fan-out for the MECL I circuit above F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V Assume load gates reduce VOH by 0.03 volts. VOH = 0.79V IRDN = 2.205 mA IB,BN = 148 A IE,BN = 7.4 mA IOH = 5.2 mA VE = -1.54 V IRE = 2.95 mA IIH = 59 A

I N = OH = 87 I IH

Power Dissipation Example

Find the average power dissipated in the MECL I circuit above IRE(NOH) = 2.64 mA IRDN(NOH) = 2.22 mA IRDO(NOH) = 1.825 mA IEE(NOH) = 6.685 mA IRE(NOL) = 2.98 mA IRDN(NOL) = 1.825 mA IRDO(NOL) = 2.22 mA IEE(NOL) = 7.035 mA PEE(avg) = 35.6 mW

Other ECL Gates

DeMorgans Theorems
NOR and OR using ANDs and NANDs NOR: OR:
A + B = AB

A + B = AB

NAND and AND using ORs and NORs NAND: AND:


AB = A + B

AB = A + B

Example
Implement the following logic using only ECL gates
(A + B)(C + D)

Solution:
(A + B)(C + D) (A + B) + (C + D)

Collector Dotting Wired-AND Gates

Complex Logic Gates with Collector Dotting

Example

Series Gating Basic ECL NAND/AND Current Switch

Series Gating NAND/AND Gate

Complex Logic Gates with Series Gating

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Example

ECL XOR/XNOR Gates

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ECL Decoding Tree

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MOS Logic

MOS Logic

NMOS gates Fabrication Modes of operation NMOS Inverters and Analysis General NMOS Inverter Resistor Loaded NMOS Inverter E-MOSFET loaded NMOS Inverter D-MOSFET loaded NMOS Inverter

NMOS (n-channel E-MOSFET) Fabrication Examples

CMOS Fabrication Example

IV Characteristics

NMOS modes of operation

(a) Cutoff mode

(b) Linear mode

(c) Saturation mode

(d) body-bias effect on threshold voltage

General NMOS Inverter

Graphical analysis when load is a resistor

Load capacitance

Power dissipation

(a) Static power dissipation PDD = VDD (IDD(OH) + IDD(OL)) / 2 VDD IDD(OL) / 2 PTOTAL = PDD + PD (b) Transient power dissipation PD = CL V2DD : frequency at which the gate is switched

Resistor Loaded NMOS

Resistor Loaded NMOS Inverter

Propagation Delay

Fall time

E-MOSFET Loaded NMOS

E-MOSFET Loaded NMOS Inverter

D-MOSFET Loaded NMOS

D-MOSFET Loaded NMOS Inverter

NMOS Gates

Symbol Shorthands

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NOR Gate

NOR Gates

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NAND Gate

WO kO = L +L B A

VOL ( NAND) > VOL (Inverter)

OR Gates

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AND Gates

Example

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AOI (AND-OR-INVERT) Gates

Examples

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XOR/XNOR Gates

Hysteresis

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Schmitt Trigger

Transmission Gate

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Transmission Gate Array

CMOS Logic

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CMOS Inverter

CMOS Inverter

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Symmetric CMOS Inverter

Capacitance Effect on Transition - 1

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Capacitance Effect on Transition - 2

Electrostatic Discharge (ESD) Protection

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CMOS Gates

Symbol Shorthands

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CMOS NAND Gate

CMOS NAND Gates

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CMOS NOR Gate

CMOS NOR Gates

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CMOS AND/NAND Gate

CMOS OR/NOR Gate

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CMOS AOI Gates

CMOS AOI Gates

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CMOS AND-OR Gate

CMOS OAI Gates

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CMOS AOI Gates

Example

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Example

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XOR Gate

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