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Introduction

The HERON-FPGA family is ideal for many of the building blocks of digital communications. Providing large easily-programmed gate arrays, often combined with interface elements like ADC or DACs, they can be used to implement many system components. The availability of hardware such as the HERON system is enabling designers to build radio systems where more and more of the system is digital. This often requires new techniques and terminology. This is an introduction to one such technique the Digital Down Converter, or DDC. This paper is not meant as a definitive reference on DDCs. Instead, it is a grounding in the basic concepts. It is enough for an experienced signal processing engineer to build his own DDC, but we have also provided references to other information sources for further reading.

A fundamental part of many communications systems is Digital Down Conversion (DDC). Digital radio receivers often have fast ADC converters delivering vast amounts of data; but in many cases, the signal of interest represents a small proportion of that bandwidth. A DDC allows the rest of that data to be discarded, allowing more intensive processing to be performed on the signal of interest. As an example, consider a radio signal lying in the range 39-40MHz. The signal bandwidth is 1MHz. However, it is often digitised with a sampling rate over 100MHZ, representing in the region of 200Mbyte/second. The DDC allows us to select the 39-40MHz band, and to shift its frequency down to baseband. Once this is complete, the sampling rate can be reduced with a 1MHz bandwidth, a sampling rate of 2.5MHz would be fine - giving a data rate of only 5Mbyte/second. This is shown in Figure 1.

How It Works

A DDC works by first shifting the bandwidth of interest to baseband by multiplying the received signal by a close approximation to the original carrier. This works on the (simplified) mathematical principle: Frequency(A) * Frequency(B) = Frequency(A-B) + Frequency(A+B) So, for our example, we need to shift the 39-40MHz band (our Frequency A) down to DC. We do this by multiplying by our estimate of the carrier say 39MHz. We now have: Input Signal * 39MHz = Signal at 0-1MHz + Signal at 78-79MHz Of course, our sampling rate (Fs) is still 100MHz. Nyquists theory says that we need to sample twice as fast as the highest frequency of interest, or we get aliasing; and that is indeed what happens. The 78-79MHz signal is aliased, and would also appear in the 0-50MHz band. In fact, aliases are something we need to be acutely aware of. To understand where the signal will appear, look at the following table, for a tone of frequency F, sampled at Fs: Lower Edge of Band DC Fs/2 Upper Edge of Band Fs/2 Fs Where Signal Appears F Fs F

Notes Conventional Nyquist sampling Spectrum inverted. Increasing the input frequency will decrease the output frequency. Signal appears as normal, but frequency shifted by Fs. Spectrum inverted. Frequency shifted by 2Fs

Fs 3Fs/2 2Fs

From this, we can see that the 78-79MHz signal is aliased back down to the 21-22MHz band, and its frequency inverted. All other signals present in the input are also shifted and may be aliased. This can be an important factor to consider in the design of a DDC; it is possible to alias significant noise sources into the bandwidth of interest to us. For example, noise signals in the 99101MHz region would alias to 1MHz right on top of our signal. (In fact, we can use the frequency shift introduced by aliasing to good effect. The principle is that with our 100MHz sample rate, we could sample a signal at 105MHz and it would be frequency shifted down to 5MHz. This is called bandpass sampling, and well look at it later.)

This process is shown in Figure 2. The hardware to implement it comprises an oscillator capable of generating our estimate of the carrier, and a multiplier these are often known as the Local Oscillator or LO, while the multiplier is often known as a mixer terminology carried over from the days of analog.

Following the mixer, all we have to do is remove the unwanted signals and their aliases, then reduce the sampling rate. This process is performed by filtering the signal to limit the bandwidth to our signal of interest, centred close to baseband. This is implemented with linear phase filters. Once this is complete, we can reduce the sampling rate by "decimating" the original signal throwing away samples until we reach the desired output rate. For integer decimation ratios this is simple for example, reducing the sampling rate by a ratio 2, 3, or 27. For non-integer decimation ratios, a more complex system is used. Returning to our example, we filter the incoming signal to limit its bandwidth to 0-1MHz. After the filter, the band-limited signal can be decimated again, to keep the maths simple, we will decimate the sampling rate by a factor of 32, dropping the sampling rate from 100MHz to 3.125MHz a far easier challenge to process. In reality wed probably drop the sampling rate to 2.5MHz using the non-integer decimation we hinted at above. We will look at that later.

In our simple explanation, we have talked exclusively about "real" signals. In fact, most DDC systems use complex arithmetic, where the signal is represented by a real and imaginary part. This brings significant benefits.

A signal can have a positive or negative frequency. Sampled using a simple ADC, you cannot tell whether that signals frequency is positive or negative not enough information is available to you. To understand this, imagine a signal generated by a single sensor. That sensor is measuring a rotating bicycle wheel. As each spoke passes the sensor, a pulse is generated. This generates a signal, but there is no way of telling which direction the bicycle wheel is rotating. By adding a second sensor close to the first, we generate two pulse trains; and we can now tell whether the wheel is rotating clockwise or counter-clockwise depending on which pulse is generated first. This is the principle of complex arithmetic. By adding the imaginary part of the sample, we can detect whether our signal has a positive or negative frequency. Now, we can implement filters that genuinely do have passbands of (say) 0-1MHz. We can also recover far more easily from carrier error if after we shift our signal, part of it is negative, we can compensate for this in later processing. In fact, its optimal to shift the signal so that it is symmetric about DC the maximum negative frequency is similar to the maximum positive frequency. In doing this, we minimise the sampling frequency we need to use. Generally, DDCs will introduce complex arithmetic at the local oscillator stage. The local oscillator generates a complex version of the carrier, with precise 90-degree phase shift between its channels. From this point on all further processing is done in complex maths.

We mentioned that the filters used to reduce the bandwidth of the signal usually have linear phase characteristics. Linear phase filters are usually more complex than those with arbitrary phase characteristics, so once again, there is a good reason for this. Communications systems often depend on the relationships between multiple carriers. These carriers may be the same frequency but with different phase; or they may be completely different frequencies. In either case, disturbing the phase relationships would be a bad thing. For this reason, most DDC designers will try to use linear phase filters exclusively. These appear as a simple delay to the signal, and as all elements of the signal are delayed by the same amount, the signals integrity is preserved.

In our description, we described decimation as simply "throwing away" samples. This is a valid thing to do for integer changes in the sampling rate; for example, when decimating a bandwidth limited signal from 3MHz to 1MHz it is perfectly OK to discard every second and third samples.

However, this is not always the case. In some systems we will want to decimate by non-integer ratios for example, 2,5MHz down to 1MHz. This represents a decimation ratio of 2.5, or 5/2. In this case, we first INCREASE the sampling rate. This is known as interpolation. We add samples, then filter the signal back to its original bandwidth. Here, we double the sample rate up to 5MHz. Once the sample rate has been increased, we can once again decimate by discarding samples. In the example, we discard four samples from every five, giving us the 1MHz output rate. All these concepts are drawn together in the block diagram of Figure 3

The concept of the DDC is to sample the whole input signal and to use digital techniques to reduce the data. However, that may require an unrealistically fast ADC. For example, Nyquists theory states that we should sample at a rate "at least double the bandwidth of interest". If we do this on a 1GHz carrier, we would need an ADC sampling at well over 2GHz; that ADC would be protected by anti-aliasing filters, removing any signal above 1GHz. However, this is beyond what can be achieved with todays technology. Frequency shifting is required before the ADC. This can be done in analog, using an IF stage; or it may be possible to use a composite approach. Typically, if the signal is at 1GHz, the bandwidth of interest may be only a MHz wide. The filters required to select such a narrow band would be large and complex; but selecting a band perhaps 40MHz wide could be practical. If we can select this band using analog filters, it is possible to sample at a reduced rate using the bandpass sampling mentioned earlier. In this case, a sample rate (Fs) of 100MHz would mean that our signal could be frequency shifted by 10Fs, bringing the 1GHz signal in at a much more reasonable 100MHz sample rate.

The more aggressively this technique is applied, the greater the strains on the anti-aliasing filters. It also places great emphasis on high analog bandwidth for the ADC, and extremely low jitter for the ADC clocks; any errors here will be magnified greatly. However, it can be used very effectively. This technique is complementary to frequency-shifting the signal to an "Intermediate Frequency" or IF. Typically the approach used direct conversion, IF or "bandpass sampling" will be chosen dependent on the frequencies involved and other system issues even down to the type of antenna deployed. Most systems use a combination approach, using an analog IF stage to bring the signal down to something that can then be processed digitally.

Plainly a DDC is implementing something which could be done in analogue its sometimes good to stop and check why wed want to do this. The DDC is typically used to convert an RF signal down to baseband. It does this by digitising at a high sample rate, and then using purely digital techniques to perform the data reduction. Being digital gives many advantages, including:

Digital stability not affected by temperature or manufacturing processes. With a DDC, if the system operates at all, it works perfectly theres never any tuning or component tolerance to worry about. Controllability all aspects of the DDC are controlled from software. The local oscillator can change frequency very rapidly indeed in many cases a frequency change can take place on the next sample. Additionally, that frequency hop can be large there is no settling time for the oscillator. Size. A single ADC can feed many DDCs, a boon for multi-carrier applications. A single DDC can be implemented in part of an FPGA device, so multiple channels can be implemented or additional circuitry could also be added.

ADC speeds are limited. It is not possible today to digitise high-frequency carriers directly. There are techniques to extend the range of ADCs, but often it is simpler to use analogue circuits to bring the carrier down to an IF that digital circuits can then manage. ADC dynamic range is limited. In many communications systems, the signals amplitude can vary greatly. Fast ADCs often only have 12bits of resolution giving an absolute maximum dynamic range of 72dB. It is often better to use analogue circuits in conjunction with the ADC to implement AGC functions to ensure that this range is best used.

In time, more and more systems will use predominantly digital technology. However, the high speeds of many communication systems will ensure that a hybrid approach, using analogue and digital, will be the best route for many systems for a long time to come. The quest for more spectral space will ensure that new systems will use ever higher frequencies, ensuring that analog approaches will be around for a long time to come!

Further Reading

There are many aspects of DDCs that we have touched on lightly in this tutorial. Try the following for more information: CIC Filters: The original paper on CIC filters is a mathematical work of art however, that doesnt make it useful for engineering purposes! A lighter introduction is available at: DSPGuru - http://www.dspguru.com/info/tutor/cic.htm This references Hogenauers original paper, but its not strictly necessary to understand all the maths to get a CIC working! Complex Maths: Another useful tutorial on the DSPguru website, complex maths explained in simple terminology essential for a full understanding of much of communications theory: DSPGuru - http://www.dspguru.com/info/tutor/quadsig.htm DDC Chips: Take a look at how the fixed-function DDC chips are structured. Many of these are overkill they have to be as they need to match the needs of many users, while your design can be application specific. You can still learn from them; Graychip in particular have excellent datasheets: Graychip has recently been acquired by Texas Instruments but you can still find their datasheets at the TI website, in the Analog & Mixed Signal section.

Introduction

A fundamental part of many communications systems is Digital DownConversion (DDC). This allows a signal to be shifted from its carrier (or IF) frequency down to baseband. The technique greatly reduces the amount of effort required for subsequent processing of the signal without loss of any of the information carried. You would never consider using a DSP like the C6000 for DDC. Historically it has been performed in analogue before digitising the baseband signal for the DSP. The HERON-FPGA family is ideal for many of the building blocks of digital communications. Providing large easily-programmed gate arrays, often combined with interface elements like ADC or DACs, they can be used to implement many system components. This note describes how a DDC can be implemented in the HERON-FPGA or HERON-IO family. While the technology looks complex, it is actually very simple, and can be implemented extremely quickly. Theory of operation is not addressed here there is a separate paper from Hunt Engineering which introduces the concepts of the DDC.

See also the very good article by Ray Andraka (Andraka Consulting Group, Inc) on the subject of DDC with FPGAs. We provide demo/frameworks of a DDC in a HERON-IO2 and a HERON-IO5 that are similar to the discussion below.

Essentially, a DDC comprises an oscillator, generating a quadrature signal; a mixer, which multiplies the incoming signal by the local oscillator; and then filtering. This combination frequency-shifts the signal. Typically the frequency shift is the frequency of the local oscillator. Many systems will try and match the local oscillator to the carrier, shifting the received signal back to baseband.

The ADC will be implemented externally to the FPGA. If youre using a module with an integrated ADC, the Hardware Interface Layer supplied will provide a macro for interfacing to the ADC converter(s). If the module does not have an ADC, you will need to gather the data using the FIFO interfaces again using macros from the library supplied. The details of this are module dependent so are not discussed further here.

This is the first stage of the DDC. The local oscillator is a quadrature oscillator, generating a highly accurate and stable version of the carrier. The Xilinx "Core Generator" tool offers a "Direct Digital Synthesiser" or DDS which will implement this function. There are a number of parameters to consider:

1. How accurate should the frequency control of the oscillator be? With a digital oscillator, you can specify very fine control at the expense of increased FPGA utilisation. 2. Do you need to program the phase of the oscillator? To what resolution? 3. How much noise can you tolerate in the oscillators output? Any noise will be passed through the mixer into the DDCs filters, and will add to the systems noise floor. You may want to analyse this. With this information, you can move to generating a core with the Xilinx toolset. The best approach is to generate the biggest DDS you can squeeze into the FPGA, but record the parameters you use. If you need to optimise the design later, you can regenerate the core with (for example) reduced frequency accuracy to increase speed. Similarly, the mixer is implemented as a pair of hard-coded multipliers. It is usually not worth trying to implement the mixer in a single multiplier. Ensure that the outputs are registered, and select the pipelined multiplier option. It should now be a simple matter to connect the oscillator to two of the multiplier inputs, while the ADC can go on the other input.

There are two main classes of DDC wideband and narrowband, differentiated by their decimation ratios. As a rough guide, if the decimation ratio is less than 32, consider the DDC wideband; if 32 or more, the DDC is narrowband. The filtering we will perform is different for narrowband or wideband, so is tackled separately. However, the decimators can be treated identically for wideband or narrowband systems. Note also that in some systems it may make sense to combine wideband and narrowband DDCs. For example, in a GSM system which uses 8 carriers, a wideband DDC could be used to shift the carriers down to a moderate frequency. This could be done using a simple oscillator no complex components. 8 narrowband DDCs could then be used to select the individual carriers. The theory is the same

With a wideband signal, we are typically reducing the sampling rate by a small amount, and the data output rate is large. Note that the output rate of a wideband DDC should be checked as part of your overall system design. In some systems that data rate will be significant, and could saturate a DSP processor if that is meant to be receiving it. The main challenge of a wideband receiver is getting enough processing to filter the signal. All the processing is performed at a fairly high rate, often 20-40MHz. Because of this, the filters tend to be very gate-intensive; a single wideband channel will typically consume more of an FPGA than several narrowband channels.

Each design has different requirements. However, the following is a rough guide to implementing the filter. The filter is best implemented as an FIR, and in fact the best approach is to use a multirate FIR. This may sound complex, but in fact a multi-rate FIR is simply an efficient way of implementing large filters with decimation. Imagine we need to implement a large filter at a high sampling rate, before decimating the signal. We could implement a 128-tap filter at 100MHz, but this would require a lot of multipliers and a huge FPGA. However, suppose we split the filter. The first filter can perform enough filtering to allow us to perform some decimation. The second filter is now operating at a much reduced sampling rate. Typically by splitting the filter in this way we can reduce the number of taps in the filter, and reduce the sampling rate that some of these taps operate it. Both reduce the amount of FPGA resource we require to build the filter. So, to implement your filter: start with a simple FIR. This stage should have a small number of taps - if you are operating at a high sampling rate, each FPGA multiplier will implement a very small number of taps. Use symmetric FIRs here the processing load is about half a nonsymmetric filter, and the core generator provides this as an option. Regardless of which FPGA you are using, this stage will take a lot of silicon! The filters bandwidth should match the output bandwidth of the DDC, but dont worry too much about the filters performance later filters will improve this. (Note: the output bandwidth is the band that were interested in typically only a few hundred KHz wide) Immediately after this filter, decimate the signal by 2, and implement a larger filter. Again, the filters bandwidth should match the DDC output bandwidth. This will improve the response of the first filter. You can afford to have more taps in this stage, as the sampling rate is lower. If you are operating a low decimation ratio, this could be all you have to do. That means that these filters have to have more taps than if we can use an additional stage. Experiment by trying cascades of filters with varying numbers of taps you will probably have to do this iteratively, using the Xilinx tools to try several different scenarios. For higher decimation ratios (e.g. 8 and up), you can afford to use a third stage filter. This can have significantly more taps than the first two, as each multiplier here can implement at least 4x as many taps as in the first stage. Again, you will want to experiment with the layout of the filters to see what gives best performance.

Narrowband DDCs have a different set of challenges. With these, we need filters that can allow large decimation ratios without consuming too much of the FPGA. A very useful filter here is the Comb-Integrator Cascade filter, or CIC filter. This filter has remarkable properties it can implement decimation within the filter, and it provides a steep cut-

off for relatively few stages. Best of all, it is implemented using only adders and delays, which makes it very well suited to FPGA implementation. The CIC has one failing it has a lot of "droop" in its passband, and serious ripples in its stopband. However, we can compensate for these with additional filtering of its output. Because of the need for additional filtering on a CICs output, it is at its best with large decimation ratios. The larger the decimation ratio, the smaller the overhead of the filters used to compensate for the CIC. This makes it unsuitable for the wideband DDC we looked at earlier as the compensation filter becomes significant. However, for the narrowband DDC, it is ideal as a first stage. We would then follow that with a multi-rate FIR filter, as with the wideband DDC. Now, we can use as many taps as a single multiplier will allow. Generally a two-stage FIR works well, decimating by 2 between the stages. For many applications, 23 taps will work well in the first filter, and should be realisable with a single multiplier design; while 63 would be ideal in the second. Again, use symmetric FIRs to reduce the processing load.

Everybody has their own favourite way of designing filters. Some will simulate the filters in Matlab or one of the other commercial packages; others may use one of the on-line tools, such as the filter design package at http://www.nauticom.net/www/jdtaft/. In all cases, studying the datasheets of commercially available DDC devices can give some guidance many of these detail the procedures for designing a DDC filter chain, and often list the coefficients. These filters may be copyright protected, but they will give good guidance on design. The CIC doesnt really need to be designed you just need to calculate the word length required in the integrators accumulators. Be careful here the CIC needs surprisingly big accumulators due to huge wordlength growth. The size of the accumulator is dependent on the number of stages in the filter and the decimation ratio check the references if you need help on this.

Once you have the filters designed, implement them. For the CIC, it is best to implement this from scratch although there is a 5-stage CIC included in the example for this white paper. Be aware that the CICs wordlength is dependent on the decimation ratio though the example CIC will overflow on larger decimation ratios. It is easily modified for longer wordlengths. For the FIRs, we will again us the Xilinx Core Generator tool this allows you to specify the parameters of the filter and it will generate an FPGA core to match. Make sure you keep a record of the settings you use this may well be an iterative process if you need to optimize the design for speed or size, and knowing what you asked for will help immensely!

The Xilinx tool will even generate decimating FIRs for you. Specify the decimation ratio, and the output will signal a valid sample at the decimated output rate an incredibly powerful tool for this type of work. Note that the Xilinx FIR tool also allows you to specify the number of clocks per output sample. Make sure you specify the maximum number of clocks; that way, the tools will be able to use the least possible amount of FPGA resource to implement your filter. Note that in a multi-rate filter, the later stages will have more clocks per output than the early stages! Once the filters have been generated, theyll be in the library for your Xilinx design. Build up the DDCs processing chain. It is worth registering the data along the chain (specify the "register output" option on the filters). Make sure the system clock is connected to all elements well see how to control the DDC in just a moment.

The Decimator

The final decimator can be implemented within the last FIR stage, if the decimation ratio is an integer. To do this, simply specify the required decimation ratio as part of the filter design. However, you may require a non-integer decimation ratio, or you may require a variable decimation ratio. In these cases, we must treat the decimator as a separate block. For non-integer decimation, run the FIR Core Generator one more time. Select an interpolating filter; this will automatically increase the sampling rate by the given amount. Place this in your design. The decimator can now be implemented as a register & counter. An example of this type of decimator can be found in the middle of the CIC filter used in this example.

The discussion above helps you to understand how the DDC is designed and works, but in fact there is a DDC block in the core generator. You enter much the same information as you would into the individual blocks but what results is a single Core generator block that probably uses less real estate than the discrete one. If your design goals can be met with this Coregen block then you should certainly use it. If it limits what you need to do then you can implement your DDC in separate blocks. We provide worked examples of implementing a DDC in a HERON-IO2 and a HERON-IO5

This demo/framework for a HERON-IO2V or a HERON-IO5V uses an example implementation of a DDC to show you how to design and build a Digital Down Converter (DDC) using blocks from the Xilinx Core Generator. It discusses how to design and implement a DDC, but also shows that the Core Generator DDC block can often be used to perform the whole task. This demonstration can be run using a HEPC9 module carrier, using a HERON-IO2V or a HERON-IO5V without re-compiling. It would be easy to recompile it to use with another HERON-IO module, or perhaps the combination of a HERON-FPGA module with a separate Analogue I/O module. The FPGA outputs a modulated signal on its DAC outputs, and digitising that signal, performs the DDC function and outputs baseband data to the HERON FIFO using the Hardware Interface Layer. There is a multiplexor controlled by the Heron Serial Bus that allows you to view the signal at various points along the processing pipeline. This helps you to better understand the operation of the DDC. The Host API is used to receive the results using a graph program running on the host PC. The demo demonstrates communicating between an FPGA and the PC, using the Heron Serial Bus to control FPGA logic and drawing a graph on the PC screen as well as using an FPGA to make a DDC.

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