INDEX

Sr.No.
1 2 3 4 5 6 7 8 9 10

Experiment
To implement half adder & half subtractor circuit using TRILOG. To implement full adder circuit using TRILOG. To implement full subtractor circuit using TRILOG. To implement equivalence detector (XNOR) circuit using TRILOG. To implement odd and even parity generator circuit using TRILOG. To implement 4 by 1 multiplexer circuit using TRILOG. To implement Boolean expression X= A+ [B (A’+C) +AC (D’+E’)] using TRILOG. To implement sequencer circuit using TRILOG. To implement lamp operator circuit using TRILOG. To implement a program to control pilot light (with given conditions) using TRILOG.

Date
12/03/12 19/03/12 26/03/12 26/03/12 2/04/12 9/04/12 9/04/12 16/04/12 23/04/12 30/04/12

Signature

Experiment # 1(a) Aim: To implement half adder circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table:

Expression:
S=A’B+AB’ C=AB

Logical Diagram:

Ladder diagram and simulation:

Experiment # 1(b)

Aim: To implement half subtractor circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table:

Expression:
D=A’B+B’A B=A’B

Logical Diagram:

Ladder diagram and simulation:

Experiment # 2 Aim: To implement full adder circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: Expression:
S=A’B’C+A’BC’+AB’C’+ABC C=A’BC+AB’C+ABC’+ABC C=AB+AC+BC

Logical Diagram:

Ladder diagram and simulation:

Experiment # 3 Aim: To implement full subtractor circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: Expression:
D=A’B’C+A’BC’+AB’C’+ABC B=A’B’C+A’BC’+A’BC+ABC

Logical Diagram:

Ladder diagram and simulation:

Experiment # 4 Aim: To implement equivalence detector (XNOR) circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: Expression:
O=A’B’+AB

Logical Diagram:

Ladder diagram and simulation:

Experiment # 5(a) Aim: To implement odd parity generator circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: Expression:
X=A’B’C’+A’BC+AB’C+ABC’

Logical Diagram:

Experiment # 5(b) Aim: To implement even parity generator circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: Expression:
PRE=A’B’C’P+A’B’CP’+A’BC’P’+ A’BCP+AB’C’P’+AB’CP+ABC’P+ ABCP’

Logical Diagram:

Ladder diagram and simulation:

Experiment # 6 Aim: To implement 4 by 1 multiplexer circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: S0 S1
0 0 1 1 0 1 0 1

Expression:
Y=I0S1’S0’+I1S0’S1+I2S0S1’+I3S0S1

Y
I0 I1 I2 I3

Logical Diagram:

Ladder diagram and simulation:

Experiment # 7 Aim: To implement Boolean expression X= A+ [B (A’+C) +AC (D’+E’)] using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: A B C D E X 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 Logical Diagram:

Expression:
(Simplified) X = A+BA’+BC+ACD’+ACE’

Ladder diagram and simulation:

Experiment # 8 Aim: To implement sequencer circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Ladder diagram and simulation:

Experiment # 9 Aim: To implement lamp operator circuit using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Ladder diagram and simulation:

Experiment # 10 Aim: To implement a program to control pilot light which will turn ON if a limit switch
LS1 closes and if either push button PB1 or limit switch LS2 closes using TRILOG.

Apparatus: I-TRILOG version 6.41

Procedure:
1. 2. 3. 4. Open I-TRILOG. Click on ‘Circuit’ and select ‘Append Circuit’. Select the appropriate inputs and outputs to form the ladder diagram. Click on ‘Simulate’ and select ‘Run (All I\O Reset)’.

Truth Table: LS1 PB1 LS2 O 0 0 0 1 1 0 1 1

Expression:
O=LS1’PB1’LS2+LS1’PB1LS2’

Logical Diagram:

Ladder diagram and simulation:

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