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ICs have made digital systems more reliable by reducing the number of external interconnection from one device to another. ICs have reduced the amount of electrical power needed to perform a given function. IC cannot handle very large currents or voltages because the heat generated in such small spaces would cause temperature to rise beyond acceptable limits ICs are principally used to perform low-power circuit operations that are commonly called information processing.

Introduction

The miniature, low-cost electronics circuits whose components are fabricated on a single, continuous piece of semiconductor material to perform a high-level function. Usually referred to as a monolithic IC, first introduced in 1958 Categorized as digital or linear ICs or according to the level of complexity of the IC. Rapidly growth from SSI, with fewer than 12 gates per chip; through MSI, with 12 to 99 equivalent gates per chip Others LSI, VLSI, ULSI and GSI There are some things IC cannot do when deal with very large current

Integration levels

SSI MSI LSI VLSI ULSI GSI -small scale integration -medium scale integration -large scale integration -very large scale integration -ultra large scale integration -giant scale integration

Levels of integration

SSI MSI

100-1000 12-99

Applications

Logic gates Op-amps Registers Filters 8 bit processor, A/D converter

LSI

1000-10000 1000

.contd

VLSI 10k gates/chip 16,32 bit processor 256KB memory DSP processor

ULSI

GSI

100k gates/chip 64 bit processor 8 MB memory Image processor 1M gates/chip 64 MB memory multiprocessor

Digital IC Terminology

VIH HIGH-state input voltage, corresponding to logic 1 at input VIL LOW-state input voltage, corresponding to logic 0 at input VOH HIGH-state output voltage, corresponding to logic 1 at output VOL LOW-state output voltage, corresponding to logic 0 at output IIH HIGH-state input current; current flowing from input when the input voltage corresponds to logic 1. IIL LOW-state input current; current flowing from an input when the input voltage corresponds to logic 0. IOH HIGH-state output current; current flowing from output when the output voltage corresponds to logic 1. IOL LOW-state output current; current flowing from an output when the output voltage corresponds to logic 0.

IOH High level output current IOL Low level output current

Transition Time

Time interval between two reference points on a waveform. These reference points are usually 10% and 90% of the voltage change. Rise time( tr ) Time interval when waveform is changing from a logic low to a logic high level. Fall time( tr ) Time interval when waveform is changing from a logic high to a logic low level.

Switching Time

Vo

tr

tf

10% Vdd

tLH

tHL

tLH- low to high rise time (tr) Time interval between 10% to 90% of Vdd

tHL- high to low time or fall time (tf) Time for signal to fall from 90%Vdd to 10%Vdd

Switching is fast with tmin=thl+tlh

Max switching freq is given by fmax=1/tmin Eg: thl =0.5 nsec, tlh=1.0 nsec tmin =1.5 nsec fmax=1/ tmin=666.67Mhz

Propagation Delay

Time it takes for a change at the input of a device to produce a change at the output of the same. tpLH is the propagation delay when the output changes from LOW to HIGH. tpHL is the propagation delay when the output changes from HIGH to LOW. tpLH and tpHL are not necessarily equal, and their values depends on the logic family.

Fan-in

Fan-in (input load factor) is the number of input signals that can be connected to a gate without causing it to operate outside its intended operating range. Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. Expressed in terms of standard inputs or units loads (ULs) Normally delay increases following a quadratic function of fan-in.

Fan out

Fan-out (output load factor) Defined as the maximum number of logic inputs that an output can drive reliably A logic circuit that specify to have 10 fan out can drive 10 logic inputs

The number of gate inputs that a single output can drive or operate without exceeding its worst case loading specifications.

IILMax is the maximum current supplied by an input when a LOW logic level voltage is applied to that input. IIHMax is the maximum current required by an input when a HIGH logic level voltage is applied to that input. IOLMax is the maximum current into an output when this output is in the LOW state. IOHMax is the maximum current provided by an output when this output is in the HIGH state.

Fan-out Of Inverter

No Load :Fan-out is 0

Gate-delay

Gate delay is the delay offered by a gate for the signal appearing at its input, before it reaches the gate output. The NOT gate has a delay of "Delta", where output X' changes only after a delay of "Delta". Gate delay is also known as propagation delay. Gate delay is not the same for both transitions, i.e. gate delay will be different for low to high transition, compared to high to low transition. Low to high transition delay is called turn-on delay and High to low transition delay is called turn-off delay. Gates are connected together with wires and these wires do delay the signal they carry, these delays become very significant when frequency increases, say when the transistor sizes are sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight time from point A to B). Wire delay is also known as transport delay.

Power Dissipation

The power consumed by the gate that must be available from the power supply. This does not include the power delivered from another gate.

VCC : supply voltage. ICCH : current drawn by the circuit when the output of the gate is HIGH. ICCL : current drawn by the circuit when the output of the gate is LOW. ICC : average current drawn by the circuit. PD : average power dissipation.

Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a certain amount of current during its operation. Since each gate can be in a High, Transition or Low state, there are three different currents drawn from power supply.

Average Power Dissipation = Vcc * (ICCH + ICCL)/2

For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.

Average Power Dissipation = Vcc * ICCT.

So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency. Total power dissipation = static power dissipation + dynamic power dissipation.

DC Noise Margins

The maximum amount of voltage variation (noise) that may be permitted for LOW or HIGH voltage levels.

VOHMin : the minimum output voltage in the HIGH state. VIHMin : the minimum input voltage guaranteed to be recognized as a HIGH. VILMax : the maximum input voltage guaranteed to be recognized as a LOW. VOLMax : the maximum output voltage in the LOW state.

VOHmin min value of output recognised as a 1

VILmax max value of input recognised as a 0 VOLmax max value of output recognised as a 0

indeterminate voltage

logic 0

Noise Immunity

Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits this unwanted signal called noise These cause the input signal to a logic circuit drop below VIH (min) or rise above VIL (max) Noise immunity refers to the circuits ability to tolerate noise without causing spurious changes in the output voltage Any voltage greater than VOH(min) considered a logic 1 Voltages lower than VOL (max) logic 0

The high state noise margin VNH is defined as VNH = VOH (min) VIH (min) The low state noise margin VNL is defined as VNL = VIL (max) VOL (max)

Unused Inputs

Handle them as follows:

Tie them to a used input in the same gate. Tie them to logic 1 through a pull-up resistor for AND & NAND gates. Tie them to logic 0 through a pull-down resistor for OR & NOR gates.

26

Logic families can be classified broadly according to the technologies they are built with as list below.

DL : Diode Logic. RTL : Resistor Transistor Logic. DTL : Diode Transistor Logic. HTL : High threshold Logic. TTL : Transistor Transistor Logic. IIL : Integrated Injection Logic. ECL : Emitter coupled logic. MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS). CMOS : Complementary Metal Oxide Semiconductor Logic.

Among these, only CMOS is most widely used by the ASIC (Chip) designers; we will still try to understand a few of the extinct / less used technologies. More in-depth explanation of CMOS will be covered in the VLSI section.

Logic Families

Transistor Transistor Logic (TTL) is one of the most popular and widespread of all logic families.

Very high number of SSI and MSI devices available in the market. Several number of sub-families that provide a wide range of speed and power consumption.

Sub families:

74xx : The original TTL family.

These devices had a propagation delay of 10ns and a power consumption of 10mW, and they were introduced in the early 60s. 28

Logic Families

Sub families:

74Hxx : High speed.

Speed was improved by reducing the internal resistors. Note that this improvement caused an increase in the power consumption.

Power consumption was improved by increasing the internal resistances, and the speed decreased.

29

Logic Families

Sub families:

74Sxx : Schottky.

The use of Schottky transistors improved the speed. The power dissipation is less than the 74Hxx sub-family.

Uses Schottky transistors to improve speed. High internal resistances improves power consumption.

30

Logic Families

Sub families:

74ASxx : Advanced Schottky.

Twice as fast as 74Sxx with approximately the same power dissipation.

Lower power consumption and higher speed than 74LSxx .

74Fxx : Fast.

Performance is between 74ASxx and 74ALSxx.

31

Logic Families

Complementary metal oxide semiconductor (CMOS) replaced TTL devices in the 90s due to advances in the design of MOS circuits made in mid 80s. Advantages:

Operate with a wider range of voltages that any other logic family. Has high noise immunity. Dissipates very low power at low frequencies. It requires an extremely low driving current. High fanout.

32

Logic Families

Disadvantages:

Power consumption increases with frequency. Susceptible to ESD - electro-static discharges.

Sub-families:

40xx : Original CMOS family.

Fairly slow, but it has a low power dissipation.

Better current sinking and sourcing than 40xx. It uses voltage supply between 2 and 6 volts. Higher voltage higher speed. 33 Lower voltage lower power consumption.

Logic Families

Sub-families:

74HCTxx : High speed CMOS, TTL compatible.

Better current sinking and sourcing than 40xx. It uses voltage supply of 5V. Compatible with TTL family.

Very fast. It can source and sink high currents. Not TTL compatible.

Same as 74ACxx, but it is compatible with TTL family. 34

Logic Families

Sub-families:

74FCTxx : Fast CMOS, TTL compatible.

It is faster and has lower power dissipation than the 74ACxx and 74ACTxx sub-families. Compatible with TTL family.

SN : Texas Instrument. MN : Motorola. DM : National N : Signetics P : Intel H : Harris AMD : Advanced Micro Devices

35

Logic Families

Suffixes, identifies the packaging. N : Plastic DIP (dual in-line package) P : Plastic DIP J : Ceramic DIP W : Ceramic flat package. D : Plastic small outline package

36

Logic Families

Note that parameters like VOHMin , VIHMin , VILMax , and VOLMax are all the same for the different sub-families, but parameters like IILMax , IIHMax , IOLMax , and IOHMax may differ. Most TTL sub-families have a corresponding 54-series (military) version, and these series operate in a wider temperature and voltage ranges.

37

MOS or Metal Oxide Semiconductor logic uses nmos and pmos to implement logic gates. One needs to know the operation of FET and MOS transistors to understand the operation of MOS logic circuits. The basic NMOS inverter is shown below: when input is LOW, NMOS transistor does not conduct, and thus output is HIGH. But when input is HIGH, NMOS transistor conducts and thus output is LOW. Normally it is difficult to fabricate resistors inside the chips, so the resistor is replaced with an NMOS gate as shown below. This new NMOS transistor acts as resistor.

CMOS

CMOS or Complementary Metal Oxide Semiconductor logic is built using both NMOS and PMOS. Below is the basic CMOS inverter circuit, which follows these rules: NMOS conducts when its input is HIGH. PMOS conducts when its input is LOW. So when input is HIGH, NMOS conducts, and thus output is LOW; when input is LOW PMOS conducts and thus output is HIGH.

CMOS

Advantages of CMOS:

Very simple circuits High input impedance. Low power consumption Will work off a wide range of power supply voltages (3-18V)

Disadvantages:

Slower speed because of high input capacitance Prone to damage by static electricity.

Logic Levels Propagation Delays Driving Capabilities Other Parameters

BJT

Transistor Types

TTL

CMOS

TTL

Faster Stronger drive capability

CMOS

Low power consumption Simpler to make Greater packing density Better noise immunity

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