VOL. 6, NO.

9, SEPTEMBER 2011

ISSN 1819-6608

ARPN Journal of Engineering and Applied Sciences

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OPTIMUM SPACE VECTOR PWM ALGORITHM FOR THREE-LEVEL INVERTER

Department of Electrical and Electronics, G. Pulla Reddy Engineering College Kurnool, A.P., India Department of Electrical and Electronics, Brindavan Institute of Technology and Sciences, Kurnool, A.P., India E-Mail: urmila913@gmail.com dsr@gmail.com
1

B. Urmila1 and D. Subba Rayudu2

ABSTRACT A Three-Level Voltage Source Inverter is used increasingly to supply a variable frequency and variable voltage for variable speed applications. A suitable pulse width modulation technique is employed to obtain the required output voltage a t the line side of the inverter. This paper studies popular multi-level topology, Diode Clamped or Neutral Point Clamped for three-level. Two methods of Sine-triangle and two methods of Space Vector Pulse Width Modulation are employed to generate the modulation wave. These modulation waves are compared against a triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves used in SPWM. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. Space Vector Modulation Technique has become the important PWM technique for three phase Voltage Source Inverters because of its increased dc bus utilization and reduced harmonic distortion compared to SPWM. The four PWM methods are simulated in MATLAB/SIMULINK software and are compared for THD and Capacitor Balance. Programs are carried out using Embedded Editor functions and Matlab editor functions. The simulation study reveals that Space vector PWM utilizes dc bus voltage more effectively, generates less THD and improved capacitor balance when compared to Sine PWM.
Keywords: Space Vector PWM, SPWM, three-level inverter, diode clamped inverter, capacitor balance, total harmonic distortion.

INTRODUCTION Increased power demand in power electronics industry urge development in power handling capacity of semiconductor devices. In spite of that, it is a constraint to make use a single power semiconductor device in medium and high power applications, since the maximum voltage supported remains an obstacle. Three-level pulse-width modulation (PWM) voltage-source inverters (VSI) are the converters of choice for many high-power applications such as medium-voltage motor drives both in industrial and other applications. Figure-1 shows the most popular type of three-level inverters, the three-phase diode clamped or neutral-point-clamped voltage source inverter [1-8]. Compared with conventional two-level inverters, a three-level inverter has several favorable features of blocking the dc link voltage to half thus reduce the voltage stress on switching devices to half, lower common mode voltage steps, low output voltage harmonic and current ripple for the same switching frequency in addition to the capability of handling higher voltages. As shown in Figure-1, each leg in three-level inverter is constituted by four controllable switches with

two clamping diodes. Two equal capacitors splits the DC bus voltage into three voltage levels +E/2, 0, -E/2 thus the name 3-level. Clamping diodes blocks the reverse voltage of the capacitor and provide connection to the neutral point. The three states available with a single leg are in Table-1 [9]. The complementary switch pairs are (Si1, Si1) and (Si2, Si2) where i is the phase indicator (i = a, b, c). Vio is the voltage between phase and fictive mid-point of the dc link. Table-1. Three-level inverter switch states State/Switch 1 0 -1 Si1 ON OFF OFF Si2 ON ON OFF Si1 OFF ON ON Si2 OFF OFF ON Vio E/2 0 -E/2

In NPC inverters, maintaining the voltage balance between the capacitors is important for proper operation of the topology.

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Figure-1.Three-level inverter. PWM strategies not only address the primary issues viz, low THD, effective dc bus voltage utilization etc but also take care of secondary issues like EMI reduction, switching loss, better spreading of harmonics over the spectrum. PWM generation methods can be broadly classified into Sine-Triangle carrier PWM (SPWM) and Space Vector based PWM (SVPWM) [1012]. SPWM considers two methods, General Common Mode SPWM (GCMSPWM) and Modified Common Mode (MCMSPWM). In SVPWM, two methods based on the concept of three hexagons (SVPWM-3H) and four regions (SVPWM-4R) are modeled and compared [2-8]. Bus Clamped technique is used in SVPWM-3H, when reference vector revolves in Hexagon 2 to reduce the THD. Simulation software Matlab/Simulink is used for simulation studies. The programs are carried out using Matlab Embedded Functions and Embedded Matlab Editor Functions. The theoretically studied three-level inverter is simulated for open loop and for a balanced three phase voltage system. SINE-TRIANGLE CARRIER PWM In sine-triangle carrier modulation each phase reference voltage is compared with two identically shaped but offset triangle carrier waveforms. Many techniques have been proposed for sine-triangle carrier modulation: Unipolar in Phase Disposition carriers, Unipolar Phase Opposition Disposition carriers and Bipolar carrier Phase Disposition [10-12]. The switching frequency is the frequency of the carriers, and their amplitude is related to the dc-link voltage. As shown in Figure-2 when the reference voltage Vr of a phase is greater than the positive carrier Va1, the phase switches to positive link; when Vr is less than negative carrier Va2, it switches to negative link; otherwise, it switches to the dc-link neutral.

Figure-2. Sine-carrier PWM and pulses. GCMSPWM In multilevel inverters, based on the modulation index (m) defined in (1), modulator takes different shapes. For high modulation index of 0.866, intermediate outer triangles (region 3 of all six sectors Figure-11) are not traversed, resulting in a waveform, very similar to that of a two-level centered space-vector modulator. As modulation index decreases to less than 0.866, the waveforms look very different, unique of the three-level behavior. The centered space-vector modulation injects a particular common-mode harmonic function into balanced three-phase voltage reference. This common-mode injection can be obtained through (2). (1) n the level of the inverter. ); I = a, b, c (2) MCMSPWM Function (2) is sufficient for m = 0.866, the same as the two-level case; for m<0.866, the common mode

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VOL. 6, NO. 9, SEPTEMBER 2011

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www.arpnjournals.com takes different functions at different instants of time as shown in Table-2 [4]. Table-2. Three-level common mode function. Condition and CM (3) Three phase reference voltages are transformed into diphase - components by Clarks transformation (4).

(4) others Generated modulation signals are compared against two triangular carriers to generate PWM pulses for the three phases. The frequency of the carrier signal is very high compared to the modulating signal. The magnitude and frequency of the fundamental component in the line side are controlled by changing the magnitude and frequency of the modulating signal. Linear control is available between 0% and 78.5% of six step voltage values, which results in poor voltage utilization. Available maximum fundamental component improvement with reduced harmonics is obtained through SVPWM. SPACE VECTOR PWM Space Vector PWM (SVPWM) method is an intensive advanced computation PWM method and possibly the best technique for variable frequency application. In SVPWM method, the voltage reference is provided using a revolving reference vector. In this case magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference voltage vector. Space vector modulation utilizes dc bus voltage more efficiently and generates less harmonic distortion in a three phase voltage source inverter. Mathematical modeling of SVPWM The revolving voltage reference vector is obtained assuming a balanced set of voltages (3)

;
Where is the angle varies from 0 to 2.

(5)

Amplitude and angle of the reference vector are found from (5). Table-3 shows the three states of three legs of the three-level inverter shown in Figure-1. From Table-1, the pole voltages are shown for 33 = 27 space vectors in Table-3. Pole voltages are related to phase voltages by (6).

(6) Calculated corresponding phase voltages, diphase voltages and the magnitude of the reference voltage vector Vref are obtained from (6), (4) and (5) and are shown in Table-3. Sa, Sb and Sc are the states of the three legs of the three level inverter. Sa1, Sa2, Sb1, Sb2, Sc1 and Sc2 are the switches of the upper leg of the three phases and Sa1, Sa2, Sb1, Sb2, Sc1 and Sc2 are the complementary switches that constitute the lower leg of the three phases a, b and c respectively shown in Figure-1.

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www.arpnjournals.com Table-3. Three-level inverters 27 States and output voltages.

Sa 0 1 0 1 0 0 -1 0 -1 0 -1 1 0 1 1 0 -1 -1 0 1 -1 1 1 -1 -1 -1 1 Sb 0 0 -1 1 0 1 0 1 0 0 -1 0 -1 1 0 1 1 0 -1 -1 -1 -1 1 1 1 -1 -1 Sc 0 0 -1 0 -1 0 -1 1 0 1 0 1 0 1 -1 -1 0 1 1 0 -1 -1 -1 -1 1 1 1 Sa1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 1 Sa2 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 Sb1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 Sb2 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 Sc1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 Sc2 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 Va0 0 E/2 0 E/2 0 0 -E/2 0 E/2 0 -E/2 E/2 0 E/2 E/2 0 -E/2 -E/2 0 E/2 -E/2 E/2 E/2 -E/2 -E/2 -E/2 E/2 Vb0 0 0 -E/2 E/2 0 E/2 0 E/2 0 0 -E/2 0 -E/2 E/2 0 E/2 E/2 0 -E/2 -E/2 -E/2 -E/2 E/2 E/2 E/2 -E/2 -E/2 Vc0 0 0 -E/2 0 -E/2 0 -E/2 E/2 0 E/2 0 E/2 0 E/2 -E/2 -E/2 0 E/2 E/2 0 -E/2 -E/2 -E/2 -E/2 E/2 E/2 E/2 Van 0 E/3 E/3 E/6 E/6 -E/6 -E/6 -E/3 -E/3 -E/6 -E/6 E/6 E/6 0 E/2 0 -E/2 -E/2 0 E/2 0 2E/3 E/3 -E/3 -2E/3 -E/3 E/3 Vbn 0 -E/6 -E/6 E/6 E/6 E/3 E/3 E/6 E/6 -E/6 -E/6 -E/3 -E/3 0 0 E/2 E/2 0 -E/2 -E/2 0 -E/3 E/3 2E/3 E/3 -E/3 -2E/3 Vcn 0 -E/6 -E/6 -E/3 -E/3 -E/6 -E/6 E/6 E/6 E/3 E/3 E/6 E/6 0 -E/2 -E/2 0 E/2 E/2 0 0 -E/3 -2E/3 -E/3 E/3 -2E/3 E/3 V 0 E/6 E/6 E/24 E/24 -E/24 -E/24 -E/6 -E/6 -E/24 -E/24 E/24 E/24 0 E.3/8 0 -E3/8 -E3/8 0 E.3/8 0 E.2/3 E/6 -E/6 -E2/3 -E/6 E/6 V 0 0 0 E/8 E/8 E/8 E/8 0 0 -E/8 -E/8 -E/8 -E/8 0 E/8 E/8 E/8 -E/8 -E/2 -E/8 0 0 E/2 E/2 0 -E/2 -E/2 Vres 0 E/6 E/6 E/6 E/6 E/6 E/6 E/6 E/6 E/6 E/6 E/6 E/6 0 E/2 E/2 E/2 E/2 E/2 E/2 0 E2/3 E2/3 E2/3 E2/3 E2/3 E2/3 Vv V0 V11 V12 V21 V21 V31 V32 V41 V42 V51 V52 V61 V62 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Sn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

The 27 state space vectors of three-level inverter are shown in Figure-4 and Table-3. According to magnitude the 27 voltage vectors are categorized into four groups: Zero vectors (ZV), Small Vectors (SV), Medium Vectors (MV) and Large Vectors (LV). Zero vectors are (000), (111), and (-1-1-1) at the origin, connecting the output to zero potential point thus producing a voltage or current amplitude of zero. Small vectors are double vectors and are again subdivided into Upper and Lower small vectors. The six vectors (100), (110), (010), (011), (001), (101) are Upper Small Vectors (USV) and (0-1-1), (00-1), (-10-1), (-100), (-1-10), (0-10) are the six Lower Small Vectors (LSV) with equal magnitude of E/6. These vectors connect the ac outputs to two consecutive DC-link voltage levels. The pair of vectors that produce same

voltage are (100, 0-1-1), (110, 00-1), (010,-10-1), (011,100), (001,-1-10) and (101, 0-10). Medium vectors are (10-1), (01-1), (-110), (-101), (011), and (1-10) have the magnitude of E/2. The length of these vectors defines the maximum amplitude of the reference vector for linear modulation and steady-state conditions, which is 3/2 the length of the large vectors. These vectors produce voltage imbalances in the capacitors and thus must be compensated. Large vectors are (1-1-1), (11-1), (-11-1), (-111), (-111), and (1-11).These vectors generate highest ac voltage with magnitude E.2/3. In fact, these six vectors are equivalent to six active two-level vectors. SVPWM-3H In this the concept of three-hexagon (3H) is utilized in generation of pulses. Three-level inverter

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VOL. 6, NO. 9, SEPTEMBER 2011

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www.arpnjournals.com shown in Figure-3 is defined by three hexagons with 18 sectors: Hexagon 1, 2 and 3 [1]. Hexagon 1 (Figure-3a) consists of six sectors a, b, c, d, e and f. The vectors in this hexagon are , , , and , , , are Upper Small Vectors and

, , , , and are Lower Small Vectors and their magnitude (Table-3) is limited to E/6, half of the magnitude of the vector in Hexagon 3. Hexagon 2 (Figure-3b) consists of six sectors g, h, I, j, k and l with six medium vectors. The vectors in this , , , and . From Table-3 hexagon are , , the magnitude of these vectors is E/2. Hexagon 3 (Figure-3c) consists of six sectors m, n, p, q, r and s with six large vectors. The vectors in this , , , , hexagon are magnitude of E.2/3 (Table-3). , and , have the Figure-3(b). Hexagon 2 state space vectors. Gating pulse generation The reference vector Vref is located in any one of the 18 sectors (each of 60 degrees) from 3 hexagons, where each sector is limited by any two adjacent vectors V and V+1 as shown in Figure-4.

Figure-3. Three-level inverter space vectors.

Figure-4. Space vector dwelling time calculation. The is obtained by (7) (7) Figure-3(a). Hexagon1 space vectors. is the sampling time, times of and the three zero vectors , and , and . (8) are the dwelling is the duration of

,respectively.

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VOL. 6, NO. 9, SEPTEMBER 2011

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www.arpnjournals.com (9) (10) Proper distribution of , and builds a symmetrical SVPWM pulse, where all switches of the inverters half-bridge have the same state in the centre and in the two ends.

(14) For sector b in hexagon1 (Figure-4b) the time calculations are: (15) (16)

(17)

(18) For sector g in Hexagon 2 (Figure-4c) the time calculations are: (19) (20)

Figure-4(a). Sector a for T1, T2 calculation.

(21)

(22)

Figure-4(b). Sector b for T2, T3 calculation. Replacing for and for the time calculations for various sectors are: For sector a of hexagon1 (Figure-4a) the time calculations are: (11) (12) (25) (13) (26)

Figure-4(c). Sector g for T8, T13 calculation. (23) (44)

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Figure-5(b). Space vector switching sequence of sector h.

Figure-4(d). Sector h for T8, T9 calculation. The sector time calculation of Hexagon3 is similar to that of Hexagon 1. The sequence of space vectors and switch duration for Hexagon 1, 2 and 3 are shown in Figures 5(a), 5(b) and 5(c). In Hexagon 1, ; ; ; In Hexagon 2, In Hexagon 3, ; ;

Figure-5(c). Space vector switching sequence of sector m. SVPWM-4R In this, the concept of four-region (4R) is utilized in generation of pulses [2-8]. The space vector diagram now is divided into six sectors, each of 60 degrees. Sector1begins at zero degrees and sector6 ends at 360 degrees. The sequence of space vectors for each region is represented in directions in Figure-6.

When the reference vector revolves in Hexagon 2, bus clamped technique is used to reduce the THD. In sector g a phase is clamped to positive bus, in sector h phase c is clamped to negative bus, in sector i phase b is clamped to positive bus, in sector j phase a is clamped to negative bus, in sector k phase c is clamped to positive bus and in sector l phase b is clamped to negative bus.

Figure-5(a). Space vector switching sequence of sector a. Figure-6. Four region space vector of three-level inverter.

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www.arpnjournals.com Calculation of vector output intervals After the determination of switching PWM patterns, the concrete vector output intervals can be calculated as follows. Assuming that the command vector V is located in sector S1 shown in Figure-7, the vector output intervals can be calculated according to the following vector equation: (29) (30) Where , , are the nearest triangle vectors (NTV) [12], [1] and , , are the corresponding vector output intervals. is the PWM control period. Among the triangles shown in Figure-7, NTV is the triangle where the tip point of the reference vector belongs. Utilizing these three voltage vectors, the reference and output voltseconds are matched every PWM cycle. The time length of each vector is calculated and summarized in Table-4. In the Table-4, is the PWM period, kn is the modulation index (magnitude of the reference voltage vector normalized by (28) Assuming two-unit length for large vector, the division of sector into regions considers the following logic. If , and then or reference vector is in region 1. , reference vector is in region 2. , and , reference vector is in region 3. , reference vector is in region 4. , and is the angle from a phase.

Figure-7. Sector1 and its 4 regions. From Figure-7 and from Parks transformation the g-h di-phase components are: (27)

For example, if the command vector , is located in area l, the surrounded three voltage vectors are = , = , = , and the corresponding vector output intervals are = , = , = . Selection of nearest three vectors to generate reference vector minimize the switching frequency of the device and electromagnetic interference and improves the quality of the output voltage spectra.

Table-4. SVPWM-4R space vector duration. Region 1 ) Region 3

Region 2

Region 4

The sequence of space vectors and switch duration for Region 1, 2, 3 and 4 are shown in Figures 8(a), 8(b), 8(c) and 8(d), respectively. In Region 1, ; ; ; In Region 2, ; ; ;

In Region 3, ; In Region 4,

; ; ;

; ;

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www.arpnjournals.com BALANCING OF DC-LINK CAPACITOR VOLTAGES The vector groups defined in section SVPWM ZV, SV, MV, LV affect the balancing of the DC-link capacitor voltages [2, 3, 8]. The ZV and LV do not affect the neutral-point voltage. The MV is somewhat effective on improving voltage unbalance with single switching state and thus the balancing cannot be provided. The SV is the most effective for balancing because USV has charging action, connecting the neutral point to upper capacitor or positive terminal and LSV has discharging action, connecting the neutral point to lower capacitor or negative terminal affecting the neutral point current in opposite ways. Thus special care must be paid in the selection between USV and LSV. Under unbalanced capacitor charges the equilateral triangles shown in Figure-6 are not possible. We can control the neutral point voltage using SV group either by closed loop or by open loop control.

Figure-8(a). Region 1 space vector switching sequence.

Figure-8(b). Region 1 space vector switching sequence.

Figure-9. Capacitor charge for space vector V6, V8. Figures 9(a) and 9(b) shows DC-link capacitor charging and discharging due to vectors Upper state and Lower state of V6. Capacitor C2 charges for the state V61 (101) and discharges during the state V62 (0-10). This states, usage of SV balances the capacitor charge. If the load is inductive these two switching states are almost symmetrical during the switching period and then the DClink capacitor voltages can be balanced. Figure-9c is for the vector V8. SIMULATION RESULTS The four PWM techniques with three-level inverter are modeled and simulated at constant switching frequency of 1500Hz for different modulation indices. GCMSPWM and MCMSPWM line, phase, pole and dc link capacitor voltages are shown in Figures 10, 11, 12, 13 and Figures 14, 15, 16 and 17, respectively at modulation index of 0.8. GCMSPWM and MCMSPWM technique show similar performance concerned to THD.

Figure-8(c). Region 3 space vector switching sequence.

Figure-8(d). Region 4 space vector switching sequence.

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www.arpnjournals.com SVPWM-3H results at modulation index of 0.9 are shown in Figures 18, 19, 20 and 21. SVPWM-4R results at modulation index of 0.7 are shown in Figures 22, 23, 24 and 25.
200 150 100 50 0 -50 -100
200

110 C1 Voltage 105 C2 Voltage

100

95

90

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-13. GCMSPWM DC link capacitor voltages.

-150
150

-200

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

100 50 0 -50

Figure-10. GCMSPWM line voltage.

150 100

-100

50 0 -50 -100 -150

-150 -200

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-14. MCMSPWM line voltage.

150

100

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1
50

Figure-11. GCMSPWM phase voltage.

100

-50

50
-100

-150

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-15. MCMSPWM phase voltage.

-50

-100

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-12. GCMSPWM pole voltage.

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100

150

100
50

50

-50
-50

-100
-100

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

-150

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-16. MCMSPWM pole voltage.

108 C1 Voltage 106 104 102 100 98 96
-60 100

Figure-19. SVPWM-3H phase voltage.

C2 Voltage

80 60 40 20 0 -20 -40

94 92

-80

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

-100

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-17. MCMSPWM DC link capacitor voltage.

200 150
100.15 100.25 100.2

Figure-20. SVPWM-3H pole voltage.

C1 Voltage C2 Voltage

100 50 0 -50

100.1 100.05 100 99.95 99.9

-100 -150 -200

99.85 99.8 99.75

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-18. SVPWM-3H line voltage.

Figure-21. SVPWM-3H DC link capacitor voltages.

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200
100.25
C1 Voltage C2 Voltage

150
100.2

100 50

100.15 100.1 100.05

0 -50 -100 -150 -200

100 99.95 99.9 99.85 99.8 99.75 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Figure-22. SVPWM-4R line voltage.

150

Figure-25. SVPWM-4R DC link capacitor voltages. Figure-26 shows the performance curve, modulation index Vs Total Harmonic Distortion of a three-level inverter run on four PWM techniques.
70

100

50
60 GCMSPWM MCMSPWM

SVPWM-4R SVPWM-3H

50

-50

40

-100

30

-150

20

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1
10 0.5 0.6 0.7 0.8 0.9 1 1.1

Figure-23. SVPWM-4R phase voltage.

100 80 60 40 20 0 -20 -40 -60 -80 -100

Figure-26. THD Vs modulation index. CONCLUSIONS The capacitor voltage unbalance is high in GCMSPWM and MCMSPWM compared to SVPWM-3H and SVPWM-4R. SVPWM-3H technique show better performance with reduced total harmonic distortion during under modulation region and increased modulation index beyond 0.75 and is obtained by using bus-clamped technique. Between 0.55 and 0.75 of modulation index, SVPWM-4R technique has shown better performance with reduced THD.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

REFERENCES [1] Hind Djeghloud, Hocine Benalla. Space Vector Pulse Width Modulation Applied to the Three-Level Voltage Inverter. [2] Nikola Celanovic, Dushan Boroyevich. 2000. A Comprehensive Study of Neutral-Point Voltage Balancing Problem in Three-Level Neutral-PointClamped Voltage Source PWM Inverters. IEEE Transactions on Power Electronics. 15(2): 242-249.

Figure-24. SVPWM-4R pole voltage.

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