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V31Editor& Digital video, J. SMPTE, Mar. 1977 (entire issue).

NTSC systems, Tektronix, Inc., 1976 I)

191 Editors, Television operational measurements--Video and RF for

(S63-M64-M77) received the B.S.E.E. degree, in 1964, from North Carolina State University and the M.S.E.E. degree, in 1966, from Duke University. In 1969, he joined Computer Labs as a Senior Engineer. During his career at Computer Labs, he has been responsible for design and development of A/D and D/A conversion equipment ranging in speed from 10 MHz to 100 MHz. He is currently involved in the design and development of a l&bit 20-MHz A/D and D/A conversion system.
Walter A. K&r

Mr. Kester has contributed significantly in the development of products for digital television applications and has presented a paper entitled Analog-to-digital conversion for video applications, at the 1977 Winter Conference of the Society of Motion Picture and Television Engineers. He has also worked on several customer-sponsored development projects ineluding a fully airborne 7-bit 5-MHz A/D converter. prior to joining Computer Labs, he was employed by Bell Telephone Laboratories as a Member of Technical Staff. During his employment at Bell Laboratories, he WBS involved in A/D converter circuit design, the development of a reference frequency standard for the Gcarrier multiplex system, and a study involving a wide-band audio digitization system for the T-2 carrier system.

An, Improved Successive-Approximation Register Design for Use in A/D Converters


Abstmet-An lmprovcd desll for a swxessive-approximation reghtex @AR) for use in A/D converters is presented. The proposed design is suitable for IL implementation such that a defiite savings in devices is obtained over previous designs using the separate sequencer and cork registerapproadLlldsparticldardeignsche~operatesinafuuysynchronous mode with the clods allowing a reduction in propagation delay to berealkd.

EOC Successive Approximation Register (SAR)


N A RECENT survey article on data conversion, it was pointed out that the most popular type of analog-to-digital (A/D) converter in use today is the one employing the successive-approximation (SA) algorithm [l]. The main reason for its popularity lies in its inherently fast conversion time which is a constant n clock periods for an n-bit converter. When compared to other A/D schemes such as the dual-slope integrating method and the servo-type method, the successive-approximation scheme offers much higher conversion rates [2]. This is a highly desirable feature in multichamel data acquisition systems [3] and in PCM telecommunication systems [4]. The main disadvantage of this scheme has in the past been the dependency upon tight-tolerance often complex networks used in the implementation of the algorithm [5]. However, with the introduction of highly accurate and stable digital-to-analog converters (DAC), and precise,
Manuscript received December 12, 1977; revised March 1, 1978. The author is with Signetics Corporation, Sunnyvale, CA 94086.

I t+%%-<

"REF D/A Converter

Fig. 1. Successive-approximation A/D converter.

high-speed comparators, this disadvantage is quickly being overcome especially in monolithic converters [6]-[9]. Basically, the successive-approximation A/D converter consists of three main components-an analog comparator, a DAC, and a successive-approximation register (SAR) all of which are connected in a feedback arrangement shown in Fig. 1. A more complete converter contains additional control logic for the CLOCK and START signals, and perhaps a set of data latches for the output bits. Because the SAR is the only digital network of the three, it has been one of the limiting factors in prior attempts to fabricate cost-competitive monolithic successive-approximation A/D converters since both analog

0098-4094/78/0700-0550$00.75 01978 IEEE






Start +


Clock C Data +

Code Register



Fig. 2. Separate sequencer and code register SAR.

and digital networks could not successfully be built on the same chip. Hence, earlier attempts at a single-chip converter employed a dual-chip approach such that the analog and digital portions of the converter were built on separatemonolithic chips and then connected on a single hybrid substrate [ 11. In this paper, a SAR design will be presented which is suitable for 12L implementation and hence well suited for application into monolithic A/D converters. The proposed design will prove to use fewer components than the separate sequencer and code register design commonly used for most successive-approximation A/D converters. Typically, for an 8-bit converter, a device savings of 14 percent may be achieved with this design. Also, since this design is fully synchronous with the clock and data input signals, a reduction in propagation delay through the register is achieved when compared to asynchronous SAR designs.



Fig. 3. Functional diagryeF;the logic
ith cell of the proposed SAR

Of the several SAR designs presently in use, the most common design uses a separate sequencer and code register made from D-type flip-flops as shown in Fig. 2 [lo]. The function of the sequencer is to control the code register by sequentially setting each flip-flop in the register to a trial state such that on the next clock pulse, the flip-flop is conditionally set by the present information on the data line. The advantage of this design lies in its simplicity and ease of layout which consists of reproducing each bit cell containing only two D-type flip-flops. When implemented with IL, it can be shown that 19n+9 devices are necessary for an n-bit SAR. However, while the sequencer operates synchronously with the clock input, the code register operates asynchronously since the clock input to a particular flip-flop is obtained from the output of the succeeding flip-flop. As seen in Fig. 2, a

three flip-flop delay occurs between the leading clock edge and the output of the code register. This delay could become significant if it is comparable to the DAC settling. time or the comparator responsetime. SAR DESIGN For the proposed SAR design, a single D-type flip-flop is used in each bit cell which functions both as sequencer and code register. This type of design is often referred to as the sequencer/code register design [lo]. However, it is necessary to include some steering logic in order to control the clock and data inputs to each cell. Fig. 3 illustrates the logic necessary for the ith cell of an n-bit SAR which is shown in Fig. 4. The logic equations for the







CA.+25,NO. 7, JULY 1978

LSB Start , Data .

Fig. 4. Proposed SAR design.

control and output variables of this cell are written as a) cell control variables Q=DATA.g+zi Ci=CLOCK+a+,+ri+, b) cell output variables
i=CZ+l+C+l Qi+,+ri+, (3)

(l) C2)





Basically, this design operates in a functionally identical manner to the separate sequencer and code register design. That is, only one bit cell at a time is placed in a trial state from which it is then conditionally set by the information appearing on the data line. The steering logic causesthe clock and data inputs to control only one cell at a time as described by (1) and (2). The cell outputs which are described by (3) and (4) set the conditions on the preceding and succeedingcells as shown in Fig. 4. There are five transition states that each cell exhibits during a complete conversion cycle of the converter-reset, pre-trial, trial, set, and post-set. These states are illustrated in Table I for the ith cell. During the reset state, the data input (Q) is inhibited while the clock input (Ci) is active. The bit output (Bi) of the cell is held in its present state until the trial state. In the trial state, Bi is inverted so that the digital value of this bit on the DAC is placed on a trial condition. The data input to the cell is now controlled by the information on the DATA line as derived from the comparator. Enough time during the trial state must be allowed for the DAC setting time and the comparator response time before the data can be

Fig. 5. I*L implementation of a negative-edge triggered D-type flip flop.

clocked into the cell during the set state. It must be noted that during the trial state, all of the logic circuits have settled out and are in a waiting condition. Since this is a synchronous design, the delays through the SAR are minimized such that the limitation on the clock frequency is mostly determined by the DAC and comparator. After the cell has been conditionally set (post-set state) the clock input is inhibited thus disabling the cell to receive any information on the data input which remains active.








Clock Pulse j 0 i-l i i+l i+2

Input State at j Reset Pre-trial Trial Set Post-set 'i 1 0 0 0 0 Tji 0 0 1

Variables ritl 0 0 0 0 1

Control Variables

Cell Di 1 0 DATAiml x x qj 1 1 0

Bit -t

0 0 0 1 x


Output $+l i 1 0 DATAiwl DATAiel DATAiml

Output r++ 0 0 0 1 1

Variables $1 e j+l , 4+2 'it2 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0





*i+2 0 t at \ 3 ri 0 CP : qi+l 0


Fig. 6. Complete I*L implementation of the proposed SAR cell.

At the end of the series of n cells, extra flip-flops are necessaryto generate the end of conversion (EOC) signal. For the design shown in Fig. 4, two D-type flip-flops are added to extend the total conversion period to n + 2 clock cycles--n for the actual conversion, one for holding the parallel data output, and one for the EOC signal. If serial data are taken from the DATA line, only one extra flip-flop is required thus shortening the conversion period to n + 1 clock cycles. 12LLoc+~cIMPLEMENTATION _ To implement this SAR design with 12L logic devices, a negative-edgetriggered D flip-flop with positive-level preset and clear inputs was used. The design of this circuit is shown in Fig. 5 which actually requires fewer devices than

one implemented directly from the functional logic necessary for a D flip-flop. Making use of the wired-AND feature of IL, the logic equations for the cell control variables are rewritten in the following manner. From (1) Di=DATAee,+,=(DATA+z,)(ti+ a) (5)

and application of DeMorgans theorem produces Oi = ( DATA 4) * (K*Q,) . (6) This expression can be realized using wired-AND logic and the Qi output rather than the Q output. Since a negative-edge clock is required for the D flip-flop, the expression for the clock input must be negated. Substitut-






CA~-~~,NO.~,JULY 1978

(7) A complete SAR cell incorporating the above circuits is shown in Fig. 6 which requires only 16 12Ldevices. For an n-bit SAR, the first two and last cells are modifications of the basic cell design shown in Fig. 6. As such,.these cells and the two flip-flops for the EOC signal require fewer devices. The total 12L device count for the SAR of Fig. 4 is 16n+ 10 yielding a 3n - 1 device savings over the design of Fig. 2 when using the D flip-flop of Fig. 5. Thus for an g-bit SAR, for example, a device savings of 14 percent may be obtained.

ing (3) into (4) and negating gives ~ -Ci= CL+r, = CL* ri.


111E. L. Zuch, Where and when to use which data converter, IEEE Spectrum, pp. 39-42, June 1977. PI Analog-Digital Comwsion Handbook, pt. II. Norwood, MA: Ana-

log Devices, Inc., 1972, ch. 1. r31 L. Mattera, Data converters latch onto microprocessors, Electronics, pi. 81--X1,Sept. 1977. [41 R. Gun ach, Large-scale mtegration is ready to answer the call of telecommunications, Electronics, pp. 93-108 A r. 1977. [51 G. Grandbois and T. Pickerell, Guantized feel back takes its ~lt~19~7analog-to-digital conversion, Electronics, pp. 103-107, ital conversion with the DAC-08, in Applications Note AN-16, Precision Monolithics Inc.. Santa Clara CA. [71 D. Comer, A monolithic 12 bit D A converter, in ZSSCC Dig. Tech. Papers, pp. 104-105, Feb. 19/ 7. 181P. Holloway.and M. Norton, A high yield, second generation 10 F;,rn;;$thx DAC, in ZSSCC Dig. Tech Papers, pp. 106-107, [91 J. C&s and A. Seales, A new high-speed comparator-The Am 685, in Adwnced Micro Deoices Data Book, Advanced Micro Devices, Inc., Sunnyvale, CA, pp. 8-45-8-52. WI T. Anderson, Optimum control logic for successive ap roximation A/D converters, Comput. Des., pp. 81-86, July 197 . i!

161D. Soder&st and J. Schoeff, Low-cost, high speed analog-to-dig-

An improved SAR design for use in monolithic A/D converters has been presented. This design is presently in use in a monolithic telecommunications codec where delays in the SAR were observed to be on the order of 300 ns for 20 PA per 12L gate. However, by using certain bipolar circuit design techniques presently available, a significant decreasein delay time will result with only a small increase in gate current. Accompanying these techniques will be a decreasein the gate density by a factor of 2 which one must consider in a tradeoff between density and speed.

The author wishes to thank the reviewers of this paper whose comments aided in the presentation of this design. A special acknowledgement is also given to P. Tucci whose lively discussion and comments helped make the design a reality.

Howard T. Russell, Jr. (SW-M67) was born in Fort Worth, TX, -on December 30, 1942. He received the B.S.E.E. and M.S.E.E. deareesfrom Texas A&M University, College St&n, TK, in 1966 and 1967, respectively, and the Ph.D. de gree from Santa Clara University, Santa Clara, CA, in 1976. Since 1971 he has been with Santa Clara University as an Instructor teaching network theory and electronics. His main interests are in active network theory and graph theory. Presently he is with Signetics Corporation where he is involved in the design of monolithic telewmmunication circuits and active channel bank filters. Dr. Russell is a member of Eta Kappa Nu and Tau Beta Pi.