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DG401, DG403, DG405

Vishay Siliconix

Low-Power, High-Speed CMOS Analog Switches

DESCRIPTION FEATURES
The DG401, DG403, DG405 monolithic analog switches • 44 V supply max. rating
were designed to provide precision, high performance • ± 15 V analog signal range
switching of analog signals. Combining low power (0.35 µW, • On-resistance - RDS(on): 30 Ω
typ.) with high speed (tON: 75 ns, typ.), the DG401 series is
• Low leakage - ID(on): 40 pA
ideally suited for portable and battery powered industrial and
military applications. • Fast switching - tON: 75 ns
• Ultra low power requirements - PD: 0.35 µW
Built on the Vishay Siliconix proprietary high-voltage • TTL, CMOS compatible
silicon-gate process to achieve high voltage rating and • Single supply capability
superior switch on/off performance, break-before-make is • Compliant to RoHS directive 2002/95/EC
guaranteed for the SPDT configurations. An epitaxial layer
prevents latchup. BENEFITS
• Wide dynamic range
Each switch conducts equally well in both directions when • Break-before-make switching action
on, and blocks up to 30 V peak-to-peak when off. On-
• Simple interfacing
resistance is very flat over the full ± 15 V analog range,
rivaling JFET performance without the inherent dynamic
range limitations. APPLICATIONS
• Audio and video switching
The three devices in this series are differentiated by the type • Sample-and-hold circuits
of switch action as shown in the functional block diagrams. • Battery operation
• Test equipment
• Communications systems
• PBX, PABX

FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION

DG401 DG401
Dual-In-Line and SOIC LCC
NC D1 NC S1 IN1
D1 S1 Key
1 16
3 2 1 20 19
NC IN1
2 15
NC 4 18 V-
NC
3 14
V- Two SPST Switches per Package
NC 5 17 GND
NC
4 13
GND TRUTH TABLE
NC 6 16 NC Logic Switch
NC VL
5 12
7 15 0 OFF
NC V+ NC VL
6 11 1 ON
NC IN2 NC 8 14 V+
7 10 Logic "0" ≤ 0.8 V
D2 S2 Logic "1" ≥ 2.4 V
8 9 9 10 11 12 13

NC D2 NC S2 IN2
Top View Top View

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 1
DG401, DG403, DG405
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION

DG403
DG403
LCC
Dual-In-Line and SOIC NC D1 NC S1 IN1
D1 Key
1 16 S1 3 2 1 20 19
NC IN1 Two SPDT Switches per Package
2 15 D3 4 18 V-
D3 V-
3 14
S3 5 17 GND
TRUTH TABLE
S3 GND Logic SW1, SW2 SW3, SW4
4 13 6 16
NC NC
S4
5 12
VL 0 OFF ON
7 15
S4 VL 1 ON OFF
D4 V+
6 11 8 14
D4 V+ Logic "0" ≤ 0.8 V
NC IN2
7 10 Logic "1" ≥ 2.4 V
D2 S2 9 10 11 12 13
8 9
NC D2 NC S2 IN2
Top View Top View

DG405 DG405

Dual-In-Line and SOIC LCC


NC D1 NC S1 IN1
D1 1 16 S1 Key
3 2 1 20 19
NC IN1
2 15
4 18 Two DPST Switches per Package
D3 V- D3 V-
3 14
5 17 TRUTH TABLE
S3 GND S3 GND
4 13 Logic Switch
S4 VL NC 6 16 NC
5 12 0 OFF
D4 V+ 7 15 1 ON
6 11 S4 VL

NC IN2 D4 8 14 V+ Logic "0" ≤ 0.8 V


7 10
Logic "1" ≥ 2.4 V
D2 8 9 S2
9 10 11 12 13

NC D2 NC S2 IN2
Top View Top View

www.vishay.com Document Number: 70049


2 S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix

ORDERING INFORMATION
Temp. Range Package Part Number
DG401
DG401DJ
16-Pin Plastic DIP
DG401DJ-E3
DG401DY
- 40 °C to 85 °C
DG401DY-T1
16-Pin Narrow SOIC
DG401DY-E3
DG401DY-T1-E3
DG403
DG403DJ
16-Pin Plastic DIP
DG403DJ-E3
DG403DY
- 40 °C to 85 °C
DG403DY-E3
16-Pin Narrow SOIC
DG403DY-T1
DG403DY-T1-E3
DG405
DG405DJ
16-Pin Plastic DIP
DG405DJ-E3

- 40 °C to 85 °C DG405DY
DG405DY-E3
16-Pin Narrow SOIC
DG405DY-T1
DG405DY-T1-E3

ABSOLUTE MAXIMUM RATINGS


Parameter Limit Unit
V+ to V- 44
GND to V- 25
VL (GND - 0.3) to (V+) + 0.3 V
(V-) - 2 to (V+) + 2
Digital Inputsa, VS, VD
or 30 mA, whichever occurs first
Current (Any Terminal) Continuous 30
mA
Current, S or D (Pulsed 1 ms, 10 % Duty) 100
Storage Temperature (DJ, DY Suffix) - 65 to 125 °C
16-Pin Plastic DIPc 450
Power Dissipation (Package)b mW
16-Pin SOICd 600

Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 7.6 mW/°C above 75 °C.

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 3
DG401, DG403, DG405
Vishay Siliconix

SPECIFICATIONSa
Test Conditions D Suffix
Unless Specified - 40 °C to 85 °C
V+ = 15 V, V- = - 15 V
Parameter Symbol VL = 5 V, VIN = 2.4 V, 0.8 Vf Temp.b Typ.c Min.d Max.d Unit
Analog Switch
Analog Signal Rangee VANALOG Full - 15 15 V
Drain-Source IS = - 10 mA, VD = ± 10 V Room 30 45
RDS(on)
On-Resistance V+ = 13.5 V, V- = - 13.5 V Full 55
Ω
Δ Drain-Source IS = - 10 mA, VD = ± 5 V, 0 V Room 3 3
ΔRDS(on)
On-Resistance V+ = 16.5 V, V- = - 16.5 V Full 5
Room - 0.01 - 0.5 0.5
IS(off)
V+ = 16.5 V, V- = - 16.5 V Hot -5 5
Switch Off Leakage Current
VD = ± 15.5 V, VS = ± 15.5 V Room - 0.01 - 0.5 0.5
ID(off) nA
Hot -5 5
V+ = 16.5 V, V- = - 16.5 V Room - 0.04 -1 1
Channel On Leakage Current ID(on)
VS = VD = ± 15.5 V Hot - 10 10
Digital Control
VIN under test = 0.8 V
Input Current VIN Low IIL Full 0.005 -1 1
All Other = 2.4 V
µA
VIN under test = 2.4 V
Input Current VIN High IIH Full 0.005 -1 1
All Other = 0.8 V
Dynamic Characteristics
Turn-On Time tON RL = 300 Ω, CL = 35 pF Room 75 150
Turn-Off Time tOFF See Figure 2 Room 30 100
ns
Break-Before-Make
tD RL = 300 Ω, CL = 35 pF Room 35 5
Time Delay (DG403)
CL = 10 nF
Charge Injection Q Room 60 pC
Vgen = 0 V, Rgen = 0 Ω
Off Isolation Reject Ratio OIRR RL = 100 Ω, CL = 5 pF Room 72
dB
Channel-to-Channel Crosstalk XTALK f = 1 MHz Room 90
Source Off Capacitance CS(off) Room 12
Drain Off Capacitance CD(off) f = 1 MHz, VS = 0 V Room 12 pF
Channel On Capacitance CD, CS(on) Room 39
Power Supplies
Room 0.01 1
Positive Supply Current I+
Full 5
Room - 0.01 -1
Negative Supply Current I-
V+ = 16.5 V, V- = - 16.5 V Full -5
µA
VIN = 0 or 5 V Room 0.01 1
Logic Supply Current IL
Full 5
Room - 0.01 -1
Ground Current IGND
Full -5
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

www.vishay.com Document Number: 70049


4 S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
7 3.5
V+ = 15 V
6 V- = -15 V 3
SW1, 2
5 2.5

VL = 7 V
4 2

V TH (V)
V T (V)

SW3, 4

3 1.5

VL = 5 V
2 1

1 0.5

0 0
0 2 4 6 8 10 12 14 16 18 5 10 15 20 25 30 35
VL - Logic Supply (V) (V+)
Input Switching Threshold vs. Logic Supply Voltage Input Switching Threshold vs. Supply Voltages

50 60
V+ = 15 V, V- = - 15 V

R DS(on) - Drain-Source On-Resistance (Ω)


TA = 25 °C
R DS(on) - Drain-Source On-Resistance (Ω)

45 VL = 5 V
40 50

35 ±6V
85 °C
30 40 ± 10 V
25 °C ± 12 V
25 ± 15 V
0 °C
± 20 V
20 30

15 - 40 °C
± 22 V
10 20

0 10
- 15 - 10 -5 0 5 10 15 - 25 - 15 -5 5 15 26
VD - Drain Voltage (V) VD - Drain Voltage (V)
RDS(on) vs. VD and Temperature RDS(on) vs. VD and Power Supply Voltage

100 50
TA = 25 °C
CL = 10 nF
R DS(on) - Drain-Source On-Resistance (Ω)

90
7.5 V 40
80
30
70 1 nF
10 V 20
60
Q (pC)

12 V 10
50
15 V
0
40 20 V
22 V 100 pF
30 - 10

20 - 20

10 - 30
0 5 10 15 20 25 - 15 - 10 -5 0 5 10 15
VD - Drain Voltage (V) VS - Source Voltage (V)
RDS(on) vs. VD and Power Supply Voltage (V- = 0 V) Charge Injection vs. Analog Voltage

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 5
DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1000p 40
V+ = 15 V
V- = -15 V ID (off)
20
VL = 5 V ID (on)
VD = ± 14 V
IS (off)
0 IS (off)
100p

I S, I D (pA)
- 20
I D (off)

ID (on)
- 40
10p
- 60
ID (off)

- 80

1p - 100
- 40 - 20 0 20 40 60 80 - 15 - 10 -5 0 5 10 15
Temperature (°C) VD or V S - Drain or Source Voltage (V)
Leakage Current vs. Temperature Leakage Current vs. Analog Voltage

100 nA I- 120
V+ = 15 V
V- = - 15 V V+ = 15 V
VL = 5 V V- = - 15 V
I+ 100 VL = 5 V tON
1 nA
IL 80
t ON , t OFF (ns)

VS = 10 V
I+, I-, IL (A)

100 pA 60 VS = - 10 V

tOFF
VS = 10 V
40
10 pA

20
VS = - 10 V

1 pA 0
- 40 - 20 0 20 40 60 80 100 - 40 - 20 0 20 40 60 80 100

TA - Temperature (°C) TA - Temperature (°C)


Supply Current vs. Temperature Switching Time vs. Temperature*

180 300
VS = 5 V
160 270 0V
VS = 5 V
140 240
VS = - 5 V 210
120
t ON, t OFF (ns)
t ON , t OFF (ns)

180 -5V
100
150
80 - 15 V
tON 120
60
90
VS = 5 V
40 tON
60 - 15 V
tOFF -5V
20 tOFF
VS = - 5 V 30
0V
0 0
0 ±5 ± 10 ± 15 ± 20 ± 25 0 5 10 15 20 25
V+, V- Positive and Negative Supplies (V) V+ - Positive Supply (V)
Switching Time vs. Power Supply Voltage* Switching Time vs. Positive Supply Voltage*
* Refer to Figure 2 for test conditions.

www.vishay.com Document Number: 70049


6 S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100 mA

10 mA

1 mA

Supply Current (A)


100 µA

10 µA

1 µA

100 nA

10 nA
10 100 1K 10K 100K 1M 10M
Frequency (Hz)
Supply Current vs. Switching Frequency

SCHEMATIC DIAGRAM Typical Channel

V+

VL
V–
Level
Shift/
VIN
Drive
V+

GND
D

V–

Figure 1.

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 7
DG401, DG403, DG405
Vishay Siliconix
TEST CIRCUITS
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and
trailing edge of the output waveform.

tf < 20 ns
Logic tf < 20 ns
50 %
+5V + 15 V Input
0V
VL V+ tOFF
Switch
VS
S D Input*
± 10 V VO VO
90 %

IN
RL CL
Switch 0V
1 kΩ 35 pF
GND V- Output tON
90 %
VO
Switch -V S
- 15 V Input*

CL (includes fixture and stray capacitance) * VS = 10 V for t ON, V S = - 10 V for tOFF


RL Note: Logic input waveform is inverted for switches that
VO = V S
have the opposite logic sense control
RL + rDS(on)

Figure 2. Switching Time

+5V + 15 V 3V
Logic
Input 50 %
VL V+
0V
S1 D1 VS1
VS1 VO1
VO1
90 %
S2 D2 VO2
VS2
Switch 0V
Output
IN VS2
RL1 CL1 VO2 90 %
GND V-
RL2
L2 CL2 Switch 0V
tD tD
Output
- 15 V

CL (includes fixture and stray capacitance)

Figure 3. Break-Before-Make

+5V + 15 V

VL V+ ΔVO
Rg
S D VO
VO

Vg IN CL IN
3V 10 nF On On
Off
GND V-
Q = ΔVO x CL

- 15 V
Figure 4. Charge Injection

www.vishay.com Document Number: 70049


8 S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TEST CIRCUITS

+5V + 15 V
C C
+5V + 15 V
VL V+
C C
VS S1 D

VL V+ Rg = 50 Ω
VS S D VO
50 Ω
VO S2
Rg = 50 Ω RL
IN 100 Ω
0 V, 2.4 V RL
IN
0.8 V
GND V- C
GND V- C

- 15 V
- 15 V
VS
Off Isolation = 20 log VS
VO XTALK Isolation = 20 log
VO
C = RF bypass C = RF bypass

Figure 5. Off Isolation Figure 7. Crosstalk

+5V + 15 V
+5V + 15 V
C C C C

VL V+
VL V+ S
VS S D VO
Meter
Rg = 50 Ω
RL IN HP4192A
IN 100 Ω 0 V, 2.4 V Impedance
0 V, 2.4 V Analyzer
D or Equivalent
GND V- C
GND V- f = 1 MHz
C

- 15 V
C = RF bypass
- 15 V

Figure 6. Insertion Loss Figure 8. Capacitances

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 9
DG401, DG403, DG405
Vishay Siliconix
APPLICATIONS

+5V + 15 V
+5V + 15 V

VL V+ VL V+ eout
Left S1 D1 S1 D1 +
ein -
Source 1 S3 D3 Left
S3 D3
Right
IN1 IN1
Left
C1
S2 D2 S2
Integrate/ D2
Source 2
Right Reset
Right S4 D4 S4 D4
TTL

C2
IN2 IN2
TTL
DG403
Channel DG403
Select GND V- Slope GND V-
Select

- 15 V - 15 V
Figure 9. Stereo Source Selector Figure 10. Dual Slope Integrator

Dual Slope Integrators:

The DG403 is well suited to configure a selectable slope +5V + 15 V


integrator. One control signal selects the timing capacitor C1
or C2. Another one selects ein or discharges the capacitor in VL V+
preparation for the next integration cycle.
S1 D1

S3 D3
Band-Pass Switched Capacitor Filter:
IN1

Single-pole double-throw switches are a common element S2 D2


for switched capacitor networks and filters. The fast ein
switching times and low leakage of the DG403 allow for S4 D4
higher clock rates and consequently higher filter operating
frequencies.
IN2

Clock DG403
GND V-

- 15 V
+
eout
-

Figure 11. Band-Pass Switched Capacitor Filter

www.vishay.com Document Number: 70049


10 S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
APPLICATIONS

Peak Detector:
A3 acting as a comparator provides the logic drive for the analog input voltage. When ein goes below eout A3 goes
operating SW1. The output of A2 is fed back to A3 and negative, turning SW1 off. The system will therefore store the
compared to the analog input ein. If ein > eout the output of A3 most positive analog input experienced.
is high keeping SW1 closed. This allows C1 to charge up to

Reset

SW2

SW1 R1

A1 +
ein + A2 eout

C1
+ DG401
A3

Figure 12. Positive Peak Detector

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70049.

Document Number: 70049 www.vishay.com


S09-2561-Rev. I, 30-Nov-09 11
Package Information
Vishay Siliconix

SOIC (NARROW): 16ĆLEAD


JEDEC Part Number: MS-012

MILLIMETERS INCHES
Dim Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.20 0.004 0.008
B 0.38 0.51 0.015 0.020
C 0.18 0.23 0.007 0.009
D 9.80 10.00 0.385 0.393
E 3.80 4.00 0.149 0.157
16 15 14 13 12 11 10 9 e 1.27 BSC 0.050 BSC

E H 5.80 6.20 0.228 0.244


L 0.50 0.93 0.020 0.037
1 2 3 4 5 6 7 8
Ĭ 0_ 8_ 0_ 8_
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5300

D H
C

All Leads
0.101 mm
A1 Ĭ
e B L
0.004 IN

Document Number: 71194 www.vishay.com


02-Jul-01 1
Package Information
Vishay Siliconix

PDIP: 16ĆLEAD

16 15 14 13 12 11 10 9

E1 E

1 2 3 4 5 6 7 8

D
S
Q1

A1 L

15°
C MAX
B1 e1 B eA

MILLIMETERS INCHES
Dim Min Max Min Max
A 3.81 5.08 0.150 0.200
A1 0.38 1.27 0.015 0.050
B 0.38 0.51 0.015 0.020
B1 0.89 1.65 0.035 0.065
C 0.20 0.30 0.008 0.012
D 18.93 21.33 0.745 0.840
E 7.62 8.26 0.300 0.325
E1 5.59 7.11 0.220 0.280
e1 2.29 2.79 0.090 0.110
eA 7.37 7.87 0.290 0.310
L 2.79 3.81 0.110 0.150
Q1 1.27 2.03 0.050 0.080
S 0.38 1.52 .015 0.060
ECN: S-03946—Rev. D, 09-Jul-01
DWG: 5482

Document Number: 71261 www.vishay.com


06-Jul-01 1
Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-16

RECOMMENDED MINIMUM PADS FOR SO-16

0.372
(9.449)

0.047
(1.194)
(6.248)

(3.861)
0.246

0.152
0.022 0.050 0.028
(0.559) (1.270) (0.711)

Recommended Minimum Pads


Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

www.vishay.com Document Number: 72608


24 Revision: 21-Jan-08
Legal Disclaimer Notice
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Disclaimer

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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.

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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED

Revision: 08-Feb-17 1 Document Number: 91000

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