Signal Integrity-(SI

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• • • • • • Why Signal Integrity What is Signal Integrity When to use Signal Integrity Where to use Signal Integrity Who does the Signal Integrity How to Validate Signal Integrity

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Why DO Signal Integrity
• • • • • • • • COST and RISK REDUCTION Project COST Control Reduce Project Risk Reduce Product Risk Quality Control and Corporate Image Product Liability Changing Times Physics & Image

What is Signal Integrity
• SI is the study of electrical signals effecting
– – – – Circuit TIMING Product RELIABILITY Product EMI and EMC Product MANUFACTURABILITY

• Effects on signaling by real world PHYSICS
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When to do SI Analysis
• • • • • • • Product Concept Design Stage Functional Distribution of System Elements Mid Design Issues - Clock Distribution, etc. PCB Placement Analysis PCB Post Layout - Pre Fabrication Manufacturing Tolerance Analysis Post Fabrication Validation

Where to Use Signal Integrity
• Critical Circuits
– Clocks – Busses – I/O

• Design Subsystems (FSB, PCI, AT, TDM) • Complete Boards • Connected System Elements

Factors Affecting Signal Integrity
• Component Variation
– Process, Voltage, Temperature, Manufacturer

• • • • •

Material Variations Power Distribution Signal Crosstalk PCB Layout PCB Construction

Who Does Signal Integrity
• Consultants
– Summit Computer Systems, Inc.

• Design Engineers • PCB Layout Facility • Signal Integrity Group

How we do the SI Analysis
• TOOLS
– QUAD Design XTK – Spice when needed

• EXPERIENCE
– 10 Years QUAD experience – 30+ Years Electrical Engineering Experience – GTL, (P)ECL, CMOS, etc. to > 1GHz

Why SI - Project COST Control
• • • • • Early determination of Project Viability Validate project in simulation vs hardware Cheaper board turn - simulation / hardware Much faster board turn - hours vs Weeks Much faster time to end product - lower costs - Fewer turns of board. • Make all customer shipments ONE WAY

Why SI - Reduce Project Risk
• • • • • • Expose Project problems EARLY Determine Reliability Risk Early Simulate until configuration works FIRST Know the project will work then BUILD Solve EMI and EMC Problems Early Test forward and backward compatibility with other system components.

Why SI - Reduce Product Risk
• Determine operational performance before first build. • Will it work at What speed? • Is it reproducible - Manufacturing tolerance • System Test Suite • Compatibility Test Suite
– Forward and Backward, other plug-in boards

Why SI - Quality Control
• Document Design Quality • Build in the Design Tolerance for Component Tolerance and aging • Show Customers Quality Results • Determine manufacturing tolerance analysis • Remove faulty timing • DESIGN QUALITY IN EARLY

Why SI - Product Liability
• Assure the product will perform as designed • Make Design defendable to management and customers • Test Product to Required Standards in simulation before fabrication • Be able to prove reasonable effort.

Why SI - Physics
• SI is ENERGY CONTROL • Generated Energy is 105 to 108 above receivers needs • High Spectral Energy is absorbed by:
– – – – Terminations Material in board coupling to nearby lines Radiation to free space (License Required)
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Why SI - Changing Times
• • • • • • • Product Life Cycles Reduced Product Design Cycle MUST be Reduced Higher Power - Higher Speed Circuits Also Lower Power - GREEN requirements More stringent environmental requirements Product liability considerations Risk Control Management

Why SI - Image
• • • • Customer Confidence! Make it work correctly for customer Reliability breeds customer loyalty Market Timing for New Technology

SI Factors: Component Variation
• Semiconductor variations
– PROCESS – VOLTAGE – TEMPERATURE

• • • •

Vendor to Vendor variations Vendor product changes over time Passive component tolerance analysis Monte Carlo analysis required

SI Factors - Material Variations
• FR4 Variations
– er range from 3.9 to 4.9 – Thickness control – Plating Control

• Gtek, Polyemide and Teflon based material • Copper/Solder conductivity variations • Etching control of geometry

SI Factors - Power Distribution
• • • • • • • What voltage Where Voltage transients Ground return currents Ground shift on boards Connector limitations Connector contact resistance vs time Heat transfer and cooling
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SI Factors - Signal Crosstalk
• • • • • • How does one signal line effect the next Coupling factors Run Length Edge Rates Ground References Return paths

SI Factors - PCB Layout
• • • • • • • What did the Router do to you Critical circuit isolation Keeping non-critical circuits non-critical Energy storage near components Signal Return Path Thermal concerns on nearby components Using Ground Plane bypass and isolation

SI Factors - PCB Construction
• All variations of PCB Fabrication process
– Material Variations – Human Factors

• • • •

Stackup control for impedance Impedance Controlled Fabrication Stackup measurement techniques Test Coupons

When SI - Product Concept Design Stage
• Test Configurations before Architecture is complete - easy to fix now. • Test Operation Limits - Marketing Claims • Test Interconnectivity required by the proposed design • Test alternative configurations • SI is Lowest cost part of Design verification

When SI - Mid Design Issues Clock Distribution, etc.
• Plan and Verify timing budgets • Simulate and VERIFY clock distribution skews to meet design requirements • Verify Memory configurations • Verify timing requirements on memory parts and Processor bus • Verify Bus topology and termination plan

When SI - PCB Placement Analysis
• Verify component placement • Add Terminations based on Component Placement • Verify Signal Timing between Components • Verify Critical sections as layout continues

When SI - PCB Post Layout - Pre Fabrication
• Verify Entire Board
– Verify Timing on board – Verify Crosstalk is within specification – Verify COMPONENT tolerance allocations

• Verify Signal Integrity on entire board • Test Board Operation with System • Test System Operation for timing and signal

When SI - Manufacturing Tolerance Analysis
• Simulate Critical Board Operations
– – – – Timing with component variations Voltage margins at destinations Board Fabrication tolerance build up Part tolerance build up

• Monte Carlo Analysis • Identify Critical Failure Items • Establish Manufacturing Restriction

When SI - Post Fabrication Validation
• • • • • • • Verify board timing against Simulation Verify signal quality against Simulation Verify models against results Validate models used Fix models as appropriate Validate Assumptions Fix assumptions if needed

Where SI - Critical Circuits
• • • • • • • Clock Trees Bus Structures Differential Clocks Differential I/O Signals All Signals above 20 MHz (50ns period) All Signals with > 4ma Drive All Signals with Transitions < 5ns

Where SI - Clocks
• • • • • Validate Clock Timing Distribution Check Clock waveform at destination Confirm Clock Skew designs Validate Clock Signal Termination Build Clock Skew budget

Where SI - Busses
• • • • • Validate Bus Topology Validate Bus Termination Schema Validate Bus Signal Integrity Validate Bus Timing Validate Bus Driver tolerance

Where SI - I/O
• • • • • • Differential I/O I/O noise coupling from board I/O noise coupling into board All I/O above 5 MHz Line terminations for Critical I/O Signal Cross Talk to local signals

Where SI - Complete Boards
• • • • Complete Timing Complete Cross Talk Component Substitution for Cost Reduction Component Replacement from alternate vendors • Component Process variations • Worse Case combinations (Monte Carlo Method)

Where SI - Connected System Elements
• Board performance in backplane • Board interconnection with remainder of system • Timing throughout connected boards • Signal Quality throughout connected boards • Bus connections between boards (100 MHz to 133+ MHz)

SI and Circuit TIMING
• • • • • • Propagation Delay Waveform analysis Timing Skew in systems Timing Quality in system Clock Driver certification Clock Driver tolerance analysis

SI and PRODUCT RELIABILITY
• Signal integrity across product for:
– Voltage tolerance – Process tolerance – Temperature tolerance

• Connector and Cable Tolerance • Manufacturing Tolerance

SI and Product EMI and EMC
• Emission Energy Suppression at Signal Quality • Cross Talk to I/O circuits • Cross Talk from I/O circuits • Advanced checking with far field analysis • Use of Quiet program

SI and Product MANUFACTURABILITY
• Test Passive Component Tolerance • Test Fabrication Tolerance
– Controlled Stack – Controlled Impedance

• Component Substitution Analysis • Material variation analysis

Effects on signaling by real world PHYSICS
• • • • • • • Signal Energy Generation Signal Energy Absorption Signal Energy Distribution Signal Energy Reception Signal Energy ESCAPE from control Signal propagation E/M Field confinement Unintentional Signal Coupling

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