A.

SANYASI RAO
Dept. of ECE

Assoc. Prof. & HoD

Balaji Institute of Engineering & Sciences Narsampet, Warangal

What is a Combinational circuit? At instant, the output of the logic circuit depends on present inputs.

Design procedure:
1.Identify the number of inputs and outputs required for the design of the circuit. 2.Derive the truth table. 3.Write the expression for the output either in SOP or POS form. 4.Simplify the expression for the output. 5.Draw the logic circuit for the simplified expression.

ADDERS
Logic circuit which performs the addition of binary numbers Adders of two types: 1. Half Adder (H.A) 2. Full Adder (F.A) Half Adder It is a combinational logic circuit which performs addition of two binary bits.

A 0 0 1 1

B 0 1 0 1

Sum(S) Carry(C ) 0 1 1 0 0 0 0 1

S = AB + A B C = AB

Full Adder
It is a combinational logic circuit which performs addition of three binary inputs.

S = A BCin + ABC in + A BC in + ABC in = A ( BCin + BC in ) + A ( BC in + BC in ) = A( B ⊕ Cin ) + A( B ⊕ Cin ) = A ⊕ B ⊕ Cin Cout = ABC in + A BCin + AB C in + ABC in = Cin ( AB + A B ) + AB (C in + Cin ) = Cin ( A ⊕ B ) + AB

Realizing Full Adder with two Half Adders and one OR gate

SUBTRACTORS
Logic circuit which performs subtraction of binary numbers. Subtractors are of two types: 1. Half Subtractor (H.S) 2. Full Subtractor (F.S) Half Subtractor
A Half Subtr actor D BOUT A 0 0 1 1 B 0 1 0 1 Difference( Borrow(B0 D) ) 0 1 1 0 0 1 0 0

B

D = AB + A B B0 = AB

Full Subtractor
Combinational circuit which performs subtraction on three binary digits.
A B Bin A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Half Subtr actor Bin 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 D

D = ABBin + AB B in + AB B in + ABCin = A ( BBin + B B in ) + A ( B B in + BBin ) = A( B ⊕ Bin ) + A( B ⊕ Bin ) = A ⊕ B ⊕ Bin Bout = ABBin + AB B in + ABBin + ABBin = Bin ( AB + AB) + AB ( B in + Bin ) = Bin ( A ⊕ B) + AB

BOUT BOUT 0 1 1 1 0 0 0 1

Realizing Full Subtractor using two Half Subtractors & one OR gate
A Half Subtractor B Bin Half Subtractor D

Bout

4-Bit Binary Parallel Adder

Each stage in the parallel adder depends on the previous stage carry. Delay time is additive.

1’s Complement Subtractor

It requires two stages of addition. When the end carry is 1, it has to be added with the LSB adder. If the end carry is zero, single stage of addition produces the result but the answer is

2’s Complement Adder/Subtractor

Adder Subtractor

if if

M=0 M=1

When the control input, M is 0 the output of XOR gates are B3B2B1B0 and the circuit functions as a 2’s complement adder. When the control input is 1 the output of XOR gates are B3’ B2’ B1’ B0’ which is the 1’s complement of the subtrahend. Since the control input is 1, the binary 1 is added with the LSB added with B3’ B2’ B1’ B0’ which

produces 2’s complement of the subtrahend.

BCD Adder
C4

A3 B3 F.A S3

A2 B2 F.A S2

A1 B1 F.A S1

A0 B0 H.A

F.A

H.A

COUT

S’3

S’2

S’1

S’0

The BCD adder requires two stages of addition when the result is greater than 9. the result will be greater than 9, if C4 = 1 or S3S2 = 1 or S3S1 = 1. Therefore the logic expression for these conditions are Y= C4 + S3S2 + S3S1
.

if Y=1, binary 6 must be

Carry Look Ahead Adder
The parallel adder is ripple carry type in which the carry output of each full adder stage is connected to the carry input of the next higher-order stage . Therefore, the sum and carry occurs; this leads to a time delay in the addition process. This delay is known as propagation delay. One method of speeding up this process by eliminating inter stage carry delay is called look ahead carry addition. The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propagate and generate logic to make addition much faster.

Ai Bi

Pi

Si

Gi Ci Ci+1

P = Ai ⊕Bi i Gi = Ai Bi The output sum and carry can be w ritten as S i = P ⊕Ci i Ci +1 = Gi + P Ci i
It uses two functions: Carry Generate & Carry Propagate.

Gi is called a carry generate and it produces on carry when both Ai and Bi are 1, regardless of the input carry. Pi is called a carry propagate because it is the term associated with the Pi = (Ai ⊕ Gi = Ai.Bi               propagation of the carry from Ci to Ci+1 B=G + C i)                       
1 0

P0.C0                                                                        C2 = A 1⊕ B 1.CC = G1 P ⊕P1.G0 + Si = Gi + P ⊕ 1 i = + Ci i i P1.P0.C0                               Since all carries' are dependent on C0 , they can C = G2 + P2.G1 + P2.P1.G0 + be3 generated simultaneously and the addition process becomes.C0                              P2.P1.P0 faster. The hardware required is more. Hence
the carry-look ahead adder is expensive compared to

C0 A0 B0

C0 P0 G0 CARRY P1 G1 A2 B2 A3 B3 LOOK AHEAD GENERAT OR C2 P2 S2 P1 C1 S1 P0 S0

A1 B1

P2 G2

P3 P3 G3 C3 C4

S3 C4

COMPARATORS
A comparator is a logic circuit use to compare the magnitudes of two binary numbers. It provide an output that is active when the two numbers are equal, or additionally provide outputs that signify which of the numbers is greater when equality does not hold. The XNOR gate (coincide gate) is a basic comparator, because its output is a 1 only if its two input bits are equal. Two binary numbers are equal, if and only if all their corresponding bits coincide. For instance, two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 are equal. To implement Equality = ( A3Θ 3 )( A2 Θ 2 )( A1Θ 1 )( A0 Θ 0 ) B B B B this logic

1-Bit Magnitude Comparator
I A0 = ad f 1 n t eeoe hr f r , I A0 = a d f 0 n t eeoe hr f r , I f A0 a d n

The logic for a 1-bit comparator: let the 1-bit numbers be A=A0 and B=B0
B0 = , t e 0 hn A> B A > :G = 0 B0 B A B 0 =, t e 1 hn A< B

A < : L = 0 B0 B A B0 c i cd on i e ,t e hn A= B

t eeoe hr f r ,

A = : E = 0 Θ0 B A B

A0 0 0 1 1

B0 0 1 0 1

L 0 1 0 0

E 1 0 0 1

G 0 0 1 0

A0

B0

2-bit Magnitude Comparator The logic for a 2-bit magnitude comparator: 1.If A1 = 1 and B1 = 0, then A > B or 2.If A1 and B1 coincide and A0 = 1 and B1 = 0, then A > B. So the logic for A > B is

A > B : G = A1 B 1 + ( A1ΘB1 ) A0 B 0
1.If A1 = 0 and B1 = 1, then A < B or 2.If AJ1 and B1 coincide and A0 = 0 and B0 = 1, then A < B. So the logic for A < B is

A < B : L = A1 B1 + ( A1ΘB1 ) A0 B0

If A1 and B1 coincide and if A0 and B0 coincide then A = B. So the logic for A = B is

A = B : E =( A1Θ 1 )( A0 Θ 0 ) B B
A1 B’
1

A0

A > B

A1 B1 A0 B0

B’
0

A = B B0

A’
0

A’
1

A < B

B1

4-Bit Magnitude Comparator
The logic for a 4-bit magnitude comparator: 1.If A3 = 1 and B3 = 0, then A > B or 2.If A3 and B3 coincide, and if A2 = 1 and B2 = 0, then A > B or 3.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=1 and B2 = 0, then A > B or 4.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=1 and B1 = 0, then A > B : G = A3 B 3 + ( A3ΘB3 ) A2 B 2 + A > or So the logic for A > B is ( A3ΘB3 )( A2 ΘB2 ) A1 B1 + ( A3ΘB3 )( A2 ΘB2 )( A1ΘB1 ) A0 B 0

The logic for A < B is: 1.If A3 = 0 and B3 = 1, then A < B or 2.If A3 and B3 coincide, and if A2 = 0 and B2 = 1, then A < B or 3.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=0 and B2 = 1, then A < B or 4.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=0 and B1 = 1, then A < B or A < B : L = SoB 3 + (logic for AB2 + is A3 the A3ΘB3 ) A2 < B ( A3ΘB3 )( A2 ΘB2 ) A1 B1 + ( A3ΘB3 )( A2 ΘB2 )( A1ΘB1 ) A0 B0

2-Bit Binary Multiplier
A1 B1 A 1 B1 P4 P3 A 1 B0 A0 B1 P2 P1 A0 B0 A0 B 0 A1 B1 B0 A0 B1 B0

H. A

H. A

P4

P3

P2

P0

MULTIPLEXERS
A Multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output. The routing of the desired data input to the output is controlled by SELECT lines. A MUX selects 1-out-of-N input data sources and transmits the selected data to a single output channel. This is called Multiplexing. MUX is also known as Many to One device.

2 i/p s
n

2n X n MUX o/p

n select lines

4 X 1 MUX

Y = S 1 S 0 I 0 + S 1S 0 I1 + S1 S 0 I 2 + S1S0 I 3
S1 I0 S1 0 0 1 1 S0 0 1 0 1 Y I0 I1 I2 I3 I1 I2 I3 Y S0

Applications of Multiplexers
1.Data selection 2.Data routing 3.Operation sequencing 4.Waveform generation 5.Parallel to serial conversion 6.Logic function generation

Logic Function Generator
•A multiplexer can be used in place of logic gates to implement a logic expression. •It can generate any Boolean algebraic function of a set of input variables. •A single IC can perform a function. •It is very easy to change the logic function implemented, if and when redesign of a system becomes necessary. Multiplexers can be used to implement a logic function directly from the function table without the need for simplification. The select inputs of the multiplexer are used as the function variables. The inputs of the multiplexer are connected to logic 1 and 0 to represent the missing and available terms.

Ex:

Implementation of F(A,B,C) = Σm(1,3,5,6) using 8 : 1 MUX
1 0 0 1 2 3 4 5 6 7 S2 S1 S0 8:1 MUX

Y

A

B

C

Ex:

Implementation of F(A,B,C) = Σm(1,3,5,6) using 8 : 1 MUX

Step 1: Select the MSB variable as input and the remaining as selector lines variables to the MUX. If the function has n variables, then the size of the required MUX is 2n-1 – to – 1. Step 2: Draw the truth table for the given function. Step 3: Complete the function table. a) if both the minterms are circled, apply 1 to the corresponding MUX input. b) if both are not circled, apply 0 to the corresponding MUX input. c) if the top is circled and bottom is not circled, apply A1 to the corresponding MUX input. d) if the top is not circled and bottom is circled, apply A to the corresponding MUX input.

I0 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 0 1 0 1 1 0 1 A A1 0 I0 I1 I2 I3 A1 A 0 0 4

I1 1 5 1

I2 2 6 A

I3 3 7 A1

4:1 MUX S1 S0 B C

Y

DEMULTIPLEXER
Demultiplexer, DEMUX does the reverse

operation of a MUX. It receives the message over one input line and directs the message to of the many output lines. Hence it known as One to Many device.

1 X 2n i/p DEMUX

2n o/p s

n select lines

S1 0 0 1 1

S0 0 1 0 1

D 1 1 1 1

Y0 1 0 0 0

Y1 0 1 0 0

Y2 0 0 1 0

Y3 0 0 0 1

S0

S1

Y0 =S 1 S 0 D Y1 =S 1 S 0 D Y2 =S1 S 0 D Y3 =S1 S 0 D
D
AND AND AND AND

Y0

Y1 Y2 Y3

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