Data Converter Architectures

DAC Architectures

Figures from CMOS Circuit Design, Layout, and Simulation

DAC Architectures
• Digital to analog Conversion can be achieved using : A) Voltage Division B) Current Steering C) Charge Scaling
DAC Architecture that we will study will be primarily based on these!

Figures from CMOS Circuit Design, Layout, and Simulation

• Different types of input codes to DAC

Figures from CMOS Circuit Design, Layout, and Simulation

• High RC time constant (slow). relative accuracy of the resistor string becomes an important factor (Derivation of INL). Remedy is to use binary switch array.• • A simple resistor string DAC fails in maintaining balance between area and power. and Simulation . Layout. Figures from CMOS Circuit Design. As resolution increases.

Layout. and Simulation .Figures from CMOS Circuit Design.

Requires matching to be within the resolution of the converter.: Common mode Voltage is fixed. Use dummy switches.• • • • • + terminal always at GND/Virtual Gnd. Also switch resistance need to be small (voltage drop will induce error). Figures from CMOS Circuit Design. Layout. There are problems: a) Vomax=Vref/2-1LSB Adv. and Simulation .

and Simulation . Layout.Figures from CMOS Circuit Design.

Area and size of elements? Figures from CMOS Circuit Design. Good current drive inherent in the system.• • • • Two Flavors: a) Unit Elements (monotonic) b) Binary weighted. and Simulation . (2^N)-1 sources required. Layout.

and Simulation .Figures from CMOS Circuit Design. Layout.

Switched capacitor-parasitic insensitive integrator may be used Capacitor array itself is a critical component here! To avoid the layout problem.• • • • Parasitic capacitance problem. Layout. Split array will be used. and Simulation . Figures from CMOS Circuit Design.

Figures from CMOS Circuit Design. Layout. and Simulation .

creating potentially large DNL and INL errors as N increases. and Simulation .• When the capacitor is fabricated. Layout. undercutting of the mask causes an error in the ratio of the capacitors. Figures from CMOS Circuit Design.

Wet and Dry Etching • • In etching. a liquid or plasma chemical agent removes the uppermost layer of the substrate in the areas that are not protected by photoresist. Undercutting of the Resist. is a phenomenon caused by the capillary action of the wet chemicals used for etching. Undercutting. causing windows or features that are larger in size than intended. Layout. Poor adhesion of the resist to the masking film can lead to undercutting during the wet etching process. Figures from CMOS Circuit Design. and Simulation . or the unwanted exposure and etching of a material beyond its defined limits. Larger windows caused by undercutting can cause adjacent metal lines to become short-circuited.

and Simulation . Layout.Figures from CMOS Circuit Design.

Figures from CMOS Circuit Design. and Simulation . Layout.

• • • LSB first For n. Biggest benefit? Figures from CMOS Circuit Design.bit word how many clock cycles are needed. and Simulation . Layout.

and Simulation .• N clock Latency! • Just a variation of Cyclic Figures from CMOS Circuit Design. Layout.

Sources of errors: RESISTOR STRING MISMATCH & COMPARATOR OFSET . Layout.• • • All of them are clocked comparators. and Simulation . For N bits. how many Comparator/Resistors? Figures from CMOS Circuit Design.

Figures from CMOS Circuit Design. Layout. and Simulation .

Layout.Figures from CMOS Circuit Design. and Simulation .

and Simulation .Figures from CMOS Circuit Design. Layout.

Figures from CMOS Circuit Design. and Simulation . Layout.

and Simulation . Layout.Figures from CMOS Circuit Design.

and Simulation .Figures from CMOS Circuit Design. Layout.

and Simulation . Layout.• How to Get rid-of RC? Figures from CMOS Circuit Design.

and Simulation .Figures from CMOS Circuit Design. Layout.

RC is cancelled. Figures from CMOS Circuit Design. and Simulation . Layout.• At the end.

Figures from CMOS Circuit Design. and Simulation . Layout.

Layout.Figures from CMOS Circuit Design. and Simulation .

Figures from CMOS Circuit Design. and Simulation . Layout.

Figures from CMOS Circuit Design. Layout. and Simulation .

Layout.Figures from CMOS Circuit Design. and Simulation .

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