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Finite State Machines

ECE 449 Computer Design Lab

George Mason University

Resources
Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right Chapter 6, Finite State Machines Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Chapter 8, Synchronous Sequential Circuits

ECE 449 Computer Design Lab

Finite State Machines


Any Circuit with Memory Is a Finite State Machine
Even computers can be viewed as huge FSMs

Design of FSMs Involves


Defining states Defining transitions between states Optimization / minimization

Above Approach Is Practical for Small FSMs Only


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Moore FSM (1)


Output Is a Function of Present State Only
Inputs Transition function Next State Memory (register) Present State

Output function
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Outputs

Mealy FSM (1)


Output Is a Function of a Present State and Inputs
Inputs Transition function

Next State
Memory (register)

Present State

Output function
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Outputs
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Moore Machine
Describe Outputs as Concurrent Statements Depending on State Only
transition condition 1 state 1 / output 1 state 2 / output 2 transition condition 2

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Mealy Machine
Describe Outputs as Concurrent Statements Depending on State and Inputs

transition condition 1 / output 1 state 2

state 1

transition condition 2 / output 2

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Moore vs. Mealy FSM (1)


Moore and Mealy FSMs Can Be Functionally Equivalent
Equivalent Mealy FSM can be derived from Moore FSM and vice versa

Mealy FSM Has Richer Description and Usually Requires Smaller Number of States
Smaller circuit area

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Moore vs. Mealy FSM (2)


Mealy FSM Computes Outputs as soon as Inputs Change
Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

Moore FSM Has No Combinational Path Between Inputs and Outputs


Moore FSM is less likely to introduce delays in critical path

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Moore FSM - Example 1


Moore FSM that Recognizes Sequence 10
0 1

S0 / 0
reset

S1 / 0

S2 / 1

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Mealy FSM - Example 1


Mealy FSM that Recognizes Sequence 10
0/0 1/0 1/0

S0
reset 0/1

S1

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Moore & Mealy FSMs Example 1

clock 0 input 1 0 0 0

S0
Moore S0 Mealy

S1
S1

S2
S0

S0
S0

S0
S0

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FSMs in VHDL
Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed
State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process
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FSM States (1)


architecture behavior of FSM is type state is (list of states); signal FSM_state: state; begin process(clk, reset) begin if reset = 1 then FSM_state <= initial state; else case FSM_state is

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FSM States (2)


case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if; end case; end if; end process;
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Moore FSM - Example 1


Moore FSM that Recognizes Sequence 10
0 1

S0 / 0
reset

S1 / 0

S2 / 1

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Moore FSM in VHDL


type state is (S0, S1, S2); signal Moore_state: state; U_Moore: process(clock, reset) Begin if(reset = 1) then Moore_state <= S0; elsif(clock = 1 and clockevent) then case Moore_state is when S0 => if input = 1 then Moore_state <= S1; end if; when S1 => if input = 0 then Moore_state <= S2; end if; when S2 => if input = 0 then Moore_state <= S0; else Moore_state <= S1; end if; end case; end if; End process; Output <= 1 when Moore_state = S2 else 0; ECE 449 Computer Design Lab 17

Mealy FSM - Example 1


Mealy FSM that Recognizes Sequence 10
0/0 1/0 1/0

S0
reset 0/1

S1

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Mealy FSM in VHDL


type state is (S0, S1); signal Mealy_state: state; U_Mealy: process(clock, reset) Begin if(reset = 1) then Mealy_state <= S0; elsif(clock = 1 and clockevent) then case Mealy_state is when S0 => if input = 1 then Mealy_state <= S1; end if; when S1 => if input = 0 then Mealy_state <= S0; end if; end case; end if; End process; Output <= 1 when (Mealy_state = S1 and input = 0) else 0;

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Moore FSM Example 2: State diagram


Reset w = 1 w = 0 A z = 0 w = 0 w = 0 w = 1 B z = 0

C z = 1

w = 1

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Moore FSM Example 2: State table

Next state Present state w = 0 w = 1 A B C A A A B C C

Output z 0 0 1

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Moore FSM Example 2: VHDL code (1)


USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN cont ...
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Moore FSM Example 2: VHDL code (2)


CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ;
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Alternative VHDL code (1)


ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ;
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Alternative VHDL code (2)


WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ;

PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ;
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Mealy FSM Example 2: State diagram

Reset w = 1 z = 0 w = 0 z = 0 A w = 0 z = 0 B w = 1 z = 1

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Mealy FSM Example 2: State table

Present state A B

Next state w= 0 A A w= 1 B B

Output z w= 0 0 0 w= 1 0 1

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Mealy FSM Example 2: VHDL code (1)


LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w z END mealy ;

: IN STD_LOGIC ; : OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ;
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Mealy FSM Example 2: VHDL code (2)


WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ;

with y select z <= '0' when A, z <= w when others;


END Behavior ;

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State Encoding Problem


State Encoding Can Have a Big Influence on Optimality of the FSM Implementation
No methods other than checking all possible encodings are known to produce optimal circuit Feasible for small circuits only

Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

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Types of State Encodings (1)


Binary State Encoded as a Binary Number
Small number of used flip-flops Potentially complex transition functions leading to slow implementations

One-Hot Only One Bit Is Active


Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs
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Types of State Encodings (2)


State
S0 S1 S2 S3 S4 S5

Binary Code
000 001 010 011 100 101

One-Hot Code
10000000 01000000 00100000 00010000 00001000 00000100

S6 S7

110 111

00000010 00000001

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A user-defined attribute for manual state assignment


(ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING ATTRIBUTE ENUM_ENCODING OF State_type SIGNAL y_present, y_next : State_type ; BEGIN cont ...

: STRING ; : TYPE IS "00 01 11" ;

Figure 8.34 ECE 449 Computer Design Lab 33

Using constants for manual state assignment (1)


ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; cont
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RTL Design Components


Data Inputs Control Inputs

Datapath Circuit

Control Circuit

Data Outputs
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Datapath Circuit
Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task Examples of Resources
Adders, Multipliers, Registers, Memories, etc.

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Control Circuit
Controls Data Movements in Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources Follows Some Program or Schedule Usually Implemented as FSM

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Control Unit Example: Arbiter (1)


reset

r1 r2 r3

g1

Arbiter

g2 g3

clock
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Control Unit Example: Arbiter (2)


Reset Idle 000

0xx

1xx

gnt1 g1 = 1
x0x

1xx
gnt2 g2 = 1 x1x

01x

xx0

001

gnt3 g3 = 1
xx1
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Control Unit Example: Arbiter (3)


Reset Idle r1 r1

r 1r 2 r 3

gnt1 g1 = 1 r2 r1 gnt2 g2 = 1 r3 r2 gnt3 g3 = 1 r3


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r 1r 2

r 1r 2 r 3

Arbiter VHDL code (1)


LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY arbiter IS PORT ( Clock, Resetn r g END arbiter ;

: IN : IN : OUT

STD_LOGIC ; STD_LOGIC_VECTOR(1 TO 3) ; STD_LOGIC_VECTOR(1 TO 3) ) ;

ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= Idle ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN Idle => IF r(1) = '1' THEN y <= gnt1 ; ELSIF r(2) = '1' THEN y <= gnt2 ; ELSIF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ;
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Arbiter VHDL code (2)


WHEN gnt1 => IF r(1) = '1' THEN y <= gnt1 ; ELSE y <= Idle ; END IF ; WHEN gnt2 => IF r(2) = '1' THEN y <= gnt2 ; ELSE y <= Idle ; END IF ; WHEN gnt3 => IF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ; END CASE ; END IF ; END PROCESS ; g(1) <= '1' WHEN y = gnt1 ELSE '0' ; g(2) <= '1' WHEN y = gnt2 ELSE '0' ; g(3) <= '1' WHEN y = gnt3 ELSE '0' ; END Behavior ;
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Hands-on Session
Enough Talking Lets Get To It !!Brace Yourselves!!

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Experiment 3 Introduction

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Experiment 3 Part 1
Non-resetting detector of the sequence: (101)+ (11)+
sd sc sb

sa Input: Output:

se

00101001011101111111011011011100101 00000000000100010101000000000100000

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Experiment 3 Part 1

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN

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Experiment 3 Part 2 Bonus


Non-resetting detector of the sequence: (001)+ (1100)
SB SA Input: Output: SC

001010011100100111001001110000101 000000000001000000010000000100000

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Experiment 3 Part 2 Bonus

English

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN

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Questions?

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