Cs-2nd yr 2011-12 (additional

)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

9/4/2012

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• The minimum mode is selected by making the MN/MX equal to 1. • The maximum mode is selected by making the MN/MX equal to 0. • Minimum mode 8086 system has one microprocessor.

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

9/4/2012

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Naveen Kr. Dubey (ECE DEPT ..RKGITW)

9/4/2012

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Dubey (ECE DEPT .Naveen Kr.RKGITW) 9/4/2012 4 ..

Dubey (ECE DEPT .RKGITW) 9/4/2012 5 .Naveen Kr..

Naveen Kr. Dubey (ECE DEPT ..RKGITW) 9/4/2012 6 .

Dubey (ECE DEPT .Naveen Kr..RKGITW) 9/4/2012 7 .

Dubey (ECE DEPT ..RKGITW) 9/4/2012 8 .Naveen Kr.

Dubey (ECE DEPT .interrupts Naveen Kr..RKGITW) 9/4/2012 9 .

RKGITW) 9/4/2012 10 ..Naveen Kr. Dubey (ECE DEPT .

.Software Interrupt Execution of INT instruction.RKGITW) 9/4/2012 11 .Hardware Interrupt External interrupt applied to nonmaskable interrupt NMI. .Interrupts in 8086 An 8086 Interrupt can come from any of three sources. Dubey (ECE DEPT . External interrupt applied to maskable interrupt INTR. . Naveen Kr.

Dubey (ECE DEPT .INTR INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge Operation INTA Interrupt Acknowledge from the MP NMI NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt request to the µP Naveen Kr..RKGITW) 9/4/2012 12 .

Dubey (ECE DEPT . the memory location to which an interrupt goes is always four times the value of the interrupt number .. INT 03h goes to 000Ch Naveen Kr.In the 8086 there are a total of 256 interrupts (or interrupt types) –INT 00 –INT 01 –… –INT FF  In 80x86.RKGITW) 9/4/2012 13 .

.RKGITW) 9/4/2012 14 . Dubey (ECE DEPT .Interrupt Vector Table IVT Naveen Kr.

RKGITW) 9/4/2012 15 .The lowest five types are dedicated to specific interrupts. Dubey (ECE DEPT .. Naveen Kr. Interrupts 5 to 31 are reserved by INTEL for complex Processors Upper 224 interrupt types ( 32 to 255) available to use for hardware or software interrupts.

Dubey (ECE DEPT . Interrupt Type one – INT 1 Single step Interrupt If trap flag is set 8086 will do a type 1 interrupt after every instruction execution.. If the quotient is too large to fit into AL/AX Divide by zero interrupt invoked.RKGITW) 9/4/2012 16 . Naveen Kr.Interrupt Type zero – INT 0 Divide by zero interrupt.

Non Maskable Interrupt – Type 2 When 8086 receives a low to high transition on its NMI input. Type 2 interrupt response cannot be disabled ( masked) by any program instruction. Naveen Kr. Dubey (ECE DEPT ..RKGITW) 9/4/2012 17 . Could be used for handling critical situations like power failure detection.

Break Point Interrupt – Type 3 INT 3 instruction – to implement breakpoint routines. Overflow Interrupt – Type 4 INTO: Interrupt on overflow instruction used for invoking an interrupt after overflow in an arithmetic operation.RKGITW) 9/4/2012 18 . The system execute instruction up to break point and then goes to break point routine. Dubey (ECE DEPT . If no overflow it will be a NOP instruction. Naveen Kr.. Used for debugging.

INTO 2. INTR 4.RKGITW) 9/4/2012 19 . INT nn.. NMI 3.Interrupt Priority HIGH 1. Divide error. Dubey (ECE DEPT . Single Step LOW Naveen Kr.

.What if 8086 receives INTR while executing DIV which produces divide-by-zero error? 8086 executes INT 00 (as it has higher priority) This clears the IF and thus disables INTR Complete routine of INT 00 is executed and in the end IRET is executed This enables the INTR again Now INTR will be processed Naveen Kr.RKGITW) 9/4/2012 20 . Dubey (ECE DEPT .

RKGITW) 9/4/2012 21 .What if 8086 receives NMI while executing DIV which produces divide-by-zero error? 8086 executes INT 00 (as it has higher priority) This clears the IF but does not disable NMI Branching to ISR0 and then again to ISR2 Return back to ISR0 and then to mainline program Naveen Kr. Dubey (ECE DEPT ..

.. DL. AH. CL. Dubey (ECE DEPT . CH. DI. Naveen Kr. -24.RKGITW) 9/4/2012 22 . memory: [BX]. immediate: 5. SREG: DS. [BX+SI+7].. SP. 10001101b. etc.(see Memory Access). DX. BP. variable. etc. SS. BX. BH. SI. and only as second operand: CS. AL. CX...     Operand types: REG: AX. BL. 3Fh. DH. ES.

Dubey (ECE DEPT . m1 m2 DW ? AX. For example: AL.RKGITW) 9/4/2012 23 . both operands must have the same size (except shift and rotate instructions). For example: REG. AX m1 DB ? AL. memory When there are two operands. DL DX. m2   􀁺  􀁺 Naveen Kr.Notes: When two operands are required for an instruction they are separated by comma..

For example: memory.Some instructions allow several operand combinations. immediate REG. immediate memory..RKGITW) 9/4/2012 24 . REG REG. SREG  Naveen Kr. Dubey (ECE DEPT .

instruction sets this flag to 0.     These marks are used to show the state of the flags: 1 . ? . r .instruction sets this flag to 1. 0 .RKGITW) 9/4/2012 25 . Naveen Kr.flag value depends on result of the instruction.flag value is undefined (maybe 1 or 0).. Dubey (ECE DEPT .

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CF) according to result.RKGITW) 9/4/2012 33 . AF.     CLC – Clear Carry Flag CLD – Clear Destination Flag CLI Clear Interrupt Flag (this disables H/W interrupts ) CMC – Compliment Carry Flag CMP . ZF. SF. immediate REG.REG. Dubey (ECE DEPT . REG memory. Naveen Kr. immediate  result is not stored anywhere. REG REG. memory memory. flags are set (OF.. PF.

CMPSB (No operands)             Compare bytes: ES:[DI] from DS:[SI]. AF.RKGITW) 9/4/2012 34 . CF if DF = 0 then SI = SI + 1 DI = DI + 1 else SI = SI .ES:[DI] set flags according to result: OF..1 DI = DI . SF.1 􀁺 􀁺 􀁺 􀁺 􀁺 􀁺 􀁺 Naveen Kr. PF. ZF. Dubey (ECE DEPT . Algorithm: DS:[SI] .

PF.2 􀁺 􀁺 􀁺 􀁺 􀁺 􀁺 􀁺 Naveen Kr. AF.ES:[DI] set flags according to result: OF. CMPSW            Compare words: ES:[DI] from DS:[SI]. Algorithm: DS:[SI] .RKGITW) 9/4/2012 35 . Dubey (ECE DEPT . SF.. ZF.2 DI = DI . CF if DF = 0 then SI = SI + 2 DI = DI + 2 else SI = SI .

RKGITW) 9/4/2012 36 . 0 . Algorithm: if high bit of AX = 1 then: DX = 65535 (0FFFFh) else DX = 0 Example: 􀁺 􀁺 MOV DX.. DX AX = 00000h:0FFFBh CWD . DX AX = 0FFFFh:0FFFBh RET Naveen Kr. AX = 0 MOV AX. -5 . CWD             Convert Word to Double word. Dubey (ECE DEPT . DX = 0 MOV AX. 0 .

. Corrects the result of subtraction of two packed BCD values. DAA  DAS Decimal adjust After Addition.RKGITW) 9/4/2012 37 . Dubey (ECE DEPT . Corrects the result of addition of two packed BCD Values  Decimal adjust After Subtraction.  Naveen Kr.

Unsigned divide.. Dubey (ECE DEPT .Memory)  Decrement.RKGITW) 9/4/2012 38 .  DEC DIV (Reg . Algorithm: when operand is a byte: AL = AX / operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus) Naveen Kr.

AX = 0FF35h MOV BL. Algorithm: when operand is a byte: AL = AX / operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus) Example: MOV AX. AL = -50 (0CEh). IDIV Signed divide. 4 IDIV BL .. Dubey (ECE DEPT . AH = -3 (0FDh) Naveen Kr.RKGITW) 9/4/2012 39 . -203 .

Dubey (ECE DEPT . Example: MOV AL. Algorithm: when operand is a byte: AX = AL * operand. -2 MOV BL.RKGITW) 9/4/2012 40 . AX = 8 RET Naveen Kr.IMUL (REG Memory)  Signed multiply.. when operand is a word: (DX AX) = AX * operand. -4 IMUL BL .

DX AX.    Interrupt 4 if Overflow flag is 1.byte AL.255). DX)  INC (reg. im. Algorithm: if OF = 1 then INT 4 Naveen Kr..RKGITW) 9/4/2012 41 . Second operand is a port number.IN (AL..  Interrupt numbered by immediate byte (0. im.byte AX. Dubey (ECE DEPT . If required to access port number over 255 DX register should be used  Increment. memory)  INT (immidiate byte)  INTO  Input from port into AL or AX.

. IRET  LAHF Interrupt Return. Algorithm: AH = flags register  􀁺 􀁺 􀁺 Naveen Kr. Dubey (ECE DEPT .RKGITW) 9/4/2012 42 . Pop from stack: IP CS flags register  Load AH from 8 low bits of Flags register.

Algorithm:  REG = first word 􀁺 ES = second word   Naveen Kr. Algorithm: 􀁺 REG = first word 􀁺 DS = second word  LES Load memory double word into word register and ES.. LDS     Load memory double word into word register and DS.RKGITW) 9/4/2012 43 . Dubey (ECE DEPT .

RKGITW) 9/4/2012 44 .Naveen Kr.. Dubey (ECE DEPT .

 􀁺 􀁺 􀁺 􀁺 Naveen Kr. Update SI. Dubey (ECE DEPT . Update SI. Algorithm: AL = DS:[SI] if DF = 0 then SI = SI + 1 else SI = SI – 1  Load word at DS:[SI] into AX..RKGITW) 9/4/2012 45 . LODSB  LODSW Load byte at DS:[SI] into AL.

jump to label if CX not zero and Not Equal (ZF = 0). Dubey (ECE DEPT .  ZF=0 .CF!=0   ZF=1 . jump to label if CX not zero and Equal (ZF = 1)  LOOPNE   LOOPNZ LOOPZ Decrease CX. jump to label if CX not zero Decrease CX. LOOP ◦ LOOPE   Decrease CX..CF!=0 Naveen Kr.RKGITW) 9/4/2012 46 .

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.RKGITW) 9/4/2012 69 .Naveen Kr. Dubey (ECE DEPT .

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