4446 Design of Microprocessor-Based Systems

I/O System Design

Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology

11-1

Introduction (cont’d)
 65,536 possible I/O ports  Data transfer between ports and the processor is over data bus  8088 uses address bus A[15:0] to locate an I/O port  AL (or AX) is the processor register that takes input data (or provide output data) Data bus
AL AX

I/O
8088

I/O

I/O

Address bus A[15:0]
11-2

Introduction
• I/O devices serve two main purposes
– To communicate with outside world – To store data

• I/O controller acts as an interface between the systems bus and I/O device
– Relieves the processor of low-level details – Takes care of electrical interface

• I/O controllers have three types of registers
– Data – Command – Status
11-3

Introduction (cont’d) 11-4 .

…) • This access depends on I/O mapping – Two basic ways » Memory-mapped I/O » Isolated I/O – A protocol to communicate (to send data. status.Introduction (cont’d) • To communicate with an I/O device. …) • Three types – Programmed I/O – Direct memory access (DMA) – Interrupt-driven I/O 11-5 . we need – Access to various registers (data.

16.and 32-bit I/O ports – Also supports memory-mapped I/O FFFFF FFFFF Memory addressing space 00000 I/O FFFF I/O addressing 0000 space Memory addressing space 11-6 00000 Direct I/O Memory-mapped I/O .Accessing I/O Devices • I/O address mapping – Memory-mapped I/O • Reading and writing are similar to memory read/write • Uses same memory read and write signals • Most processors use this I/O mapping – Isolated I/O • Separate I/O address space • Separate I/O read and write signals are needed • Pentium supports isolated I/O – 64 KB address space » Can be any combination of 8-.

DX – DX gives the port address . memory address in ES:(E)DI • outs: port address in DX.Accessing I/O Devices (cont’d) • Accessing I/O ports in 80x86 – Register I/O instructions in in accumulator. port8 . direct format – Useful to access first 256 ports accumulator. memory address in ES:(E)SI • We can use rep prefix for block transfer of data 11-7 . indirect format – Block I/O instructions • ins and outs – Both take no operands---as in string instructions • ins: port address in DX.

80H 6H AL AX FFFF 00FF Accessed through DX Accessed directly by instructions  Accessing through DX IN IN OUT OUT AL. 0A0H. 3CH. AX. DX DX AL AX 00F8 0000 11-8 .8088 Port Addressing Space  Addressing Space  Accessing directly by instructions IN IN OUT OUT AL. AX. DX. DX.

the gating device transfers input data to CPU data bus — The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus 11-9 .Input Port Implementation Data Bus Gating device Decoder Other control signals 8088 Input Address bus — The outputs of the gating device are high impedance when the processor is not accessing the input port — When the processor is accessing the input port.

Input Port Implementation  Circuit Implementation — Assume that the address of the input port is 9CH A7 A6 A5 A4 A3 A2 A1 A0 Data bus Tri-state buffer CE Input data RD IO/M 11-10 .

Input Port Implementation 11-11 .

Output Port Implementation  Circuit Implementation — Assume that the address of the output port is 9CH A7 A6 A5 A4 A3 A2 A1 A0 Data bus Latch CLK Output data WR IO/M 11-12 .

Output Port Implementation 11-13 .

A Reconfigurable Port Decoder 1 A7 A6 A5 A4 A=B B3 A3 B2 A2 Vcc R A1 A0 B1 B0 A=B A3 A2 A1 A=B B3 A3 B2 A2 A1 A0 B1 B0 A0 A=B RD or WR IO/M 11-14 .

An Example I/O Device • Keyboard – Keyboard controller scans and reports – Key depressions and releases • Supplies key identity as a scan code – Scan code is like a sequence number of the key » Key’s scan code depends on its position on the keyboard » No relation to the ASCII value of the key – Interfaced through an 8-bit parallel I/O port • Originally supported by 8255 programmable peripheral interface chip (PPI) 11-15 .

An Example I/O Device (cont’d) • 8255 PPI has three 8-bit registers • Port A (PA) • Port B (PB) • Port C (PC) – These ports are mapped as follows 8255 register PA (input port) PB (output port) PC (input port) Command register Port address 60H 61H 62H 63H 11-16 .

An Example I/O Device (cont’d) Mapping of 8255 I/O ports 11-17 .

An Example I/O Device (cont’d) • Mapping I/O ports is similar to mapping memory – Partial mapping – Full mapping • Keyboard scan code and status can be read from port 60H – 7-bit scan code is available from • PA0 – PA6 – Key status is available from PA7 • PA7 = 0 – key depressed • PA0 = 1 – key released 11-18 .

I/O Data Transfer • Data transfer involves two phases – A data transfer phase • It can be done either by – Programmed I/O – DMA – An end-notification phase • Programmed I/O • Interrupt • Three basic techniques – Programmed I/O – DMA – Interrupt-driven I/O 11-19 .

I/O Data Transfer (cont’d) • Programmed I/O – Done by busy-waiting • This process is called polling • Example – Reading a key from the keyboard involves • Waiting for PA7 bit to go low – Indicates that a key is pressed • Reading the key scan code • Translating it to the ASCII value • Waiting until the key is released 11-20 .

8255 Programmable Peripheral Interface 11-21 .

8255 Programmable Peripheral Interface Data bus D[7:0] 8088 A0 A1 RD WR RESET Control port PC[7:0] PA[7:0] PB[7:0] A7 A6 A5 A4 A3 A2 IO/M CS A1 0 0 1 1 A0 0 1 0 1 Port PA PB PC Control 11-22 .

8255 Programmable Peripheral Interface 11-23 .

and mode 2 11-24 . mode 1.Programming 8255  8255 has three operation modes: mode 0.

Programming 8255  Mode 0: — Ports A. 5 PB[7:0] OBFB ACKB INTRB 11-25 . 7 PB[7:0] STBB IBFB INTRB 8255 PC2 PC1 PC0 PC4. B. and C can be individually programmed as input or output ports — Port C is divided into two 4-bit ports which are independent from each other  Mode 1: — Ports A and B are programmed as input or output ports — Port C is used for handshaking PA[7:0] PC4 PC5 PC3 STBA IBFA INTRA PC7 PC6 PC3 PA[7:0] OBFA ACKA INTRA 8255 PC2 PC1 PC0 PC6.

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Programming 8255  Mode 2: — Port A is programmed to be bi-directional — Port C is for handshaking — Port B can be either input or output in mode 0 or mode 1 PA[7:0] PC7 PC6 OBFA ACKA STBA IBFA INTRA In In In PB[7:0] Out Out Out STBB IBFB INTRB OBFB ACKB INTRB 8255 PC4 PC5 PC3 PC0 PC0 PC0 1. 2. PC0-PC3 as input. port A as input. Mode 1 Mode 0 Can you design a decoder for an 8255 chip such that its base address is 40H? Write the instructions that set 8255 into mode 0. PC4-PC7 as output ? 11-28 . port B as output.

Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams. .

BIT5 JZ Read IN AL.test IBF . read portc . PORTA • READ ENDP 11-30 .Example: Mode 1 Input 8255 keyboard • BIT5 EQU • PORTC • PORTA • READ • Read: – – – – 20H EQU EQU PA0 22H 20H PA7 PROC NEAR .if IBF=0 . PORTC TEST AL.Read Data STB PC4 DAV IN AL.

Example: Mode 1 output 8255 PB0 PB7 Printer ACK PC2 PC4 ACK DS Data Strobe : to tell the printer to latch the incoming data. Generated Externally 11-31 .

get data OUT PORTB. AL MOV AL.send character to printer MOV AL.test OBF JZ PRINT .if OBF=0 buffer is full PRINT ENDP 11-32 .print data . AL . AL . PORTC .Example: Mode 1 output BIT1 EQU PORTC PORTB CMD EQU PRINT PROC 2 EQU 62H EQU 61H 63H NEAR . check printer ready? IN AL. 8 . send data strobe to printer MOV AL.rising the data at the positive edge of DS RET .clear DS OUT CMD.get OBF TEST AL.clear DS OUT CMD. BIT1 . AH . 9 .

Keyboard example 1/2 11-33 .

Keyboard example 2/2

11-34

Bouncing Problem

11-35

Bouncing

11-36

Software Solution 11-37 .

De-bouncing Circuitry Two asynchronous flip-flop solutions are given below • The basic idea is that these flip-flops store the values even if the D/D nodes both float 11-38 .

Another Solution 11-39 .

External Interface • Two ways of interfacing I/O devices – Serial • Cheaper • Slower – Parallel • Faster • Data skew • Limited to small distances 11-40 .

External Interface (cont’d) Two basic modes of data transmission 11-41 .

External Interface (cont’d) • Serial transmission – Asynchronous • Each byte is encoded for transmission – Start and stop bits • No need for sender and receiver synchronization – Synchronous • Sender and receiver must synchronize – Done in hardware using phase locked loops (PLLs) • Block of data can be sent • More efficient – Less overhead than asynchronous transmission • Expensive 11-42 .

External Interface (cont’d) 11-43 .

External Interface (cont’d) Asynchronous transmission 11-44 .

External Interface (cont’d) • EIA-232 serial interface – Low-speed serial transmission – Adopted by Electronics Industry Association (EIA) • Popularly known by its predecessor RS-232 – It uses a 9-pin connector DB-9 • Uses 8 signals – Typically used to connect a modem to a computer 11-45 .

External Interface (cont’d) • Transmission protocol uses three phases – Connection setup • Computer A asserts DTE (Data Terminal Equipment) Ready – Transmits phone# via Transmit Data line (pin 2) • Modem B alerts its computer via Ring Indicator (pin 9) – Computer B asserts DTE Ready (pin 4) – Modem B generates carrier and turns its DCE (Data Communication Equipment) Ready • Modem A detects the carrier signal from modem B – Data transmission – Modem A alters its computer via Carrier Detect (pin 1) – Turns its DCE Ready • Done by handshaking using • Done by deactivating RTS – Connection termination – request-to-send (RTS) and clear-to-send (CTS) signals 11-46 .

and fault • Can be initialized with INIT – Clears the printer buffer and resets the printer 11-47 . computer waits for ACK • 5 lines for printer status – Busy.External Interface (cont’d) • Parallel printer interface – A simple parallel interface – Uses 25-pin DB-25 • 8 data signals – Latched by strobe (pin 1) • Data transfer uses simple handshaking – Uses acknowledge (CK) signal » After each byte. online/offline. autofeed. out-of-paper.

External Interface (cont’d) 11-48 .

However. including start. . it requires clock signal Frame Asynchronous Data transfer data Start bit B0 B1 B2 B3 B4 B5 B6 Stop bits Parity Synchronous Data transfer clk data B0 B1 B2 B3 B4 B5 11-49 Baud (Baud is # of bits transmitted/sec. data and parity). However. Synchronous — Asynchronous transfer does not require clock signal. stop. it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits.s.Serial Data Transfer  Asynchronous v.

8251 USART Interface 8251 D[7:0] RD WR A0 CLK RD WR C/D CLK RS232 TxD RxD TxC RxC A7 A6 A5 A4 A3 A2 A1 IO/M 11-50 .

11-51 .

8251 BLOCK DIAGRAM 11-52 .

8251 PIN DIAGRAM 11-53 .

Mode x1 clock x16 clock x64 clock Parity 0: odd 1: even 11-54 .Programming 8251  8251 mode register 7 6 5 4 3 2 1 0 Mode register Number of Stop bits 00: 01: 10: 11: invalid 1 bit 1.5 bits 2 bits Parity enable 0: disable 1: enable Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: 01: 10: 11: Syn.

DTR pin will be low RxE: receiver enable SBPRK: send break character.Programming 8251  8251 command register EH IR RTS ER SBRK RxE DTR TxE command register TxE: transmit enable DTR: data terminal ready. TxD pin will be low ER: error reset RTS: request to send. CTS pin will be low IR: internal reset EH: enter hunt mode 11-55 .

Programming 8251  8251 status register DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register TxRDY: RxRDY: TxEMPTY: PE: OE: FE: SYNDET: DSR: transmit ready receiver ready transmitter empty parity error overrun error framing error sync. character detected data set ready 11-56 .

Simple Serial I/O Procedures  Read start  Write start Check RxRDY No Is it logic 1? Yes Check TxRDY No Is it logic 1? Yes Read data register* end * This clears RxRDY Write data register* end * This clears TxRDY 11-57 .

Errors – Parity error: Received data has wrong error -transmission bit flip due to noise. • Software is failing to read the data from the FIFO. – Framing error: Start and stop bits not in their proper places. 11-58 . – Overrun error: Data has overrun the internal receiver FIFO buffer. • This usually results if the receiver is receiving data at the incorrect baud rate.

Programmable Timer 8254 11-59 .

8254 Programming 11-60 .

– If two bytes are programmed. 11-61 . and the second byte (MSB) starts the counter with the new count. • Each counter has a program control word used to select the way the counter operates. then the first byte (LSB) stops the count. – Minimum count is 1 all modes except 2 and 3 with minimum count of 2.8254 Programming • Each counter may be programmed with a count of 1 to FFFFH.

8254 Read Back Command  8254 Read Back Command 1 1 COUNT STATUS CNT2 CNT1 CNT0 0  8254 status word format OUTPUT COUNT NULL RW1 RW0 M2 M1 M0 BCD NULL COUNT: goes low when the new count written to a counter is actually loaded into the counter 11-62 .

Mode 1: One-shot mode. – – The G input triggers the counter to output a 0 pulse for `count' clocks.8254 Modes • – Mode 0: An events counter enabled with G. The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts. 11-63 . Counter reloaded if G is pulsed again.

8254 Modes • Mode 2: Counter generates a series of pulses 1 clock pulse wide. 50% duty cycle otherwise OUT is high 1 cycle longer. • If count is even. 11-64 . – The seperation between pulses is determined by the count. – The cycle is repeated until reprogrammed or G pin set to 0. – Mode 3: Generates a continuous square-wave with G set to 1.

• Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.8254 Modes • Mode 4: Software triggered one-shot – (G must be 1). 11-65 .

Motor Control 11-66 .

Motor Control 11-67 .

11-68 .

DMA • Direct memory access (DMA) – Problems with programmed I/O • Processor wastes time polling – In our example » Waiting for a key to be pressed. » Waiting for it to be released • May not satisfy timing constraints associated with some devices – Disk read or write – DMA • Frees the processor of the data transfer responsibility 11-69 .

– Multiple instructions would be required to accomplish data transfer • • • • read the byte from the hard disk place it in memory increment a memory pointer test for another byte to read 11-70 .DMA Example • A hard disk data transfer rate of 5MB/s – One byte every 200 ns !! • A microprocessor hardly can execute even one instruction in 200 ns.

DMA 11-71 .

or vice versa) 11-72 .DMA • DMA is implemented using a DMA controller – DMA controller • Acts as slave to processor • Receives instructions from processor • Example: Reading from an I/O device – Processor gives details to the DMA controller » I/O device number » Main memory buffer address » Number of bytes to transfer » Direction of transfer (memory  I/O device.

memory buffer pointer.DMA • Steps in a DMA operation – Processor initiates the DMA controller • Gives device number. it is ready for data transfer – When ready. loops back to repeat the process – Notify the processor when done • Typically uses an interrupt 11-73 . I/O device informs the DMA controller • DMA controller starts the data transfer process – – – – – Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read. … – Called channel initialization • Once initialized.

I/O Data Transfer (cont’d) DMA controller details 11-74 .