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PRESENTATION

ON COMPUTER ORGANISATION AND ARCHITECTURE

Submitted by : RAVI RANJAN (CS Deptt)

 REGISTER TRANSFER AND LANGUAGE
A register transfer is defined as the transfer of information b/w register with the help of common bus

• Register : Register is defined as group of flip flop with each flip flop capable of storing 1 byte • BUS : Group of wire carrying information from one place to another

Register A

Register B

Register C

Register D

Bus lines

 TYPES OF REGISTERS :
1. 2. 3. 4. 5. 6. 7. 8. accumulator (AC) Program counter (PC) Temporary register (TR) Instruction register (IR) Data register (DR) Address register (AR) Input register (INPR) Output register (OUTR)

Register symbol No of bits Register name DATA REGISTER ADRESS REGISTER ACCUMULATOR REGISTER INSTRUCTION REGISTER PROGRAM REGISTER TEMPORARY REGISTER INPUT REGISTER OUTPUT REGISTER Function register Hold memory operand Hold address memory Processor register Hold instruction code Hold address Hold temporary data Hold input character Hold output character DR AR AC IR PC TR INPR OUTR 16 12 16 16 12 16 8 8 .

 The basic data movements possible within a four-bit shift register . with the output of one flip-flop being connected to the input of its neighbour. The logical configuration of a serial shift register consists of a chain of flip-flops connected in cascade. Shift register A register that is capable of shifting data one bit at a time is called a shift register.

 TYPES OF REGISTERS : 1. 7. 2. 6. 4. 8. 5. 3. accumulator (AC) Program counter (PC) Temporary register (TR) Instruction register (IR) Data register (DR) Address register (AR) Input register (INPR) Output register (OUTR) .

by carrying out all communications over a single data channel.  The construction of a bus system for four registers : S1 S0 0 0 0 1 1 0 1 1 Register selected A B C D . BUS AND MEMORY TRANSFER The purpose of buses is to reduce the number of "pathways" needed for communication between the components.

it is called read and when the information is stored in memory it is called write operation Memory read : A transfer information into DR from the memory word M selected by the address in AR Memory Write : A transfer information from R1 into the memory word M selected by the address in AR NOTE : in both operation the memory word is specified by an address. Memory Transfer When the information is transfer from memory . This memory word is represented by symbol ( M). .

encoders 7. For example. or ALU. that does mathematical calculations is constructed using combinational logic. such as 1. COMBINATIONAL CIRCUITS : Combinational logic is used in computer circuits to do Boolean algebra on input signals and on stored data. the part of an arithmetic logic unit. full adders 3. Other circuits used in computers. full subtractors 5. Practical computer circuits normally contain a mixture of combinational and sequential logic. half subtractors 4. half adders 2.decoders . multiplexers 6.

 ADDERS : an adder or is a digital circuit that performs addition of numbers. Truth table for Half adder INPUTS A 0 0 1 1 B 0 1 0 1 OUTPUTS SUM 0 1 1 0 CARRY 0 0 0 1 .  Half adder : The simplest combinational circuit which performs the arithmetic addition of two binary digit is a half adder.

Contd : LOGIC DIAGRAM : .

FULL ADDER : A combination that performs addition of 3 bits (2 significant bit) and 1 previous carry is known as full adder. Truth table for full adder : INPUTS A 0 B 0 C 0 OUTPUTS SUM 0 CARRY 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 1 0 1 1 1 S = A’B’C+A’BC’+AB’C’+AB’C’+ABC C = A’BC+AB’C+ABC’+ABC .

LOGIC DIAGRAM : .

K MAP for full adder : C AB 0 0 1 1 00 1 0 K map for sum 01 0 1 11 1 0 10 K map for carry C AB 0 0 1 0 00 0 1 01 1 1 11 0 1 10 .

HALF – SUBTRACTOR : A half subtractor is a combinational circuit that subtracts 2 bits & produce their difference. Truth table INPUTS MINUENED X 0 0 1 1 SUTRAHEND Y 0 1 0 1 OUTPUTS DIFFERENCE B 0 1 1 0 BORROW DOUT 0 1 0 0 D = X’Y+XY’ B = X’Y .

FULL SUBTRACTOR : It is a combinational circuit that perform substraction involving 3 bit and the borrow from the previous stage. TRUTH TABLE INPUTS X 0 0 0 0 1 Y 0 0 1 1 0 BIN 0 1 0 1 0 OUTPUTS D 0 1 1 0 1 BOUT 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 1 S = X’Y’B+X’YB’+XY’B’+XYB .

K – MAP for sum : B 0 0 1 1 XY 00 1 1 01 0 1 11 0 0 10 LOGIC SYMBOL .

X Y  A 3*8 decoder has three inputs and eight outputs (Z0 to Z7 ) .DECODERS : A decoder is a combinational circuit that performs or that converts binary information for n output lines to max of 2n uni-output lines.

TRUTH TABLE : INPUTS A0 A1 0 0 0 0 1 1 0 0 1 1 0 0 OUTPUTS Z0 Z1 1 0 0 0 0 0 0 1 0 0 0 0 A2 0 1 0 1 0 1 Z2 0 0 1 0 0 0 Z3 0 0 0 1 0 0 Z4 0 0 0 0 1 0 Z5 0 0 0 0 0 1 Z6 0 0 0 0 0 0 Z7 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 .

LOGIC DIAGRAM : .

one each for the octal digit & 3 output lines that generate binary number . It is constructed with OR gate. Ex of encoder – Octal to binary encoder which consist of 8 input lines.ENCODER: An encoder is a combinational circuit that produce a reverse operation from that of a decoder. An encoder consist of 2n input lines & output lines which operates the binary code for 2n input variables. .

TRUTH TABLE: INPUTS D0 D1 D2 D3 D4 D5 D6 D7 OUTPUTS Q0 Q1 Q2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 .

LOGIC DIAGRAM : .

A digital multiplexer is a combinational circuit that select binary information from one of Many input lines & direct it to a single output lines. The selection of particular input lines is controlled by a set of selection Lines for n selection lines.MULTIPLEXER : The term multiplexer means many into one. There are 2n input lines each of four input i=0 to i=3 applied to one output of AND gate. Selection line S1 & S0 are decoded to select a particular AND gate. INPUT 4*1 MUX S0 S1 .

The OR gate output is equal to Value of I2 and providing a path from a select input .TRUTH TABLE OF 4*1 MULTIPLEXER : S1 0 S0 0 X D0 0 1 1 1 0 1 D1 D2 D3 The other 3 AND gates has a least n input equal to zero .

LOGIC DIAGRAM : .

These lines are meant to carry information. Address bus ( 16 lines) 2. Data bus (8 lines) 3. Control bus (5 lines) .  There are three types of buses : 1.BUS ARCHITECTURE: Bus is a group of wires used to carry binary information .it is collection Of parallel wires of transmitting address data and control signals. Memory & input output devices connected to CPU through a group of Lines are called bus.

It is identified by binary numbers. Address bus is used to carry 16 bit address. the address bus is unidirectional bit flow in one directional.ADDRESS BUS : The address bus is group of 16 lines generally identified as A0 to A15. The microprocessor unit uses address bus to identify a peripheral memory location. Address bus 16 LINES Data bus 8 LINES CPU I/O DEVICES OR MEMORY Control bus 5 LINES .

memory 8085 Microprocessor input Data bus output . The microprocessor uses data bus to tranfer in the binary information.Data bus : It is a group of 8 lines used for data flow. These lines are bi-directional Data flow in both direction between microprocessor & memory & Peripheral devices.

EISA . BUS ARCHITECTURE: 1. ISA . MCA .Extended Industry Standard Architecture 3. Local bus .Industry Standard Architecture 2.Micro Channel Architecture 4.Control bus : The control bus carries commands from the cpu & returns status signals from the device.

but the 2 are completely incompatible. ISA bus is a standard bus architecture that allows 16 bits at a time to flow between Motherboard circuit and an expansion slot card & its associated driver. It does not take full advantage of 32 bit address bus & 32 bit data bus of a 32 bit microprocessor. ISA bus : It stands for INDUSTRY STANDARD ARCHITECTURE . This reduces the data transfer rule of the system.  MCA bus : Micro channel architecture has been developed by IBM. Micro channel Architecture Bus possess the same types of signals and accomplishes the same functions as the EISA.  EISA bus : It uses 32 bit address bus and 32 bit data bus to fulfill the needs of a 32 bit microprocessor data transfer rate. It is a 24 address line & 16 data line bus. . It is twice of that of ISA. MCA boards are smaller and use different edge connectors.

The ISA. Parallel buses usually have 8.32 and 64 data lines. Typically they have one data line and the bits are send one after the other as a packet. The usb and IEEE 1394 bus architecture are examples of serial bus.PCI and EISA buses are example of parallel data bus.BUS ARBITRATION : 1. . Serial bus uses the same line to transfer different data bits of same of the same byte. a controller called bus arbiter decides who gets the bus. Arbitration is mostly done in favor of a master micro processor with the highest priority. Parallel arbitration In a single bus architecture when more than one device requests the bus.16.  Parallel arbitration : Buses that transfer several data bits at the same time are called parallel bus. Serial arbitration 2. this is called the bus arbitration. It is desirable to have wide buses because large chunks of data can be transferred quickly when multiple lines can be used.  Serial arbitration : serial arbitration is also known as daisy chain arbitration.

Each processor has to wait in the queue for its term to use the system bus on FIFO manner. Time slice : In this algorithm the time slice of the bus time is fixed length and allocates sequentially to each processor in round robin manner irrespective of the location of the unit in the system. 2. No processor is given the preference as the priority change dynamically so that each processor can access the system. Each unit is given the same amount of time to communicate it with the system bus and no preference is given to any unit. 3. LRU : (Least recent use) The device that has not used the system bus for longer period has been given highest priority. FIFO: First In First Out queue is established in the same order as the request are received from the processor. .Dynamic arbitration algorithm : This algorithm is followed in three steps: 1.

Increment v. i. Decrement and elementary operation perform all the information stored in one Or more register “R” during 1 cycle. iii.  i. iv. Shift ii. ii.Micro operation : The operation of data on registers are called micro operation . Load iii. Clear iv. The function built into register are example of micro operation . Computer system micro operation perform 4 types: Register transfer micro operation Arithmetic micro operation Logic micro operation Shift micro operation .