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Introduction to FinFet

Haiying Zhao

What does FinFet look like

Gate

Source

Drain

3D view of FinFET

3D view of multi-fin FinFET

What does FinFet look like

Moores law and scaling theory

Ideal scaling: Reduce W,L by a factor of a Reduce the threshold voltage and supply voltage by a factor of a Increasing all of the doping levels by a (W,L,tox,VDD,VTH, etc, are scaled down by a factor a) For a ideal square-law device, Id is reduced by a, but gm and intrinsic gain Gm* ro remain the same. As scaling into submicron region, Short Channel effects prevent further scaling.

Short Channel Effects:DIBL


DIBL: drain induced barrier lowering. DIBL = d(Vth)/d(Vds)

Barrier lowering increases as channel length is reduced, even at zero applied drain bias, because the source and drain form pn junction with the body, and so have associated built-in depletion layers associated with them that become significant partners in charge balance at short channel lengths, even with no reverse bias applied to increase depletion width

Short Channel Effects: Subthreshold swing


Biasing a nmos in subthreshold resgion, Vgs < Vth, Vds is large enough.

Id = u Cd W/L (KT/q)^2 (exp(Vgs Vth)/M))


Cd is capacitance of the depletion layer under gate. M = (1 + Cd/Cox)*KT/q
Id = f(Vgs-Vth) To turn off the transistor, How much reduction of (Vgs-Vth) could lead to a small enough Id. Subthreshold Swing S = d(Vgs)/d(log(Id)) = 2.3 KT/q( 1+ Cd/Cox) The smaller S is , the better it is. Bad Subthreshold Swing will result in higher off-state current if the Vgs applied to turn off the transistor is the same.

Short Channel Effects: Velocity Saturation

V = u E ( E is small enough) V = Vsat ( E is strong enough)


As Vgs increases , the drain current saturates well before pinch-off occurs.

Short Channel Effects:DIBL


DIBL: drain induced barrier lowering. DIBL = d(Vth)/d(Vds)

Barrier lowering increases as channel length is reduced, even at zero applied drain bias, because the source and drain form pn junction with the body, and so have associated built-in depletion layers associated with them that become significant partners in charge balance at short channel lengths, even with no reverse bias applied to increase depletion width

Conclusion

To reduce short channel effects, we need to reduce Xd(channel depletion layer thickness), Xj( Junction depletion width),Xox (oxide layer thickness under gate).

The scale length of bulk MOSFET is an indication of Lg. Lg>

Dealing with Short Channel Effects in bulk MOSFET


1.Increasing body doping concentration 2.Using halo implant

High doping density results in: Lower carrier mobility; high tunneling effect which increases off-state currents; Larger depletion capacitors leading to high subthreshold swing which increases off-state currents; Larger parasitic capacitance, Cgd, Cds.

Dealing with Short Channel Effects in Fully depleted Silicon on Insulator (SOI)

Use ultra-thin film (tsi is small) as the conducting body, depletion layer is confined in the film.( Xd<= tsi).

Eliminate the junction parasitic capacitors. Cuff off the leakage current path from drain to substrate.

From FD/SOI to FinFET


Bend up the gate and narrow the gate. Fin width = 2* film thickness The effect body thickness is reduced by 2. Xd can be regarded as Fin width /2. To obtain good control of SCE, Leff > 1.5*Wfin ( Fin width). Finfet can operate at two mode, single gate and double gate.

FinFet characteristics

Lg = 15nm Some values:


Threshold Voltage = 0.196 V Subthreshold Slope = 72 mV/decade Off Current = 70 A/m

Lg = 30nm

DIBL = 64.67 mV/V

Approximate dc I-V equations?

Square law? One way is using nth power law to computer the FinFet current.

FinFet: Challenges or Opportunities


Carrier mobility: Lightly doped or undoped fin body increases carrier mobility. Short channel length enables velocity overshoot, which increases mobility. Low Vth decreases the vertical electric field ,which increases carrier mobility.

FinFet: Challenges or Opportunities

Tunneling effects: Gate to channel tunneling, Band to band tunneling at PN junction

FinFet: Challenges or Opportunities


Parasitic resistance: a raised source/drain structure can be used to reduce the parasitic resistance. However, the overlap capacitance is increased. Prasitic resistance is the main adverse factor which prevents finfets application, which leads to lower speed and high noise.
rg Gate Cgs ri + vgs gm*vgs Cgd Cds rds rd Drain

rs

Source

FinFet: big advantages


1. Having excellent control of short channel effects in submicron regime and making transistors still scalable. Due to this reason, the small- length transistor can have a larger intrinsic gain compared to the bulk counterpart. Much Lower off-state current compared to bulk counterpart. Promising matching behavior.

2. 3.

Applications

1. Low power design in digital circuit, such as RAM, because of its low off-state current. 2. Power amplifier or other application in analog area which requires good linearity.