CMOS Digital Integrated Circuits
Lec 3
MOS Transistor I
CMOS Digital Integrated Circuits 2
Goals
• Understand the basic MOSFET operation
• Learn the components of the threshold voltages
• Be able to handle body effect
• Be able to calculate drain currents for MOSFET
• Be able to extract basic MOSFET static parameters from IV
plots
CMOS Digital Integrated Circuits 3
MOS Transistor Basics
Two Terminal Structure
Two terminal structure (psubstrate): The MOS capacitor
Important derived parameters. With V
G
= V
B
= 0:
• 
F
– Buck Fermi Potential (Substrate)
• 
S
– Surface Potential (Substrate)
A D I
V
G
V
B
CMOS Digital Integrated Circuits 4
MOS Transistor Basics
Two Terminal Structure (Continued)
• V
FB
– Flat Band Voltage (applied external voltage to GB to flatten bands
of substrate – equal to builtin potential difference of MOS – equal to work
function difference 
GB
between the substrate (channel) and gate.
Operation
With V
G
<0, V
B
=0, Accumulation – Holes accumulate at substrateoxide
interface due to attraction of negative bias
With V
G
>0, but small, V
B
=0, Depletion – Holes repelled from substrate
oxide interface due to positive bias leaving negatively charged fixed
acceptors ions behind. The result is a region below the interface that is
depleted of mobile carriers.
Depletion region thickness
N
q
A
F S
d
S i
x
 
c
÷
=
2
CMOS Digital Integrated Circuits 5
MOS Transistor Basics
Two Terminal Structure (Continued)
Depletion region charge density
Note that this density is per unit of area.
With V
G
>0 and larger, V
B
=0, Inversion – A ntype inversion layer forms,
a condition known as surface inversion. The surface is inverted when the
density of electrons at the surface equals the density of holes in the bulk.
This implies that 
s
has the same magnitude but opposite sign to 
F.
At the
point depletion
depth fixed and the maximum depletion region depth is at

s
= 
F.
This depth is:
N
q
A
F S
dm
i
x

c
2
2
=
 
c
F s S
A d A
i
N
q
x N
q Q ÷ ÷ = ÷ = 2
CMOS Digital Integrated Circuits 6
MOS Transistor Basics
Two Terminal Structure (Continued)
The corresponding depletion charge density (per unit area) at surface
inversion is
The inversion phenomena is the mechanism that forms the nchannel. The
depletion depth and the depletion region charge are critical in determining
properties of MOSFET.

c
F S
A d A
i
N
q
x N
q Q 2 2
0
÷ ÷ = ÷ =
CMOS Digital Integrated Circuits 7
MOS Transistor Basics
Four Terminal Structure
pSubstrate
The MOS nchannel transistor structure:
L
G(ate)
D(rain)
n+
B(ody, Bulk or Substrate)
S(ource)
n+
p
CMOS Digital Integrated Circuits 8
MOS Transistor Basics
Four Terminal Structure (Continued)
Symbols: nchannel  psubstrate; pchannel – nsubstrate
Nchannel (for Pchannel, reverse arrow or add bubbles)
Pchannel
Enhancement mode: no conducting channel exists at V
GS
= 0
Depletion mode: a conducting channel exists at V
GS
= 0
G
D
B
S
G
D
S
G
D
S
G G
D
S
S
D
CMOS Digital Integrated Circuits 9
MOS Transistor Basics
Four Terminal Structure (Continued)
Source and drain identification
G
D
B
S
V
DS
V
SB
V
GS
CMOS Digital Integrated Circuits 10
Threshold Voltage Components
Consider the prior 3D drawing: Set V
S
=0, V
DS
=0, and V
SB
=0.
• Increase V
GS
until the channel is inverted. Then a conducting channel is
formed and the depletion region thickness (depth) is maximum as is the
surface potential.
• The value of V
GS
needed to cause surface inversion (channel creation) is
the threshold voltage V
T0
. The 0 refers to V
SB
=0.
• V
GS
<
V
T0
: no channel implies no current flow possible. With V
GS
>
V
T0
,
existence the channel implies possible current flow.
Threshold Voltage Components
1) u
GC
work function difference between gate and channel
material which is the builtin voltage that must be offset by
voltage applied to flatten the bands at the surface.
2) Apply voltage to achieve surface inversion 2
F
CMOS Digital Integrated Circuits 11
Threshold Voltage Components (Cont.)
3) Additional voltage must be applied to offset the depletion region
charge due to the acceptor ions. At inversion, this charge with V
SB
=0
is Q
B0
= Q
0.
For V
SB
nonzero,
The voltage required to offset the depletion region charge is defined
by –Q
B
/C
ox
where C
ox
= ε
ox
/t
ox
with t
ox
, the oxide thickness, and C
ox
,
the gate oxide capacitance per unit area.
4) The final component is a fixed positive charge density that appears at
the interface between the oxide and the substrate, Q
ox
. The voltage to
offset this charge is:
V N
q Q
SB
F S
A
i
+ ÷ ÷ = 
c
2 2
C
Q
ox
ox
÷
CMOS Digital Integrated Circuits 12
Threshold Voltage Components (Cont.)
These components together give:
For V
SB
=0, V
T0
has Q
B
replaced by Q
B0
. This gives a relationship
between V
T
and V
T0
which is:
Thus the actual threshold voltage V
T
differs from V
T0
by the term
given. Going back to the definition of Q
B
, this term is equal to:
In which γ is the substratebias (or body effect) coefficient.
ox
B B
T T
C
Q Q
V V
0
0
÷
÷ =
( )
F SB F
V   ¸ 2 2 ÷ + ÷ +
ox
ox
ox
B
F GC
T
C
Q
C
Q
V
÷ ÷ ÷ u =  2
CMOS Digital Integrated Circuits 13
Threshold Voltage Components (Cont.)
The final expression for V
T0
and V
T
are
and
• The threshold voltage depends on the sourcetobulk voltage which
is clearly separated out. The component is referred to as body
effect. If the source to body voltage V
SB
is nonzero, the corrective
term must be applied to V
T0
.
C
N
q
ox
S
A
i
c
¸
2
=
( )
F SB F
T T
V
V V
  ¸ 2 2
0
÷ + ÷ + =
ox
ox
ox
B
F GC
T
C
Q
C
Q
V
÷ ÷ ÷ u =
0
0
2
CMOS Digital Integrated Circuits 14
Threshold Voltage Components (Cont.)
Those parameters in the V
T
equation are signed. The
following table gives their signs for nMOS and pMOS
transistor.
For real designs, the threshold voltage, due to variation in
oxide thickness, impurity concentrations, etc., V
T0
and γ
should be measured from the actual process.
Parameter nMOS pMOS

F
÷ +
Q
B
, Q
B0
÷ +
γ + ÷
V
SB
+ ÷
CMOS Digital Integrated Circuits 15
Threshold Voltage
Adjustment by Ion Implant
Depletion mode nMOS
A channel implanted with donors can be present for V
GS
<0.
For this nMOS V
T
<0. Its symbols are as follows:
G
D
B
S
G
D
S
D
S
G G
D
S
CMOS Digital Integrated Circuits 16
MOSFET Modes of Operation
Cutoff
Assume nchannel MOSFET and V
SB
=0
Cutoff Mode: 0≤V
GS
<V
T0
• The channel region is depleted and no current can flow
gate
drain source
I
DS
=0
V
GS
< V
T0
CMOS Digital Integrated Circuits 17
MOSFET Modes of Operation
Linear
Linear (Active, Triode) Mode: V
GS
≥V
T0,
0≤V
DS
≤V
D(SAT)
• Inversion has occurred; a channel has formed
• For V
DS
>0, a current proportional to V
DS
flows from source to
drain
• Behaves like a voltagecontrolled resistance
gate
drain source
current
I
DS
V
DS
< V
GS
– V
T0
CMOS Digital Integrated Circuits 18
MOSFET Modes of Operation
PinchOff
PinchOff Point (Edge of Saturation) : V
GS
≥V
T0,
V
DS
=V
D(SAT)
• Channel just reaches the drain
• Channel is reduced to zero inversion charge at the drain
• Drifting of electrons through the depletion region between the channel
and drain has begun
gate
drain source
current
I
DS
V
DS
= V
GS
– V
T0
CMOS Digital Integrated Circuits 19
MOSFET Modes of Operation
Saturation
Saturation Mode: V
GS
≥V
T0,
V
DS
≥V
D(SAT)
• Channel ends before reaching the drain
• Electrons drift, usually reaching the drift velocity limit, across the
depletion region to the drain
• Drift due to high Efield produced by the potential V
DS
V
D(SAT)
between the drain and the end of the channel
gate
drain source
I
DS
V
DS
> V
GS
– V
T0
CMOS Digital Integrated Circuits 20
MOSFET IV Characteristics
Gradual Channel Approximation
Preliminaries
• Gradual channel approximation will reduce the analysis to a one
dimensional current flow problem.
• Assumption
» V
SB
=0
» V
T0
is constant along the entire channel
» E
y
dominates E
x
¬ Only need to consider the currentflow in
the ydimension
Cutoff Mode: 0≤V
GS
<V
T0
• I
DS(cutoff)
=0
CMOS Digital Integrated Circuits 21
Gradual Channel Approximation
Linear Mode
Linear Mode: V
GS
≥V
T0,
0≤V
DS
≤V
D(SAT)
=> V
DS
– V
GS
<V
T0
• The channel reaches to the drain.
• V
c
(y): Channel voltage with respect to the source at position y
• Boundary Conditions: V
c
(y=0)=V
s
=0; V
c
(y=L)=V
DS
Drain
n+
Source
n+
Substrate (pSi)
(p+)
(p+)
Oxide
x
Channel
Depletion region
V
B
=0
V
S
=0
V
GS
>V
T0
V
DS
<V
DSAT
y=0
y
y=L
CMOS Digital Integrated Circuits 22
Gradual Channel Approximation
Linear Mode (Cont.)
• Q
I
(y): the mobile electron charge density in the surface inversion layer.
Q
I
(y)=C
ox
·[V
GS
V
C
(y)V
T0
]
• The differential resistance (dR) of the channels can represented in terms
of the mobile electron charge (Q
I
(y)) in the surface inversion layer, and
the electron surface mobility μ
n
(about ½ of the bulk electron mobility)
dy
Source end
Drain end
x
l
Channel
CMOS Digital Integrated Circuits 23
Gradual Channel Approximation
Linear Mode (Cont.)
• The differential resistance (dR) of the channels can represented in
terms of the mobile electron charge (Q
I
(y)) in the surface
inversion layer, and the electron surface mobility μ
n
(about ½ of
the bulk electron mobility)
) ( ) ( y
I n
y
d A
n
n n
Q W
dy
Wx N
q
dy
A
dy
dR
µ µ
o
÷ = ÷ = ÷ =
dy
Source end
Drain end
x
d
Channel
dy
Q W
I
dR I dV
y
I n
D
D c
) ( µ
÷ = =
CMOS Digital Integrated Circuits 24
Gradual Channel Approximation
Linear Mode (Cont.)
• Integrating the Ohm’s Law equality between the differential voltage
in the channel and the differential resistance times the drain current,
dV
Q W dy
I
c
DS
y
V
I n
L
D
) (
0 0
} }
÷ = µ
dy
Source end
Drain end
x
d
Channel
( )
dV V V V C
W
L I
c
V
T c GS ox
n
D
DS
}
÷ ÷ =
0
0
µ
CMOS Digital Integrated Circuits 25
Gradual Channel Approximation
Linear Mode (Cont.)
• Finally, the drain current is
• To simplify the equation, we define
κ’: the process transconductance parameter
κ: the device transconductance parameter
 
V V V V
L
W
C
I
DS DS T GS
ox
n
lin D
2
0 ) (
) ( 2
2
÷ ÷ =
µ
L
W
C
L
W
ox
n
µ
k k = = '
CMOS Digital Integrated Circuits 26
Gradual Channel Approximation
PinchOff, Saturation
PinchOff Point (Edge of Saturation) : V
GS
≥V
T0,
V
DS
=V
D(SAT)
• Channel just reaches the drain but is reduced to zero inversion charge
at the drain
• Electrons drift through the depletion region between the channel and
drain
Saturation Mode: V
GS
≥V
T0,
V
DS
≥V
GS
 V
T0
• In pinchoff voltage from the channel end to the source is V
D(SAT)
=V
GS
 V
T0.
Substituting this for V
DS
in the equation for I
D
gives:
2
0 ) (
) (
2
V V
L
W
C
I
T GS
ox
n
SAT D
÷ =
µ
CMOS Digital Integrated Circuits 27
MOSFET IV Characteristics
IV Plots, Channel Length Modulation
• Saturation equation yields curves independent of V
DS
. Not sure! So
we consider the effect of channel length modulation.
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
4
V
DS
(V)
I
D
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
V
DS
= V
GS
 V
T
CMOS Digital Integrated Circuits 28
MOSFET IV Characteristics
Channel Length Modulation
Channel Length Modulation
• With pinchoff the channel at the point y such that V
c
(y)=V
GS
 V
T0
, The
effective channel length is equal to L’ = L – ΔL
ΔL is the length of channel segment over which Q
I
=0.
• Place L’ in the I
D(SAT)
equation:
2
0 ) (
) (
2
V V
L
W
C
I
T GS
ox
n
SAT D
÷
'
=
µ
ΔL
Drain
n+
Source
n+
Substrate (pSi)
(p+)
(p+)
Oxide
0
y
L’
L
Channel
Pinchoff point (Q
I
=0)
Depletion region
V
B
=0
V
S
=0
V
GS
>V
T0
V
DS
>V
DSAT
CMOS Digital Integrated Circuits 29
MOSFET IV Characteristics
Channel Length Modulation
ΔL increases with an increase in V
DS
. We can use
λ: channel length modulation coefficient
I
D(SAT)
can be rewritten as
• The above form produces a discontinuity of current at V
DS
=V
GS
V
T0
.
We can include the term in I
D(lin)
with little error since λ is typically
less than 0.1. We will usually ignore λ in manual calculations.
( )
V
L
V
L
L
ΔL
L
L
ΔL L
L ΔL L L
DS
DS
ì
ì
+ =
÷
=
÷
=
÷
=
÷
= 1
1
1
1 1
1
1 1 1 1 1
'
1
) 1 ( ) (
2
2
0 ) ( V V V
L
W
C
I
DS T GS
ox
n
SAT D
ì
µ
+ ÷ =
CMOS Digital Integrated Circuits 30
MOSFET IV Characteristics
Substrate Bias Effect
• So far, V
SB
=0 and thus V
T0
used in the equations.
• Clearly not always true – must consider body effect
• Two MOSFETs in series:
V
SB(M1)
= V
DS(M2)
≠ 0. Thus, V
T0
in the M1 equation is replaced by
V
T
= V
T(V
SB
)
as developed in the threshold voltage section.
D
S
G
D
G
M1
M2
V
SB
S
CMOS Digital Integrated Circuits 31
MOSFET IV Characteristics
Substrate Bias Effect (Cont.)
The general form of I
D
can be written as
I
D
= f (V
GS
,V
DS
,V
SB
)
which due to the body effect term is nonlinear and more difficult to
handle in manual calculations
CMOS Digital Integrated Circuits 32
MOSFET IV Characteristics
Summary of Analytical Equations
• The voltage directions and relationships for the three modes of
pMOS are in contrast to those of nMOS.
nMOS
Mode I
D
Voltage Range
Cutoff 0 V
GS
<V
T
Linear (μ
n
C
ox
/2)(W/L)[2(V
GS
V
T
)V
DS
V
DS
2
] V
GS
>V
T
，V
DS
< V
GS
V
T
Saturation (μ
n
C
ox
/2)(W/L)(V
GS
V
T
)
2
(1+λV
DS
) V
GS
> V
T
，V
DS
> V
GS
V
T
pMOS
Cutoff 0 V
GS
>V
T
Linear (μ
n
C
ox
/2)(W/L)[2(V
GS
V
T
)V
DS
V
DS
2
] V
GS
s
V
T
，V
DS
> V
GS
V
T
Saturation (μ
n
C
ox
/2)(W/L)(V
GS
V
T
)
2
(1+λV
DS
) V
GS
s V
T
，V
DS
sV
GS
V
T
G
D
B
S
V
DS
V
SB
V
GS
I
D
G
S
B
D
V
DS
V
SB
V
GS
I
D
CMOS Digital Integrated Circuits 33
More Parameter Extraction
• Need numerical values for parameters in V
T
and I
D
equations
• Parameters can be derived from the measured IV characteristics
for a given MOSFET process.
• To illustrate, seeking Level 1 Spice model parameters V
T0
, μ
n
(κ
n
),
γ, and λ
• To obtain V
T0
, μ
n
(κ
n
), and γ, we plot (I
D
)
1/2
vs V
DS
= V
GS
with V
SB
set to zero and one positive value. MOSFET is in saturation mode
(ignoring channel length modulation):
• Note that this (ideally!) gives a linear relationship that will allow
us to determine κ
n
and V
TO
.
» The slope of the lines is
» The intercept of the V
SB
= 0 line with the V
GS
axis is V
T0
) (
2
0
V V I
T GS
n
D
÷ =
k
2 /
kn
CMOS Digital Integrated Circuits 34
More Parameter Extraction (Cont.)
• Using the intercept of the line for V
SB
nonzero, the body effect
coefficient γ can be found

F
can be obtained from the substrate acceptor density N
A
and
other known physical constants
( )
 
¸
F
SB
F
T SB T
V
V V V
2 2
0
÷ +
÷
=
I
D
V
DS
= V
GS
V
SB
V
T1
V
T0
I
D
V
GS
V
SB
= 0
V
SB
> 0
Slope =
2 /
n
k
CMOS Digital Integrated Circuits 35
More Parameter Extraction (Cont.)
• The IV curve for V
GS
= V
T0
+1 can be used to obtain λ.
I
D
(sat) = κ
n
/2．(V
GS
V
T0
)
2
．(1+ λ V
DS
)= κ
n
/2．(1+ λ V
DS
)
Therefore
λ =2S/κ
n
where S is the slope of this curve in the saturation region.
I
D
V
DS
V
GS
V
DS2
V
DS1
V
DS
I
D1
V
GS
= V
T0
+ 1
I
D2
I
D
CMOS Digital Integrated Circuits 36
More Parameter Extraction (Cont.)
• The Level 1 model is valid only for long devices and is obsolete
for most of today’s technologies for detail simulation.
• Parameter extraction for more advanced models such as Level 3 or
4 is usually performed by an automatic parameter extraction
system that optimizes the combined parameter values for a best
nonlinear fit to the IV curves.
• Due to this optimization, derivation of Level 1 model by simply
deleting selected parameters from a Level 3 model is invalided.
Instead, use the Level 3 model to produce IV curves and linear
curve fitting to extract Level 1 parameters.
CMOS Digital Integrated Circuits 37
Summary
Basic MOSFET operation
Components of the threshold voltage
Threshold voltage and body effect
Drain currents
MOSFET static parameter extraction from IV plots
All of the above for both nMOS and pMOS.