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Roth’s D-Algorithm

Truly Great work
 First algorithm for test generation that is programmable on a

computer  Previous methods before D-Algorithm inception are :
 Truth-table method  Method by complements  Pruning

 Tracing

 Introduced D notation (called D-cubes)
D

 D’

-

“1” in the good circuit, “0” in the faulty “0” in the good circuit, “1” in the faulty (Dbar)

 Defined the calculus and algorithms for ATPG using Dcubes

Singular cover
 Minimal set of input signal assignments needed to represent essential

prime implicants in Karnaugh map  The cube 0X0 (in the table) stands for the two vertices ; 000 & 010  For the circuit shown below,
 0X0 + 001 => 0X001 is one example of singular cover

AND 1 2 3

a 0 X 1

b X 0 1

d 0 0 1

NOR d 4 5 6 1 X 0

e X 1 0

F 0 0 1

D-Cube
 Collapsed truth table entry

 For example, combine rows 3 and 1 of the

AND gate singular cover, and express it in Roth's 5-valued algebra (row 3 is good machine) D1D

 Rows 3 and 2 yield 1 D D ; A third is DDD  Inverting D to D’ in each of these yields

Is there any difference between ‘X’ and ‘D’ “1xxl0x” ; each x can take 0 or 1 on, independent of any other x ;23 combinations But, “D1D0DD” represents only two vertices

the other 3 D-cubes for the AND gate.

 3 of the NOR gate D-cubes are:

D 0 D’ ;

0 D D’ ; D D D’

D-intersection  Defines how different D-cubes can coexist for different gates 0∩0=0∩X=X∩0=0 1∩1=1∩X=X∩1=1 X∩X=X  Rule: If one cube assigns a specific signal value. the other cubes must assign either the same signal or X  For example. 0XX intersect 1XX is the empty cube (incompatible). D-intersection 0 0 1 X D D’ 0 φ 0 ψ ψ 1 X D D’ φ 1 1 ψ ψ 0 1 X D D λ μ ψ ψ D μ ψ ψ D λ .

 If the values are incompatible during propagation or implications. then convert D -> D’ and D’ -> D and continue with the above rule  D-contains: Cube ‘A’ D-contains cube ‘B’ if the set of A cube vertices contains (is a superset of) the B cube vertices. then D ∩ D = D and D’ ∩ D’ = D’  If only ‘λ’ occurs. then the cubes are incompatible  If only ‘μ’ occurs.Intersection Rules  φ and ψ represent incompatible assignments.  If both μ and λ occur. .D. the assignment is called inconsistent and backtracking is necessary.

from AND to OR).g. the PDF for output SA0 is 1 1 D ..a set of inputs to a module that will sensitize a specific fault within the module  These model faults including:  SA0 (represented by D)  SA1 (represented by D)  Bridging faults (short circuits)  Arbitrary change in logic gate function (e.Primitive D cube of failure . X 0 D  Note the “PDF’s are distinct from the propagation D-cubes”  The former models a failure at the gate.  For the AND gate.Primitive D-cubes of failure (PDF)  PDF . SA1 are 0 X D.  The latter models the conditions for fault effect propagation .

Construction of PDF  Make cube set a1 when good machine output is 1 and set a0 when good machine output is 0  Make cube set b1 when failing machine output is 1 and b0 when it is 0  Change a1 outputs to 0 and D-intersect each cube with every b0. change output of cube to D . change output of cube to D  Change a0 outputs to 1 and D-intersect each cube with every b1. If intersection works. If intersection works.

PDF Example .1 Wired-OR bridging fault short-circuiting wires a and b .

2 Cube-set a b c Cube-set a b c a0 a1 b0 b1 0 X 1 0 1 X X 0 1 0 X 1 0 0 1 0 1 1 PDFs for AND changing to OR 0 1 1 0 D D AND Converted to OR .PDF Example .

D.  Model the fault with the appropriate PDF  Select propagation D-cubes to propagate fault-effect to PO(‘s) (D-drive procedure)  Select singular cover cubes to justify internal circuit signals (consistency procedure) “The main limitation of D-algorithm is that it selects cubes and singular covers arbitrarily during test generation” .Algorithm Procedure  Number all circuit lines in increasing level order from PIs to POs.

1 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 0 1 0 0 0 0 A 1 0 B 1 0 1 0 C d 1 0 0 e F 1 0 1 0 0 1 1 1 0 0 0 1 Truth Table Steps in D-Algorithm A D 1 D B 1 D D D 1 D Singular Cover (Used for justifying lines) C Step A 1 1 B 1 C d D e F Type of Cube PDF for AND gate Propagation DD' cube for NOR gate d D D D e F 1 D D D 0 D D-cubes 2 D 0 3 1 1 0 Singular cover of NAND gate D' D' D’ 0 D D D’ D’ D’ .Example .

Flowchart *Picked from chintan Patel slides .

Example .2 .

Step 1 – D-Drive – Set A = 1 Step 4 – Consistency – Set g = 1 Step 2 – D-Drive – Set f = 0 Step 5 – Consistency – f = 0 Already set Step 3 – D-Drive – Set k = 1 Step 6 – Consistency – Set c = 0. Set e = 0 .

Primitive D-cube of Failure Fault s sa1 .Example – 3 .

Propagation D-cube for v .

Forward & Backward Implications .

since only one fault effect propagated to a PO is sufficient for a test .Limitations of D-Algorithm  Insists on propagating the D-frontier strictly in the order of increasing      circuit signal numbers listed in the D-frontier Insists on justifying unjustified internal signals in the order of decreasing signal numbers in the active test cube These methods are often counterproductive. This is unnecessary. rather than to 0 Better heuristic is needed for selecting the value of the assignment Insists on propagating all D-frontier fault effects to POs. whenever possible. better heuristics are needed for deciding which signals are best to manipulate at each stage of the computation Algorithm selects a singular cover to set an input to 1 first.

PODEM Path oriented Decision making .

IBM introduced error correction and translation (ECAT) to their DRAM to increase reliability  Error correction and translation (ECAT)  A logic circuit is characterized as being ECAT type if portions of it are constituted by XOR (EXCLUSIVE-OR) gates with reconvergent fan-out  DALG is extremely inefficient ECAT type functions .Into the history books…  TEST generation for combinational circuits has traditionally been considered a solved problem  In late '70s.

ECAT Problem  D-ALG fails on attempts to generate tests for these circuits because the search is not directed  D-ALG will eventually determine that n = q is not realizable by this circuit .

better heuristics are needed for deciding which signals are best to manipulate at each stage of the computation  “Algorithm selects a singular cover to set an input to 1 first. whenever possible. since only one fault effect propagated to a PO is sufficient for a test . This is unnecessary.Other Limitations of D-Algorithm  Insists on propagating the D-frontier strictly in the order of increasing circuit signal numbers listed in the D-frontier  Insists on justifying unjustified internal signals in the order of decreasing signal numbers in the active test cube  These methods are often counterproductive. rather than to 0” – Most important wrt ECAT circuits  Better heuristic is needed for selecting the value of the assignment  Insists on propagating all D-frontier fault effects to POs.

PODEM introduced objectives and realized that choosing PIs to set was important in efficiently realizing objectives. D-ALG tended to continue intersecting D-cubes even when the Dfrontier disappeared. Backtracing was used to obtain a PI assignment given an initial objective. not around all circuit      signals . PODEM introduced a subroutine to test if D-frontier still existed. . Reduces the size of the tree from 2n to 2num_PIs.PODEM – Several new Concepts  Expands the binary decision tree around the PI’s. PODEM considered the length of the path between the objective and the POs and used controllability measures to guide the ATPG algorithm.

exit: untestable fault Set untried combination of values on assigned PIs using objectives and backtrace.PODEM High-Level Flow  Assign binary value to      unassigned PI Determine implications of all PI’s Test Generated? If so. Then. go to Step 1 Is there untried combination of values on assigned PIs? If not. go to Step 2 . done. Test possible with more assigned PIs? If maybe.

PODEM backtraced through the hardest-to-control input first. .  If only one logic gate input needed to be set to achieve the objective.Assumptions Made  Set’s the gate objective of obtaining  a ‘1’ on that gate output if it was an AND or an OR gate  a ‘0’ if it was a NAND or a NOR gate to propagate the D forward  During Backtracing. That way. PODEM backtraced through the easiest-to-control input.  If all logic gate inputs had to be set to achieve the objective. if controlling that input failed. it wasted no time trying easier-tocontrol inputs.

Example PODEM’s objectives/ Implication stack .

.

Select path s – Y for fault propagation .

Initial objective: Set r to 1 to excite fault .

Backtrace from r .

Set A = 0 in implication stack .

Forward implications: d = 0. X = 1 .

Initial objective: set r to 1 .

Backtrace from r again .

Set B to 1. Implications in stack: A = 0. B = 1 .

u = D. s = D. Y = 1. v = D.Forward implications: k = 1. q = 1. r = 1. m = 0. Z = 1 .

X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared) .

Set B = 0 (alternate assignment) .

X = 1. r = 0. Fault not sensitized . m = 1. Z = 1. s = 1.Backtrack Forward implications: d = 0. q = 0. Y = 1. v = 0.

Set A = 1 (alternate assignment) .

Backtrace from r again .

Implications in stack: A = 1.Set B = 0. B = 0 .

Backtrack . r = 0. m = 1.Forward implications: d = 0. X = 1. Conflict: fault not sensitized.

Set B = 1 (alternate assignment) .

Forward implications: d = 1. m = 1. Y = D Fault Tested . q = 0. r = 1. X = 0. s = D. v = D.

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History of Algorithm Speedups .