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Vineet Sahula
Finite State Machine Model
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p=2l
Input variables, xi ●Input vector I ={x ,x , ...x } j 1 2 l ●Input alphabet I={I ,I , ...I } 1 2 p
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Finite State Machine Model
q=2m ●Output variables, z i ●Input vector O ={z ,z , ...z } j 1 2 m ●Input alphabet O={O ,O , ...O } 1 2 q
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Finite State Machine Model
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n=2k
State variables, yi ●Input vector S ={y ,y , ...y } j 1 2 k ●Input alphabet S={S ,S , ...S } 1 2 n
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Machine Specification  Set theoritic
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M=(I,O,S,)
: I×S → S
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: I×S → O
: S → O
Mealy machine
Moore machine
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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State Machine model Tabular
x S S1 S2 x X1 S2 S3 X2 S1 S2 S S1 S2 S3 X1 Y1 Y3 Y2 X2 Y2 Y1 Y3
S3
S2 X S
S1 S2
S1
X1 S2 Y1 S3 S2 S1
state
outputs
X2
Y2
Y3
S2 Y2 S1
Y1
Y3
6
S3
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
Mealy Machine Model Graph
X2/Y2 X S S1 S2 S3 S2 X1 S1 X2 X1/Y1 S1 X2/Y1
Y1
S3 Y3 S2 Y2 S1 S2
Y2
X1/Y2 Y1 Y3 S3 X2/Y3
S2
X1/Y3
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Moore Machine Model Graph
x S S1 S2 S3 X2
X1
S2 S3 S2
X2
S1 S2 S1
Y
Y2 Y1 Y3 S2/Y1 X2 X1 S1/Y2 X1
X1
S3/Y3
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Capabilities & Limitations of FSMs
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What FSM can do?
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Transit through sequence of states For input of a length of more than n vectors (each vector is ltuple, and is one of p vectors)
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Machine will arrive in one of n states for more than n inputs
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Limitations
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The FSM can transit to one of nstates The maximal length of nonrepeating sequence is ≤n
Computer Arith. & Microarchitecture: FSM1 9
V. Sahula, 201213
kdistinguishablility
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Two states Si, Sj are distinguishable
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If there exists at least one finite input sequence, which when applied to FSM M, causes different output sequence, depending on whether Si or Sj is INITIAL state The sequence which distinguishes these states is called a distinguishing sequence of pair (Si,Sj)
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(Si,Sj) is called kdistinguishable, if a distinguishable seq. Of length k exists
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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kequivalence
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Two states Si, Sj are kequivalent
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If they are NOT kdistinguishable
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If they are kequivalent
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They are also requivalent, r < k If they are kequivalent for all k
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They are equivalent
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If states Si, Sj are equivalent
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All their corresponding Xsuccessors are also equivalent
Computer Arith. & Microarchitecture: FSM1 11
V. Sahula, 201213
State Minimization
Goal : identify and remove redundant states
(states which can not be observed from the FSM I/O behavior)
Why : 1. Reduce number of latches
assign minimumlength encoding – only as the logarithm of the number of states 2. Increase the number of unassigned states codes – heuristic to improve stateassignment and logicoptimization
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V. Sahula, 201213 Computer Arith. & Microarchitecture: FSM1 12
Algorithmic State Minimization
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Goal – identify and combine states that have equivalent behavior Equivalent States:
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Same output For all input combinations, states transition to same or equivalent states
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Algorithm Sketch
1. Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state transitions 4. Repeat (3) until no further partitioning is required
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states left in the same set are equivalent
Polynomial time procedure
Computer Arith. & Microarchitecture: FSM1
V. Sahula, 201213
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State Minimization Definition
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Completelyspecified state machine – two states are equivalent if outputs are identical for all input combinations Next states are equivalent for all input combinations – equivalence of states is an equivalence relation which partitions the states into disjoint equivalence classes Incompletely specified state machines
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Classical State Minimization
1. Partition states based on input output values asserted in the state 2. Define the partitions so that all states in a partition transition into the same nextstate partition (under corresponding inputs)
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Classical State Minimization Algorithm
Only for Completely specified Machines
1. Partition the set of internal states based on input output values asserted in the state 2. Define the partitions so that all states in a partition transition into the same nextstate partition (under corresponding inputs)
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Machine M1
PS
NS x=0 x=1
D,1
D,0 B,1 B,0 F,1 C,0
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● ● ● ●
(ABCDEF)
(ACE)(BDF)
A
B C D E F
E,0
F,0 E,0 F,0 C,0 B,0
(ACE)(BD)(F)
(AC)(E)(BD)(F) (AC)(E)(BD)(F)
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Example (FSM in PSNS state format)
Ex : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0
G has other inputoutput response than other states
D has other inputoutput response than other states because it goes to G which is known to be nonequivalent stategoes to red and blue groups
(A,B,C,D,E,F,H) (G) (A,B,C,E,F,H)(G)(D) (A,C,E)(G)(D)(B,F)(H)
B and F go to D
Please check this using triangular table
States A, C and E can be combined to one state States B and F can be combined to one state
You can also marke each new group with a new symbol and check transitions to thus marked groups
Computer Arith. & Microarchitecture: FSM1 18
V. Sahula, 201213
Example of partition based minimization
Ex : 0A 1A 0B 1B 0C 1C 0D 1D 0E 1E 0F 1F 0G 1G 0H 1H B0 C0 D0 E0 F0 A0 H0 G0 B0 C0 D0 E0 F1 A0 H0 A0
(A,B,C,D,E,F,H)(G) (A,B,C,E,F,H)(G)(D) (A,C,E,H)(G)(D)(B,F) (A,C,E)(G)(D)(B,F)(H)
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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State Minimization Example
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Sequence Detector for 010 or 110
Input Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0
0/0 0/0 S3 0/0 S1 1/0 S4 0/1
S0
1/0 0/0 S5 0/0 S2 1/0 S6 0/1 1/0
1/0
1/0
1/0
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Method of Successive Partitions
Input Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0
( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 )
S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6
( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )
( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Minimized FSM
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State minimized sequence detector for 010 or 110
Input Sequence Reset 0+1 X0 X1 Present State S0 S1' S3' S4' Next State X=0 X=1 S1' S3' S0 S0 S1' S4' S0 S0 Output X=0 X=1 0 0 0 1 0 0 0 0
S0 X/0 0/0 S3’ X/0 0/1 S1’ 1/0 S4’ 1/0
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Asynchronous sr flipflop
r
U2
Q
NOR2
U3
s NOR2
notQ
U5
s
U4
S
Q ~Q
U2
Q
R
NAND2
SR_FF
NAND2
r
U1
U3
notQ
NAND2
V. Sahula, 201213
NAND2
Computer Arith. & Microarchitecture: FSM1 23
asynchronous flipflop sr
Q(t)Q(t+1) s 0 0 1 1 r 0 1 0 1 Q(t+1) 0 Q(t) 0 0 1 1 0 1 0
s 0 1 0
r 0 1
1

1

0
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Negated sr FF
not_s
U2
Q
U5
~S Q
NAND2
U3
not_r NAND2 notQ
~R ~Q
SR_FF
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Negated sr FF
This version has negated inputs s r This FF realizes the function:
s
0 0 1 1
r
0 1 0 1
Q(t+1)
1 0 Q(t)
Q(t)Q(t+1)
0 0 1 1 0 1 0 1
s
0 1 0
r
0 1 0 
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Classical State Minimization Algorithm
InCompletely specified Machines
1. State transitions are NOT defined Pressure that machine starts only in KNOWN state, OR
Presume unspecified STATE to be labeled, may be T
2. Outputs are NOT defined
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Covering State
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States Si, of M1 is said to cover or contain Sj of machine M2 iff every input sequence applicable to Sj is also applicable to Si
And its application to M1 and M2 when they are initially in Si, Sj respectively, results in identical output sequences whenever the outputs of M2 are specified
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Covering Machine
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Machine M1 is said to cover M2 iff for every state Sj in M2 , there is corresponding Si in M1 Si covers Sj
If state Si, of M covers another state Sj of the same machine, then only Si must be retained, while Sj maybe deleted
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Compatible states
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Two states Si, Sj of machine M are compatible iff, for every input sequence applicable to both Si, Sj , the same output sequence will be produced whenever both outputs are specified and regardless of whether Si, or Sj , is initial state Hence, Si, Sj are compatible iff their outputs are NOT conflicting and their Iisuccessors for every Ii for which both are specified, are either same OR also compatible
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V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Compatibility
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Three or more states are compatible, iff they are pairwise compatible
A set of compatible states (Si, Sj,Sk.....) is called compatible A compatible Ci is said to cover (or larger than) another compatible Cj if every state in Cj is also contained in Ci A compatible is maximal if it is not covered by any other compatible
Computer Arith. & Microarchitecture: FSM1 31
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V. Sahula, 201213
Closed set of Compatibles
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A set of compatibles is said to be closed if for every compatible contained in the set, all its implied compatibles are also contained
A closed set of compatibles which contain all the states of M is called closed covering
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Teh set of all possible maximal compatibles is a closed covering
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It is also an upper bound on # of states in reduced machine
V. Sahula, 201213
Computer Arith. & Microarchitecture: FSM1
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Minimization Procedure
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Form merger TABLE or merger GRAPH
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Form a GROUP of all possible pairwise compatible states
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Opton1
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Find all possible CLIQUES in graph Find minimal set of cliques (clique cover) so that all vertices are covered. Here, each vertex represents a pair of compatible state
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Option2
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From table, proceed from right to left, columnwise and keep finding maximal compatibles
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From set of maximal compatibles find minimal closed cover
Computer Using compatibilityArith. & Microarchitecture: FSM1 graph 33
V. Sahula, 201213 ●
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