The 8051 Microcontroller

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-1

8051 Basic Component
4K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface
CPU I/O Port RAM ROM Serial Timer COM Port

A single chip Microcontroller

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-2

Block Diagram
External Interrupts

Interrupt Control

4k ROM

128 bytes RAM

Timer 1 Timer 2

CPU

OSC

Bus Control

4 I/O Ports

Serial

P0 P2 P1 Addr/Data
hsabaghianb @ kashanu.ac.ir

P3

TXD RXD
Microprocessors 1-3

ac. 3 internal.WR  Code memory is selectable by EA (internal or external)  We may have External memory as data and code hsabaghianb @ kashanu. Reset)  64K external code (program) memory(only read)PSEN  64K external data memory(can be read and write) by RD.ir Microprocessors 1-4 .Other 8051 featurs  only 1 On chip oscillator (external crystal)  6 interrupt sources (2 external .

8051 Internal Block Diagram

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-5

8051 Schematic Pin out

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-6

8051 Foot Print

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5
(WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8051
(8031) (8751) (8951)

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)
Microprocessors 1-7

hsabaghianb @ kashanu.ac.ir

   Each port can be used as input or output (bi-direction) hsabaghianb @ kashanu.General Purpose I/O Port 2 (pins 21-28):P2(P2.0~P1.7)  General Purpose I/O  if not using any of the internal peripherals (timers) or external interrupts.ac.0~P2.General Purpose I/O  Or high byte of the address bus for external memory design Port 3 (pins 10-17):P3(P3.7)  8-bit R/W .General Purpose I/O  Or acts as a multiplexed low byte address and data bus for external memory design  Port 1 (pins 1-8) :P1(P1.0~P3.7)  Only 8-bit R/W .0~P0.7)  8-bit R/W .P3)  Port 0 (pins 32-39):P0(P0.IMPORTANT PINS (IO Ports)  One of the most useful features of the 8051 is that it contains four I/O ports (P0 .ir Microprocessors 1-8 .

ir Microprocessors 1-9 .ac.Port 3 Alternate Functions hsabaghianb @ kashanu.

ac.ir Microprocessors 1-10 .8051 Port 3 Bit Latches and I/O Buffers hsabaghianb @ kashanu.

ac.ir Microprocessors 1-11 .X pin M1 TB1 Read pin hsabaghianb @ kashanu.X Clk Q P1.Hardware Structure of I/O Pin Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch D Q P1.

ac.ir Microprocessors 1-12 .Hardware Structure of I/O Pin  Each pin of I/O ports Internally connected to CPU bus A D latch store the value of this pin Write to latch=1:write data into the D latch 2 Tri-state buffer: TB1: controlled by “Read pin” Read pin=1:really read the data present at the pin TB2: controlled by “Read latch” Read latch=1:read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close hsabaghianb @ kashanu.

ac. output pin is 1.X Clk Q P1.Writing “1” to Output Pin P1.X pin output 1 TB1 Read pin hsabaghianb @ kashanu.X Read latch TB2 Vcc Load(L1) 2.ir Microprocessors 1-13 . write a 1 to the pin Internal CPU bus Write to latch D Q Vcc 1 0 M1 P1.

X Read latch TB2 Vcc Load(L1) 2.X Clk Q P1.ac.ir Microprocessors 1-14 .Writing “0” to Output Pin P1. write a 0 to the pin Internal CPU bus Write to latch D Q ground 0 1 M1 P1. output pin is 1.X pin output 0 TB1 Read pin hsabaghianb @ kashanu.

TXD: UART pins for serial I/O on Port 3  XTAL1 & XTAL2: Crystal inputs for internal oscillator. hsabaghianb @ kashanu.ac.IMPORTANT PINS PSEN (out):  ALE (out):  EA (in): Program Store Enable. active low to access external program memory locations 0 to 4K  RXD.ir Microprocessors 1-15 . Address Latch Enable. to latch address outputs at Port0 and Port2 External Access Enable. the read signal for external program memory (active low).

hsabaghianb @ kashanu.  GND(pin 20):ground  XTAL1 and XTAL2(pins 19.18): These 2 pins provide external clock. The voltage source is +5V.Pins of 8051  Vcc(pin 40): Vcc provides supply voltage to the chip.ir Microprocessors 1-16 . Way 1:using a quartz crystal oscillator Way 2:using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.ac.

ir Microprocessors 1-17 . The high pulse must be high at least 2 machine cycles. Upon applying a high pulse to RST.ac. the microcontroller will reset and all values in registers will be lost.  power-on reset. Reset values of some 8051 registers  power-on reset circuit hsabaghianb @ kashanu.Pins of 8051  RST(pin 9):reset  input pin and active high(normally low).

 For 8051. /EA pin is connected to Vcc.  /PSEN(pin 29):program store enable  This is an output pin and is connected to the OE pin of the ROM.  “/” means active low.ir Microprocessors 1-18 .  /PSEN & ALE are used for external ROM. hsabaghianb @ kashanu.ac.  The /EA pin is connected to GND to indicate the code is stored externally.Pins of 8051  /EA(pin 31):external access  There is no on-chip ROM in 8031 and 8032 .

ir Microprocessors 1-19 . hsabaghianb @ kashanu.Pins of 8051  ALE(pin 30):address latch enable It is an output pin and is active high.ac. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.

ac.ir Microprocessors 1-20 .Address Multiplexing for External Memory Figure 2-7 Multiplexing the address (low-byte) and data bus hsabaghianb @ kashanu.

ac.ir Microprocessors 1-21 .Address Multiplexing for External Memory Figure 2-8 Accessing external code memory hsabaghianb @ kashanu.

ir Microprocessors 1-22 .hsabaghianb @ kashanu.ac.

ac.ir Microprocessors 1-23 .hsabaghianb @ kashanu.

ac.On-Chip Memory Internal RAM hsabaghianb @ kashanu.ir Microprocessors 1-24 .

2.Registers 1F Bank 3 18 17 Four Register Banks Each bank has R0-R7 Selectable by psw.ir Microprocessors 1-25 .ac.3 Bank 2 10 0F Bank 1 08 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 Bank 0 hsabaghianb @ kashanu.

23h.2 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 0F 07 06 05 04 03 02 01 1A 10 08 00 hsabaghianb @ kashanu.Bit Addressable Memory 2F 2E 2D 7F 78 20h – 2Fh (16 locations X 8-bits = 128 bits) Bit addressing: mov C. 1Ah or mov C.ir Microprocessors 1-26 .ac.

Special Function Registers DATA registers CONTROL registers Timers Serial ports Interrupt system Analog to Digital converter Digital to Analog converter Etc.ac.ir Microprocessors 1-27 . Addresses 80h – FFh Direct Addressing used to access SPRs hsabaghianb @ kashanu.

ir Microprocessors 1-28 .ac.Bit Addressable RAM Figure 2-6 Summary of the 8051 on-chip data memory (RAM) hsabaghianb @ kashanu.

ir Microprocessors 1-29 .ac.RS0] bit  Permits fast “context switching” in interrupt service routines (ISR).Register Banks  Active bank selected by PSW [RS1. hsabaghianb @ kashanu.

ir Microprocessors 1-30 .ac.hsabaghianb @ kashanu.

8051 CPU Registers A (Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR (Data Pointer) Used in assembler instructions hsabaghianb @ kashanu.ac.ir Microprocessors 1-31 .

ac.ir Microprocessors 1-32 .Registers A B R0 R1 R2 R3 R4 R5 R6 R7 PC PC DPTR DPH DPL Some 8051 16-bit Register Some 8-bit Registers of the 8051 hsabaghianb @ kashanu.

ir Microprocessors 1-33 .ac.The 8051 Assembly Language hsabaghianb @ kashanu.

ac.Overview Data transfer instructions Addressing modes Data processing (arithmetic and logic) Program flow instructions hsabaghianb @ kashanu.ir Microprocessors 1-34 .

move byte . byte XCHD a.ir Microprocessors 1-35 .exchange accumulator and byte . source Stack instructions PUSH byte POP byte dest  source pointer.move from stack .exchange low nibbles of .decrement Exchange instructions XCH a.Data Transfer Instructions MOV dest. byte .ac. on stack to byte.increment stack . stack pointer .accumulator and byte hsabaghianb @ kashanu.

#0 mov R4.R4 = 00010001 .B = 00001011 mov DPTR. #11h mov B.A = 00000000 .put 11 decimal in b register .ac. #11 .#7521h .ir Microprocessors 1-36 .Addressing Modes Immediate Mode – specify data by its value mov A.put 11hex in the R4 register .DPTR = 0111010100100001 hsabaghianb @ kashanu.put 7521 hex in DPTR .put 0 in the accumulator .

#75 COUNT EGU 30 ~ ~ mov R4.ir Microprocessors 1-37 .Addressing Modes Immediate Mode – continue MOV DPTR.ac.#MYDATA ~ ~ 0RG 200H MYDATA:DB “IRAN” hsabaghianb @ kashanu. #COUNT MOV DPTR.#7521h MOV DPL.#21H MOV DPH.

R7 is incorrect hsabaghianb @ kashanu.R4 A.ir Microprocessors 1-38 .#25F5H R5.ac.DPH Note that MOV R4.R7 A.R7 DPTR.DPL R.Addressing Modes Register Addressing – either source or destination is one of CPU register MOV MOV ADD ADD MOV MOV MOV R0.A A.

Direct Mode – specify data by its 8-bit address
Usually for 30h-7Fh of RAM
; ; ; ; Mov Mov Mov Mov a, 70h R0,40h 56h,a 0D0h,a copy contents of RAM at 70h to a copy contents of RAM at 70h to a put contents of a at 56h to a put contents of a into PSW

Addressing Modes

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-39

Addressing Modes
Direct Mode – play with R0-R7 by direct address
MOV A,4 MOV A,7 MOV 7,2

  

MOV A,R4 MOV A,R7 MOV R7,R6 ;Put 5 in R2 ;Put content of RAM at 5 in R2

MOV R2,#5 MOV R2,5

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-40

Addressing Modes
Register Indirect – the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address:
mov psw, #0 mov r0, #0x3C mov @r0, #3 ; use register bank 0

; memory at 3C gets #3 ; M[3C]  3
; dptr  9000h ; a  M[9000]

Uses DPTR register for 16-bit addresses:
mov dptr, #0x9000 movx a, @dptr

Note that 9000 is an address in external memory
hsabaghianb @ kashanu.ac.ir Microprocessors 1-41

ir Microprocessors 1-42 .ac.a  M[4005] hsabaghianb @ kashanu. #4000h mov a. @a + dptr .Addressing Modes Register Indexed Mode – source or destination address is the sum of the base address and the accumulator(Index) Base address can be DPTR or PC mov dptr. #5 movc a.

ac.a  M[1008] PC  Table Lookup  MOVC only can read internal code memory Microprocessors 1-43 hsabaghianb @ kashanu. #5 movc a. @a + PC Nop .ir .Addressing Modes Register Indexed Mode continue  Base address can be DPTR or PC ORG 1000h 1000 1002 1003 mov a.

r1 mov acc.r1 hsabaghianb @ kashanu.ac.00h  Also this 3 instruction 070B E9 070C 89E0 070E 89E0 mov a.Acc Register  A register can be accessed by direct and register mode  This 3 instruction has same function with different code 0703 E500 0705 8500E0 0708 8500E0 mov a.r1 mov 0e0h.ir Microprocessors 1-44 .00h mov acc.00h mov 0e0h.

tmod.r4  P0~P3 – are direct address 0704 F580 0706 F580 0708 859080 mov p0.00h mov b.00h mov 0f0h.a mov p0. psw.ir Microprocessors 1-45 .) hsabaghianb @ kashanu.….a mov 80h.ac.SFRs Address  B – always direct mode .except in MUL & DIV 0703 8500F0 0706 8500F0 0709 8CF0 070B 8CF0 mov b.p1  Also other SFRs (pcon.r4 mov 0f0h.

TMOD.SFRs Address All SFRs such as (ACC.ac. PSW. B. PCON. …) are accessible by name and direct address But both of them Must be coded as direct address hsabaghianb @ kashanu.ir Microprocessors 1-46 . P0~P3.

ir Microprocessors 1-47 . . not a hsabaghianb @ kashanu. Therefore.Stack  Stack-oriented data transfer  Only one operand (direct addressing)  SP is other operand – register indirect . must use acc. . to push/pop the accumulator.ac.implied  Direct addressing mode must be used in Push and Pop mov sp. #0x40 push 0x55 . M[SP]  M[55] M[41]  M[55] b  M[55] pop b Note: can only specify RAM or SFRs (direct mode) to push or pop. . Initialize SP SP  SP+1.

is .Stack (push.ac.is .b Microprocessors 1-48 hsabaghianb @ kashanu.is .is .acc .is invalid invalid invalid correct correct correct .ir .is .pop)  Therefore Push Push Push push Push Push Push Push Push Pop Pop Push Pop a r0 r1 acc psw b 13h 0 1 7 8 0e0h 0f0h .

. . R0 .Exchange Instructions two way data transfer XCH a.ac. @R0 XCHD a.. R0 XCH a.4] R0[3.4] a[3.ir Microprocessors 1-49 .0] R0[7..0] Only 4 bits exchanged hsabaghianb @ kashanu.. a  M[30] a  R0 a  M[R0] exchange “digit” a[7. 30h XCH a. ..

7 hsabaghianb @ kashanu.ac.  Carry flag (C) (bit 7 in the PSW) is used as a singlebit accumulator  RAM bits in addresses 20-2F are bit addressable mov C.ir Microprocessors 1-50 . 67h mov C.Bit-Oriented Data Transfer  transfers between individual bits. P0. 2ch.0 mov C.

(80. hsabaghianb @ kashanu.ac.ir Microprocessors 1-51 .SFRs that are Bit Addressable SFRs with addresses ending in 0 or 8 are bit-addressable. 90. etc) Notice that all 4 parallel I/O ports are bit addressable. 98. 88.

Data Processing Instructions Arithmetic Instructions Logic Instructions hsabaghianb @ kashanu.ac.ir Microprocessors 1-52 .

ir Microprocessors 1-53 .Arithmetic Instructions Add Subtract Increment Decrement Multiply Divide Decimal adjust hsabaghianb @ kashanu.ac.

put result in A add with carry SUBB A.Arithmetic Instructions Mnemonic ADD A.ir . byte Description add A to byte. byte ADDC A.ac. byte INC A INC byte INC DPTR subtract with borrow increment A increment byte in memory increment data pointer DEC A DEC byte MUL AB DIV AB decrement accumulator decrement byte multiply accumulator by b register divide accumulator by b register DA A decimal adjust the accumulator Microprocessors 1-54 hsabaghianb @ kashanu.

ac. or visa versa. a  a + byte addc a. byte . hsabaghianb @ kashanu. byte .ir Microprocessors 1-55 . a  a + byte + C These instructions affect 3 bits in PSW: OV = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 C = 1 if there is a carry out of bit 7. but not from bit 6.ADD Instructions add a.

ir Microprocessors 1-56 .Instructions that Affect PSW bits hsabaghianb @ kashanu.ac.

ac. OV flags after the second instruction is executed? C = 1 AC = 1 OV = 0 hsabaghianb @ kashanu. #D3h 0011 1111 1101 0011 0001 0010  What is the value of the C.ir Microprocessors 1-57 .ADD Examples mov a. #3Fh add a. AC.

ac.Signed Addition and Overflow 2’s 0000 … 0111 1000 … 1111 complement: 0000 00 0 1111 0000 1111 7F 127 80 -128 FF -1 0011 1111 (positive) 1101 0011 (negative) 0001 0010 (never overflows) 0111 1111 (positive 127) 0111 0011 (positive 115) 1111 0010 (overflow cannot represent 242 in 8 bits 2’s complement) 1000 1111 1101 0011 0110 0010 (negative 113) (negative 45) (overflow) hsabaghianb @ kashanu.ir Microprocessors 1-58 .

X add a. Computes Z = X + Y . Adds values at locations 78h and 79h and puts them in 7Ah .----------------------------------------------------------------org 00h ljmp Main .-----------------------------------------------------------------X equ 78h Y equ 79h Z equ 7Ah .Addition Example . a end hsabaghianb @ kashanu.ir Microprocessors 1-59 . Y mov Z.----------------------------------------------------------------org 100h Main: mov a.ac.

a end hsabaghianb @ kashanu. Y+1 mov Z+1.Y.----------------------------------------------------------------org 00h ljmp Main .Z are 16 bit) . X add a. X+1 adc a. Y mov Z.ac. a mov a.----------------------------------------------------------------org 100h Main: mov a.The 16-bit ADD example . Computes Z = X + Y (X.ir Microprocessors 1-60 .-----------------------------------------------------------------X equ 78h Y equ 7Ah Z equ 7Ch .

Subtract SUBB A.ir .A  A – 4F Microprocessors 1-61 . Therefore. #0x4F . Example: Clr c SUBB A.ac. it is necessary to clear the C flag. byte subtract with borrow Example: SUBB A. if a subtraction without borrow is desired.A  A – 4F – C Notice that There is no subtraction WITHOUT borrow. #0x4F hsabaghianb @ kashanu.

not decrement.  Notice we can only INCREMENT the data pointer.ac. hsabaghianb @ kashanu.Increment and Decrement INC A INC byte increment A increment byte in memory INC DPTR DEC A DEC byte increment data pointer decrement accumulator decrement byte  The increment and decrement instructions do NOT affect the C flag.ir Microprocessors 1-62 .

add C to most significant byte hsabaghianb @ kashanu. #1 mov r2.Example: Increment 16-bit Word Assume 16-bit word in R3:R2 mov a. #0 mov r3. r2 add a.ac.ir Microprocessors 1-63 . a mov a. r3 addc a. a . use add rather than increment to affect C .

the size of the maximum product is 16-bits FF x FF = FE01 (255 x 255 = 65025) MUL AB .ac. BA  A * B Note : B gets the High byte A gets the Low byte hsabaghianb @ kashanu.ir Microprocessors 1-64 .Multiply When multiplying two 8-bit numbers.

Division Integer Division DIV AB .ac. divide A by B A  Quotient(A/B) B  Remainder(A/B) OV .ir Microprocessors 1-65 . C – set to zero hsabaghianb @ kashanu.used to indicate a divide by zero condition.

a  a + 6 = 52 hsabaghianb @ kashanu. #29h add a. Adds “6” to either high or low nibble after an addition to create a valid BCD number.Decimal Adjust DA a .ir Microprocessors 1-66 . #23h mov b. Example: mov a. a  23h + 29h = 4Ch (wanted 52) . decimal adjust a Used to facilitate BCD addition.ac. b DA a .

Logic Instructions  Bitwise logic operations  (AND. NOT)  Clear  Rotate  Swap Logic instructions do NOT affect the flags in PSW hsabaghianb @ kashanu.ir Microprocessors 1-67 . OR. XOR.ac.

Bitwise Logic ANL  AND ORL  OR XRL  XOR CPL  Complement Examples: 00001111 ANL 10101100 00001100 00001111 ORL 10101100 10101111 00001111 XRL 10101100 10100011 CPL 10101100 01010011 Microprocessors 1-68 hsabaghianb @ kashanu.ac.ir .

indirect.ir Microprocessors 1-69 . #constant CPL – Complement a ex: cpl a hsabaghianb @ kashanu. reg. immediate byte.Address Modes with Logic ANL – AND ORL – OR XRL – eXclusive oR a.ac. a direct byte. byte direct. reg.

Uses of Logic Instructions  Force individual bits low. orl PSW. #0x18 .PSW AND 11100111  Force individual bits high.P1 XRL 01000000 hsabaghianb @ kashanu. #0xE7 . anl PSW.ac. without affecting other bits. #0x40 .ir Microprocessors 1-70 .PSW OR 00011000  Complement individual bits xrl P1.

ac.Other Logic Instructions CLR RL RLC RR RRC SWAP – – – – – clear rotate left rotate left through Carry rotate right rotate right through Carry swap accumulator nibbles hsabaghianb @ kashanu.ir Microprocessors 1-71 .

ir Microprocessors 1-72 .CLR ( Set all bits to 0) CLR CLR CLR CLR A byte Ri @Ri (direct mode) (register mode) (register indirect mode) hsabaghianb @ kashanu.ac.

#0xF0 RR a hsabaghianb @ kashanu. a 11110000 .Rotate Rotate instructions operate only on a RL a Mov a.#0xF0 RR a . a 11100001 RR a Mov a. a 11110000 .ir .ac. a 01111000 Microprocessors 1-73 .

c  1 . a  01111001. a  A9 .Rotate through Carry RRC a mov a. C0 . #14h rrc a C . a  01011110. #0A9h add a.ir Microprocessors 1-74 . #3ch setb c rlc a . a  3ch(00111100) . C1 C RLC a mov a. C1 hsabaghianb @ kashanu. a  BD (10111101).ac.

ac.ir Microprocessors 1-75 . . . . A C A A A 00000011 0 00000110 00001100 00000110 (3) (6) (12) (6) hsabaghianb @ kashanu. shift right is divide by 2 mov clr rlc rlc rrc a.Rotate and Multiplication/Division Note that a shift left is the same as multiplying by 2. . #3 C a a a .

Swap SWAP a mov a. a  27h . a  27h hsabaghianb @ kashanu.ir Microprocessors 1-76 . #72h swap a .ac.

Bit Logic Operations  Some logic operations can be used with single bit operands ANL C.ac. hsabaghianb @ kashanu. bit CLR C CLR bit CPL C CPL bit SETB C SETB bit  “bit” can be any of the bit-addressable RAM locations or SFRs. bit ORL C.ir Microprocessors 1-77 .

hsabaghianb @ kashanu.ac.Shift/Mutliply Example Program segment to multiply by 2 and add 1.ir Microprocessors 1-78 .

ir Microprocessors 1-79 .Program Flow Control Unconditional jumps (“go to”) Conditional jumps Call and return hsabaghianb @ kashanu.ac.

so jump can be up to 127 locations forward. relative address is 8-bit 2’s complement number.ac.ir Microprocessors 1-80 . AJMP <address 11> . LJMP <address 16> .Unconditional Jumps SJMP <rel addr> Short jump. Long jump . or 128 locations back. JMP @A + DPTR indexed jump Absolute jump to anywhere within 2K block of program memory . Long hsabaghianb @ kashanu.

loop: mov a. if a=0. P1 jz loop mov b.ac. Otherwise. . else goto next instruction  There is no zero flag (z)  Content of A checked for zero on time hsabaghianb @ kashanu. program execution continues with the next instruction. a . goto loop.Conditional Jump  These instructions cause a jump to occur only if a condition is true.ir Microprocessors 1-81 .

bit &clear CJNE A.Conditional jumps Mnemonic JZ <rel addr> JNZ <rel addr> JC <rel addr> JNC <rel addr> JB <bit>.ac. <rel addr> Description Jump if a = 0 Jump if a != 0 Jump if C = 1 Jump if C != 1 Jump if bit = 1 Jump if bit != 1 Jump if bit =1.ir Microprocessors 1-82 . <rel addr> Compare A and memory. jump if not equal hsabaghianb @ kashanu. direct. <rel addr> JNB <bit>.<rel addr> JBC <bir>.

#data <rel addr> Compare Rn and memory. <rel addr> hsabaghianb @ kashanu. <rel addr> Decrement Rn and then jump if not zero Decrement memory and then jump if not zero DJNZ direct. jump if not equal CJNE @Rn.ac. jump if not equal Compare Rn and data. #data <rel addr> Description Compare A and data.More Conditional Jumps Mnemonic CJNE A.ir Microprocessors 1-83 . #data <rel addr> CJNE Rn. jump if not equal DJNZ Rn.

but Call pushes PC on stack before branching acall <address ll> . stack  PC . PC  address 16 bit lcall <address 16> hsabaghianb @ kashanu.ac. stack  PC .Call and Return Call is similar to a jump. PC  address 11 bit .ir Microprocessors 1-84 .

ir Microprocessors 1-85 . PC  stack hsabaghianb @ kashanu. but Return instruction pops PC from stack to get address to jump to ret .Return Return is also similar to a jump.ac.

acall sublabel .ir Microprocessors 1-86 . .. ....Subroutines call to the subroutine Main: . the subroutine ret sublabel: hsabaghianb @ kashanu.....ac.. ..

Initializing Stack Pointer  SP is initialized to 07 after reset. #2Fh hsabaghianb @ kashanu.  When using subroutines.ac. mov SP.(Same address as R7)  With each push operation 1st . Location 2Fh is often used. so it is very important to initialize the stack pointer. the stack will be used to store the PC. pc is increased.ir Microprocessors 1-87 .

ac.9.a mul ab pop b ret  8 byte and 11 machine cycle square: square: inc a movc a.4.36.49.@a+pc ret table: db 0.ir Microprocessors 1-88 .81  13 byte and 5 machine cycle hsabaghianb @ kashanu.Subroutine .1.64.25.16.Example push b mov b.

4 of A reset service main program sqrt: subroutine data Microprocessors 1-89 Sqrs: hsabaghianb @ kashanu.3.2. org 0 ljmp Main Main: loop: mov P3.2. (bits 3-0) and output on Port 1. a sjmp loop inc a movc a. Port 3 is an input .3 end .2. P3 anl a. Clear bits 7.. #0xFF mov a.2.3.1.Subroutine – another example .1.1.2. @a + PC ret db 0. #0x0F lcall sqrt mov P1.3.3.ac.ir .3. Program to compute square root of value on Port 3 .3.

hsabaghianb @ kashanu.ir Microprocessors 1-90 .ac.Why Subroutines? Subroutines allow us to have "structured" assembly language programs. This is useful for breaking a large design into manageable parts. It saves code space when subroutines can be called many times in the same program.

ir Microprocessors 1-91 .8051 timer hsabaghianb @ kashanu.ac.

6 NEXT: reti return Microprocessors 1-92 . R1 addc a. #20 mul ab add a. b mov a. b mov R1. a end hsabaghianb @ kashanu. a mov R1. R0 mov R0. a mov a. #2 mov b. #12 mov b.r7 jnz NEXT cpl P1. #16 mul ab mov R0.Interrupts … mov a.ir Program Execution interrupt ISR: inc r7 mov a.ac.

Interrupt Sources Original 8051 has 5 sources of interrupts      Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full. another serial port (UART) hsabaghianb @ kashanu. more external interrupts.ir Microprocessors 1-93 . etc) Enhanced version has 22 sources  More timers. ADC.ac. programmable counter array. buffer empty.

When a RETI instruction is encountered. AND interrupts are enabled.ac. 2. Program execution continues at the interrupt vector address for that interrupt.ir Microprocessors 1-94 . the PC is popped from the stack and program execution resumes where it left off. hsabaghianb @ kashanu.Interrupt Process If interrupt event occurs AND interrupt flag for that event is enabled. Current PC is pushed on stack. then: 1. 3.

All interrupts have a default priority order.ir Microprocessors 1-95 . Priority can also be set to “high” or “low”. hsabaghianb @ kashanu.ac.Interrupt Priorities What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first.

ir Microprocessors 1-96 .ac.Interrupt SFRs Interrupt enables for the 5 original 8051 interrupts: Timer 2 Serial (UART0) Timer 1 Global Interrupt Enable – External 1 must be set to 1 for any Timer 0 1 = Enable interrupt to be enabled External 0 0 = Disable hsabaghianb @ kashanu.

External Interrupt 0: Timer 0 overflow: External Interrupt 1: Timer 1 overflow: Serial : Timer 2 overflow(8052+) 0003h 000Bh 0013h 001Bh 0023h 002bh Note: that there are only 8 memory locations between vectors.ac.ir Microprocessors 1-97 . hsabaghianb @ kashanu.Interrupt Vectors Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.

. hsabaghianb @ kashanu. at EX7 vector . Interrupt service routine . Can go after main program .ac...ir Microprocessors 1-98 . and subroutines.Interrupt Vectors To avoid overlapping Interrupt Service routines.. Main program ... it is common to put JUMP instructions at the vector address. This is similar to the reset vector. . . org 009B ljmp EX7ISR cseg at 0x100 Main: . at Main program .. reti .. EX7ISR:.

complement LED value . R5-R7. #02h mov R6.Modifies R0.ir Microprocessors 1-99 . $ djnz R6. #00h mov R5. .save state of status word .select register bank 3 .Example Interrupt Service Routine . Loop2 pop PSW reti .6 djnz R0.EX7 ISR to blink the LED 5 times.---------------------------------------------------- ISRBLK: Loop2: Loop1: Loop0: push PSW mov PSW.initialize counter .go on then off 10 times hsabaghianb @ kashanu. bank 3. Loop1 cpl P1. #10 mov R7.ac.delay a while . .#18h mov R0. #00h djnz R5. Loop0 djnz R7.

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