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IKI10201 04b-Simplification of Boolean Functions

Bobby Nazief Semester-I 2005 - 2006

The materials on these slides are adopted from Prof. Daniel Gajskis transparency for Principles of Digital Design.

Tabulation Method

Map method is a trial-and-error procedure Tabulation method performs thorough search It starts with SOM and consists of 2 steps: PIs generation group minterms by number of 1s compare minterms & find pairs that differ in 1 variable generate subcubes repeat the above 3 steps to generate subcubes until no more subcubes can be generated Minimal cover generation find EPIs through a selection table find minimal cover through the POS of PIs

Example: simplify wyz + wz + xyz + wy

K-map representation: yz 00 01 wx
00 01 11 10 1 1 0 0 0 0 1 1 11 1 1 1 1 10 1 1 0 0

PIs generation: 0-subcubes

Example: simplify wyz + wz + xyz + wy (cont.)

1-subcubes

2-subcubes

Example: simplify wyz + wz + xyz + wy (cont.)

Minimal cover generation: EPIs selection

PI list: EPI list: POS:

wz, wy, yz, wz wz, wz (P2 + P3)(P2 + P3) = P2 + P3

Minimal cover expressions: F1 = wz + wz + wy F2 = wz + wz + yz


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Another example

K-map representation: yz 00 01 wx
00 01 11 10 0 0 0 1 0 0 1 1 11 0 1 1 0 10 1 1 0 0

PIs generation: 0-subcubes, 1-subcubes

Another example (cont.)

Minimal cover generation: EPIs selection

PI list: EPI list: POS:

wyz, xyz, wxy, wxz, xyz, wyz wyz, xyz (P3 + P5)(P4 + P6)(P5 + P6) = (P3 + P5)(P4P5 + P5P6 + P4P6 + P6) = P3P4P5 + P4P5 + P3P6 + P5P6

Minimal cover expressions: F1 = wyz + xyz + wxz + xyz F2 = wyz + xyz + wxy + wyz F3 = wyz + xyz + xyz + wyz

Technology Mapping for Gate Arrays



Gate arrays contain only one type of m-input gate (such as 3-input NAND, 3-input NOR) Technology mapping is a transformation of Boolean expressions into a logic schematic containing only this type (NAND or NOR) of gate SOP/POS NAND/NOR gate implementation

Conversion & Optimization

Conversion:

Optimization:

Conversion procedure: replace AND & OR gates with NAND (NOR) gates by using Rules 1 & 2 (3 & 4), and eliminate double inverters whenever possible

Translation standard forms to NAND/NOR schematics

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Conversion to NAND (NOR) gates

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Technology Mapping for Custom Libraries



Libraries contain gates with different functions and different delays Technology mapping means covering schematic with library gates Minimize delay on critical paths Minimize cost on non-critical paths

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Example design with custom libraries



F = wz + z(w + y) AND-OR implementation (delay = 7.2ns, cost = 28)

NAND implementation (delay = 5.2ns, cost = 22)

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Example design with custom libraries (cont.)

Alternatif A (delay = 5.4ns, cost = 20)

Alternatif B (delay = 3.8ns, cost = 20)

Alternatif B-optimized (delay = 3.8ns, cost = 18)

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Design with static 1-hazard


Timing Diagram

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Hazard-free design
Timing Diagram

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