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Dr. Bernard Chen Ph.D.
University of Central Arkansas Spring 2009
32-bit floating point format. Leftmost bit = sign bit (0 positive or 1 negative). Exponent in the next 8 bits. Use a biased representation. Final portion of word (23 bits in this example) is the significant (sometimes called mantissa).
Convert the following number;37.75 into floating point format to fit in 32 bit register. Convert the number from decimal into binary 100101.11 Normalize all digits including the fraction to determine the exponent. 5 1.0010111 x 2
0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0
For register R0 to R3 in a 4 bit system
4-line common bus
4*1 MUX 3 3 2 1 0 4*1 MUX 2 3 2 1 0 3 4*1 MUX 1 2 1 0 3 4*1 MUX 0 2 1 0
S1 0 0 1 1
S0 0 1 0 1
Register selected A B C D
Used for highest bit from each register
Used for lowest bit
For register R0 to R63 in a 16 bit system:
What is the MUX size we use? How many MUX we need? How many select bit?
Memory Transfer The transfer of information from a memory word to the outside environment is called a read operation The transfer of new information to be stored into the memory is called a write operation .
Memory Read and Write AR: address register DR: data register Read: DR M[AR] Write: M[AR] R1 .
Arithmetic Microoperations A single circuit does both arithmetic addition and subtraction depending on control signals. It denotes addition) . • Arithmetic addition: R3 R1 + R2 (Here + is not logical OR.
Adding 1 to the one’s complement is equivalent to taking the 2’s complement of R2 and adding it to R1. .Arithmetic Microoperations Arithmetic subtraction: R3 R1 + R2 + 1 where R2 is the 1’s complement of R2.
.BINARY ADDER Binary adder is constructed with fulladder circuits connected in cascade.
BINARY ADDER-SUBTRACTOR .
4-bit Binary Incrementer B3 B2 B1 B0 1 x y x y x y x y Always added to 1 HA C S HA C S HA C S HA C S C4 S3 S2 S1 S0 .
Shift Microoperations Symbolic designation R ← shl R R ← shr R R ← cil R R ← cir R R ← ashl R R ← ashr R Description Shift-left register R Shift-right register R Circular shift-left register R Circular shift-right register R Arithmetic shift-left R Arithmetic shift-right R TABLE 4-7. Shift Microoperations .
Logical Shift A logical shift transfers 0 through the serial input The bit transferred to the end position through the serial input is assumed to be 0 during a logical shift (Zero inserted) R1 shl R1 R 2 shr R 2 0 0 .
Circular Shift The circular shift circulates the bits of the register around the two ends without loss of information .
Arithmetic Shift An arithmetic shift shifts a signed binary number to the left or right An arithmetic shift-left multiplies a signed binary number by 2 An arithmetic shift-right divides the number by 2 In arithmetic shifts the sign bit receives a special treatment .
so on. Rn-3 receives Rn-2. 1 is shifted from the sign bit to the right. A negative number is represented by the 2’s complement.Arithmetic Shift Right Arithmetic right-shift: Rn-1 remains unchanged. For a negative number. The sign bit remained unchanged. . Rn-2 receives Rn-1.
Arithmetic Shift Left The operation is same with Logic shift-left The only difference is you need to check overflow problem Carry out Sign bit R2 ashl R2 LSB Rn-1 Rn-2 0 insert Vs=1 : Overflow Vs=0 : use sign bit .
Purpose of Chapter5 In this chapter we introduce a basic computer and show how its operation can be specified with register transfer statements. .
data.Instruction Codes A process is controlled by a program A program is a set of instructions that specify the operations. and the control sequence An instruction is stored in binary code that specifies a sequence of microoperations Instruction codes together with data are stored in memory (Stored Program Concept) .
Program statements and computer instructions Computer instruction Field specifying the operation to be executed Field specifying the data To be operated on .
Code + Address Op. Code : specify 16 possible operations(4 bits) Address : specify the address of an operand(12 bits) If an operation in an instruction code does not need an operand from memory.Instruction code format Instruction code format with two parts : Op. Code Address data instruction Not an instruction . the rest of the bits in the instruction(address field) can be used for other purpose 15 12 11 0 15 12 11 0 Op.
Address is selected in memory and its Data placed on the bus to be loaded into the Data Register to be used for requested instructions . Address part of IR is placed on the bus and loaded back into the AR 2.Direct address Occurs When the Operand Part Contains the Address of Needed Data. 1.
Direct address .
New Address is selected in memory and placed on the bus to be loaded into the DR to use later . 1. Address part of IR is placed on the bus and loaded back into the AR 2.Indirect address Occurs When the Operand Contains the Address of the Address of Needed Data. Address is selected in memory and placed on the bus to be loaded Back into the AR 3.
Indirect address .
Effective address: • Effective address: Address where an operand is physically located Effective address: 457 Effective address: 1350 .
AC and INPR : ADD DR to AC. The input register is connected only to the ALU .Computer Registers Accumulator(AC) : takes input from ALU The ALU takes input from DR. AND DR to AC Note) Input register is not connected to the bus.
12 bit width .5-2 Computer Registers Data Register(DR) : hold the operand(Data) read from memory Accumulator Register(AC) : general purpose processing register Instruction Register(IR) : hold the instruction read from memory Temporary Register(TR) : hold a temporary data during processing Address Register(AR) : hold a memory address.
memory read cycle is initiated. and PC is incremented by one(next instruction fetch) .5-2 Computer Registers Program Counter(PC) : hold the address of the next instruction to be read from memory after the current instruction is executed Instruction words are read and executed in sequence unless a branch instruction is encountered A branch instruction calls for a transfer to a nonconsecutive instruction in the program The address part of a branch instruction is transferred to PC to become the address of the next instruction To read instruction.
5-2 Computer Registers Input Register(INPR) : receive an 8-bit character from an input device Output Register(OUTR) : hold an 8-bit character for an output device .
Mano's simple Computer: Instructions 15 12 11 I 000 AND 001 ADD 010 LDA (Load Accumulator) 011 STA (Store Accumulator) 0 Any bits other than 0111 and 1111 are called memory reference instructions 100 BUN (Branch Unconditional) 101 BSA (Branch and Store Address) 110 ISZ (Increment and Skip if Zero) .
Computer Instruction 3 Instruction Code Formats : Fig. ION. 5-5 Memory-reference instruction Opcode = 000 110 I=0 : 0xxx ~ 6xxx. I=1 : Indirect I Opcode Address Register-reference instruction 15 14 12 11 0 7xxx (7800 ~ 7001) : CLA. OUT.5-3. 0 1 1 1 Register Operation Input-Output instruction Fxxx(F800 ~ F040) : INP. I=1: 8xxx ~Exxx 15 14 12 11 0 I=0 : Direct. SKI. CMA. 15 14 12 11 0 1 1 1 1 I/O Operation Symbol AND ADD LDA STA BUN BSA ISZ CLA CLE CMS CME CIR CIL INC SPA SNA SZA SZE HLT INP OUT SKI SKO ION IOF Hex Code I=0 I=1 0xxx 8xxx 1xxx 9xxx 2xxx Axxx 3xxx Bxxx 4xxx Cxxx 5xxx Dxxx 6xxx Exxx 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001 F800 F400 F200 F100 F080 F040 Description And memory word to AC Add memory word to AC Load memory word to AC Store content of AC in memory Branch unconditionally Branch and Save return address Increment and skip if zero Clear AC Clear E Complement AC Complement E Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is 0 Halt computer Input character to AC Output character from AC Skip on input flag Skip on output flag Interrupt On Interrupt Off .
Mano. Inc. INR OUTR . Copyright (C) 1993 Prentice-Hall.Mano’s Computer Figure 5-4 Memory Unit 4096x16 WRITE AR LD LD LD Adder & Logic E Address s0 s1 s2 Bus 7 READ 1 CLR INR PC 2 CLR INR DR INR AC 3 CLR 4 CLR LD INR INPR IR 5 6 CLR Clock LD TR LD LD 16-bit common bus Computer System Architecture.
A 4-bit binary sequence counter (SC) to count from 0 to 15 to achieve time sequencing. ...... T15 A digital circuit with inputs D0. I. T15. bus.. > A 4x16 decoder to decode the output of the counter into 16 timing signals. . T0. D7... . and address bits in IR (11-0) to generate control outputs supplied to control inputs and select signals of registers . T0. ..
decode Next Instruction Interrupts Enabled Execute Instruction Interrupt cycle HALT .Instruction and Interrupt cycles Interrupt Cycle Instruction cycle Interrupts Disabled START Fetch.
REGISTER-REFERENCE INSTRUCTIONS • The 12 register-reference instructions are recognized by I = 0 and D7 = 1 (IR(12-14) = 111). Each operation is designated by the presence of 1 in one of the bits in IR(0-11). Therefore D7I`T3 r = 1 is common to all register-transfer instructions. .
. In binary this is equivalent to: 0000 0000 0111 (CIR) • B6 = 006 (in hexadecimal).. In binary this is equivalent to: 0000 0000 0110 (CIL) .For example • B7 = 007 (in hexadecimal).
For example • B3 = 008 (in hexadecimal). In binary this is equivalent to: 0000 0000 1000 (Complement E) • B4 = 010 (Bi=bit in position i =4) in binary is 0000 0001 0000 (skip if positive) ..
.6 Memory Reference Instructions • Opcode (000 .5.110) or the decoded output Di (i = 0.. . 6) are used to select one memory-reference operation out of 7...
Output Register(OUTR) • These two registers communicate with a communication interface serially and with the AC in parallel • Each quantity of information has eight bits of an alphanumeric code .7 IO and Interrupt • Input-Output Configuration : – Input Register(INPR).5.
Output Flag(FGO) – FGI : set when INPR has information. clear when INPR is empty – FGO : set when operation is completed. clear when output device is active (for example a printer is in the process of printing) .IO and Interrupt • Input Flag(FGI).
T0'T1'T2' ( IEN )( FGI FGO) : R 1 Instruction cycle =0 R =1 Interrupt cycle Fetch and decode instruction Store return address in location 0 M PC =0 Execute instruction IEN =1 =1 Branch to location 1 PC 1 FGI =0 =1 FGO =0 IEN R 0 0 R 1 .
TR PC RT1 : M [ AR] TR. R 0.Program Interrupt • Demonstration of the interrupt cycle : – The memory location at address 0 is the place for storing the return address – Interrupt Branch to memory location 1 – Interrupt cycle IEN=0 0 256(return address) PC = 1 255 256 0 BUN 1120 Main Program Interrupt Here Save Return Address(PC) at 0 Jump to 1(PC=1) RT0 : AR 0. IEN 0. SC 0 1120 1 Interrupt Service Routine BUN 0 . PC 0 RT2 : PC PC 1.
Program Interrupt Demonstration of the interrupt cycle : The memory location at address 0 is the place for storing the return address Interrupt Branch to memory location 1 Interrupt cycle IEN=0 0 256(return address) PC = 1 255 256 0 BUN 1120 Main Program Interrupt Here Save Return Address(PC) at 0 Jump to 1(PC=1) RT0 : AR 0. PC 0 RT2 : PC PC 1. R 0. IEN 0. TR PC RT1 : M [ AR] TR. SC 0 1120 1 Interrupt Service Routine BUN 0 .
General Register Organization Clock R1 R2 R3 R4 R5 R6 R7 Input Bus organization for 7 CPU registers: 2 Load (7 lines) SELA MUX MUX SELB MUX A and BUS B 3×8 decoder A bus B bus BUS ALU 3 SELD OPR Arithmetic logic unit (ALU) X 8 Decoder Output (a) Block diagram 3 3 3 5 SELA SELB SELD OPR (b) Control word .8-2.
General Register Organization Bus organization for 7 CPU registers: 2 MUX: select one of 7 register or external data input by SELA and SELB BUS A and BUS B : form the inputs to a common ALU ALU : OPR determine the arithmetic or logic microoperation The result of the microoperation is available for external data output and also goes into the inputs of all registers 3 X 8 Decoder: select the register (by SELD) that receives the information from ALU .8-2.
Encoding of Register Selection Fields: »SELA or SELB = 000 (External Input) : MUX selects the external data »SELD = 000 (None) : no destination register is selected but the contents of the output bus are available in the external output .
Control word Field: Symbol: Control word: SELA R2 010 SELB R3 011 SELD R1 001 OPR SUB 00101 . Micro-operation R1 R2 .R3 2.Example (Example 2) 1.
Symbol AND ADD LDA STA BUN BSA ISZ CLA CLE CMS CME CIR CIL INC SPA SNA SZA SZE HLT INP OUT SKI SKO ION IOF Hex Code I=0 I=1 0xxx 8xxx 1xxx 9xxx 2xxx Axxx 3xxx Bxxx 4xxx Cxxx 5xxx Dxxx 6xxx Exxx 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 7001 F800 F400 F200 F100 F080 F040 Description And memory word to AC Add memory word to AC Load memory word to AC Store content of AC in memory Branch unconditionally Branch and Save return address Increment and skip if zero Clear AC Clear E Complement AC Complement E Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is 0 Halt computer Input character to AC Output character from AC Skip on input flag Skip on output flag Interrupt On Interrupt Off .
Mano's Computer: RTL .
Register Transfer Statement Initial Values Instru 1 Instru 2 Instru 3 Instru 4 Instru 5 Instru 6 Instru 7 E AC DR PC AR M[AR] IR 0 0 0 0 0 0 0 0 2A34 2A34 2A34 2A34 2A34 2A34 D5CB 151A 00C7 00C7 2A34 2A34 2A34 2A34 2A34 2A34 025 026 027 619 620 621 622 623 237 200 200 619 400 400 200 080 0400 2A34 2A34 B200 2A34 2A34 0400 Not shown 0000 3200 0200 4619 B200 8200 7200 7080 .
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