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Decoder Explanation

Decoder Explanation

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2b)

VHDL 4

Building blocks of a computer

VHDL 4 : (ver.2b)

We will study the building blocks of a computer.

decoders, multiplexers etc. Beware that , there are usually more than one way to design the same digital system in VHDL

VHDL 4 : (ver.2b)

A typical CPU

FFs=Flip-flops

A state machine

contains FFs

Address bus

(latches) data-bus Memory

(state machine)

ALU

(state machine)

Transceivers

(bi-directional buffers )

VHDL 4 : (ver.2b)

1) latch, 2) flipflop with asynchronous reset, 3) flipflop with synchronous reset, 4) tri state buffer, 5) decoder, 6) multiplexer, 7) bi-directional buffer,

VHDL 4 : (ver.2b)

VHDL Exercise 4 1) Latch: when gate=1, output follows input (level sensitive)

1 entity latch_ex is

2 port (gate, in1 : in std_logic; 3

out1 : out std_logic); 4 end latch_ex; 5 architecture latch_ex_arch of latch_ex is 6 begin sensitivity list 7 process (gate,in1) 8 begin 9 if (gate = '1') then 10 out1 <= in1; http://faculty.kfupm.edu.sa/COE/ashraf/Ric hFilesTeaching/COE022_200/Chapter4_1.ht 11 end if; m, or P.72 Advanced Digital Design with 12 end process; the Veriolog HDL by M.D. Ciletti 13 end latch_ex_arch; The process executes once when gate or in1 changes

VHDL 4 : (ver.2b)

In1 gate in1 Latch q

gate

q

VHDL 4 : (ver.2b)

statement

1 architecture dff_asyn_arch of dff_asyn is

2 begin

3 process(clock, reset) 4 begin 5

sensitivity list

if (reset = '1') then 6 out1 <= '0'; 7 elsif clock = '1' and clock'event then 8 out1 <= in1; 9 end if; 10 end process; 11 end dff_asyn_arch;

in1 clock

reset

VHDL 4 : (ver.2b)

D CK CK

Edge (50%) triggered FF

qe

qe

VHDL 4 : (ver.2b)

When will line 3 be executed? Which is more powerful: clock or reset?

1 architecture dff_asyn_arch of dff_asyn is

2 begin

3 process(clock, reset) 4 begin 5

For asyn. reset flipflop asyn. reset and clock must be in the sensitivity list

if (reset = '1') then 6 out1 <= '0'; 7 elsif clock = '1' and clock'event then 8 out1 <= in1; 9 end if; 10 end process; 11 end dff_asyn_arch;

VHDL 4 : (ver.2b)

10

What is the difference between level triggered and edge

triggered flip-flops? **In Xilinx-Foundation all flip-flops are treated as 50% edge triggered flip-flops. What is the difference between

synchronous reset (syn-reset) flip-flops and asynchronous reset (asyn-reset) flip-flops?

VHDL 4 : (ver.2b)

11

3) Flip-flop with syn. reset: clock before reset statement 1 architecture dff_syn_arch of dff_syn is 2 begin process(clock,reset) reset can be removed, 4 begin -but allowed 5 if clock = '1' and clock'event then edge triggered clock 6 if (reset = '1') then 7 out1 <= '0'; 8 else reset 9 out1 <= in1; out1 10 end if; in1 11 end if; D 12 end process; clock 13 end dff_syn_arch;

Discuss why reset is not needed in the sensitivity list

VHDL 4 : (ver.2b)

12

The order of the statements inside the

Syn. Reset Flip-Flop (check clock first)

Asyn. Reset Flip-Flop (check reset first)

VHDL 4 : (ver.2b)

13

(Use capital letter big Z for float, Z is a reserved character)

remember: Z is a scissor

1 entity tri_ex is

2 port (in1, control : in std_logic; 3

out1 : out std_logic); 4 end tri_ex; 5 architecture tri_ex_arch of tri_ex is 6 begin 7 out1 <= in1 when control = '1' else 'Z'; 8 end tri_ex_arch;

VHDL 4 : (ver.2b)

14

VHDL 4 : (ver.2b)

15

1 architecture decoder_a of decoder is 2 begin 3 process (in1, in2)

sensitivity list

4 begin

5 6 7

8

9 10 11 12 13 14

if in1 = '0' and in2 = '0' then out00 <= '1'; else case 1 out00 <= '0'; end if; if in1 = '0' and in2 = '1' then out01 <= '1'; else out01 <= '0'; case 2 end if;

out01

VHDL 4 : (ver.2b)

16

(contin.)Decoder

15 if in1 = '1' and in2 = '0' then 16 out10 <= '1'; case 3 (open the safe) 17 else 18 out10 <= '0'; 19 end if; 20 if in1 = '1' and in2 = '1' then 21 out11 <= '1'; 22 else 23 out11 <= '0'; case 4 24 end if; 25 end process; 26 end decoder_a;

VHDL 4 : (ver.2b)

17

1 architecture mux_arch of mux is 2 begin 3 process (in1, in2, ctrl) 4 begin 5 if ctrl = '0' then 6 out1 <= in1; 7 else 8 out1 <= in2; 9 end if; 10 end process; end mux_arch;

out1

Mux

VHDL 4 : (ver.2b)

18

1 entity inout_ex is

3

ctrl : in std_logic); 4 end inout_ex; 5 6 architecture inout_ex_a of inout_ex is 7 --signal outbuf, inbuf : std_logic; 8 begin 9 io1 <= io2 when ctrl = '1' else 'Z'; 10 io2 <= io1 when ctrl = '0' else 'Z'; 11 end inout_ex_a;

ctrl

io2

io1

concurrent statements

VHDL 4 : (ver.2b)

19

Crt=1, io1 follow io2_in Crt=0, io2 follow io1_in Plot io1 io2

io2

R=10K

ctrl io1

R=10K

Io2_in

Io1_in

VHDL 4 : (ver.2b)

20

Quick revision

You should know how to design asynchronous , synchronous reset flip-flops tri state buffers, Combination logics

decoders,

multiplexers,

bi-directional buffers,

VHDL 4 : (ver.2b)

21

practice: Initialize variables before use; assign values to variables from input first)

library IEEE; use IEEE.std_logic_1164.all; entity test is port (a,reset_v1: in std_logic; b ,c: out std_logic); end test; architecture test_arch of test is begin label_proc1: process (a,reset_v1)

variable v1 : std_logic; begin if reset_v1 ='1' then v1:= not a; end if; b<=a; c<=v1; end process label_proc1;

end test_arch;

**The answer is yes. That means after a process is called, the state of a variable will be stored for the next time the process is being run again.

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