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MOSFETS

Dr. Mohammed Morsy

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 2

Faculty of Engineering - Alexandria University

Four terminals: gate (G), source (S), drain (D), body (B)

Gate–oxide–body stack looks like a capacitor

Gate and body are conductors

SiO

2

(oxide) is a very good insulator

Called metal – oxide – semiconductor (MOS) capacitor

Even though gate is no longer made of metal

nMOS Transistor

EE 4E4 VLSI Modeling and Design 3

Faculty of Engineering - Alexandria University

Body is usually tied to ground (0 V)

When the gate is at a low voltage

P-type body is at low voltage

Source-body and drain-body diodes are OFF

No current flows, transistor is OFF

nMOS Operation (1/2)

EE 4E4 VLSI Modeling and Design 4

Faculty of Engineering - Alexandria University

When the gate is at a high voltage

Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type

Now current can flow through n-type silicon from source through

channel to drain, transistor is ON

nMOS Operation (2/2)

EE 4E4 VLSI Modeling and Design 5

Faculty of Engineering - Alexandria University

Similar, but doping and voltages reversed

Body tied to high voltage (VDD)

Gate “low”: transistor ON

Gate “high”: transistor OFF

Bubble indicates inverted behavior

pMOS Transistor

EE 4E4 VLSI Modeling and Design 6

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 7

Faculty of Engineering - Alexandria University

Ideal Switches (1/3)

CMOS integrated circuits use bi-directional devices called

MOSFETs as logic switches

» Controlled switches, e.g, assert-high and assert-low switches

An assert-high switch is showing in Figure 2.1

Figure 2.1 Behavior of an assert-high switch

(a) Open (b) Closed

EE 4E4 VLSI Modeling and Design 8

Faculty of Engineering - Alexandria University

Ideal Switches (2/3)

g = (a．1) ．b = (a．1) ．b

g = (a．1) + (b．1) = a + b

Figure 2.2 Series-connected switches

Figure 2.4 Parallel-connected switches

EE 4E4 VLSI Modeling and Design 9

Faculty of Engineering - Alexandria University

Ideal Switches (3/3)

Figure 2.5 An assert-low switch

(a) Closed

(b) Open

Figure 2.6 Series-connected complementary switches

Figure 2.7 An assert-low switch

Figure 2.8 A MUX-based

NOT gate

EE 4E4 VLSI Modeling and Design 10

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 11

Faculty of Engineering - Alexandria University

MOSFET as Switches

MOSFET: Metal-Oxide-Semiconductor

Field-Effect Transistor

nFET: an n-channel MOSFET that uses

negatively charged electrons for

electrical current flow

pFET: a p-channel MOSFET that uses

positive charges for current flow

In many ways, MOSFETs behave like

the idealized switches introduced in the

previous section

The voltage applied to the gate

determines the current flow between

the source and drain terminals

Figure 2.9 Symbols used

for nFETs and pFETs

(a) nFET symbol

(b) pFET symbol

EE 4E4 VLSI Modeling and Design 12

Faculty of Engineering - Alexandria University

Early generations of silicon

MOS logic circuits used both

positive and negative supply

voltages as Figure 2.10

showing

Modern designs require only a

single positive voltage V

DD

and

the ground connection, e.g.

V

DD

= 5 V and 3.3 V or lower

The relationship between logic

variables x and it’s voltages V

x

MOSFET as Switches

Figure 2.11 Single voltage power supply

(a) Power supply connection (b) Logic definitions

DD x

V V s s 0

V V that means x

x

0 0 = =

DD x

V V that means x = =1

(2.14)

(2.15)

EE 4E4 VLSI Modeling and Design 13

Faculty of Engineering - Alexandria University

In general,

The transition region between the

highest logic 0 voltage and the lowest

logic 1 voltage is undefined

nFET

pFET

Switching Characteristics of MOSFET

Figure 2.13 pFET switching characteristics

(a) Open (b) Closed

Figure 2.12 nFET switching characteristics

(a) Open (b) Closed

Low voltages correspond to logic 0 values

High voltages correspond to logic 1 values

1 = · = A iff valid is which A x y

0 = · = A iff valid is which A x y

(2.16)

(2.17)

EE 4E4 VLSI Modeling and Design 14

Faculty of Engineering - Alexandria University

An nFET is characterized by a threshold

voltage V

Tn

that is positive, typical is around

V

Tn

= 0.5 V to 0.7 V

If , then the transistor acts like an

open (off) circuit and there is no current flow

between the drain and source

If , then the nFET drain and source

are connected and the equivalent switch is

closed (on)

Thus, to define the voltage V

A

that is

associated with the binary variable A

nMOS FET Threshold Voltages

Figure 2.14 Threshold voltage of an nFET

(a) Gate-source voltage

(b) Logic translation

Tn GSn

V V s

Tn GSn

V V >

GSn A

V V = (2.20)

EE 4E4 VLSI Modeling and Design 15

Faculty of Engineering - Alexandria University

An pFET is characterized by a threshold

voltage V

Tp

that is negative, typical is around

V

Tp

= –0.5 V to –0.8 V

If , then the transistor acts like an

open (off) switch and there is no current flow

between the drain and source

If , then the pFET drain and source are

connected and the equivalent switch is closed

(on)

Thus, to the applied voltage V

A

we first sum

voltage to write

pMOS FET Threshold Voltages

Figure 2.15 pFET threshold voltage

(a) Source-gate voltage

(b) Logic translation

Tp SGp

V V s

Tp SGp

V V >

DD SGp A

V V V = +

V V

A

0 =

DD A

V V =

SGp DD A

V V V ÷ = ¬

(2.23)

(2.24)

(2.26)

Tp DD

V V ÷

(2.25)

Note that the transition between a

logic 0 and a logic 1 is at Eqn (2.25) !

EE 4E4 VLSI Modeling and Design 16

Faculty of Engineering - Alexandria University

An ideal electrical switch can

pass any voltage applied to it

As Figure 2.16(b), the output

voltage V

y

is reduced to a value

which is less than the input voltage

VDD, called threshold voltage loss

Thus, we say that the nFET can

only pass a weak logic 1; in

other word, the nFET is said to

pass a strong logic 0 can

pass a voltage in the range [0, V

1

]

nFET Pass Characteristics

Figure 2.16 nFET pass characteristics

(a) Logic 0 transfer

(b) Logic 1 transfer

Tn DD

V V V ÷ =

1

since

Tn GSn

V V = (2.27)

EE 4E4 VLSI Modeling and Design 17

Faculty of Engineering - Alexandria University

Figure 2.17(a) portrays the case where

V

x

= V

DD

corresponding to a logic 1 input.

The output voltage is

Figure 2.17(b), the transmitted voltage

can only drop to a minimum value of

The results of the above discussion

nFETs pass strong logic 0 voltages, but

weak logic 1 values

pFETs pass strong logic 1 voltages, but

weak logic 0 levels

Use pFETs to pass logic 1 voltages of V

DD

Use nFETs to pass logic 0 voltages of V

SS

= 0 V

pFET Pass Characteristics

Figure 2.17 pFET pass characteristics

(a) Logic 0 transfer

(b) Logic 1 transfer

DD y

V V =

Tp y

V V =

since

Tp SGp

V V =

,which is an ideal logic 1 level

(2.29)

(2.30)

EE 4E4 VLSI Modeling and Design 18

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 19

Faculty of Engineering - Alexandria University

Digital logic circuits are nonlinear networks

that use transistors as electronic switches to

divert one of the supply voltages V

DD

or 0 V

to the output

The general switching network

Basic Logic Gates in CMOS

Figure 2.18 General CMOS logic gate

Figure 2.19 Operation of a CMOS logic gate

(a) f = 1 output

(b) f = 0 output

EE 4E4 VLSI Modeling and Design 20

Faculty of Engineering - Alexandria University

The NOT Gate (1/2)

Figure 2.20 A complementary pair

(b) x = 1 input

(b) Truth Table

(a) Logic symbol (a) x = 0 input

Figure 2.22 NOT gate

Figure 2.21 Operation of

the complementary pair

EE 4E4 VLSI Modeling and Design 21

Faculty of Engineering - Alexandria University

The NOT Gate (2/2)

Figure 2.23 CMOS not gate (b) x = 1 input

(a) x = 0 input

Figure 2.24 Operation of

the CMOS NOT gate

EE 4E4 VLSI Modeling and Design 22

Faculty of Engineering - Alexandria University

The NOR Gate (1/2)

(b) Truth Table

(a) Logic symbol

(a) Logic diagram

(b) Voltage network

Figure 2.26 NOR2

using a 4:1 multiplexor Figure 2.25 NOR logic gate

Figure 2.27 NOR2 gate

Karnaugh map

EE 4E4 VLSI Modeling and Design 23

Faculty of Engineering - Alexandria University

NOR (2/2)

Figure 2.30 NOR3 in CMOS

Figure 2.28 NOR2 in CMOS

Figure 2.29 Operational summary of the NOR2 gate

EE 4E4 VLSI Modeling and Design 24

Faculty of Engineering - Alexandria University

NAND (1/2)

(b) Truth Table

(a) Logic symbol

(a) Logic diagram

(b) Voltage network

Figure 2.32 NAND2

using 4:1 multiplexor

Figure 2.31 NAND2 logic gate

Figure 2.33 NAND2 K-map

EE 4E4 VLSI Modeling and Design 25

Faculty of Engineering - Alexandria University

NAND (2/2)

Figure 2.36 NAND3 in CMOS

Figure 2.34 CMOS NAND2 logic circuit

Figure 2.35 Operational summary of the NAND2 gate

EE 4E4 VLSI Modeling and Design 26

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 27

Faculty of Engineering - Alexandria University

Complex or combinational logic gates

Useful in VLSI system-level design

Consider a Boolean expression

Expanding by simply ANDing the result with a

logical 1

Complex Logic Gate (1/3)

1 )] ( [

) (

) ( ) , , (

· · + =

+ + =

+ · =

c b a

c b a

c b a c b a F

) ( ) , , ( c b a c b a F + · =

1 ) ( 1 · · + · = c b a F (2.51)

(2.50)

EE 4E4 VLSI Modeling and Design 28

Faculty of Engineering - Alexandria University

Complex Logic Gate (2/3)

Figure 2.37 Logic function example

Figure 2.38 pFET circuit for F

function from equation (2.51)

Figure 2.39 nFET circuit for F

Figure 2.40 Karnaugh for nFET circuit

nFET array that

gives F=0 when

necessary

1 ) ( 1 · · + · = c b a F

EE 4E4 VLSI Modeling and Design 29

Faculty of Engineering - Alexandria University

Complex Logic Gate (3/3)

Figure 2.41 Finished complex

CMOS logic gate circuit

The characteristics of

Complementary CMOS

For CMOS circuits, due to the completely

symmetrical structure, if the input voltage is 0

~ VDD (full swing), the output signal is also

VDD to 0 (inverting) the full-swing (strong

output levels).

There is no static power consumption.

Process variations will not affect the full swing

output of CMOS circuits. Such variations

would perhaps affect the electrical

characteristics such as the speed or power

consumption, etc., but do not affect its proper

function. This feature leverages reliable mass

production of CMOS VLSI circuits.

EE 4E4 VLSI Modeling and Design 30

Faculty of Engineering - Alexandria University

CMOS logic gates are intrinsically inverting

Output always produces a NOT operation acting on the input

variables

Structured Logic Design (1/4)

Figure 2.42 Origin of the inverting

characteristic of CMOS gates

EE 4E4 VLSI Modeling and Design 31

Faculty of Engineering - Alexandria University

Structured Logic Design (2/4)

Figure 2.43 nFET logic formation

(a) Series-connected nFETs

(b) Parallel-connected nFETs

Figure 2.44 nFET AOI circuit

Figure 2.45 nFET OAI circuit

EE 4E4 VLSI Modeling and Design 32

Faculty of Engineering - Alexandria University

Structured Logic Design (3/4)

Figure 2.46 pFET logic formation

(a) Parallel-connected pFETs

(b) Series-connected pFETs

Figure 2.47 pFET arrays for AOI and OAI gates

(a) pFET AOI circuit

(b) pFET OAI circuit

EE 4E4 VLSI Modeling and Design 33

Faculty of Engineering - Alexandria University

Structured Logic Design (4/4)

Figure 2.48 Complete CMOS AOI and OAI circuits

(a) AOI circuit (b) OAI circuit

EE 4E4 VLSI Modeling and Design 34

Faculty of Engineering - Alexandria University

Bubble Pushing

Figure 2.51 Assert-low models for pFETs

(a) Parallel-connected pFETs

(b) Series-connected pFETs

Figure 2.52 Bubble pushing using DeMorgan rules

(a) NAND - OR

(b) NOR - AND

EE 4E4 VLSI Modeling and Design 35

Faculty of Engineering - Alexandria University

An important example of

using an AOI circuit is

constructing Exclusive-OR

(XOR) and Exclusive-NOR

circuits

XOR and XNOR Gates

b a b a b a · + · = ©

b a b a b a · + · = ©

b a b a b a b a · + · = © = © ¬ ) (

b a b a b a · + · = © ¬

Figure 2.57 AOI XOR and XNOR gates

(a) Exclusive-OR (b) Exclusive-NOR

Figure 2.58 General naming convention

(a) AOI22 (b) AOI321 (c) AOI221

Figure 2.56 XOR

(2.71)

(2.72)

(2.73)

(2.74)

EE 4E4 VLSI Modeling and Design 36

Faculty of Engineering - Alexandria University

The Fundamental MOSFETs

Ideal Switches and Boolean Operations

MOSFETs as Switches

Basic Logic Gates in CMOS

Complex Logic Gates in CMOS

Transmission Gate Circuits

Outline

EE 4E4 VLSI Modeling and Design 37

Faculty of Engineering - Alexandria University

A CMOS TG is created by connecting an nFET and pFET

in parallel

Bi-directional

Transmit the entire voltage range [0, V

DD

]

Transmission Gate Circuits

1 = · = s iff s x y

(2.78)

Figure 2.60 Transmission gate (TG)

EE 4E4 VLSI Modeling and Design 38

Faculty of Engineering - Alexandria University

Multiplexors

TG based 2-to-1 multiplexor

The 2-to-1 extended to a 4:1 network by using the

2-bit selector word (s

1

, s

o

)

Logic Design using TG (1/3)

s P s P F · + · =

1 0

(2.79)

0 1 3 0 1 2 0 1 1 0 1 0

s s P s s P s s P s s P F · · + · · + · · + · · =

(2.80)

Figure 2.61 A TG-based 2-to-1 multiplexor

EE 4E4 VLSI Modeling and Design 39

Faculty of Engineering - Alexandria University

TG based XOR/XNOR

TG based OR gate

Logic Design using TG (2/3)

b a b a b a © = · + · b a b a b a b a © = · + · = ©

(2.81) (2.82)

b a

b a a

b a a a f

+ =

· + =

· + · = ) (

(2.83)

Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits

(a) XOR circuit

(b) XNOR circuit

Figure 2.63 A TG-based OR gate

EE 4E4 VLSI Modeling and Design 40

Faculty of Engineering - Alexandria University

Alternate XOR/XNOR Circuits

Mixing TGs and FETs which are designed for

exclusive-OR and equivalence (XNOR) functions

It’s important in adders and error detection/correction

algorithms

Logic Design using TG (3/3)

Figure 2.64 An XNOR gate that used both TGs and FETs

EE 4E4 VLSI Modeling and Design 41

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