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Brief history of ARM

• It defines a 32-bit RISC architecture

ARM in general!

Evolution of ARM 4 Improved ARM/Thumb Interworking 5TE Jazelle Java bytecode execution ARM9EJ-S ARM7EJ-S 1 2 3 Early ARM architectures 5TEJ DSP multiplyaccumulate instructions ARM926EJ-S ARM1026EJ-S Thumb instruction set ARM7TDMI ARM720T 4T ARM9TDMI ARM940T ARM1020E XScale ARM9E-S ARM966E-S SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support 6 ARM1136EJ-S .

ARM Revisions .

ARM Core Families .

Comparison of ARM with other Microcontrollers .

Why ARM? • Improve Code density .

Architecture of ARM The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles. The RISC instruction set and related decode mechanism are much simpler than those of Complex Instruction Set Computer (CISC) designs. .

Von-Neumann Vs Harvard No separate Program and data memories Separate Program as well as data memory area Different bus lines for program and data flow Common bus between CPU and memory .

CISC Vs RISC  Complex Instructions  Microcoded instruction  Slower Instruction execution  Less performance  Eg. 8051 Family MIPS Intel 960 IBM Power PC HP PA RISC Sun SPARC  Simple Instructions  No need for microcode  Faster instruction execution  Higher performance  Eg. PIC series ARM series Intel Pentium series Celerone AMD athlone .

ARM Advantages  A high instruction throughput  An excellent real-time interrupt response  A small. cost-effective. processor macrocell  Low Power  High performance .

ARM Manufactures .

ARM Powered Products .

ARM7 .

LPC2148 Board .

LPC2148 PIN Diagram .

LPC2148 Features .

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ARM7TDMI-S stands for ARM: Advanced RISC Machines 7 : Version number of the architecture T : THUMB: 32-bit wide instruction words 16-bit wide memory D : Debug: two break points to stop the CPU (both hardware and software) M : Multiplier: Has one multiplier I : embeddedICE S : Synthesizable (Soft Intellectual Property) .

ARM7TDMI-S Features  3-Stage Instruction pipeline  Von-Neumann Architecture  Average Instruction cycle time is ~32ns with 60 MHz Operation  Switch between ARM stage and the THUMB stage  Code density improved by 30% in THUMB stage .

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Applications        Industrial control Medical systems Access control Point-of-sale Communication gateway Embedded soft modem General purpose applications .

. .Branching.Block transfer. . .Data processing.Multiply.Data transfer.Software interrupt. .ARM Instruction Set     All ARM instructions are 32-bit long Many instructions execute in a single cycle Most ARM instructions can be conditionally executed ARM instructions can be divided into six classes . .

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THUMB .

JAZELLE .

ARM Compiler Market Players .

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ARM Connected World .

Conclusion .