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Subroutine & Interrupts

Sequence of a subroutine

it shouldn’t interfere with subroutine pgm – Call (subroutine entry address-11+2 address bits) – Return .• Note: – Stack should remain undisturbed – Registers in main pgm & subroutine should not get mixed up – Goto instruction to be used wisely.

Sequence of a nested subroutine .

it shouldn’t interfere with subroutine pgm – Call (subroutine entry address-11+2 address bits) – Return . 8 return addresses can be stored in stack – Goto instruction to be used wisely.• Note: – Stack should remain undisturbed – Storage & Retrieval of address from stack takes place one after the other – 8 level stack-LIFO – In a sequence.

Interrupts • Special task to be done on priority basis • Examples – Monitoring AC supply & emergency back up – Measuring temperature & pressure during a particular time slot – Alarm setting .

Interrupts • Main pgm execution • Interrupt signals generated from different sources • When interrupted. Special task execution • Special task completion • Resume main pgm .

Difference between Subroutine & Interrupts Subroutine Subroutine call occurs at specific & pre-determined location in the main pgm Software initiated Structured routine set of instructions Interrupt Interrupt call can occur without any prior notice at any point of the main pgm Hardware initiated Emergency condition-saving the status of registers required .

Interrupts-Procedure .

Interrupt enabling PIR – Interrupt request PIE – Interrupt mask register GIE – Global Interrupt Enable .

Bank0 Bank1 .

Interrupt timing diagram .

vector to ox04 location – 3 to 5instruction cycles – save mc status .• Single interrupt – IRQ – IE – GIE – Dummy cycles – ISR-starts @ ox04 • Interrupt status saving – Bank switching – Common scratchpad area • Return from Interrupt – RETFIE – GIE enabled • Interrupt response time – 3 to 4 instruction cycles – execution of active instruction. save return address.

0x04h PROGRAM: Service routine A Y Interrupt from Source A N Service routine B 004H:BTFSC PIR. A GOTO SRA ISR FOR B RETFIE SRA: ISR FOR A RETFIE .

Ports .

Port B – Circuit .

Port-Output operation-Write F0-Phase before port pin is configured F1-Configuring into output mode F2-Data written into port .

Read F0-Phase before port pin is configured F1-Configuring into input mode F2-Data read from port .Port-Input operation.

Pull up • Input mode • Stray signals destroy ic • Resistance connected from pin to supply • PMOS transistor kept in active state forms pull up • L2-1 nand RBPU-0 => PMOS gate – 0 state .

• Every port has port register • In Output mode-data written to port register • Ports A.D.B.E-can be configured as input or output pins .C.