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VHDL

VHDL:
“VHSIC Hardware description language” VHSIC: Very High Speed Integrated Circuit

Features of VHDL:
The U.S department of Defense (DoD) and IEEE developed a highly capable HDL with the following features. * Designs may be decomposed hierarchically * Each design has a both well defined interface ( for connecting it to other elements)and a precise behavioral specification ( for simulating it) * Behavioral specification may use either algorithm or an actual hardware structure to define an elements operation. * Concurrency , timing , and clocking can all be modeled. VHDL handles asynchronous as well as synchronous circuit structures. * The logical operation and timing behavior of a design can be simulated.

DESIGN FLOW
There are several steps in a VHDL based design process often called as “Design Flow”. These steps are applicable to any HDL based design process. The steps are,

Hierarchy/ Block diagram

Coding

Compilation

Simulation/ Verification

Synthesis

Fitting/ Place + Route

Timing verification

VHDL Program Structure:
VHDL was designed with principles of structured programming in mind, borrowing ideas from the pascal and Ada software programming languages, The key idea is, “ Defining the interface of a hardware module while hiding its internal details

Program structure of VHDL consists two parts *VHDL entity * VHDL Architecture An entity is simply a declaration of modules Input and outputs

.

Entity Declaration

An architecture is a detailed description of the module‟s internal structure or behavior

Architecture Definition

VHDL Entities and Architectures: Entity Wrapper concept Architecture Entity A Architecture A Entity B Architecture B Entity C Architecture C Entity D Architecture D Entity E Hierarchical use Architecture E Entity F Architecture F .

. port.  Reserved words and identifiers are not case sensitive  Every statement ends with a semicolon.  User defined identifiers begin with a letter and contain letters. in. digits and underscores.  Comment lines start with two hyphens(--) and end at the end of the line  Space and line breaks are ignored  VHDL defines many special character strings called “Reserved words” or “key words” Ex: Entity. out. end etc. is.Characteristics of VHDL: Some of the characteristics of VHDL are.

Mode : One of four reserved words specifying the signal direction.Syntax for entity declaration: The main purpose of entity declaration is to define its external interface signals or ports in its port declaration part. Entity entity-name is port ( signal-names : mode signal-type. Signal-names : A comma separated list of one or more user defined identifiers to name external interface signals.. ... ....... in : Signal is input to the entity out : signal is output to the entity Buffer : The signal is output to the entity and also its value can be read inside the entity‟s architecture inout : The signal can be used as input and output of the entity Signal-type: A built in or user defined signal type. signal-names : mode signal-type). It consists of . signal-names : mode signal-type.. End entity-name. Entity-name: A user selected identifier to name the entity.

Architecture architecture-name of entity-name is type declarations signal declarations constant declarations Function definitions procedure definitions component declarations Begin Concurrent statement Concurrent statement …. The syntax is as follows..Syntax for Architecture definition: The main purpose of architecture definition is to define entity‟s internal operation. Concurrent statement End Architecture-name. .

. process etc.Signal declaration: This signal declaration gives the same information about a signal as in a port declaration except mode is not specified. Variable declaration: Variables are same as signals except they don‟t have physical significance in the circuit . Signal signal-name : signal-type. Variable variable-name : variable-type. procedures . signal defined using this declaration refers to the names of the wires used in the logic diagram. Variables are normally used in VHDL functions.

Integer is defined as the range of integers including at least the range (-2^31+1 to 2^31-1) Boolean has two values true and false Character type contains all the characters in the ISO 8-bit character set. rem . The various integer and boolean operators are +. character. time. integer. boolean. Bit_vector.Types and constants: All the signals. * . string. or. * * . Severity_level. nor. . / . xor . abs . nand . The first 128 are ASCII characters.Integer operators and.xnor . not  Boolean operators . variables.. The “type” specifies the set or range of values that a object can take on. constants used in the VHDL should have some associated “type”. mod . real. VHDL Predefined types are: bit.

. go). Enumerated types are the types whose values are specified by listing their values.constant constant-name : type-name:=value. wait. Ex: constant pi : integer :=abs(3. Ex: subtype bitnum is integer range 31 down to 0.subtype subtype-name is type-name start down to end. Ex: type traffic-light-state is (reset. Ex: subtype twoval_logic is std-logic range ‘0’ to „1‟. stop. -. Ex: Character.subtype subtype-name is type-name start to end. -.type type-name is (value-list).14). -. constant bus_size : integer :=32.The most commonly used types in VHDL are User defined types and enumerated types. Boolean Syntax for types and constant declarations: -. subtype negint is integer range -2^31+1 to -1.

-. SYNTAX FOR VHDL ARRAY DECLATRATIONS: --type type-name is array (start to end ) of element-type. . VHDL defines an array as an ordered set of elements of the same type. -.VHDL also defines an important category of user defined types called as Array types. -. Ex: type lightstate is array (traffic-light-state ) of integer.type type-name is array (start down to end ) of element-type. Ex: type monthly-count is array (1 to 12) of integer .type type-name is array (range-type start down to end) of elementtype.type type-name is array (range-type start to end) of element-type. where each element is selected by an array index. Ex: type input is array (7 down to 0) of std_logic.type type-name is array (range-type) of element-type. -.

‟x‟. ‟w‟. „1‟. W:=(0=>‟1‟.) B<=“111111” ARRAYSLICE: Ex:M(6 to 9). „0‟.‟H‟.Ex: --type STD_ULOGIC is („u‟. „1‟.‟-‟). subtype std_logic is resolved std-ulogic . „1‟). ‟z‟. Concatenation operator: Ex: ‟0‟&‟1‟&‟1‟&‟z‟=> “011z” B( 6 down to 0) & B(7)=>B(7 down to 0) . bus size(31 down to 5). „1‟. ARRAY LITERALS: EX: B<=(„1‟.8=>‟1‟……. ‟L‟.

Each of the argument and the result in a VHDL function or a function call have a predetermined type.. signal-name : signal-type.Functions and Procedures: Like in a high level language. sequential-statement end function-name. . Syntax For Function Definition: Function function-name (signal-name : signal-type. in VHDL also a function accepts a number of arguments and returns a result. ……. signal-name : signal-type) return return-type is type declarations variable declarations constant declarations function definitions procedure definitions begin sequential-statement ………………….

Procedures: A VHDL procedure is similar to a function except it does not return any result. . a procedure call can be used in place of an statement. A procedure allow their arguments to be specified with type out or inout. A function call can be used in the place of an expression.

The designer specifies the name of such a library using LIBRARY clause at the beginning of the design file. simulation and synthesis of the design. but it must also refer to a common library containing shared definitions. Specifying the name of the library in the design gives it access to any previously analyzed entities and the architectures but will not allow access to type definitions.LIBRARIES AND PACKAGES: Library: A VHDL library is a place where the VHDL compiler stores information about a particular design project. The compiler automatically creates and uses a library named “work”. For a VHDL design. Ex: library IEEE. . including intermediate files that are used in the analysis. Each project has its own “work” library.

use ieee . Std_logic_1164. Std_logic_unsigned.Packages: Specifying the name of the library in the design gives it access to any previously analyzed entities and the architectures but will not allow access to type definitions. function. Std_logic_signed. Accessing of type definitions is possible using packages with use clause. use ieee . Std_logic_arith. all. Objects that can be put into packages are signal. Ex : use ieee . Designer can use a package in the design by including a use clause at the beginning of the design file. . all. and component declarations. all. procedures. use ieee . A VHDL package is a file containing definitions of objects that can be used in other programs. constant. type . all.

Syntax for user defined package: package package-name is type declarations signal declarations variable declarations constant declarations component declarations function definitions procedure definitions End package-name. . package body package-name is type declarations constant declarations function definitions procedure definitions End package-name.

Behavior design model -. Based on this. different models are specified based on way of using concurrent and sequential executable statements.Mixed design model (often used) .Architecture design methodologies: Executable portion of a VHDL design i. architecture can be modeled in different ways. the different design models of architecture are.e. --Structural design model --Data flow design model -.

because it defines the precise interconnection structure of signals and entities that realizes the entity.Structural design elements: A VHDL architecture that uses components is often called a structural description or structural design. signal-names : mode signal-type. .. Syntax for component declaration: component component-name port ( signal-names : mode signal-type. signal-names : mode signal-type). port n=>signal n). signaln). ---label: component-name port map (port1=>signal1....... Component statement: Syntax for component instantiation: ---label: component-name port map (signal1. port2=>signal2. End component. …………signal(n-1)... signal2. …………port(n-1)=>signal(n-1). ..

if the design consists multiple copies of a particular structure with in the an architecture. .Generate statement: Generate statement is used in the design. Syntax for VHDL for-generate statement: label: for identifier in range generate concurrent statement End generate. Generate statement allows the creation of repetitive structures using a kind “for loop”. with out having to write out all of the component instantiations individually.

use ieee.std-logic_1164.EX: Program to perform inversion of a bus. End inv8.b: out std_logic). End inv8. library ieee. Begin g1:for k in 1 to 8 generate U1:inv port map (x (k). . End component. all. End generate. Entity inv8 is port (x: in std_logic_vector(1 to 8). Architecture inv8 of inv8 is Component inv is port (a: in std_logic . y: out std_logic_vector(1 to 8)). y (k)).

signal-names : mode signal-type).. constant-name : constant-type. constant-name : constant-type).. .. ……………. signal-names : mode signal-type.Generic constant: Syntax: Entity entity-name is Generic (constant-name : constant-type.... ... port ( signal-names : mode signal-type.. End entity-name..

Entity geninv is generic (width : positive) port (x: in std_logic_vector(Width-1 down to 0). Architecture geninv of geninv is Component inv is port (a: in std_logic . Begin g1:for k in width-1 down to 0 generate U1:inv port map (x (k). all. .b: out std_logic). End geninv. End component. library ieee.Ex: program illustrating generic constant declaration. use ieee.std-logic_1164. End geninv. y (k)). End generate. y: out std_logic_vector(width-1 down to 0)).

End component. u3: geninv generic map (width=>32) port map(x32. End businv. Entity businv is port (x8: in std_logic_vector(7 down to 0). all. End businv. y8). y32). y8: out std_logic_vector(7 down to 0). Begin u1: geninv generic map (width=>8) port map(x8. y16).Ex: program illustrating generic map library ieee. Architecture businv of businv is Component geninv is generic (width : positive) port (x: in std_logic_vector(Width-1 down to 0). y: out std_logic_vector(width-1 down to 0)).std-logic_1164. y32: out std_logic_vector(31 down to 0)). x16: in std_logic_vector(15 down to 0). u2: geninv generic map (width=>16) port map(x16. y16: out std_logic_vector(15 down to 0). . x32: in std_logic_vector(31 down to 0). use ieee.

when boolean-expres. .when boolean-expres.signal_name<=expression..Dataflow Design Elements: If concurrent statements allow VHDL to describe a circuit in terms of the flow of data and operations on it within the circuit. else expression. --signal_name<= expres. else ------------expres.then this style is called a dataflow description or dataflow design..... Two additional concurrent statements use in dataflow designs are.when boolean-expres.. else expres. Concurrent signal assignment statements: -.

it assigns the corresponding signal-value to signal-name. The keyword others can be used in the last when clause to denote all values of expression that have not yet been covered. ------signal-value when choices. The choices in each when clause may be a single value of expression or a list of values seperated by vertical bars(|). syntax: with expression select signal-name<=signal-value when choices.Selected signal assignment statement: This statement evaluates the given expression and when matches with one of the choices. . signal-value when choices.

x(2) when “10”.Ex: Illustrating the usage of select signal statement library ieee. x(1) when “01”.std_logic_1164. End 4:1mux. use ieee. End 4:1mux. Architecture 4:1mux of 4:1mux is Begin with s select y<=x(0) when “00”. s: in std_logic_vector(1 down to 0). y: out std_logic). Entity 4:1mux is port (x: in std_logic_vector(0 to 3). x(3) when “11”. all. „x‟ when others. .

BEHAVIORAL DESIGN ELEMENTS: The key benefit of any hardware description language is its ability to create a behavioral design or behavioral description. Using the process we can specify a complex interaction of signals and events in a way that executes in essentially zero simulated time during simulation and that gives rise to synthesized combinational or sequential circuit5 that performs the modelled operation directly. “process” is a collection of sequential statements that executes in parallel with other concurrent statements or other process. A process statement can be used anywhere that a concurrent statement can be used. . VHDL‟s key behavioral element is “process”.

Syntax of a VHDL Process statement: process (signal-name. signal-name….signal-name) type declarations variable declarations constant declarations function definitions procedure definitions begin sequential-statement ----------sequential-statement End process. ……. ...

If any signal in the sensitivity list changes value as a result of running the process.Sensitivity list: The list of signals in the process definition is called sensitivity list. determines when the process runs. This process continues untill no signal changes its value. when any signal in its sensitivity list changes its value. the process starts execution. A VHDL process is always running or suspended. it runs again. starting with its first sequential statement and continuing untill the end. .

* if Boolean-expression then sequential-statement elsif Boolean-expression then sequential-statement …………………. --IF statement: * if Boolean-expression then sequential-statement end if. * if Boolean-expression then sequential-statement elsif Boolean-expression then sequential-statement …………………. elsif Boolean-expression then sequential-statement else Boolean-expression end if.--Sequential signal assignment: signal-name <= expression. --Variable signal assignment: variable-name := expression. elsif Boolean-expression then sequential-statement end if. . * if Boolean-expression then sequential-statement else sequential-statement end if.

end case. .Case statement: When we need to select among multiple alternatives based on the value of just one signal or expression. a case statement is usually more readable and may yield a better synthesized circuit. syntax: case expression is when choices=>sequential-statement. ---------when choices =>sequential-statement.

when “11”=> y<=x(3).std_logic_1164. . all. when others=>‟x‟. End process.Ex: Illustrating the usage of case statement library ieee. End 4:1mux. use ieee. Entity 4:1mux is port (x: in std_logic_vector(0 to 3). End 4:1mux. when “10”=> y<=x(2). Architecture 4:1mux of 4:1mux is Begin Process(s) begin case s is when “00”=> y<=x(0). when “01”=> y<=x(1). s: in std_logic_vector(1 down to 0). y: out std_logic). End case.

--------------sequential-statemnt. End loop. FOR LOOP: for identifier in range loop sequntial-statement. end loop. ----------------sequential-statement. .LOOP STATEMENT: syntax: loop sequential-statement.

AFTER STATEMENT: WAIT STATEMENT: . end loop.WHILE LOOP: While boolean-expression loop sequential-statement. --------------sequential-statemnt.