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Optical Receiver Design

ECE 453 Final Presentation
Dave Bowen Wei Min Chan Ben Cipriany Kent En Loh

December 2nd 2005

Optical Network Motivations

Data transmission occurs typically at baseband – optical wavelength’s frequency is the carrier Short, medium, and long-haul applications Typically high-data rate communications Low extrinsic noise and interference at optical frequencies

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Basic Optical Receiver Front-End
Current to Voltage Signal Conversion
Photodiode Transimpendence Amplifier (TIA)

Reshapes Signal for Input to Digital System
Limiting Amplifier (LA) Output Buffer (OB) Output Drive and Circuit Buffer

Automatic Gain Control (AGC)

To Maintain Signal Linearity and Gain Level

Optical IN -> Electrical OUT

Optical Receiver Application Requirements

General:
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Low-noise electronics for optical to electrical signal conversion Short to medium haul application 2+ Gbps data rate

Input side:
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InGaAs Photodiode with junction capacitance ~ 100 fF’s Optical powers ranging from -20 to +10 dBm, causing input currents from 10uA to 10mA

Output side:
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Drive a capacitive load representing subsequent MOSFET gate Digital signal RZ-type output

Transimpedance Amplifier  Adjustable gain     Prevent damage to subsequent stages Maximize range of small-signal operation Prevent data distortion from clipping Output 100+ mV to LA stage for proper operation Must provide 2+ GHz bandwidth over entire adjustable range Be able to provide a consistent DC bias level at stage output  Simple and fast   .

Transimpedance Amplifier  Variable Gain TIA  Common gate configuration  All NFETs for maximum bandwidth  Gain adjustment transistor operating in linear regime  Fixed Gain Differential Amplifier Cascade  Basic NFET differential pair design for maximum bandwidth .

4 GHz+ (Over all gain levels)  Variable Transimpedance Gain: 50 – 620  Current Consumption: ~250 uA (for a 2.2 GHz (Over all input levels)  Composite Fixed Gain: 15  .Transimpedance Amplifier  Achieved Specifications:  Variable Gain TIA  Bandwidth: 2.5 single supply) Fixed Gain Differential Amplifier Cascade  Bandwidth: 2.

Time for Varying Current Input Input Conditions: 2GHz. square pulse.Transimpedance Amplifier: Adjustable Gain Output Voltage vs. 50% duty cycle .

50% duty cycle .Transimpedance Amplifier: Linear Dynamic Range Output Voltage vs. Time for Varying Current Input Input Conditions: 2GHz. square pulse.

50% duty cycle .Transimpedance Amplifier: Linear Dynamic Range Output Voltage vs. Time for Varying Current Input Input Conditions: 2GHz. square pulse.

Automatic Gain Controller (AGC) .

.Automatic Gain Controller (AGC)   Assume AC signal centered around some DC offset Mean of any periodic DC offset signal will be the DC Offset – How do we measure the AC portion?  Solution? Use the square of the input AC Signal.

3 Input AC Magnitude 0.25 0.22 3.12  2 0 ( A0 sin(t )  Vdc ) 2 dt 1 2 2 2 ( A0 sin 2 (t )  2 * A0 sin(t ) * Vdc  Vdc )dt  0 2 2* pi 2 A 2 2 * A0 * Vdc 2 1 2  0  dt sin 2 (t )  dt sin(  t )  V dt dc   2 0   0 0 A 2  0  0  2 * Vdc 2 2 0 0.Envelope Detector: Math Envelope detector Output 3.18 3.15 0.28 3.26 3.16 3.1 0.05 0.14 3.45 0.24 This is the expected output of mixed and integrated sinusoid with DC voltage offset: 1 2  Output DC Voltage 3.4 0.2 3.35 0.2 0.5 .

5 1 0.Automatic Gain Controller (AGC) Signal Input 3.5 Voltage 2 1.5 0 50 100 150 200 Time 250 300 350 400 AGC Input Signal .5 3 2.

Automatic Gain Controller (AGC) Mixer Output 3.5 Voltage 2 1.5 0 50 100 150 200 Time 250 300 350 400 AGC Output DC voltage .5 1 0.5 3 2.

Automatic Gain Controller (AGC) .

Automatic Gain Control (AGC) AGC response to varying input AC magnitudes .

Automatic Gain Control (AGC) AGC Signal response through output CS amplifier cascade .

Automatic Gain Control (AGC) Fanning effect of output amplifiers in AGC circuit .

Automatic Gain Control (AGC) TIA output controlled by AGC output .

Limiting Amplifier .Design Considerations       TIA output .few hundred millivolts To drive digital circuitry as our load LA output – need signal swing close to logical levels Need high voltage gain and swing Bandwidth-Gain trade off Cascaded amplifier stages of diff amps .

Cascade Issues .

lower gain .Gain-Bandwidth Trade-off  Higher.

Schematic .Limiting Amplifier .

Differential Amplifier .Schematic .

Schmitt Trigger .

Limiting Amplifier .Simulation LA output with noisy input .

Output Waveform of LA .

Time for Varying Current Inputs .Output Buffer Stage Output Buffer Signal vs.

Output Buffer Implementation .

Output Buffer Implementation .

Output Buffer Implementation .

Output Buffer Implementation .

Output Buffer Stage .

Output Buffer Topology Description Cascaded inverter topology    Why use inverters?  Boost output of previous stage up to rail-to-rail voltage for driving minimal inverter First inverters have small swing and act as linear amplifiers  Somewhere in the chain it is amplified until it clips against the power supply. Subsequent inverters shape the signal by giving it faster rise and fall times. Advantages   Large dynamic range Simple design => less poles => easier to achieve high bandwidth .

Analog Option .Inductive Peaking Buffer .

0 GHz Bit rate: 4.10% Non-linearity) Bandwidth: 2.0 Gbps (depending on coding) Maximum Power Consumption: 108mW (2. .Performance Review     Input Dynamic Range: 50uA .5mA (+.5V supply) Additional Tests to be Performed     CMRR and PSRR Operational Temperature Range Extrinsic and Intrinsic Noise Affect on Dynamic Range Etc.

References    High Speed CMOS Circuits for Optical Receivers. S. 1997.Ingels and M. M.Steyaert. J. Razavi. SPIE Press. Alexander. Integrated CMOS Circuits for Optical Communications. . Kluwer Academic Publishers. 2004. 2001. Savoj and B. Optical Communication Receiver Design. Springer Publications.

Questions? Thank you! .

Output Buffer Implementation .