• Section 1 Microprocessors course By: Munish Vashishath

Sunday, April 12, 2009 Munish Vashishath

Contents:
Introduction Block Diagram and Pin Description of the 8051 Registers Some Simple Instructions Structure of Assembly language and Running an 8051 program Memory mapping in 8051 8051 Flag bits and the PSW register Addressing Modes 16-bit, BCD and Signed Arithmetic in 8051 Stack in the 8051 LOOP and JUMP Instructions CALL Instructions I/O Port Programming

Sunday, April 12, 2009

Munish Vashishath

General-purpose microprocessor
• • • CPU for Computers No RAM, ROM, I/O on CPU chip itself Example : Intel’s x86, Motorola’s 680x0

Introduction

CPU GeneralPurpose Microprocessor

Data Bus

Many chips on mother’s board

RAM

ROM

I/O Port

Timer

Serial COM Port

Address Bus General-Purpose Microprocessor System
Sunday, April 12, 2009 Munish Vashishath

Microcontroller :
• A smaller computer • On-chip RAM, ROM, I/O ports... • Example : Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU I/O Port

RAM ROM Serial Timer COM Port

A single chip
Microcontroller
Munish Vashishath

Sunday, April 12, 2009

Microprocessor vs. Microcontroller
Microprocessor • CPU is stand-alone, RAM, ROM, I/O, timer are separate • designer can decide on the amount of ROM, RAM and I/O ports. • expansive • versatility • general-purpose Microcontroller • CPU, RAM, ROM, I/O and timer are all on a single chip • fix amount of on-chip ROM, RAM, I/O ports • for applications in which cost, power and space are critical • single-purpose

Sunday, April 12, 2009

Munish Vashishath

Embedded System
• Embedded system means the processor is embedded into that application. • An embedded product uses a microprocessor or microcontroller to do one task only. • In an embedded system, there is only one application software that is typically burned into ROM. • Example : printer, keyboard, video game player

Sunday, April 12, 2009

Munish Vashishath

Three criteria in Choosing a Microcontroller
1. meeting the computing needs of the task efficiently and cost effectively • speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption • easy to upgrade • cost per unit 2. availability of software development tools • assemblers, debuggers, C compilers, emulator, simulator, technical support 3. wide availability and reliable sources of the microcontrollers.

Sunday, April 12, 2009

Munish Vashishath

8051 Features
• • • • • • • • • • 4K ROM 128 Bytes RAM Four 8 Bit I/O Ports Two 16 Bit Timers Serial Interface 64K external code memory space 64K external data memory space Boolean Processor 210 bit-addressable locations 4usec multiply/divide instructions
Sunday, April 12, 2009 Munish Vashishath

Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data
Sunday, April 12, 2009 Munish Vashishath

Comparison of the 8051 Family Members

Feature 8051 ROM (program space in bytes) 4K RAM (bytes) 128 Timers 2 I/O pins 32 Serial port 1 Interrupt sources 6

8052 8K 256 3 32 1 8

8031 0K 128 2 32 1 6

Sunday, April 12, 2009

Munish Vashishath

Sunday, April 12, 2009

Munish Vashishath

Pin Description of the 8051
PDIP/Cerdip
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0 P0.1(AD1) ) P0.2(AD2 P0.3(AD3) ) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 P2.5(A13 ) P ) 2.4(A12 P ) 2.3(A11 P2.2(A10) ) P2.1(A9) P2.0(A8)

8051 (8031)

Sunday, April 12, 2009

Munish Vashishath

Pins of 8051 ( 1/4 )
• Vcc ( pin 40 ): – Vcc provides supply voltage to the chip. – The voltage source is +5V. • GND ( pin 20 ): ground • XTAL1 and XTAL2 ( pins 19,18 ): – These 2 pins provide external clock. – Way 1 : using a quartz crystal oscillator  – Way 2 : using a TTL oscillator  – Example shows the relationship between XTAL and the machine cycle. 

Sunday, April 12, 2009

Munish Vashishath

Pins of 8051 ( 2/4 )
• RST ( pin 9 ): reset – It is an input pin and is active high ( normally low ) . • The high pulse must be high at least 2 machine cycles. – It is a power-on reset. • Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. • Reset values of some 8051 registers  – Way 1 : Power-on reset circuit  – Way 2 : Power-on reset with debounce 

Sunday, April 12, 2009

Munish Vashishath

Pins of 8051 ( 3/4 )

• /EA ( pin 31 ): external access – There is no on-chip ROM in 8031 and 8032 . – The /EA pin is connected to GND to indicate the code is stored externally. – /PSEN & ALE are used for external ROM. – For 8051, /EA pin is connected to Vcc. – “/” means active low. • /PSEN ( pin 29 ): program store enable – This is an output pin and is connected to the OE pin of the ROM.
Sunday, April 12, 2009 Munish Vashishath

Pins of 8051 ( 4/4 )

• ALE ( pin 30 ): address latch enable – It is an output pin and is active high. – 8051 port 0 provides both address and data. – The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. • I/O port pins – The four ports P0, P1, P2, and P3. – Each port uses 8 pins. – All I/O pins are bi-directional.
Sunday, April 12, 2009 Munish Vashishath

XTAL Connection to 8051
• • Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND

Sunday, April 12, 2009

Munish Vashishath

XTAL Connection to an External Clock Source

N C • • Using a TTL oscillator XTAL2 is unconnected.
EXTERNAL OSCILLATOR SIGNAL

XTAL2

XTAL1

GND

Sunday, April 12, 2009

Munish Vashishath

Example :
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 µs (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 µs

Sunday, April 12, 2009

Munish Vashishath

RESET Value of Some 8051 Registers:

Register PC ACC B PSW SP DPTR RAM are all zero.
Sunday, April 12, 2009

Reset Value 0000 0000 0000 0000 0007 0000

Munish Vashishath

Power-On RESET Circuit
Vcc

+ 10 uF 30 pF 8.2 K 30 pF 11.0592 MHz 31 19 18 EA/VPP X1 X2

9 RST

Sunday, April 12, 2009

Munish Vashishath

Power-On RESET with Debounce
Vcc

31 10 uF 30 pF

EA/VPP X1

9 8.2 K

X2 RST

Sunday, April 12, 2009

Munish Vashishath

Pins of I/O Port
• The 8051 has four I/O ports – Port 0 ( pins 32-39 ): P0 ( P0.0 ~ P0.7 ) – Port 1 ( pins 1-8 ) : P1 ( P1.0 ~ P1.7 ) – Port 2 ( pins 21-28 ): P2 ( P2.0 ~ P2.7 ) – Port 3 ( pins 10-17 ): P3 ( P3.0 ~ P3.7 ) – Each port has 8 pins. • Named P0.X ( X=0,1,...,7 ) , P1.X, P2.X, P3.X • Ex : P0.0 is the bit 0 ( LSB ) of P0 • Ex : P0.7 is the bit 7 ( MSB ) of P0 • These 8 bits form a byte. • Each port can be used as input or output (bi-direction).
Sunday, April 12, 2009 Munish Vashishath

Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL

Sunday, April 12, 2009

Munish Vashishath

Memory mapping in 8051
• ROM memory map in 8051 family
4k
0000H 0000H

8k
0000H

32k

0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

Sunday, April 12, 2009

Munish Vashishath

Memory Organization
• • • Separate memory for code & data Internal(4K) and/or external (64K) ROM for code On-chip RAM:
• • • • General Purpose Register Bit-addressable storage Register banks Special Function Registers

• •

I/O ports are memory mapped directly to SFR RAM locations Stack resides within internal RAM

Sunday, April 12, 2009

Munish Vashishath

• RAM memory space allocation in the 8051

7FH Scratch pad RAM/ General purpose RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1)

Register Bank 0

Sunday, April 12, 2009

Munish Vashishath

Program Memory

Sunday, April 12, 2009

Munish Vashishath

Lower 128 Bytes of Internal RAM

Sunday, April 12, 2009

Munish Vashishath

Internal Data Memory

Sunday, April 12, 2009

Munish Vashishath

Upper 128 Bytes of Internal RAM

Sunday, April 12, 2009

Munish Vashishath

Special Function Register
Sunday, April 12, 2009 Munish Vashishath

Name A B DPH DPL IE IP P0 P1 P2 P3 PCON
Sunday, April 12, 2009

Function Accumulator Arithmetic Addressing External Memory Addressing External Memory Interrupt Enable Control Interrupt priority I/O port Latch I/O port Latch I/O port Latch I/O port Latch Power Control
Munish Vashishath

Internal Ram address E0* F0* 83 82 A8* B8* 80* 90* A0* B0* 87

PSW SCON SBUF SP TMOD TCON TL0 THO TL1 THI
Sunday, April 12, 2009

Program status Word Serial Port Control Serial Port Data Buffer Stack Pointer Timer/Counter Mode Control Timer/Counter Control Timer 0 Low Byte Timer 0 High Byte Timer 1 Low Byte Timer 1 High Byte
Munish Vashishath

D0* 98* 99 81 89 88* 8A 8C 8B 8D
* Bit Addressable

Stack in the 8051
• The register used to access the stack is called SP (stack pointer) register. • The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0

Sunday, April 12, 2009

Munish Vashishath

8051 Flag bits and the PSW register
• PSW Register
CY AC F0 RS1 RS0 OV -P

Carry flag Auxiliary carry flag Available to the user for general purpose Register Bank selector bit 1 Register Bank selector bit 0 Overflow flag User define bit Parity flag Set/Reset odd/even parity

PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

CY AC -RS1 RS0 OV -P

RS1 0 0 1 1

RS0 0 1 0 1

Register Bank 0 1 2 3

Address 00H-07H 08H-0FH 10H-17H 18H-1FH

Sunday, April 12, 2009

Munish Vashishath

MCS51 External R/W Operation

Sunday, April 12, 2009

Munish Vashishath

MCS51 Program Memory Access

Sunday, April 12, 2009

Munish Vashishath

MCS51

Sunday, April 12, 2009

Munish Vashishath

Addressing Modes
• • • • • • • • Immediate Register Direct Register Indirect Relative Absolute Long Indexed

Sunday, April 12, 2009

Munish Vashishath

Immediate Addressing Mode
MOV MOV MOV MOV MOV A,#65H A,#’A’ R6,#65H DPTR,#2343H P1,#65H

Example : Num … MOV MOV … ORG data1: EQU 30

R0,Num DPTR,#data1 100H db

“IRAN”

Sunday, April 12, 2009

Munish Vashishath

Register Addressing Mode
MOV ADD MOV MOV MOV Rn, A A, Rn DPL, R6 DPTR, A Rm, Rn ;n=0,..,7

Sunday, April 12, 2009

Munish Vashishath

Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 – 7FH. MOV MOV MOV MOV R0, 40H 56H, A A, 4 6, 2

; ≡ MOV A, R4 ; copy R2 to R6 ; MOV R6,R2 is invalid !

SFR register and their address
MOV MOV MOV 0E0H, #66H 0F0H, R2 80H,A ; ≡ MOV A,#66H ; ≡ MOV B, R2 ; ≡ MOV P1,A
Munish Vashishath

Sunday, April 12, 2009

Register Indirect Addressing Mode
• In this mode, register is used as a pointer to the data. A,@Ri @R1,B ; move content of RAM loc.Where address is held by Ri into A ( i=0 or 1 ) MOV MOV

In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. Solution: MOV R0,#37h MOV R1,#59h MOV R2,#10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1
Sunday, April 12, 2009

; source pointer ; dest pointer ; counter

jump

Munish Vashishath

Relative, Absolute, & Long Addressing
Used only with jump and call instructions: SJMP ACALL,AJMP LCALL,LJMP

Sunday, April 12, 2009

Munish Vashishath

Indexed Addressing Mode And On-Chip ROM Access
• This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051 MOVC A,@A+DPTR A= content of address A +DPTR from ROM Note: Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The “C” means code.
Sunday, April 12, 2009 Munish Vashishath

Some Simple Instructions
MOV dest,source
MOV MOV MOV MOV MOV MOV MOV MOV A,#72H A, #’r’ R4,#62H B,0F9H DPTR,#7634H DPL,#34H DPH,#76H P1,A ;mov A to port 1

; dest = source
;A=72H ;A=‘r’ OR 72H ;R4=62H ;B=the content of F9’th byte of RAM

Note 1:
MOV A,#72H After instruction “MOV ≠ MOV A,72H A,72H ” the content of 72’th byte of RAM will replace in Accumulator.

8086
MOV MOV MOV MOV AL,72H AL,’r’ BX,72H AL,[BX] A,R3 ≡

8051
MOV MOV MOV MOV A,#72H A,#’r’ A,72H A,3

Note 2:
MOV

Sunday, April 12, 2009

Munish Vashishath

ADD A, Source

;A=A+SOURCE

ADD ADD ADD ADD

A,#6 A,R6 A,6 A,0F3H

;A=A+6 ;A=A+R6 ;A=A+[6] or A=A+R6 ;A=A+[0F3H]

Sunday, April 12, 2009

Munish Vashishath

SUBB
SETB C SUBB A,R5

A,source ;A=A-source-CY
;CY=1 ;A=A-R5-1

ADC
SETB C ADC

A,source ;A=A+source+CY
;CY=1 A,R5 ;A=A+R5+1

Sunday, April 12, 2009

Munish Vashishath

MUL & DIV
• MUL MOV MOV MUL AB ;B|A = A*B A,#25H B,#65H AB ;25H*65H=0E99 ;B=0EH, A=99H

• DIV AB ;A = A/B, B = A mod B MOV A,#25 MOV B,#10 Sunday, April 12, 2009 Munish Vashishath DIV AB ;A=2, B=5

SETB CLR
SETB SETB SETB SETB SETB
Note:

bit bit
C P0.0 P3.7 ACC.2 05

; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h
Bit Addressable Page 359,360

CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
Sunday, April 12, 2009 Munish Vashishath

DEC INC
INC DEC DEC

byte byte
R7 A 40H

;byte=byte-1 ;byte=byte+1

; [40]=[40]-1

CPL
Example: L01: MOV CPL MOV ACALL SJMP

A

;1’s complement
A,#55H ;A=01010101 B A P1,A DELAY L01

NOP & RET & RETI
All are like 8086 instructions.

Sunday, April 12, 2009

Munish Vashishath

RR – RL – RRC – RLC A EXAMPLE: RR A RR: RRC: RL: RLC:
Sunday, April 12, 2009 Munish Vashishath

C

C

ANL - ORL – XRL Bitwise Logical Operations: AND, OR, XOR
EXAMPLE: MOV R5,#89H ANL R5,#08H

CPL
Example: MOV L01: CPL MOV ACALL SJMP
Sunday, April 12, 2009

A

;1’s complement
A,#55H ;A=01010101 B A P1,A DELAY L01
Munish Vashishath

Stack in the 8051
• The register used to access the stack is called SP (stack pointer) register. • The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0

Sunday, April 12, 2009

Munish Vashishath

Example: MOV MOV MOV PUSH PUSH PUSH R6,#25H R1,#12H R4,#0F3H 6 1 4

0BH 0AH 09H 08H Start SP=07H

0BH 0AH 09H 08H 25

0BH 0AH 09H 08H 12 25

0BH 0AH 09H 08H F3 12 25

SP=08H

SP=09H

SP=08H

Sunday, April 12, 2009

Munish Vashishath

LOOP and JUMP Instructions
Conditional Jumps :
JZ JNZ DJNZ CJNE A,byte CJNE reg,#data JC JNC JB JNB JBC Jump if A=0 Jump if A/=0 Decrement and jump if A/=0 Jump if A/=byte Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit

Sunday, April 12, 2009

Munish Vashishath

DJNZ:
Write a program to clear ACC, then add 3 to the accumulator ten time Solution: MOV MOV ADD DJNZ MOV A,#0 R2,#10 A,#03 R2,AGAIN ;repeat until R2=0 (10 times) R5,A

AGAIN:

Sunday, April 12, 2009

Munish Vashishath

LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory location from 0000 to FFFFH. AJMP(absolute jump) In this 2-byte instruction, It allows a jump to any memory location within the 2k block of program memory. SJMP(short jump) In this 2-byte instruction. The relative address range of 00FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.

Sunday, April 12, 2009

Munish Vashishath

CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.

• LCALL(long call) This 3-byte instruction can be used to call subroutines located anywhere within the 64K byte address space of the 8051. • ACALL (absolute call) ACALL is 2-byte instruction. the target address of the subroutine must be within 2K byte range.
Sunday, April 12, 2009 Munish Vashishath

Instructions that Affect Flag Bits:

Note: X can be 0 or 1

Sunday, April 12, 2009

Munish Vashishath

Example: Write a program to copy a block of 10 bytes from RAM location starting at 37h to RAM location starting at 59h. Solution: MOV R0,#37h MOV R1,#59h MOV R2,#10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1
Sunday, April 12, 2009

; source pointer ; dest pointer ; counter

Munish Vashishath

Structure of Assembly language and Running an 8051 program
ORG MOV MOV MOV ADD ADD HERE: SJMP END
Sunday, April 12, 2009

0H R5,#25H R7,#34H Myfile.lst A,#0 A,R5 A,#12H HERE

EDITOR PROGRAM Myfile.asm ASSEMBLER PROGRAM Other obj file Myfile.obj LINKER PROGRAM

Myfile.abs OH PROGRAM Myfile.hex

Munish Vashishath

Example: MOV A,#88H ADD A,#93H 88 +93 ---11B CY=1 AC=0 10001000 +10010011 -------------00011011 P=0

Example: MOV A,#9CH ADD A,#64H 9C +64 ---100 CY=1 AC=1 10011100 +01100100 -------------00000000 P=0

Example: MOV A,#38H ADD A,#2FH 38 +2F ---67 CY=0 AC=1
Sunday, April 12, 2009

00111000 +00101111 -------------01100111 P=1
Munish Vashishath

Example: Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the bytes into RAM locations starting at 40h. Solution: ORG 0 MOV DPTR,#MYDATA MOV R0,#40H L1: CLR A MOVC A,@A+DPTR JZ L2 MOV @R0,A INC DPTR INC R0 SJMP L1 L2: SJMP L2 ;------------------------------------ORG 250H MYDATA: DB “Hello”,0 END Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.
Sunday, April 12, 2009 Munish Vashishath

Example: Write a program to get the x value from P1 and send x2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81 END

Sunday, April 12, 2009

Munish Vashishath

Timers /Counters Programming
• The 8051 has 2 timers/counters: timer/counter 0 and timer/counter 1. They can be used as • The timer is used as a time delay generator. – The clock source is the internal crystal frequency of the 8051. • An event counter. – External input from input pin to count the number of events on registers. – These clock pulses can represent the number of people passing through an entrance, or the number of wheel rotations, or any other event that can be converted to pulses.
Sunday, April 12, 2009 Munish Vashishath

Timer
• • • • Set the initial value of registers Start the timer and then the 8051 counts up. Input from internal system clock (machine cycle) When the registers equal to 0 and the 8051 sets a bit to denote time out 8051
Set Timer 0 P2 P1
TH0 TL0
Sunday, April 12, 2009 Munish Vashishath

to LCD

Counter
• Count the number of events – Show the number of events on registers – External input from T0 input pin (P3.4) for Counter 0 – External input from T1 input pin (P3.5) for Counter 1 – External input from Tx input pin. 8051 – We use Tx to denote T0 or T1.
TH0 TL0

P1

to LCD

a switch
Sunday, April 12, 2009

T0

P3.4

Munish Vashishath

Basic Registers of the Timer
• Both timer 0 and timer 1 are 16 bits wide. – These registers stores • the time delay as a timer • the number of events as a counter – Timer 0: TH0 & TL0 • Timer 0 high byte, timer 0 low byte – Timer 1: TH1 & TL1 • Timer 1 high byte, timer 1 low byte – Each 16-bit timer can be accessed as two separate registers of low byte and high byte.
Sunday, April 12, 2009 Munish Vashishath

Timer Registers
TH0
D15 D14 D13 D12 D11 D10 D9 D8

TL0
D7 D6 D5 D4 D3 D2 D1 D0

Timer 0

TH1
D15 D14 D13 D12 D11 D10 D9 D8

TL1
D7 D6 D5 D4 D3 D2 D1 D0

Timer 1
Sunday, April 12, 2009 Munish Vashishath

TCON Register:

• • • • • • • • •

TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag. Bit Addressable as TCON.0 to TCON.7
Munish Vashishath

Sunday, April 12, 2009

TCON Register (1/2)
• Timer control register: TMOD – Upper nibble for timer/counter, lower nibble for interrupts • TR (run control bit) – TR0 for Timer/counter 0; TR1 for Timer/counter 1. – TR is set by programmer to turn timer/counter on/off. • TR=0: off (stop) • TR=1: on (start)

(MSB) TF1 TR1 Timer 1
Sunday, April 12, 2009

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

Munish Vashishath

TCON Register (2/2)
• TF (timer flag, control flag) – TF0 for timer/counter 0; TF1 for timer/counter 1. – TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is set to 1. • TF=0 : not reach • TF=1: reach • If we enable interrupt, TF=1 will trigger ISR.

(MSB) TF1 TR1 Timer 1

TF0 TR0 Timer0

IE1

IT1 IE0 for Interrupt

(LSB) IT0

Sunday, April 12, 2009

Munish Vashishath

Equivalent Instructions for the Timer Control Register For timer 0
SETB TR0 CLR TR0 SETB TF0 CLR TF0 For timer 1 SETB TR1 CLR TR1 = = SETB TCON.6 CLR TCON.6 = = = = SETB TCON.4 CLR TCON.4 SETB TCON.5 CLR TCON.5

SETB TF1 = SETB TCON.7 CLR TF1 = CLR TCON.7 TCON: Timer/Counter Control Register
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Sunday, April 12, 2009 Munish Vashishath

TMOD Register
• Timer mode register: TMOD MOV TMOD,#21H – An 8-bit register – Set the usage mode for two timers • Set lower 4 bits for Timer 0 (Set to 0000 if not used) • Set upper 4 bits for Timer 1 (Set to 0000 if not used) – Not bit-addressable

(MSB) GATE C/T M1 Timer 1
Sunday, April 12, 2009

M0 GATE C/T M1 Timer 0
Munish Vashishath

(LSB) M0

TMOD Register
GATE Gating control when set. Timer/counter is enabled only while the INTx pin is high and the TRx control pin is set. When cleared, the timer is enabled whenever the TRx control bit is set. C/T Timer or counter selected cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin). M1 Mode bit 1 M0 Mode bit 0
(MSB) (LSB) GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 M0

Sunday, April 12, 2009

Munish Vashishath

C/T (Clock/Timer)
• This bit is used to decide whether the timer is used as a delay generator or an event counter. • C/T = 0 : timer • C/T = 1 : counter

Sunday, April 12, 2009

Munish Vashishath

Gate
• Every timer has a mean of starting and stopping. – GATE=0 • Internal control • The start and stop of the timer are controlled by way of software. • Set/clear the TR for start/stop timer. – GATE=1 • External control • The hardware way of starting and stopping the timer by software and an external source. • Timer/counter is enabled only while the INT pin is high and the TR control pin is set (TR).
Sunday, April 12, 2009 Munish Vashishath

M1, M0
• M0 and M1 select the timer mode for timers 0 & 1. M1 M0 Mode 0 0 0 0 1 1 0 1 2 Operating Mode 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1) 16-bit timer mode 8-bit THx + 8-bit TLx 8-bit auto reload 8-bit auto reload timer/counter; THx holds a value which is to be reloaded into TLx each time it overflows. Split timer mode
Munish Vashishath

1 1

3

Sunday, April 12, 2009

Timer/Counter Control Logic
XTAL oscillator

Timer
12

÷
C/T = 0

T1/0 Input Pin

Counter
TR0/1

C/T = 1

Gate

INT1/0 Input Pin

Sunday, April 12, 2009

Munish Vashishath

Sunday, April 12, 2009

Munish Vashishath

Example
Find the value for TMOD if we want to program timer 0 in mode 2, use 8051 XTAL for the clock source, and use instructions to start and stop the timer. Solution:
timer 1 timer 0

TMOD= 0000 0010 Timer 1 is not used. Timer 0, mode 2, C/T = 0 to use XTAL clock source (timer) gate = 0 to use internal (software) start and stop method.

Sunday, April 12, 2009

Munish Vashishath

Interrupt :

Sunday, April 12, 2009

Munish Vashishath

Interrupt Enable Register :

• • • • • • • •

EA : Global enable/disable. --: Undefined. ET2 :Enable Timer 2 interrupt (Reserved for Future Use). ES :Enable Serial port interrupt. ET1 :Enable Timer 1 overflow interrupt. EX1 :Enable External 1 interrupt. ET0 : Enable Timer 0 overflow interrupt. EX0 : Enable External 0 interrupt.
Munish Vashishath

Sunday, April 12, 2009

Interrupt Priority Special Function Register :
PT2 PT1 PX1 PT0 PX0

• • • • • • • •

--- : Undefined. --- : Undefined. PT2 : Reserved for Future Use PS : Priority of Serial port interrupt. Set/cleared by program PT1 : Priority of timer1 overflow interrupt. Set/cleared by program PX1 : Priority of external interrupt1. Set/cleared by program PT0 : Priority of timer 0 overflow interrupt. Set/cleared by program PX0 : Priority of external interrupt0. Set/cleared by program

Sunday, April 12, 2009

Munish Vashishath

I/O Port Programming
Port 1 ( pins 1-8 )
• Port 1 is denoted by P1. – P1.0 ~ P1.7 • We use P1 as examples to show the operations on ports. – P1 as an output port (i.e., write CPU data to the external pin) – P1 as an input port (i.e., read pin data into CPU bus)

Sunday, April 12, 2009

Munish Vashishath

A Pin of Port 1
Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch
D Q

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

P0.x
8051 IC

Sunday, April 12, 2009

Munish Vashishath

Hardware Structure of I/O Pin
• Each pin of I/O ports – Internal CPU bus : communicate with CPU – A D latch store the value of this pin • D latch is controlled by “Write to latch” – Write to latch = 1 : write data into the D latch – 2 Tri-state buffer : • TB1: controlled by “Read pin” – Read pin = 1 : really read the data present at the pin • TB2: controlled by “Read latch” – Read latch = 1 : read value from internal latch – A transistor M1 gate • Gate=0: open • Gate=1: close
Munish Vashishath

Sunday, April 12, 2009

Tri-state Buffer
Output Input

Tri-state control (active high)

L

L

H

H

Low

H

H

Highimpedance (open-circuit)

Sunday, April 12, 2009

Munish Vashishath

Writing “1” to Output Pin P1.X
Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 1 to the pin
Internal CPU bus Write to latch
D Q

Vcc

1 0
M1

P1.X
Clk Q

P1.X pin

output 1

TB1 Read pin

Sunday, April 12, 2009

Munish Vashishath

8051 IC

Writing “0” to Output Pin P1.X
Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 0 to the pin
Internal CPU bus Write to latch
D Q

ground
P1.X pin

0 1
M1

P1.X
Clk Q

output 0

TB1 Read pin

Sunday, April 12, 2009

Munish Vashishath

8051 IC

Port 1 as Output ( Write to a Port )
• Send data to Port 1 : MOV A,#55H MOV P1,A ACALL DELAY CPL A SJMP BACK

BACK:

– Let P1 toggle. – You can write to P1 directly.
Sunday, April 12, 2009 Munish Vashishath

Reading Input v.s. Port Latch
• When reading ports, there are two possibilities : – Read the status of the input pin. ( from external pin value ) • MOV A, PX • JNB P2.1, TARGET ; jump if P2.1 is not set • JB P2.1, TARGET ; jump if P2.1 is set • Figures C-11, C-12 – Read the internal latch of the output port. • ANL P1, A ; P1 ← P1 AND A • ORL P1, A ; P1 ← P1 OR A • INC P1 ; increase P1 • Figure C-17 • Table C-6 Read-Modify-Write Instruction (or Table 8-5) See Section 8.3
Munish Vashishath

Sunday, April 12, 2009

Reading “High” at Input Pin
Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 1 P1.X pin Vcc 2. MOV A,P1 external pin=High

D

Q
P1.X

Write to latch

Clk

Q

0

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 Sunday, April 12, 2009 Munish Vashishath

8051 IC

Reading “Low” at Input Pin
Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 0 Vcc 2. MOV A,P1 external pin=Low

D

Q
P1.X

P1.X pin

Write to latch

Clk

Q

0

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 Sunday, April 12, 2009 Munish Vashishath

8051 IC

Port 1 as Input ( Read from Port )
• In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV MOV MOV MOV SJMP A,#0FFH P1,A A,P1 P2,A BACK ;A=11111111B ;make P1 an input port ;get data from P0 ;send data to P2

BACK:

– To be an input port, P0, P1, P2 and P3 have similar methods.

Sunday, April 12, 2009

Munish Vashishath

Instructions For Reading an Input Port
• Following are instructions for reading external pins of ports: Examples MOV A,P2 JNB P2.1,TARGET JB P1.3,TARGET MOV C,P2.4 Description Bring into A the data at P2 pins Jump if pin P2.1 is low Jump if pin P1.3 is high Copy status of pin P2.4 to CY

Mnemonics MOV A,PX JNB PX.Y,.. JB PX.Y,.. MOV C,PX.Y

Sunday, April 12, 2009

Munish Vashishath

Reading Latch
• Exclusive-or the Port 1 : MOV P1,#55H ;P1=01010101 ORL P1,#0F0H ;P1=11110101 1. The read latch activates TB2 and bring the data from the Q latch into CPU. • Read P1.0=0 2. CPU performs an operation. • This data is ORed with bit 1 of register A. Get 1. 3. The latch is modified. • D latch of P1.0 has value 1. 4. The result is written to the external pin. • External pin (pin 1: P1.0) has value 1.
Munish Vashishath

Sunday, April 12, 2009

Reading the Latch
1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially) Read latch TB2 2. CPU compute P1.X OR 1 Internal CPU bus 1 Write to latch 3. write result to latch Read pin=0 Read latch=0 Write to latch=1 Load(L1) 0 0 0 1 4. P1.X=1 P1.X pin Vcc

D

Q
P1.X

Clk

Q

M1

TB1 Read pin 8051 IC Sunday, April 12, 2009 Munish Vashishath

Read-modify-write Feature
• Read-modify-write Instructions – Table C-6 • This features combines 3 actions in a single instruction : 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin – Note that 8 pins of P1 work independently.
Sunday, April 12, 2009 Munish Vashishath

Port 1 as Input ( Read from latch )
• Exclusive-or the Port 1 : MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN – Note that the XOR of 55H and FFH gives AAH. – XOR of AAH and FFH gives 55H. – The instruction read the data in the latch (not from the pin). – The instruction result will put into the latch and the pin.

Sunday, April 12, 2009

Munish Vashishath

Read-Modify-Write Instructions
Mnemonics ANL ORL XRL JBC PX.Y, TARGET CPL INC DEC DJNZ PX, TARGET MOV PX.Y,C CLR PX.Y SETB PX.Y
Sunday, April 12, 2009

Example ANL P1,A ORL P1,A XRL P1,A JBC P1.1, TARGET CPL P1.2 INC P1 DEC P1 DJNZ P1,TARGET MOV P1.2,C CLR P1.3 SETB P1.4
Munish Vashishath

Other Pins
• P1, P2, and P3 have internal pull-up resisters. – P1, P2, and P3 are not open drain. • P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. – P0 is open drain. – Compare the figures of P1.X and P0.X.  • However, for a programmer, it is the same to program P0, P1, P2 and P3. • All the ports upon RESET are configured as output.
Sunday, April 12, 2009 Munish Vashishath

A Pin of Port 0
Read latch TB2

Internal CPU bus Write to latch

D

Q

P1.X
Clk Q

P0.X pin M1

TB1 Read pin

P1.x
8051 IC

Sunday, April 12, 2009

Munish Vashishath

Port 0 ( pins 32-39 )
• P0 is an open drain. – Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. • When P0 is used for simple data I/O we must connect it to external pull-up resistors. – Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. – With external pull-up resistors connected upon reset, port 0 is configured as an output port.
Sunday, April 12, 2009 Munish Vashishath

Port 0 with Pull-Up Resistors
Vcc 10 K

P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7

Port 0

Sunday, April 12, 2009

Munish Vashishath

Dual Role of Port 0
• When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions. – 8031 is capable of accessing 64K bytes of external memory. – 16-bit address : P0 provides both address A0-A7, P2 provides address A8-A15. – Also, P0 provides data lines D0-D7. • When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address. – There is no need for external pull-up resistors as shown in Chapter 14.

Sunday, April 12, 2009

Munish Vashishath

74LS373
PSEN ALE P0.0 P0.7
G D

74LS373

OE OC A0 A7 D0

EA P2.0 P2.7
Sunday, April 12, 2009

D7

A8 A15
Munish Vashishath

8051

ROM

Reading ROM (1/2)
PSEN ALE P0.0 P0.7 Address D0 EA P2.0 P2.7 D7 1. Send address to ROM 2. 74373 latches the address and send to OE ROM OC G 74LS373 A0
D

A7

A8 A12

8051
Sunday, April 12, 2009 Munish Vashishath

ROM

Reading ROM (2/2)
PSEN ALE P0.0 P0.7 2. 74373 latches the address and send to ROM
G D

74LS373

OE OC A0 A7 D0

Address

EA P2.0 P2.7
Sunday, April 12, 2009

D7 3. ROM send the instruction back A8 A12
Munish Vashishath

8051

ROM

ALE Pin
• The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
– When ALE=0, P0 provides data D0-D7. – When ALE=1, P0 provides address A0-A7. – The reason is to allow P0 to multiplex address and data.

Sunday, April 12, 2009

Munish Vashishath

Port 2 ( pins 21-28 )
• Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. • In an 8031-based system, P2 are used to provide address A8-A15.

Sunday, April 12, 2009

Munish Vashishath

Port 3 ( pins 10-17 )
• Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. • Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. • Port 3 has the additional function of providing signals. – Serial communications signal : RxD, TxD. – External interrupt : /INT0, /INT1 ( – Timer/counter : T0, T1 () – External memory accesses in 8031-based system : /WR, /RD ( s
Sunday, April 12, 2009 Munish Vashishath

Sign up to vote on this title
UsefulNot useful