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VHDL
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VHDL
VHDL is a product of VHSIC program of US Department of Defense (DoD). VHDL
Origin of VHDL
Initiated by US Governments VHSIC Program in 1981. IBM, TI and Intermetrics started the development of VHDL in 1983
abstraction in VHDL.
Data flow
Gate level
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Features of VHDL
Case insensitive
inputa, INPUTA and InputA are refer to same variable
Comments
-- until end of line If you want to comment multiple lines, -- need to be put at the beginning of every single line
Model
Digital System
Internal Views
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. . . . Entity N
Device model N
Actual Hardware
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VHDL View
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In 2nd phase , system is partitioned into different levels of decomposition such as - System Design : System is decomposed
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- RTL Design : Architecture is translated into an interconnection of RTL Modules. - Logic design: RTL Modules are constructed using logic gates.
Advantages of VHDL
Can verify design functionality early in the design process and simulate a design written as a VHDL description. Logic Synthesis and optimization converts a VHDL description to a gate level implementation in a given technology. Reduces circuit design time and errors. VHDL descriptions provide technology independent documentation for a design and its functionality.
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Advantages of VHDL
Power and Flexibility
Powerful constructs to write complex logic
It has multiples levels of design descriptions
Advantages of VHDL
Device independent design
VHDL permits to create a design without first choosing the device for implementation
Portability
VHDL is an IEEE standard. Libraries of VHDL models of components can be shared across platforms,tools organization and technical group ASIC Migration Quick time to market and low cost
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Capabilities
VHDL supports design hierarchies
Capabilities
Various modeling techniques such as FSM, algorithmic and Boolean equations can be modeled using VHDL. Any large design can be modeled using VHDL No limitation imposed by the size of a design
Capabilities
Propagation delays, set-up and hold time timing constraints can be described in VHDL Generics and attributes are useful in describing parameterized design Models written in VHDL can be verified by Simulation
Summary
VHDL modeling can be used to model hardware at multiples levels of abstraction. VHDL is independent of technology and design methodologies and promotes portable descriptions ,rapid prototyping and free exchange of models among organizations and individuals.
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