You are on page 1of 17

INTRODUCTION TO

VHDL
6/18/2013 1

VHDL
VHDL is a product of VHSIC program of US Department of Defense (DoD). VHDL

Very High Speed Integrated Circuit

Hardware Description Language


VHDL is an industry standard HDL for the Description, Modeling and Synthesis of digital circuits and systems.
6/18/2013 2

Origin of VHDL
Initiated by US Governments VHSIC Program in 1981. IBM, TI and Intermetrics started the development of VHDL in 1983

VHDL Ver. 7.2 released in 1985


IEEE Std 1076-1987 in 1987

IEEE Std 1076-1993 - revision in 1993 ,


2000
6/18/2013 3

Levels of Design Abstraction


Can model a digital system at many levels of

abstraction in VHDL.

The algorithmic or functional level

Data flow
Gate level

6/18/2013

Features of VHDL
Case insensitive
inputa, INPUTA and InputA are refer to same variable

Comments
-- until end of line If you want to comment multiple lines, -- need to be put at the beginning of every single line

User defined names


letters, numbers, underscores (_) starts with a letter
6/18/2013 5

Device Vs Device Model


Device Device Model
External View

Model
Digital System

Internal Views

6/18/2013

A VHDL View of a Device

Entity 1 Entity 2 Device

Device model 1 Device model 2

. . . . Entity N

Device model N

Actual Hardware
6/18/2013

VHDL View
7

Design process of digital system


Design process of a digital system has 4 phases - Requirement Analysis & Specification - Design - Implementation & Testing - Manufacturing In 1st phase, Function,Performance and

interface requirements are determined and specified.


6/18/2013 8

In 2nd phase , system is partitioned into different levels of decomposition such as - System Design : System is decomposed

several subsystems and the communication protocol


among them is also defined. - Architectural Design : Architectural style and performance of each subsystem is determined.

6/18/2013

- RTL Design : Architecture is translated into an interconnection of RTL Modules. - Logic design: RTL Modules are constructed using logic gates.

In 3rd phase, subsystems are implemented and


tested including partitioning,placement and routing to produce a layout of circuit.

In final phase , process is to prototype ,


manufacture the design.
6/18/2013 10

Advantages of VHDL
Can verify design functionality early in the design process and simulate a design written as a VHDL description. Logic Synthesis and optimization converts a VHDL description to a gate level implementation in a given technology. Reduces circuit design time and errors. VHDL descriptions provide technology independent documentation for a design and its functionality.
6/18/2013 11

Advantages of VHDL
Power and Flexibility
Powerful constructs to write complex logic
It has multiples levels of design descriptions

It supports design libraries and the creation


of reusable components It provides for design hierarchies to create module design
6/18/2013 12

Advantages of VHDL
Device independent design
VHDL permits to create a design without first choosing the device for implementation

Portability
VHDL is an IEEE standard. Libraries of VHDL models of components can be shared across platforms,tools organization and technical group ASIC Migration Quick time to market and low cost
6/18/2013 13

Capabilities
VHDL supports design hierarchies

A digital system can be modeled as a set of interconnected components


It supports flexible design methodologies

Top-down , Bottom-up or mixed.


VHDL is not technology specific.

It can support various hardware technologies


It supports both synchronous and asynchronous timing models
6/18/2013 14

Capabilities
Various modeling techniques such as FSM, algorithmic and Boolean equations can be modeled using VHDL. Any large design can be modeled using VHDL No limitation imposed by the size of a design

Test benches can be written in VHDL to test other models.


6/18/2013 15

Capabilities
Propagation delays, set-up and hold time timing constraints can be described in VHDL Generics and attributes are useful in describing parameterized design Models written in VHDL can be verified by Simulation

Behavioral models are capable of being synthesized to gate- level description


6/18/2013 16

Summary
VHDL modeling can be used to model hardware at multiples levels of abstraction. VHDL is independent of technology and design methodologies and promotes portable descriptions ,rapid prototyping and free exchange of models among organizations and individuals.

6/18/2013

17

You might also like