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DIPLOMA IN VLSI DESIGN

VHDL CONSTRUCTS - I

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Clock Skew • Definitions: The difference between arrival times of the clock at different devices is called clock skew.

• Example of clock skew:

2004  Centre for Development of Advanced Computing

• The buffering method of figure (a) produces excessive clock skew. All of the clock signals go through identical buffers. and thus have roughly equal delays. since CLOCK1 and CLOCK2 are delayed through an extra buffer compared to CLOCK.I 2 Clock Skew • Buffering the clock: In a large system. • A recommended method is shown in figure (b). the single clock signal may not have adequate fanout to drive all of the devices. so it may be necessary to provide one or two copies of the clock signal.DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS . 2004  Centre for Development of Advanced Computing .

DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS . 2004  Centre for Development of Advanced Computing .I 3 Minimizing the clock skew • Add Delay in Data Path: The amount of the inserted delay (number of BUFD or INVD macros) in the data path should be large enough so that the delay becomes sufficiently greater than the clock skew.

2004  Centre for Development of Advanced Computing .DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS . the clock signal arrives at the clock port of the destination register sooner than the source register.I 4 Minimizing the clock skew • Clock Reversing: • In this method. the destination register will clock in the source register (current) value before the source register receives it’s clock edge. Therefore. • The clock reversing method will not be effective in circular structures such as Johnson counters because it is not possible to define the source register explicitly.

DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS .I 5 Minimizing the clock skew • Clock Reversing in circular structure: • In this example. 2004  Centre for Development of Advanced Computing . the clock skew problem exists between flip-flops U1 and U3.

I 6 Minimizing the clock skew •Alternate Phase Clocking: The following are the most common methods of alternate phase clocking: 1. Clocking on alternate edges 2.DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS . • This method provides a short path-clock skew margin of about one-half clock cycle. Clocking on alternate edges: • In this method. the sequentially adjacent registers are clocked on opposite edges of the clock. 2004  Centre for Development of Advanced Computing . Clocking with two phases 1.

I 7 Minimizing the clock skew • Signal propagation for previous circuit: 2004  Centre for Development of Advanced Computing .DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS .

between each two adjacent registers. the sequentially adjacent registers are alternatively clocked on two different phases of the same clock. • In this case. 2004  Centre for Development of Advanced Computing .I 8 Minimizing the clock skew • Clocking with two phases: • In this method.DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS . there is a safety margin approximately equal to the phase difference of the two phases.

DIPLOMA IN VLSI DESIGN VHDL CONSTRUCTS .I 9 THANK YOU 2004  Centre for Development of Advanced Computing .