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DIPLOMA IN VLSI DESIGN

STATE MACHINES - I 1
2000 © Centre for Development of Advanced Computing
State Machines in VHDL
Nayan Suthar
Hardware Technology Development Group
C-DAC, Pune.
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2000 © Centre for Development of Advanced Computing
What is a sequential circuit ?
• A machine that generates outputs based on the present
inputs and the history of past inputs is called a sequential
circuit.
• The history of the sequential circuit is represented by the
state of the machine.
• The history of the past inputs is saved in the state
memory.
• The memory of a practical machine is finite. The
summary of the history of the inputs is used. Hence it is
called a finite state machine.
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Sequential circuit
State machines exist in many forms. It can be a
mechanical system, a software program, electronics
hardware, etc.

State Machines are described in various forms. State
tables, state diagrams, flow charts, high level
description, etc.
Eg: give an example
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State machines
• After a transition the circuit will settle down to
equilibrium unless a further change of input symbol is
made. i.e. The machine settles into a new state.
• A circuit is stable internally if none of the internal signals
is unstable or changing.
• There will be a transition period followed by a stable
period whenever a state changes.
Draw a time graph for the example to display stable and transition regions
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Asynchronous state machines
• Let state time be the minimum time between two state
transitions.
• A circuit whose state time depends solely upon the
internal logic circuit delays is called as asynchronous
sequential circuit.
• A circuit is said to be working in fundamental mode
(asynchronous) if and only if the inputs are never
changed unless the circuit is stable internally.
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Practical asynchronous machines
• Due to stray delays and non ideal characteristics of
electronic devices it is impossible to have several
inputs and state variables to change at the same
instant.
• Thus to avoid possible undesirable operations, only one
input variable of an asynchronous sequential circuit is
allowed to change at a time.
• An asynchronous sequential circuit is difficult to design
and maintain. The delays of the circuit are technology
dependent and also vary with the environment.
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Synchronous state machines
• A sequential circuit that is based on an equal state
time or a state time defined by external means (such
as clock) is called as synchronous sequential circuit.
• In synchronous circuits, the inputs are treated as
snapshots of logic values during the stable period.
• Synchronous circuits which are timed by an external
clock and use edge sensitive elements are the most
stable circuits, easiest to design and are widely used.
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Formally a finite state machine is defined as a quintuple :

M = (¿, Q, Z, o, ì)

where
¿ = finite, non empty set of input symbols o
1
, o
2
, ... o
n

Q = finite, non empty set of states q
1
, q
2
, ... q
n

Z = finite, non empty set of output symbols z
1
, z
2
, ... z
n

o = next state function : Q x ¿ ÷ Q
ì = output function : Q x ¿ ÷ Z
Mathematical representation
Input and output symbols are combinations of inputs and outputs resp.
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FSMs In Hardware
Moore Machine
¿
Next-State
Function o
Memory
Q
Next
State
Present
State
Inputs Outputs
Z
Output
Function ì
• Memory is implemented as flip-flops
• The two functions are random logic
• Present state represents the summary of the past inputs
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FSMs In Hardware
Mealy Machine
Next-State
Function o
Memory
Q
Next
State
Present
State
Inputs Outputs
¿
Z
Output
Function ì
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State Machine e.g.
• Draw the state diagram of a 2 bit counter.

• Draw the state diagram of a 2 bit counter with count
enable.
Demonstrate the concept of finite states, and define equivalence of states
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State Machine e.g.
• Design a state machine to detect a sequence of “101”
from an input bit stream.
Mealy/Moore machines. Explain conversion between the two(Z homogenous machines). Difference in the time at which output is asserted.
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Mealy/Moore Machines
• Moore machines are more simple as compared to the
Mealy machines. The output functions are less
complex and hence are generally faster.
• But the Moore machine may give rise to too many
states in case of complex machines.
• The Mealy machines have one additional control on
the outputs which gives flexibility. But the input delays
are propogated to the outputs.
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FSMs in VHDL
• A finite state machine in VHDL can be defined either
implicitly or explicitly.

Eg:
Write a behavioral description to generate a pulse train
whenever stop = „0‟, using a while loop and wait until
statements.

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process
begin
. . .
Pulse_gen : while stop = „0‟ loop
trigger <= „1‟;
wait until clk‟event and clk = „1‟;
trigger <= „0‟;
wait until clk‟event and clk = „1‟;
end loop pulse_gen;
. . .
end process;
e.g. Implicit state machine
Write the same description inside a clocked process
using if statement. Hint: use a flag.
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process(clk, reset)
begin
if (reset = „1‟) then
trigger <= „0‟;
flag <= „0‟;
elsif (clk‟event and clk = „1‟) then
if (flag = „0‟) then
if (stop = „0‟) then
flag <= „1‟; trigger <= „1‟;
end if;
else
flag <= „0‟;
trigger <= „0‟;
end if;
end if;
end process;
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e.g. Implicit state machine
process(clk, reset)
begin
if (reset = „1‟) then
count <= (others => „0‟);
elsif (clk‟event and clk = „1‟) then
if (enable = „1‟) then
count <= count + 1;
end if;
end if;
end process;
In this case the state flip-flops itself are the output flip-flops.
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e.g. Implicit state machine
Design a sequence detector using a shift register.

Design a sequence detector using a counter to keep a
track of the state.
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2000 © Centre for Development of Advanced Computing
Specification of ¿ and Z is done with the VHDL entity
declaration itself:

entity fsm is
port (clk, reset : in std_logic;
bus_req0 : in std_logic;
bus_req1 : in std_logic;
bus_gnt0 : out std_logic;
bus_gnt1 : out std_logic );
end entity;
Specifying an explicit FSM in VHDL
¿ = (clk, reset, bus_req0, bus_req1)
Z = (bus_gnt0, bus_gnt1)
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The set of states is generally defined as an
enumerated type :

type device_states is (idle, grant_to_zero,
S5, ERROR);

A state vector is created to take the state values :
signal state_v: device_states;

This completely specifies Q, the state set.
Specifying an explicit FSM in VHDL
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In some compilers you can include an attribute to specify
explicitly that state_v is the state vector

attribute state vector: string;
attribute state_vector of FSM_A :
architecture is “state_v”;
Specifying a FSM in VHDL
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What still remains to be specified is o , the next state
function, and ì, the output function.
Both of these are specified in the architecture, in different
ways.
This gives rise to differently synthesized circuits, and with
different consequences.
We will take a look at the different methods of writing
architectures which describe state machines.
Specifying a FSM in VHDL
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In this style, only one process is created, and both
the outputs & next state are specified in it.
fsm_P: process(clk, reset)
begin
if (reset = „1‟) then
bus_gnt <= „0‟; .....
state_v <= idle;
elsif (clk‟event and clk = „1‟) then
case state_v is
when idle =>
bus_gnt <= „0‟; bus_gnt1 <= „1‟;
....
state_v <= S0;
when S0 =>
bus_gnt0 <= „1‟;
.....
state_v <= .......
Models o and
ì in one
process.
Specifying a FSM in VHDL : STYLE 1
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Give a demonstration of a real problem coding, synthesis and schematic
viewing. Take the example of a bus arbiter with three requests and three
grants with fixed priority. Use some editor to display the program in large
fonts.
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Style 1
• This style invariably generates registered outputs. So
the advantages/disadvantages of registered outputs are
associated with this style.
• Note that the outputs here are described as outputs in
the next state.
• The tool will optimize the next state and the output
functions together.
• The next state and the outputs are described in the
same process. This makes understanding and
debugging easy.
• It is the easiest way to write state machine description
and beginners should use this style.
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Thank you